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perf bpf: Move perf_event_output() from stdio.h to bpf.h
[linux/fpc-iii.git] / drivers / media / platform / imx-pxp.c
blobb76cd0e8313c81e1fb30a4584695f823f59aa24d
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * i.MX Pixel Pipeline (PXP) mem-to-mem scaler/CSC/rotator driver
4 *
5 * Copyright (c) 2018 Pengutronix, Philipp Zabel
6 *
7 * based on vim2m
8 *
9 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
10 * Pawel Osciak, <pawel@osciak.com>
11 * Marek Szyprowski, <m.szyprowski@samsung.com>
12 */
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
24
25 #include <linux/platform_device.h>
26 #include <media/v4l2-mem2mem.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-ioctl.h>
29 #include <media/v4l2-ctrls.h>
30 #include <media/v4l2-event.h>
31 #include <media/videobuf2-dma-contig.h>
32
33 #include "imx-pxp.h"
34
35 static unsigned int debug;
36 module_param(debug, uint, 0644);
37 MODULE_PARM_DESC(debug, "activates debug info");
38
39 #define MIN_W 8
40 #define MIN_H 8
41 #define MAX_W 4096
42 #define MAX_H 4096
43 #define ALIGN_W 3 /* 8x8 pixel blocks */
44 #define ALIGN_H 3
45
46 /* Flags that indicate a format can be used for capture/output */
47 #define MEM2MEM_CAPTURE (1 << 0)
48 #define MEM2MEM_OUTPUT (1 << 1)
49
50 #define MEM2MEM_NAME "pxp"
51
52 /* Flags that indicate processing mode */
53 #define MEM2MEM_HFLIP (1 << 0)
54 #define MEM2MEM_VFLIP (1 << 1)
55
56 #define dprintk(dev, fmt, arg...) \
57 v4l2_dbg(1, debug, &dev->v4l2_dev, "%s: " fmt, __func__, ## arg)
58
59 struct pxp_fmt {
60 u32 fourcc;
61 int depth;
62 /* Types the format can be used for */
63 u32 types;
64 };
65
66 static struct pxp_fmt formats[] = {
67 {
68 .fourcc = V4L2_PIX_FMT_XBGR32,
69 .depth = 32,
70 /* Both capture and output format */
71 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
72 }, {
73 .fourcc = V4L2_PIX_FMT_ABGR32,
74 .depth = 32,
75 /* Capture-only format */
76 .types = MEM2MEM_CAPTURE,
77 }, {
78 .fourcc = V4L2_PIX_FMT_BGR24,
79 .depth = 24,
80 .types = MEM2MEM_CAPTURE,
81 }, {
82 .fourcc = V4L2_PIX_FMT_RGB565,
83 .depth = 16,
84 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
85 }, {
86 .fourcc = V4L2_PIX_FMT_RGB555,
87 .depth = 16,
88 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
89 }, {
90 .fourcc = V4L2_PIX_FMT_RGB444,
91 .depth = 16,
92 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
93 }, {
94 .fourcc = V4L2_PIX_FMT_YUV32,
95 .depth = 32,
96 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
97 }, {
98 .fourcc = V4L2_PIX_FMT_UYVY,
99 .depth = 16,
100 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
101 }, {
102 .fourcc = V4L2_PIX_FMT_YUYV,
103 .depth = 16,
104 /* Output-only format */
105 .types = MEM2MEM_OUTPUT,
106 }, {
107 .fourcc = V4L2_PIX_FMT_VYUY,
108 .depth = 16,
109 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
110 }, {
111 .fourcc = V4L2_PIX_FMT_YVYU,
112 .depth = 16,
113 .types = MEM2MEM_OUTPUT,
114 }, {
115 .fourcc = V4L2_PIX_FMT_GREY,
116 .depth = 8,
117 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
118 }, {
119 .fourcc = V4L2_PIX_FMT_Y4,
120 .depth = 4,
121 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
122 }, {
123 .fourcc = V4L2_PIX_FMT_NV16,
124 .depth = 16,
125 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
126 }, {
127 .fourcc = V4L2_PIX_FMT_NV12,
128 .depth = 12,
129 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
130 }, {
131 .fourcc = V4L2_PIX_FMT_NV21,
132 .depth = 12,
133 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
134 }, {
135 .fourcc = V4L2_PIX_FMT_NV61,
136 .depth = 16,
137 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
138 }, {
139 .fourcc = V4L2_PIX_FMT_YUV422P,
140 .depth = 16,
141 .types = MEM2MEM_OUTPUT,
142 }, {
143 .fourcc = V4L2_PIX_FMT_YUV420,
144 .depth = 12,
145 .types = MEM2MEM_OUTPUT,
146 },
147 };
148
149 #define NUM_FORMATS ARRAY_SIZE(formats)
150
151 /* Per-queue, driver-specific private data */
152 struct pxp_q_data {
153 unsigned int width;
154 unsigned int height;
155 unsigned int bytesperline;
156 unsigned int sizeimage;
157 unsigned int sequence;
158 struct pxp_fmt *fmt;
159 enum v4l2_ycbcr_encoding ycbcr_enc;
160 enum v4l2_quantization quant;
161 };
162
163 enum {
164 V4L2_M2M_SRC = 0,
165 V4L2_M2M_DST = 1,
166 };
167
168 static struct pxp_fmt *find_format(struct v4l2_format *f)
169 {
170 struct pxp_fmt *fmt;
171 unsigned int k;
172
173 for (k = 0; k < NUM_FORMATS; k++) {
174 fmt = &formats[k];
175 if (fmt->fourcc == f->fmt.pix.pixelformat)
176 break;
177 }
178
179 if (k == NUM_FORMATS)
180 return NULL;
181
182 return &formats[k];
183 }
184
185 struct pxp_dev {
186 struct v4l2_device v4l2_dev;
187 struct video_device vfd;
188
189 struct clk *clk;
190 void __iomem *mmio;
191
192 atomic_t num_inst;
193 struct mutex dev_mutex;
194 spinlock_t irqlock;
195
196 struct v4l2_m2m_dev *m2m_dev;
197 };
198
199 struct pxp_ctx {
200 struct v4l2_fh fh;
201 struct pxp_dev *dev;
202
203 struct v4l2_ctrl_handler hdl;
204
205 /* Abort requested by m2m */
206 int aborting;
207
208 /* Processing mode */
209 int mode;
210 u8 alpha_component;
211
212 enum v4l2_colorspace colorspace;
213 enum v4l2_xfer_func xfer_func;
214
215 /* Source and destination queue data */
216 struct pxp_q_data q_data[2];
217 };
218
219 static inline struct pxp_ctx *file2ctx(struct file *file)
220 {
221 return container_of(file->private_data, struct pxp_ctx, fh);
222 }
223
224 static struct pxp_q_data *get_q_data(struct pxp_ctx *ctx,
225 enum v4l2_buf_type type)
226 {
227 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
228 return &ctx->q_data[V4L2_M2M_SRC];
229 else
230 return &ctx->q_data[V4L2_M2M_DST];
231 }
232
233 static u32 pxp_v4l2_pix_fmt_to_ps_format(u32 v4l2_pix_fmt)
234 {
235 switch (v4l2_pix_fmt) {
236 case V4L2_PIX_FMT_XBGR32: return BV_PXP_PS_CTRL_FORMAT__RGB888;
237 case V4L2_PIX_FMT_RGB555: return BV_PXP_PS_CTRL_FORMAT__RGB555;
238 case V4L2_PIX_FMT_RGB444: return BV_PXP_PS_CTRL_FORMAT__RGB444;
239 case V4L2_PIX_FMT_RGB565: return BV_PXP_PS_CTRL_FORMAT__RGB565;
240 case V4L2_PIX_FMT_YUV32: return BV_PXP_PS_CTRL_FORMAT__YUV1P444;
241 case V4L2_PIX_FMT_UYVY: return BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
242 case V4L2_PIX_FMT_YUYV: return BM_PXP_PS_CTRL_WB_SWAP |
243 BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
244 case V4L2_PIX_FMT_VYUY: return BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
245 case V4L2_PIX_FMT_YVYU: return BM_PXP_PS_CTRL_WB_SWAP |
246 BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
247 case V4L2_PIX_FMT_GREY: return BV_PXP_PS_CTRL_FORMAT__Y8;
248 default:
249 case V4L2_PIX_FMT_Y4: return BV_PXP_PS_CTRL_FORMAT__Y4;
250 case V4L2_PIX_FMT_NV16: return BV_PXP_PS_CTRL_FORMAT__YUV2P422;
251 case V4L2_PIX_FMT_NV12: return BV_PXP_PS_CTRL_FORMAT__YUV2P420;
252 case V4L2_PIX_FMT_NV21: return BV_PXP_PS_CTRL_FORMAT__YVU2P420;
253 case V4L2_PIX_FMT_NV61: return BV_PXP_PS_CTRL_FORMAT__YVU2P422;
254 case V4L2_PIX_FMT_YUV422P: return BV_PXP_PS_CTRL_FORMAT__YUV422;
255 case V4L2_PIX_FMT_YUV420: return BV_PXP_PS_CTRL_FORMAT__YUV420;
256 }
257 }
258
259 static u32 pxp_v4l2_pix_fmt_to_out_format(u32 v4l2_pix_fmt)
260 {
261 switch (v4l2_pix_fmt) {
262 case V4L2_PIX_FMT_XBGR32: return BV_PXP_OUT_CTRL_FORMAT__RGB888;
263 case V4L2_PIX_FMT_ABGR32: return BV_PXP_OUT_CTRL_FORMAT__ARGB8888;
264 case V4L2_PIX_FMT_BGR24: return BV_PXP_OUT_CTRL_FORMAT__RGB888P;
265 /* Missing V4L2 pixel formats for ARGB1555 and ARGB4444 */
266 case V4L2_PIX_FMT_RGB555: return BV_PXP_OUT_CTRL_FORMAT__RGB555;
267 case V4L2_PIX_FMT_RGB444: return BV_PXP_OUT_CTRL_FORMAT__RGB444;
268 case V4L2_PIX_FMT_RGB565: return BV_PXP_OUT_CTRL_FORMAT__RGB565;
269 case V4L2_PIX_FMT_YUV32: return BV_PXP_OUT_CTRL_FORMAT__YUV1P444;
270 case V4L2_PIX_FMT_UYVY: return BV_PXP_OUT_CTRL_FORMAT__UYVY1P422;
271 case V4L2_PIX_FMT_VYUY: return BV_PXP_OUT_CTRL_FORMAT__VYUY1P422;
272 case V4L2_PIX_FMT_GREY: return BV_PXP_OUT_CTRL_FORMAT__Y8;
273 default:
274 case V4L2_PIX_FMT_Y4: return BV_PXP_OUT_CTRL_FORMAT__Y4;
275 case V4L2_PIX_FMT_NV16: return BV_PXP_OUT_CTRL_FORMAT__YUV2P422;
276 case V4L2_PIX_FMT_NV12: return BV_PXP_OUT_CTRL_FORMAT__YUV2P420;
277 case V4L2_PIX_FMT_NV61: return BV_PXP_OUT_CTRL_FORMAT__YVU2P422;
278 case V4L2_PIX_FMT_NV21: return BV_PXP_OUT_CTRL_FORMAT__YVU2P420;
279 }
280 }
281
282 static bool pxp_v4l2_pix_fmt_is_yuv(u32 v4l2_pix_fmt)
283 {
284 switch (v4l2_pix_fmt) {
285 case V4L2_PIX_FMT_YUV32:
286 case V4L2_PIX_FMT_UYVY:
287 case V4L2_PIX_FMT_YUYV:
288 case V4L2_PIX_FMT_VYUY:
289 case V4L2_PIX_FMT_YVYU:
290 case V4L2_PIX_FMT_NV16:
291 case V4L2_PIX_FMT_NV12:
292 case V4L2_PIX_FMT_NV61:
293 case V4L2_PIX_FMT_NV21:
294 case V4L2_PIX_FMT_YUV420:
295 case V4L2_PIX_FMT_YUV422P:
296 case V4L2_PIX_FMT_GREY:
297 case V4L2_PIX_FMT_Y4:
298 return true;
299 default:
300 return false;
301 }
302 }
303
304 static void pxp_setup_csc(struct pxp_ctx *ctx)
305 {
306 struct pxp_dev *dev = ctx->dev;
307 enum v4l2_ycbcr_encoding ycbcr_enc;
308 enum v4l2_quantization quantization;
309
310 if (pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
311 !pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_DST].fmt->fourcc)) {
312 /*
313 * CSC1 YUV/YCbCr to RGB conversion is implemented as follows:
314 *
315 * |R| |C0 0 C1| |Y + Yoffset |
316 * |G| = |C0 C3 C2| * |Cb + UVoffset|
317 * |B| |C0 C4 0 | |Cr + UVoffset|
318 *
319 * Results are clamped to 0..255.
320 *
321 * BT.601 limited range:
322 *
323 * |R| |1.1644 0.0000 1.5960| |Y - 16 |
324 * |G| = |1.1644 -0.3917 -0.8129| * |Cb - 128|
325 * |B| |1.1644 2.0172 0.0000| |Cr - 128|
326 */
327 static const u32 csc1_coef_bt601_lim[3] = {
328 BM_PXP_CSC1_COEF0_YCBCR_MODE |
329 BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
330 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
331 BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
332 BF_PXP_CSC1_COEF1_C1(0x198) | /* 1.5938 (-0.23 %) */
333 BF_PXP_CSC1_COEF1_C4(0x204), /* 2.0156 (-0.16 %) */
334 BF_PXP_CSC1_COEF2_C2(0x730) | /* -0.8125 (+0.04 %) */
335 BF_PXP_CSC1_COEF2_C3(0x79c), /* -0.3906 (+0.11 %) */
336 };
337 /*
338 * BT.601 full range:
339 *
340 * |R| |1.0000 0.0000 1.4020| |Y + 0 |
341 * |G| = |1.0000 -0.3441 -0.7141| * |Cb - 128|
342 * |B| |1.0000 1.7720 0.0000| |Cr - 128|
343 */
344 static const u32 csc1_coef_bt601_full[3] = {
345 BM_PXP_CSC1_COEF0_YCBCR_MODE |
346 BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
347 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
348 BF_PXP_CSC1_COEF0_Y_OFFSET(0),
349 BF_PXP_CSC1_COEF1_C1(0x166) | /* 1.3984 (-0.36 %) */
350 BF_PXP_CSC1_COEF1_C4(0x1c5), /* 1.7695 (-0.25 %) */
351 BF_PXP_CSC1_COEF2_C2(0x74a) | /* -0.7109 (+0.32 %) */
352 BF_PXP_CSC1_COEF2_C3(0x7a8), /* -0.3438 (+0.04 %) */
353 };
354 /*
355 * Rec.709 limited range:
356 *
357 * |R| |1.1644 0.0000 1.7927| |Y - 16 |
358 * |G| = |1.1644 -0.2132 -0.5329| * |Cb - 128|
359 * |B| |1.1644 2.1124 0.0000| |Cr - 128|
360 */
361 static const u32 csc1_coef_rec709_lim[3] = {
362 BM_PXP_CSC1_COEF0_YCBCR_MODE |
363 BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
364 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
365 BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
366 BF_PXP_CSC1_COEF1_C1(0x1ca) | /* 1.7891 (-0.37 %) */
367 BF_PXP_CSC1_COEF1_C4(0x21c), /* 2.1094 (-0.30 %) */
368 BF_PXP_CSC1_COEF2_C2(0x778) | /* -0.5312 (+0.16 %) */
369 BF_PXP_CSC1_COEF2_C3(0x7ca), /* -0.2109 (+0.23 %) */
370 };
371 /*
372 * Rec.709 full range:
373 *
374 * |R| |1.0000 0.0000 1.5748| |Y + 0 |
375 * |G| = |1.0000 -0.1873 -0.4681| * |Cb - 128|
376 * |B| |1.0000 1.8556 0.0000| |Cr - 128|
377 */
378 static const u32 csc1_coef_rec709_full[3] = {
379 BM_PXP_CSC1_COEF0_YCBCR_MODE |
380 BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
381 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
382 BF_PXP_CSC1_COEF0_Y_OFFSET(0),
383 BF_PXP_CSC1_COEF1_C1(0x193) | /* 1.5742 (-0.06 %) */
384 BF_PXP_CSC1_COEF1_C4(0x1db), /* 1.8555 (-0.01 %) */
385 BF_PXP_CSC1_COEF2_C2(0x789) | /* -0.4648 (+0.33 %) */
386 BF_PXP_CSC1_COEF2_C3(0x7d1), /* -0.1836 (+0.37 %) */
387 };
388 /*
389 * BT.2020 limited range:
390 *
391 * |R| |1.1644 0.0000 1.6787| |Y - 16 |
392 * |G| = |1.1644 -0.1874 -0.6505| * |Cb - 128|
393 * |B| |1.1644 2.1418 0.0000| |Cr - 128|
394 */
395 static const u32 csc1_coef_bt2020_lim[3] = {
396 BM_PXP_CSC1_COEF0_YCBCR_MODE |
397 BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
398 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
399 BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
400 BF_PXP_CSC1_COEF1_C1(0x1ad) | /* 1.6758 (-0.29 %) */
401 BF_PXP_CSC1_COEF1_C4(0x224), /* 2.1406 (-0.11 %) */
402 BF_PXP_CSC1_COEF2_C2(0x75a) | /* -0.6484 (+0.20 %) */
403 BF_PXP_CSC1_COEF2_C3(0x7d1), /* -0.1836 (+0.38 %) */
404 };
405 /*
406 * BT.2020 full range:
407 *
408 * |R| |1.0000 0.0000 1.4746| |Y + 0 |
409 * |G| = |1.0000 -0.1646 -0.5714| * |Cb - 128|
410 * |B| |1.0000 1.8814 0.0000| |Cr - 128|
411 */
412 static const u32 csc1_coef_bt2020_full[3] = {
413 BM_PXP_CSC1_COEF0_YCBCR_MODE |
414 BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
415 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
416 BF_PXP_CSC1_COEF0_Y_OFFSET(0),
417 BF_PXP_CSC1_COEF1_C1(0x179) | /* 1.4727 (-0.19 %) */
418 BF_PXP_CSC1_COEF1_C4(0x1e1), /* 1.8789 (-0.25 %) */
419 BF_PXP_CSC1_COEF2_C2(0x76e) | /* -0.5703 (+0.11 %) */
420 BF_PXP_CSC1_COEF2_C3(0x7d6), /* -0.1641 (+0.05 %) */
421 };
422 /*
423 * SMPTE 240m limited range:
424 *
425 * |R| |1.1644 0.0000 1.7937| |Y - 16 |
426 * |G| = |1.1644 -0.2565 -0.5427| * |Cb - 128|
427 * |B| |1.1644 2.0798 0.0000| |Cr - 128|
428 */
429 static const u32 csc1_coef_smpte240m_lim[3] = {
430 BM_PXP_CSC1_COEF0_YCBCR_MODE |
431 BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
432 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
433 BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
434 BF_PXP_CSC1_COEF1_C1(0x1cb) | /* 1.7930 (-0.07 %) */
435 BF_PXP_CSC1_COEF1_C4(0x214), /* 2.0781 (-0.17 %) */
436 BF_PXP_CSC1_COEF2_C2(0x776) | /* -0.5391 (+0.36 %) */
437 BF_PXP_CSC1_COEF2_C3(0x7bf), /* -0.2539 (+0.26 %) */
438 };
439 /*
440 * SMPTE 240m full range:
441 *
442 * |R| |1.0000 0.0000 1.5756| |Y + 0 |
443 * |G| = |1.0000 -0.2253 -0.4767| * |Cb - 128|
444 * |B| |1.0000 1.8270 0.0000| |Cr - 128|
445 */
446 static const u32 csc1_coef_smpte240m_full[3] = {
447 BM_PXP_CSC1_COEF0_YCBCR_MODE |
448 BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
449 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
450 BF_PXP_CSC1_COEF0_Y_OFFSET(0),
451 BF_PXP_CSC1_COEF1_C1(0x193) | /* 1.5742 (-0.14 %) */
452 BF_PXP_CSC1_COEF1_C4(0x1d3), /* 1.8242 (-0.28 %) */
453 BF_PXP_CSC1_COEF2_C2(0x786) | /* -0.4766 (+0.01 %) */
454 BF_PXP_CSC1_COEF2_C3(0x7c7), /* -0.2227 (+0.26 %) */
455 };
456 const u32 *csc1_coef;
457
458 ycbcr_enc = ctx->q_data[V4L2_M2M_SRC].ycbcr_enc;
459 quantization = ctx->q_data[V4L2_M2M_SRC].quant;
460
461 if (ycbcr_enc == V4L2_YCBCR_ENC_601) {
462 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
463 csc1_coef = csc1_coef_bt601_full;
464 else
465 csc1_coef = csc1_coef_bt601_lim;
466 } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
467 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
468 csc1_coef = csc1_coef_rec709_full;
469 else
470 csc1_coef = csc1_coef_rec709_lim;
471 } else if (ycbcr_enc == V4L2_YCBCR_ENC_BT2020) {
472 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
473 csc1_coef = csc1_coef_bt2020_full;
474 else
475 csc1_coef = csc1_coef_bt2020_lim;
476 } else {
477 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
478 csc1_coef = csc1_coef_smpte240m_full;
479 else
480 csc1_coef = csc1_coef_smpte240m_lim;
481 }
482
483 writel(csc1_coef[0], dev->mmio + HW_PXP_CSC1_COEF0);
484 writel(csc1_coef[1], dev->mmio + HW_PXP_CSC1_COEF1);
485 writel(csc1_coef[2], dev->mmio + HW_PXP_CSC1_COEF2);
486 } else {
487 writel(BM_PXP_CSC1_COEF0_BYPASS, dev->mmio + HW_PXP_CSC1_COEF0);
488 }
489
490 if (!pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
491 pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_DST].fmt->fourcc)) {
492 /*
493 * CSC2 RGB to YUV/YCbCr conversion is implemented as follows:
494 *
495 * |Y | |A1 A2 A3| |R| |D1|
496 * |Cb| = |B1 B2 B3| * |G| + |D2|
497 * |Cr| |C1 C2 C3| |B| |D3|
498 *
499 * Results are clamped to 0..255.
500 *
501 * BT.601 limited range:
502 *
503 * |Y | | 0.2568 0.5041 0.0979| |R| |16 |
504 * |Cb| = |-0.1482 -0.2910 0.4392| * |G| + |128|
505 * |Cr| | 0.4392 0.4392 -0.3678| |B| |128|
506 */
507 static const u32 csc2_coef_bt601_lim[6] = {
508 BF_PXP_CSC2_COEF0_A2(0x081) | /* 0.5039 (-0.02 %) */
509 BF_PXP_CSC2_COEF0_A1(0x041), /* 0.2539 (-0.29 %) */
510 BF_PXP_CSC2_COEF1_B1(0x7db) | /* -0.1445 (+0.37 %) */
511 BF_PXP_CSC2_COEF1_A3(0x019), /* 0.0977 (-0.02 %) */
512 BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
513 BF_PXP_CSC2_COEF2_B2(0x7b6), /* -0.2891 (+0.20 %) */
514 BF_PXP_CSC2_COEF3_C2(0x7a2) | /* -0.3672 (+0.06 %) */
515 BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
516 BF_PXP_CSC2_COEF4_D1(16) |
517 BF_PXP_CSC2_COEF4_C3(0x7ee), /* -0.0703 (+0.11 %) */
518 BF_PXP_CSC2_COEF5_D3(128) |
519 BF_PXP_CSC2_COEF5_D2(128),
520 };
521 /*
522 * BT.601 full range:
523 *
524 * |Y | | 0.2990 0.5870 0.1140| |R| |0 |
525 * |Cb| = |-0.1687 -0.3313 0.5000| * |G| + |128|
526 * |Cr| | 0.5000 0.5000 -0.4187| |B| |128|
527 */
528 static const u32 csc2_coef_bt601_full[6] = {
529 BF_PXP_CSC2_COEF0_A2(0x096) | /* 0.5859 (-0.11 %) */
530 BF_PXP_CSC2_COEF0_A1(0x04c), /* 0.2969 (-0.21 %) */
531 BF_PXP_CSC2_COEF1_B1(0x7d5) | /* -0.1680 (+0.07 %) */
532 BF_PXP_CSC2_COEF1_A3(0x01d), /* 0.1133 (-0.07 %) */
533 BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
534 BF_PXP_CSC2_COEF2_B2(0x7ac), /* -0.3281 (+0.32 %) */
535 BF_PXP_CSC2_COEF3_C2(0x795) | /* -0.4180 (+0.07 %) */
536 BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
537 BF_PXP_CSC2_COEF4_D1(0) |
538 BF_PXP_CSC2_COEF4_C3(0x7ec), /* -0.0781 (+0.32 %) */
539 BF_PXP_CSC2_COEF5_D3(128) |
540 BF_PXP_CSC2_COEF5_D2(128),
541 };
542 /*
543 * Rec.709 limited range:
544 *
545 * |Y | | 0.1826 0.6142 0.0620| |R| |16 |
546 * |Cb| = |-0.1007 -0.3385 0.4392| * |G| + |128|
547 * |Cr| | 0.4392 0.4392 -0.3990| |B| |128|
548 */
549 static const u32 csc2_coef_rec709_lim[6] = {
550 BF_PXP_CSC2_COEF0_A2(0x09d) | /* 0.6133 (-0.09 %) */
551 BF_PXP_CSC2_COEF0_A1(0x02e), /* 0.1797 (-0.29 %) */
552 BF_PXP_CSC2_COEF1_B1(0x7e7) | /* -0.0977 (+0.30 %) */
553 BF_PXP_CSC2_COEF1_A3(0x00f), /* 0.0586 (-0.34 %) */
554 BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
555 BF_PXP_CSC2_COEF2_B2(0x7aa), /* -0.3359 (+0.26 %) */
556 BF_PXP_CSC2_COEF3_C2(0x79a) | /* -0.3984 (+0.05 %) */
557 BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
558 BF_PXP_CSC2_COEF4_D1(16) |
559 BF_PXP_CSC2_COEF4_C3(0x7f6), /* -0.0391 (+0.12 %) */
560 BF_PXP_CSC2_COEF5_D3(128) |
561 BF_PXP_CSC2_COEF5_D2(128),
562 };
563 /*
564 * Rec.709 full range:
565 *
566 * |Y | | 0.2126 0.7152 0.0722| |R| |0 |
567 * |Cb| = |-0.1146 -0.3854 0.5000| * |G| + |128|
568 * |Cr| | 0.5000 0.5000 -0.4542| |B| |128|
569 */
570 static const u32 csc2_coef_rec709_full[6] = {
571 BF_PXP_CSC2_COEF0_A2(0x0b7) | /* 0.7148 (-0.04 %) */
572 BF_PXP_CSC2_COEF0_A1(0x036), /* 0.2109 (-0.17 %) */
573 BF_PXP_CSC2_COEF1_B1(0x7e3) | /* -0.1133 (+0.13 %) */
574 BF_PXP_CSC2_COEF1_A3(0x012), /* 0.0703 (-0.19 %) */
575 BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
576 BF_PXP_CSC2_COEF2_B2(0x79e), /* -0.3828 (+0.26 %) */
577 BF_PXP_CSC2_COEF3_C2(0x78c) | /* -0.4531 (+0.11 %) */
578 BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
579 BF_PXP_CSC2_COEF4_D1(0) |
580 BF_PXP_CSC2_COEF4_C3(0x7f5), /* -0.0430 (+0.28 %) */
581 BF_PXP_CSC2_COEF5_D3(128) |
582 BF_PXP_CSC2_COEF5_D2(128),
583 };
584 /*
585 * BT.2020 limited range:
586 *
587 * |Y | | 0.2256 0.5823 0.0509| |R| |16 |
588 * |Cb| = |-0.1226 -0.3166 0.4392| * |G| + |128|
589 * |Cr| | 0.4392 0.4392 -0.4039| |B| |128|
590 */
591 static const u32 csc2_coef_bt2020_lim[6] = {
592 BF_PXP_CSC2_COEF0_A2(0x095) | /* 0.5820 (-0.03 %) */
593 BF_PXP_CSC2_COEF0_A1(0x039), /* 0.2227 (-0.30 %) */
594 BF_PXP_CSC2_COEF1_B1(0x7e1) | /* -0.1211 (+0.15 %) */
595 BF_PXP_CSC2_COEF1_A3(0x00d), /* 0.0508 (-0.01 %) */
596 BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
597 BF_PXP_CSC2_COEF2_B2(0x7af), /* -0.3164 (+0.02 %) */
598 BF_PXP_CSC2_COEF3_C2(0x799) | /* -0.4023 (+0.16 %) */
599 BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
600 BF_PXP_CSC2_COEF4_D1(16) |
601 BF_PXP_CSC2_COEF4_C3(0x7f7), /* -0.0352 (+0.02 %) */
602 BF_PXP_CSC2_COEF5_D3(128) |
603 BF_PXP_CSC2_COEF5_D2(128),
604 };
605 /*
606 * BT.2020 full range:
607 *
608 * |Y | | 0.2627 0.6780 0.0593| |R| |0 |
609 * |Cb| = |-0.1396 -0.3604 0.5000| * |G| + |128|
610 * |Cr| | 0.5000 0.5000 -0.4598| |B| |128|
611 */
612 static const u32 csc2_coef_bt2020_full[6] = {
613 BF_PXP_CSC2_COEF0_A2(0x0ad) | /* 0.6758 (-0.22 %) */
614 BF_PXP_CSC2_COEF0_A1(0x043), /* 0.2617 (-0.10 %) */
615 BF_PXP_CSC2_COEF1_B1(0x7dd) | /* -0.1367 (+0.29 %) */
616 BF_PXP_CSC2_COEF1_A3(0x00f), /* 0.0586 (-0.07 %) */
617 BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
618 BF_PXP_CSC2_COEF2_B2(0x7a4), /* -0.3594 (+0.10 %) */
619 BF_PXP_CSC2_COEF3_C2(0x78b) | /* -0.4570 (+0.28 %) */
620 BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
621 BF_PXP_CSC2_COEF4_D1(0) |
622 BF_PXP_CSC2_COEF4_C3(0x7f6), /* -0.0391 (+0.11 %) */
623 BF_PXP_CSC2_COEF5_D3(128) |
624 BF_PXP_CSC2_COEF5_D2(128),
625 };
626 /*
627 * SMPTE 240m limited range:
628 *
629 * |Y | | 0.1821 0.6020 0.0747| |R| |16 |
630 * |Cb| = |-0.1019 -0.3373 0.4392| * |G| + |128|
631 * |Cr| | 0.4392 0.4392 -0.3909| |B| |128|
632 */
633 static const u32 csc2_coef_smpte240m_lim[6] = {
634 BF_PXP_CSC2_COEF0_A2(0x09a) | /* 0.6016 (-0.05 %) */
635 BF_PXP_CSC2_COEF0_A1(0x02e), /* 0.1797 (-0.24 %) */
636 BF_PXP_CSC2_COEF1_B1(0x7e6) | /* -0.1016 (+0.03 %) */
637 BF_PXP_CSC2_COEF1_A3(0x013), /* 0.0742 (-0.05 %) */
638 BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
639 BF_PXP_CSC2_COEF2_B2(0x7aa), /* -0.3359 (+0.14 %) */
640 BF_PXP_CSC2_COEF3_C2(0x79c) | /* -0.3906 (+0.03 %) */
641 BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
642 BF_PXP_CSC2_COEF4_D1(16) |
643 BF_PXP_CSC2_COEF4_C3(0x7f4), /* -0.0469 (+0.14 %) */
644 BF_PXP_CSC2_COEF5_D3(128) |
645 BF_PXP_CSC2_COEF5_D2(128),
646 };
647 /*
648 * SMPTE 240m full range:
649 *
650 * |Y | | 0.2120 0.7010 0.0870| |R| |0 |
651 * |Cb| = |-0.1160 -0.3840 0.5000| * |G| + |128|
652 * |Cr| | 0.5000 0.5000 -0.4450| |B| |128|
653 */
654 static const u32 csc2_coef_smpte240m_full[6] = {
655 BF_PXP_CSC2_COEF0_A2(0x0b3) | /* 0.6992 (-0.18 %) */
656 BF_PXP_CSC2_COEF0_A1(0x036), /* 0.2109 (-0.11 %) */
657 BF_PXP_CSC2_COEF1_B1(0x7e3) | /* -0.1133 (+0.27 %) */
658 BF_PXP_CSC2_COEF1_A3(0x016), /* 0.0859 (-0.11 %) */
659 BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
660 BF_PXP_CSC2_COEF2_B2(0x79e), /* -0.3828 (+0.12 %) */
661 BF_PXP_CSC2_COEF3_C2(0x78f) | /* -0.4414 (+0.36 %) */
662 BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
663 BF_PXP_CSC2_COEF4_D1(0) |
664 BF_PXP_CSC2_COEF4_C3(0x7f2), /* -0.0547 (+0.03 %) */
665 BF_PXP_CSC2_COEF5_D3(128) |
666 BF_PXP_CSC2_COEF5_D2(128),
667 };
668 const u32 *csc2_coef;
669 u32 csc2_ctrl;
670
671 ycbcr_enc = ctx->q_data[V4L2_M2M_DST].ycbcr_enc;
672 quantization = ctx->q_data[V4L2_M2M_DST].quant;
673
674 if (ycbcr_enc == V4L2_YCBCR_ENC_601) {
675 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
676 csc2_coef = csc2_coef_bt601_full;
677 else
678 csc2_coef = csc2_coef_bt601_lim;
679 } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
680 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
681 csc2_coef = csc2_coef_rec709_full;
682 else
683 csc2_coef = csc2_coef_rec709_lim;
684 } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
685 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
686 csc2_coef = csc2_coef_bt2020_full;
687 else
688 csc2_coef = csc2_coef_bt2020_lim;
689 } else {
690 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
691 csc2_coef = csc2_coef_smpte240m_full;
692 else
693 csc2_coef = csc2_coef_smpte240m_lim;
694 }
695 if (quantization == V4L2_QUANTIZATION_FULL_RANGE) {
696 csc2_ctrl = BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV <<
697 BP_PXP_CSC2_CTRL_CSC_MODE;
698 } else {
699 csc2_ctrl = BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr <<
700 BP_PXP_CSC2_CTRL_CSC_MODE;
701 }
702
703 writel(csc2_ctrl, dev->mmio + HW_PXP_CSC2_CTRL);
704 writel(csc2_coef[0], dev->mmio + HW_PXP_CSC2_COEF0);
705 writel(csc2_coef[1], dev->mmio + HW_PXP_CSC2_COEF1);
706 writel(csc2_coef[2], dev->mmio + HW_PXP_CSC2_COEF2);
707 writel(csc2_coef[3], dev->mmio + HW_PXP_CSC2_COEF3);
708 writel(csc2_coef[4], dev->mmio + HW_PXP_CSC2_COEF4);
709 writel(csc2_coef[5], dev->mmio + HW_PXP_CSC2_COEF5);
710 } else {
711 writel(BM_PXP_CSC2_CTRL_BYPASS, dev->mmio + HW_PXP_CSC2_CTRL);
712 }
713 }
714
715 static int pxp_start(struct pxp_ctx *ctx, struct vb2_v4l2_buffer *in_vb,
716 struct vb2_v4l2_buffer *out_vb)
717 {
718 struct pxp_dev *dev = ctx->dev;
719 struct pxp_q_data *q_data;
720 u32 src_width, src_height, src_stride, src_fourcc;
721 u32 dst_width, dst_height, dst_stride, dst_fourcc;
722 dma_addr_t p_in, p_out;
723 u32 ctrl, out_ctrl, out_buf, out_buf2, out_pitch, out_lrc, out_ps_ulc;
724 u32 out_ps_lrc;
725 u32 ps_ctrl, ps_buf, ps_ubuf, ps_vbuf, ps_pitch, ps_scale, ps_offset;
726 u32 as_ulc, as_lrc;
727 u32 y_size;
728 u32 decx, decy, xscale, yscale;
729
730 q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
731
732 src_width = ctx->q_data[V4L2_M2M_SRC].width;
733 dst_width = ctx->q_data[V4L2_M2M_DST].width;
734 src_height = ctx->q_data[V4L2_M2M_SRC].height;
735 dst_height = ctx->q_data[V4L2_M2M_DST].height;
736 src_stride = ctx->q_data[V4L2_M2M_SRC].bytesperline;
737 dst_stride = ctx->q_data[V4L2_M2M_DST].bytesperline;
738 src_fourcc = ctx->q_data[V4L2_M2M_SRC].fmt->fourcc;
739 dst_fourcc = ctx->q_data[V4L2_M2M_DST].fmt->fourcc;
740
741 p_in = vb2_dma_contig_plane_dma_addr(&in_vb->vb2_buf, 0);
742 p_out = vb2_dma_contig_plane_dma_addr(&out_vb->vb2_buf, 0);
743
744 if (!p_in || !p_out) {
745 v4l2_err(&dev->v4l2_dev,
746 "Acquiring DMA addresses of buffers failed\n");
747 return -EFAULT;
748 }
749
750 out_vb->sequence =
751 get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE)->sequence++;
752 in_vb->sequence = q_data->sequence++;
753 out_vb->vb2_buf.timestamp = in_vb->vb2_buf.timestamp;
754
755 if (in_vb->flags & V4L2_BUF_FLAG_TIMECODE)
756 out_vb->timecode = in_vb->timecode;
757 out_vb->field = in_vb->field;
758 out_vb->flags = in_vb->flags &
759 (V4L2_BUF_FLAG_TIMECODE |
760 V4L2_BUF_FLAG_KEYFRAME |
761 V4L2_BUF_FLAG_PFRAME |
762 V4L2_BUF_FLAG_BFRAME |
763 V4L2_BUF_FLAG_TSTAMP_SRC_MASK);
764
765 /* Rotation disabled, 8x8 block size */
766 ctrl = BF_PXP_CTRL_VFLIP0(!!(ctx->mode & MEM2MEM_VFLIP)) |
767 BF_PXP_CTRL_HFLIP0(!!(ctx->mode & MEM2MEM_HFLIP));
768 /* Always write alpha value as V4L2_CID_ALPHA_COMPONENT */
769 out_ctrl = BF_PXP_OUT_CTRL_ALPHA(ctx->alpha_component) |
770 BF_PXP_OUT_CTRL_ALPHA_OUTPUT(1) |
771 pxp_v4l2_pix_fmt_to_out_format(dst_fourcc);
772 out_buf = p_out;
773 switch (dst_fourcc) {
774 case V4L2_PIX_FMT_NV12:
775 case V4L2_PIX_FMT_NV21:
776 case V4L2_PIX_FMT_NV16:
777 case V4L2_PIX_FMT_NV61:
778 out_buf2 = out_buf + dst_stride * dst_height;
779 break;
780 default:
781 out_buf2 = 0;
782 }
783
784 out_pitch = BF_PXP_OUT_PITCH_PITCH(dst_stride);
785 out_lrc = BF_PXP_OUT_LRC_X(dst_width - 1) |
786 BF_PXP_OUT_LRC_Y(dst_height - 1);
787 /* PS covers whole output */
788 out_ps_ulc = BF_PXP_OUT_PS_ULC_X(0) | BF_PXP_OUT_PS_ULC_Y(0);
789 out_ps_lrc = BF_PXP_OUT_PS_LRC_X(dst_width - 1) |
790 BF_PXP_OUT_PS_LRC_Y(dst_height - 1);
791 /* no AS */
792 as_ulc = BF_PXP_OUT_AS_ULC_X(1) | BF_PXP_OUT_AS_ULC_Y(1);
793 as_lrc = BF_PXP_OUT_AS_LRC_X(0) | BF_PXP_OUT_AS_LRC_Y(0);
794
795 decx = (src_width <= dst_width) ? 0 : ilog2(src_width / dst_width);
796 decy = (src_height <= dst_height) ? 0 : ilog2(src_height / dst_height);
797 ps_ctrl = BF_PXP_PS_CTRL_DECX(decx) | BF_PXP_PS_CTRL_DECY(decy) |
798 pxp_v4l2_pix_fmt_to_ps_format(src_fourcc);
799 ps_buf = p_in;
800 y_size = src_stride * src_height;
801 switch (src_fourcc) {
802 case V4L2_PIX_FMT_YUV420:
803 ps_ubuf = ps_buf + y_size;
804 ps_vbuf = ps_ubuf + y_size / 4;
805 break;
806 case V4L2_PIX_FMT_YUV422P:
807 ps_ubuf = ps_buf + y_size;
808 ps_vbuf = ps_ubuf + y_size / 2;
809 break;
810 case V4L2_PIX_FMT_NV12:
811 case V4L2_PIX_FMT_NV21:
812 case V4L2_PIX_FMT_NV16:
813 case V4L2_PIX_FMT_NV61:
814 ps_ubuf = ps_buf + y_size;
815 ps_vbuf = 0;
816 break;
817 case V4L2_PIX_FMT_GREY:
818 case V4L2_PIX_FMT_Y4:
819 ps_ubuf = 0;
820 /* In grayscale mode, ps_vbuf contents are reused as CbCr */
821 ps_vbuf = 0x8080;
822 break;
823 default:
824 ps_ubuf = 0;
825 ps_vbuf = 0;
826 break;
827 }
828 ps_pitch = BF_PXP_PS_PITCH_PITCH(src_stride);
829 if (decx) {
830 xscale = (src_width >> decx) * 0x1000 / dst_width;
831 } else {
832 switch (src_fourcc) {
833 case V4L2_PIX_FMT_UYVY:
834 case V4L2_PIX_FMT_YUYV:
835 case V4L2_PIX_FMT_VYUY:
836 case V4L2_PIX_FMT_YVYU:
837 case V4L2_PIX_FMT_NV16:
838 case V4L2_PIX_FMT_NV12:
839 case V4L2_PIX_FMT_NV21:
840 case V4L2_PIX_FMT_NV61:
841 case V4L2_PIX_FMT_YUV422P:
842 case V4L2_PIX_FMT_YUV420:
843 /*
844 * This avoids sampling past the right edge for
845 * horizontally chroma subsampled formats.
846 */
847 xscale = (src_width - 2) * 0x1000 / (dst_width - 1);
848 break;
849 default:
850 xscale = (src_width - 1) * 0x1000 / (dst_width - 1);
851 break;
852 }
853 }
854 if (decy)
855 yscale = (src_height >> decy) * 0x1000 / dst_height;
856 else
857 yscale = (src_height - 1) * 0x1000 / (dst_height - 1);
858 ps_scale = BF_PXP_PS_SCALE_YSCALE(yscale) |
859 BF_PXP_PS_SCALE_XSCALE(xscale);
860 ps_offset = BF_PXP_PS_OFFSET_YOFFSET(0) | BF_PXP_PS_OFFSET_XOFFSET(0);
861
862 writel(ctrl, dev->mmio + HW_PXP_CTRL);
863 /* skip STAT */
864 writel(out_ctrl, dev->mmio + HW_PXP_OUT_CTRL);
865 writel(out_buf, dev->mmio + HW_PXP_OUT_BUF);
866 writel(out_buf2, dev->mmio + HW_PXP_OUT_BUF2);
867 writel(out_pitch, dev->mmio + HW_PXP_OUT_PITCH);
868 writel(out_lrc, dev->mmio + HW_PXP_OUT_LRC);
869 writel(out_ps_ulc, dev->mmio + HW_PXP_OUT_PS_ULC);
870 writel(out_ps_lrc, dev->mmio + HW_PXP_OUT_PS_LRC);
871 writel(as_ulc, dev->mmio + HW_PXP_OUT_AS_ULC);
872 writel(as_lrc, dev->mmio + HW_PXP_OUT_AS_LRC);
873 writel(ps_ctrl, dev->mmio + HW_PXP_PS_CTRL);
874 writel(ps_buf, dev->mmio + HW_PXP_PS_BUF);
875 writel(ps_ubuf, dev->mmio + HW_PXP_PS_UBUF);
876 writel(ps_vbuf, dev->mmio + HW_PXP_PS_VBUF);
877 writel(ps_pitch, dev->mmio + HW_PXP_PS_PITCH);
878 writel(0x00ffffff, dev->mmio + HW_PXP_PS_BACKGROUND_0);
879 writel(ps_scale, dev->mmio + HW_PXP_PS_SCALE);
880 writel(ps_offset, dev->mmio + HW_PXP_PS_OFFSET);
881 /* disable processed surface color keying */
882 writel(0x00ffffff, dev->mmio + HW_PXP_PS_CLRKEYLOW_0);
883 writel(0x00000000, dev->mmio + HW_PXP_PS_CLRKEYHIGH_0);
884
885 /* disable alpha surface color keying */
886 writel(0x00ffffff, dev->mmio + HW_PXP_AS_CLRKEYLOW_0);
887 writel(0x00000000, dev->mmio + HW_PXP_AS_CLRKEYHIGH_0);
888
889 /* setup CSC */
890 pxp_setup_csc(ctx);
891
892 /* bypass LUT */
893 writel(BM_PXP_LUT_CTRL_BYPASS, dev->mmio + HW_PXP_LUT_CTRL);
894
895 writel(BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(0)|
896 BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1)|
897 BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(0)|
898 BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(0)|
899 BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(0)|
900 BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(0)|
901 BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(1)|
902 BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(0)|
903 BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(0)|
904 BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(0)|
905 BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(0)|
906 BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(0)|
907 BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(0)|
908 BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(0)|
909 BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(0)|
910 BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(0),
911 dev->mmio + HW_PXP_DATA_PATH_CTRL0);
912 writel(BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1) |
913 BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(1),
914 dev->mmio + HW_PXP_DATA_PATH_CTRL1);
915
916 writel(0xffff, dev->mmio + HW_PXP_IRQ_MASK);
917
918 /* ungate, enable PS/AS/OUT and PXP operation */
919 writel(BM_PXP_CTRL_IRQ_ENABLE, dev->mmio + HW_PXP_CTRL_SET);
920 writel(BM_PXP_CTRL_ENABLE | BM_PXP_CTRL_ENABLE_CSC2 |
921 BM_PXP_CTRL_ENABLE_LUT | BM_PXP_CTRL_ENABLE_ROTATE0 |
922 BM_PXP_CTRL_ENABLE_PS_AS_OUT, dev->mmio + HW_PXP_CTRL_SET);
923
924 return 0;
925 }
926
927 static void pxp_job_finish(struct pxp_dev *dev)
928 {
929 struct pxp_ctx *curr_ctx;
930 struct vb2_v4l2_buffer *src_vb, *dst_vb;
931 unsigned long flags;
932
933 curr_ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
934
935 if (curr_ctx == NULL) {
936 pr_err("Instance released before the end of transaction\n");
937 return;
938 }
939
940 src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
941 dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
942
943 spin_lock_irqsave(&dev->irqlock, flags);
944 v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
945 v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
946 spin_unlock_irqrestore(&dev->irqlock, flags);
947
948 dprintk(curr_ctx->dev, "Finishing transaction\n");
949 v4l2_m2m_job_finish(dev->m2m_dev, curr_ctx->fh.m2m_ctx);
950 }
951
952 /*
953 * mem2mem callbacks
954 */
955 static void pxp_device_run(void *priv)
956 {
957 struct pxp_ctx *ctx = priv;
958 struct vb2_v4l2_buffer *src_buf, *dst_buf;
959
960 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
961 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
962
963 pxp_start(ctx, src_buf, dst_buf);
964 }
965
966 static int pxp_job_ready(void *priv)
967 {
968 struct pxp_ctx *ctx = priv;
969
970 if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) < 1 ||
971 v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) < 1) {
972 dprintk(ctx->dev, "Not enough buffers available\n");
973 return 0;
974 }
975
976 return 1;
977 }
978
979 static void pxp_job_abort(void *priv)
980 {
981 struct pxp_ctx *ctx = priv;
982
983 /* Will cancel the transaction in the next interrupt handler */
984 ctx->aborting = 1;
985 }
986
987 /*
988 * interrupt handler
989 */
990 static irqreturn_t pxp_irq_handler(int irq, void *dev_id)
991 {
992 struct pxp_dev *dev = dev_id;
993 u32 stat;
994
995 stat = readl(dev->mmio + HW_PXP_STAT);
996
997 if (stat & BM_PXP_STAT_IRQ0) {
998 /* we expect x = 0, y = height, irq0 = 1 */
999 if (stat & ~(BM_PXP_STAT_BLOCKX | BM_PXP_STAT_BLOCKY |
1000 BM_PXP_STAT_IRQ0))
1001 dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
1002 writel(BM_PXP_STAT_IRQ0, dev->mmio + HW_PXP_STAT_CLR);
1003
1004 pxp_job_finish(dev);
1005 } else {
1006 u32 irq = readl(dev->mmio + HW_PXP_IRQ);
1007
1008 dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
1009 dprintk(dev, "%s: irq = 0x%08x\n", __func__, irq);
1010
1011 writel(irq, dev->mmio + HW_PXP_IRQ_CLR);
1012 }
1013
1014 return IRQ_HANDLED;
1015 }
1016
1017 /*
1018 * video ioctls
1019 */
1020 static int pxp_querycap(struct file *file, void *priv,
1021 struct v4l2_capability *cap)
1022 {
1023 strlcpy(cap->driver, MEM2MEM_NAME, sizeof(cap->driver));
1024 strlcpy(cap->card, MEM2MEM_NAME, sizeof(cap->card));
1025 snprintf(cap->bus_info, sizeof(cap->bus_info),
1026 "platform:%s", MEM2MEM_NAME);
1027 return 0;
1028 }
1029
1030 static int pxp_enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1031 {
1032 int i, num;
1033 struct pxp_fmt *fmt;
1034
1035 num = 0;
1036
1037 for (i = 0; i < NUM_FORMATS; ++i) {
1038 if (formats[i].types & type) {
1039 /* index-th format of type type found ? */
1040 if (num == f->index)
1041 break;
1042 /*
1043 * Correct type but haven't reached our index yet,
1044 * just increment per-type index
1045 */
1046 ++num;
1047 }
1048 }
1049
1050 if (i < NUM_FORMATS) {
1051 /* Format found */
1052 fmt = &formats[i];
1053 f->pixelformat = fmt->fourcc;
1054 return 0;
1055 }
1056
1057 /* Format not found */
1058 return -EINVAL;
1059 }
1060
1061 static int pxp_enum_fmt_vid_cap(struct file *file, void *priv,
1062 struct v4l2_fmtdesc *f)
1063 {
1064 return pxp_enum_fmt(f, MEM2MEM_CAPTURE);
1065 }
1066
1067 static int pxp_enum_fmt_vid_out(struct file *file, void *priv,
1068 struct v4l2_fmtdesc *f)
1069 {
1070 return pxp_enum_fmt(f, MEM2MEM_OUTPUT);
1071 }
1072
1073 static int pxp_g_fmt(struct pxp_ctx *ctx, struct v4l2_format *f)
1074 {
1075 struct vb2_queue *vq;
1076 struct pxp_q_data *q_data;
1077
1078 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1079 if (!vq)
1080 return -EINVAL;
1081
1082 q_data = get_q_data(ctx, f->type);
1083
1084 f->fmt.pix.width = q_data->width;
1085 f->fmt.pix.height = q_data->height;
1086 f->fmt.pix.field = V4L2_FIELD_NONE;
1087 f->fmt.pix.pixelformat = q_data->fmt->fourcc;
1088 f->fmt.pix.bytesperline = q_data->bytesperline;
1089 f->fmt.pix.sizeimage = q_data->sizeimage;
1090 f->fmt.pix.colorspace = ctx->colorspace;
1091 f->fmt.pix.xfer_func = ctx->xfer_func;
1092 f->fmt.pix.ycbcr_enc = q_data->ycbcr_enc;
1093 f->fmt.pix.quantization = q_data->quant;
1094
1095 return 0;
1096 }
1097
1098 static int pxp_g_fmt_vid_out(struct file *file, void *priv,
1099 struct v4l2_format *f)
1100 {
1101 return pxp_g_fmt(file2ctx(file), f);
1102 }
1103
1104 static int pxp_g_fmt_vid_cap(struct file *file, void *priv,
1105 struct v4l2_format *f)
1106 {
1107 return pxp_g_fmt(file2ctx(file), f);
1108 }
1109
1110 static inline u32 pxp_bytesperline(struct pxp_fmt *fmt, u32 width)
1111 {
1112 switch (fmt->fourcc) {
1113 case V4L2_PIX_FMT_YUV420:
1114 case V4L2_PIX_FMT_NV12:
1115 case V4L2_PIX_FMT_NV21:
1116 case V4L2_PIX_FMT_YUV422P:
1117 case V4L2_PIX_FMT_NV16:
1118 case V4L2_PIX_FMT_NV61:
1119 return width;
1120 default:
1121 return (width * fmt->depth) >> 3;
1122 }
1123 }
1124
1125 static inline u32 pxp_sizeimage(struct pxp_fmt *fmt, u32 width, u32 height)
1126 {
1127 return (fmt->depth * width * height) >> 3;
1128 }
1129
1130 static int pxp_try_fmt(struct v4l2_format *f, struct pxp_fmt *fmt)
1131 {
1132 v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W, ALIGN_W,
1133 &f->fmt.pix.height, MIN_H, MAX_H, ALIGN_H, 0);
1134
1135 f->fmt.pix.bytesperline = pxp_bytesperline(fmt, f->fmt.pix.width);
1136 f->fmt.pix.sizeimage = pxp_sizeimage(fmt, f->fmt.pix.width,
1137 f->fmt.pix.height);
1138 f->fmt.pix.field = V4L2_FIELD_NONE;
1139
1140 return 0;
1141 }
1142
1143 static void
1144 pxp_fixup_colorimetry_cap(struct pxp_ctx *ctx, u32 dst_fourcc,
1145 enum v4l2_ycbcr_encoding *ycbcr_enc,
1146 enum v4l2_quantization *quantization)
1147 {
1148 bool dst_is_yuv = pxp_v4l2_pix_fmt_is_yuv(dst_fourcc);
1149
1150 if (pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) ==
1151 dst_is_yuv) {
1152 /*
1153 * There is no support for conversion between different YCbCr
1154 * encodings or between RGB limited and full range.
1155 */
1156 *ycbcr_enc = ctx->q_data[V4L2_M2M_SRC].ycbcr_enc;
1157 *quantization = ctx->q_data[V4L2_M2M_SRC].quant;
1158 } else {
1159 *ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(ctx->colorspace);
1160 *quantization = V4L2_MAP_QUANTIZATION_DEFAULT(!dst_is_yuv,
1161 ctx->colorspace,
1162 *ycbcr_enc);
1163 }
1164 }
1165
1166 static int pxp_try_fmt_vid_cap(struct file *file, void *priv,
1167 struct v4l2_format *f)
1168 {
1169 struct pxp_fmt *fmt;
1170 struct pxp_ctx *ctx = file2ctx(file);
1171
1172 fmt = find_format(f);
1173 if (!fmt) {
1174 f->fmt.pix.pixelformat = formats[0].fourcc;
1175 fmt = find_format(f);
1176 }
1177 if (!(fmt->types & MEM2MEM_CAPTURE)) {
1178 v4l2_err(&ctx->dev->v4l2_dev,
1179 "Fourcc format (0x%08x) invalid.\n",
1180 f->fmt.pix.pixelformat);
1181 return -EINVAL;
1182 }
1183
1184 f->fmt.pix.colorspace = ctx->colorspace;
1185 f->fmt.pix.xfer_func = ctx->xfer_func;
1186
1187 pxp_fixup_colorimetry_cap(ctx, fmt->fourcc,
1188 &f->fmt.pix.ycbcr_enc,
1189 &f->fmt.pix.quantization);
1190
1191 return pxp_try_fmt(f, fmt);
1192 }
1193
1194 static int pxp_try_fmt_vid_out(struct file *file, void *priv,
1195 struct v4l2_format *f)
1196 {
1197 struct pxp_fmt *fmt;
1198 struct pxp_ctx *ctx = file2ctx(file);
1199
1200 fmt = find_format(f);
1201 if (!fmt) {
1202 f->fmt.pix.pixelformat = formats[0].fourcc;
1203 fmt = find_format(f);
1204 }
1205 if (!(fmt->types & MEM2MEM_OUTPUT)) {
1206 v4l2_err(&ctx->dev->v4l2_dev,
1207 "Fourcc format (0x%08x) invalid.\n",
1208 f->fmt.pix.pixelformat);
1209 return -EINVAL;
1210 }
1211
1212 if (!f->fmt.pix.colorspace)
1213 f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
1214
1215 return pxp_try_fmt(f, fmt);
1216 }
1217
1218 static int pxp_s_fmt(struct pxp_ctx *ctx, struct v4l2_format *f)
1219 {
1220 struct pxp_q_data *q_data;
1221 struct vb2_queue *vq;
1222
1223 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1224 if (!vq)
1225 return -EINVAL;
1226
1227 q_data = get_q_data(ctx, f->type);
1228 if (!q_data)
1229 return -EINVAL;
1230
1231 if (vb2_is_busy(vq)) {
1232 v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
1233 return -EBUSY;
1234 }
1235
1236 q_data->fmt = find_format(f);
1237 q_data->width = f->fmt.pix.width;
1238 q_data->height = f->fmt.pix.height;
1239 q_data->bytesperline = f->fmt.pix.bytesperline;
1240 q_data->sizeimage = f->fmt.pix.sizeimage;
1241
1242 dprintk(ctx->dev,
1243 "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
1244 f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
1245
1246 return 0;
1247 }
1248
1249 static int pxp_s_fmt_vid_cap(struct file *file, void *priv,
1250 struct v4l2_format *f)
1251 {
1252 struct pxp_ctx *ctx = file2ctx(file);
1253 int ret;
1254
1255 ret = pxp_try_fmt_vid_cap(file, priv, f);
1256 if (ret)
1257 return ret;
1258
1259 ret = pxp_s_fmt(file2ctx(file), f);
1260 if (ret)
1261 return ret;
1262
1263 ctx->q_data[V4L2_M2M_DST].ycbcr_enc = f->fmt.pix.ycbcr_enc;
1264 ctx->q_data[V4L2_M2M_DST].quant = f->fmt.pix.quantization;
1265
1266 return 0;
1267 }
1268
1269 static int pxp_s_fmt_vid_out(struct file *file, void *priv,
1270 struct v4l2_format *f)
1271 {
1272 struct pxp_ctx *ctx = file2ctx(file);
1273 int ret;
1274
1275 ret = pxp_try_fmt_vid_out(file, priv, f);
1276 if (ret)
1277 return ret;
1278
1279 ret = pxp_s_fmt(file2ctx(file), f);
1280 if (ret)
1281 return ret;
1282
1283 ctx->colorspace = f->fmt.pix.colorspace;
1284 ctx->xfer_func = f->fmt.pix.xfer_func;
1285 ctx->q_data[V4L2_M2M_SRC].ycbcr_enc = f->fmt.pix.ycbcr_enc;
1286 ctx->q_data[V4L2_M2M_SRC].quant = f->fmt.pix.quantization;
1287
1288 pxp_fixup_colorimetry_cap(ctx, ctx->q_data[V4L2_M2M_DST].fmt->fourcc,
1289 &ctx->q_data[V4L2_M2M_DST].ycbcr_enc,
1290 &ctx->q_data[V4L2_M2M_DST].quant);
1291
1292 return 0;
1293 }
1294
1295 static int pxp_s_ctrl(struct v4l2_ctrl *ctrl)
1296 {
1297 struct pxp_ctx *ctx =
1298 container_of(ctrl->handler, struct pxp_ctx, hdl);
1299
1300 switch (ctrl->id) {
1301 case V4L2_CID_HFLIP:
1302 if (ctrl->val)
1303 ctx->mode |= MEM2MEM_HFLIP;
1304 else
1305 ctx->mode &= ~MEM2MEM_HFLIP;
1306 break;
1307
1308 case V4L2_CID_VFLIP:
1309 if (ctrl->val)
1310 ctx->mode |= MEM2MEM_VFLIP;
1311 else
1312 ctx->mode &= ~MEM2MEM_VFLIP;
1313 break;
1314
1315 case V4L2_CID_ALPHA_COMPONENT:
1316 ctx->alpha_component = ctrl->val;
1317 break;
1318
1319 default:
1320 v4l2_err(&ctx->dev->v4l2_dev, "Invalid control\n");
1321 return -EINVAL;
1322 }
1323
1324 return 0;
1325 }
1326
1327 static const struct v4l2_ctrl_ops pxp_ctrl_ops = {
1328 .s_ctrl = pxp_s_ctrl,
1329 };
1330
1331 static const struct v4l2_ioctl_ops pxp_ioctl_ops = {
1332 .vidioc_querycap = pxp_querycap,
1333
1334 .vidioc_enum_fmt_vid_cap = pxp_enum_fmt_vid_cap,
1335 .vidioc_g_fmt_vid_cap = pxp_g_fmt_vid_cap,
1336 .vidioc_try_fmt_vid_cap = pxp_try_fmt_vid_cap,
1337 .vidioc_s_fmt_vid_cap = pxp_s_fmt_vid_cap,
1338
1339 .vidioc_enum_fmt_vid_out = pxp_enum_fmt_vid_out,
1340 .vidioc_g_fmt_vid_out = pxp_g_fmt_vid_out,
1341 .vidioc_try_fmt_vid_out = pxp_try_fmt_vid_out,
1342 .vidioc_s_fmt_vid_out = pxp_s_fmt_vid_out,
1343
1344 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
1345 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
1346 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
1347 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
1348 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
1349 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
1350 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
1351
1352 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
1353 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
1354
1355 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1356 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1357 };
1358
1359 /*
1360 * Queue operations
1361 */
1362 static int pxp_queue_setup(struct vb2_queue *vq,
1363 unsigned int *nbuffers, unsigned int *nplanes,
1364 unsigned int sizes[], struct device *alloc_devs[])
1365 {
1366 struct pxp_ctx *ctx = vb2_get_drv_priv(vq);
1367 struct pxp_q_data *q_data;
1368 unsigned int size, count = *nbuffers;
1369
1370 q_data = get_q_data(ctx, vq->type);
1371
1372 size = q_data->sizeimage;
1373
1374 *nbuffers = count;
1375
1376 if (*nplanes)
1377 return sizes[0] < size ? -EINVAL : 0;
1378
1379 *nplanes = 1;
1380 sizes[0] = size;
1381
1382 dprintk(ctx->dev, "get %d buffer(s) of size %d each.\n", count, size);
1383
1384 return 0;
1385 }
1386
1387 static int pxp_buf_prepare(struct vb2_buffer *vb)
1388 {
1389 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1390 struct pxp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1391 struct pxp_dev *dev = ctx->dev;
1392 struct pxp_q_data *q_data;
1393
1394 dprintk(ctx->dev, "type: %d\n", vb->vb2_queue->type);
1395
1396 q_data = get_q_data(ctx, vb->vb2_queue->type);
1397 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
1398 if (vbuf->field == V4L2_FIELD_ANY)
1399 vbuf->field = V4L2_FIELD_NONE;
1400 if (vbuf->field != V4L2_FIELD_NONE) {
1401 dprintk(dev, "%s field isn't supported\n", __func__);
1402 return -EINVAL;
1403 }
1404 }
1405
1406 if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
1407 dprintk(dev, "%s data will not fit into plane (%lu < %lu)\n",
1408 __func__, vb2_plane_size(vb, 0),
1409 (long)q_data->sizeimage);
1410 return -EINVAL;
1411 }
1412
1413 vb2_set_plane_payload(vb, 0, q_data->sizeimage);
1414
1415 return 0;
1416 }
1417
1418 static void pxp_buf_queue(struct vb2_buffer *vb)
1419 {
1420 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1421 struct pxp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1422
1423 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
1424 }
1425
1426 static int pxp_start_streaming(struct vb2_queue *q, unsigned int count)
1427 {
1428 struct pxp_ctx *ctx = vb2_get_drv_priv(q);
1429 struct pxp_q_data *q_data = get_q_data(ctx, q->type);
1430
1431 q_data->sequence = 0;
1432 return 0;
1433 }
1434
1435 static void pxp_stop_streaming(struct vb2_queue *q)
1436 {
1437 struct pxp_ctx *ctx = vb2_get_drv_priv(q);
1438 struct vb2_v4l2_buffer *vbuf;
1439 unsigned long flags;
1440
1441 for (;;) {
1442 if (V4L2_TYPE_IS_OUTPUT(q->type))
1443 vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1444 else
1445 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1446 if (vbuf == NULL)
1447 return;
1448 spin_lock_irqsave(&ctx->dev->irqlock, flags);
1449 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
1450 spin_unlock_irqrestore(&ctx->dev->irqlock, flags);
1451 }
1452 }
1453
1454 static const struct vb2_ops pxp_qops = {
1455 .queue_setup = pxp_queue_setup,
1456 .buf_prepare = pxp_buf_prepare,
1457 .buf_queue = pxp_buf_queue,
1458 .start_streaming = pxp_start_streaming,
1459 .stop_streaming = pxp_stop_streaming,
1460 .wait_prepare = vb2_ops_wait_prepare,
1461 .wait_finish = vb2_ops_wait_finish,
1462 };
1463
1464 static int queue_init(void *priv, struct vb2_queue *src_vq,
1465 struct vb2_queue *dst_vq)
1466 {
1467 struct pxp_ctx *ctx = priv;
1468 int ret;
1469
1470 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1471 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1472 src_vq->drv_priv = ctx;
1473 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1474 src_vq->ops = &pxp_qops;
1475 src_vq->mem_ops = &vb2_dma_contig_memops;
1476 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1477 src_vq->lock = &ctx->dev->dev_mutex;
1478 src_vq->dev = ctx->dev->v4l2_dev.dev;
1479
1480 ret = vb2_queue_init(src_vq);
1481 if (ret)
1482 return ret;
1483
1484 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1485 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1486 dst_vq->drv_priv = ctx;
1487 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1488 dst_vq->ops = &pxp_qops;
1489 dst_vq->mem_ops = &vb2_dma_contig_memops;
1490 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1491 dst_vq->lock = &ctx->dev->dev_mutex;
1492 dst_vq->dev = ctx->dev->v4l2_dev.dev;
1493
1494 return vb2_queue_init(dst_vq);
1495 }
1496
1497 /*
1498 * File operations
1499 */
1500 static int pxp_open(struct file *file)
1501 {
1502 struct pxp_dev *dev = video_drvdata(file);
1503 struct pxp_ctx *ctx = NULL;
1504 struct v4l2_ctrl_handler *hdl;
1505 int rc = 0;
1506
1507 if (mutex_lock_interruptible(&dev->dev_mutex))
1508 return -ERESTARTSYS;
1509 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1510 if (!ctx) {
1511 rc = -ENOMEM;
1512 goto open_unlock;
1513 }
1514
1515 v4l2_fh_init(&ctx->fh, video_devdata(file));
1516 file->private_data = &ctx->fh;
1517 ctx->dev = dev;
1518 hdl = &ctx->hdl;
1519 v4l2_ctrl_handler_init(hdl, 4);
1520 v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1521 v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1522 v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_ALPHA_COMPONENT,
1523 0, 255, 1, 255);
1524 if (hdl->error) {
1525 rc = hdl->error;
1526 v4l2_ctrl_handler_free(hdl);
1527 kfree(ctx);
1528 goto open_unlock;
1529 }
1530 ctx->fh.ctrl_handler = hdl;
1531 v4l2_ctrl_handler_setup(hdl);
1532
1533 ctx->q_data[V4L2_M2M_SRC].fmt = &formats[0];
1534 ctx->q_data[V4L2_M2M_SRC].width = 640;
1535 ctx->q_data[V4L2_M2M_SRC].height = 480;
1536 ctx->q_data[V4L2_M2M_SRC].bytesperline =
1537 pxp_bytesperline(&formats[0], 640);
1538 ctx->q_data[V4L2_M2M_SRC].sizeimage =
1539 pxp_sizeimage(&formats[0], 640, 480);
1540 ctx->q_data[V4L2_M2M_DST] = ctx->q_data[V4L2_M2M_SRC];
1541 ctx->colorspace = V4L2_COLORSPACE_REC709;
1542
1543 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
1544
1545 if (IS_ERR(ctx->fh.m2m_ctx)) {
1546 rc = PTR_ERR(ctx->fh.m2m_ctx);
1547
1548 v4l2_ctrl_handler_free(hdl);
1549 v4l2_fh_exit(&ctx->fh);
1550 kfree(ctx);
1551 goto open_unlock;
1552 }
1553
1554 v4l2_fh_add(&ctx->fh);
1555 atomic_inc(&dev->num_inst);
1556
1557 dprintk(dev, "Created instance: %p, m2m_ctx: %p\n",
1558 ctx, ctx->fh.m2m_ctx);
1559
1560 open_unlock:
1561 mutex_unlock(&dev->dev_mutex);
1562 return rc;
1563 }
1564
1565 static int pxp_release(struct file *file)
1566 {
1567 struct pxp_dev *dev = video_drvdata(file);
1568 struct pxp_ctx *ctx = file2ctx(file);
1569
1570 dprintk(dev, "Releasing instance %p\n", ctx);
1571
1572 v4l2_fh_del(&ctx->fh);
1573 v4l2_fh_exit(&ctx->fh);
1574 v4l2_ctrl_handler_free(&ctx->hdl);
1575 mutex_lock(&dev->dev_mutex);
1576 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
1577 mutex_unlock(&dev->dev_mutex);
1578 kfree(ctx);
1579
1580 atomic_dec(&dev->num_inst);
1581
1582 return 0;
1583 }
1584
1585 static const struct v4l2_file_operations pxp_fops = {
1586 .owner = THIS_MODULE,
1587 .open = pxp_open,
1588 .release = pxp_release,
1589 .poll = v4l2_m2m_fop_poll,
1590 .unlocked_ioctl = video_ioctl2,
1591 .mmap = v4l2_m2m_fop_mmap,
1592 };
1593
1594 static const struct video_device pxp_videodev = {
1595 .name = MEM2MEM_NAME,
1596 .vfl_dir = VFL_DIR_M2M,
1597 .fops = &pxp_fops,
1598 .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
1599 .ioctl_ops = &pxp_ioctl_ops,
1600 .minor = -1,
1601 .release = video_device_release_empty,
1602 };
1603
1604 static const struct v4l2_m2m_ops m2m_ops = {
1605 .device_run = pxp_device_run,
1606 .job_ready = pxp_job_ready,
1607 .job_abort = pxp_job_abort,
1608 };
1609
1610 static void pxp_soft_reset(struct pxp_dev *dev)
1611 {
1612 int ret;
1613 u32 val;
1614
1615 writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR);
1616 writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR);
1617
1618 writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_SET);
1619
1620 ret = readl_poll_timeout(dev->mmio + HW_PXP_CTRL, val,
1621 val & BM_PXP_CTRL_CLKGATE, 0, 100);
1622 if (ret < 0)
1623 pr_err("PXP reset timeout\n");
1624
1625 writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR);
1626 writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR);
1627 }
1628
1629 static int pxp_probe(struct platform_device *pdev)
1630 {
1631 struct pxp_dev *dev;
1632 struct resource *res;
1633 struct video_device *vfd;
1634 int irq;
1635 int ret;
1636
1637 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1638 if (!dev)
1639 return -ENOMEM;
1640
1641 dev->clk = devm_clk_get(&pdev->dev, "axi");
1642 if (IS_ERR(dev->clk)) {
1643 ret = PTR_ERR(dev->clk);
1644 dev_err(&pdev->dev, "Failed to get clk: %d\n", ret);
1645 return ret;
1646 }
1647
1648 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1649 dev->mmio = devm_ioremap_resource(&pdev->dev, res);
1650 if (IS_ERR(dev->mmio)) {
1651 ret = PTR_ERR(dev->mmio);
1652 dev_err(&pdev->dev, "Failed to map register space: %d\n", ret);
1653 return ret;
1654 }
1655
1656 irq = platform_get_irq(pdev, 0);
1657 if (irq < 0) {
1658 dev_err(&pdev->dev, "Failed to get irq resource: %d\n", irq);
1659 return irq;
1660 }
1661
1662 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, pxp_irq_handler,
1663 IRQF_ONESHOT, dev_name(&pdev->dev), dev);
1664 if (ret < 0) {
1665 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
1666 return ret;
1667 }
1668
1669 clk_prepare_enable(dev->clk);
1670 pxp_soft_reset(dev);
1671
1672 spin_lock_init(&dev->irqlock);
1673
1674 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1675 if (ret)
1676 goto err_clk;
1677
1678 atomic_set(&dev->num_inst, 0);
1679 mutex_init(&dev->dev_mutex);
1680
1681 dev->vfd = pxp_videodev;
1682 vfd = &dev->vfd;
1683 vfd->lock = &dev->dev_mutex;
1684 vfd->v4l2_dev = &dev->v4l2_dev;
1685
1686 video_set_drvdata(vfd, dev);
1687 snprintf(vfd->name, sizeof(vfd->name), "%s", pxp_videodev.name);
1688 v4l2_info(&dev->v4l2_dev,
1689 "Device registered as /dev/video%d\n", vfd->num);
1690
1691 platform_set_drvdata(pdev, dev);
1692
1693 dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
1694 if (IS_ERR(dev->m2m_dev)) {
1695 v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
1696 ret = PTR_ERR(dev->m2m_dev);
1697 goto err_v4l2;
1698 }
1699
1700 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1701 if (ret) {
1702 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1703 goto err_m2m;
1704 }
1705
1706 return 0;
1707
1708 err_m2m:
1709 v4l2_m2m_release(dev->m2m_dev);
1710 err_v4l2:
1711 v4l2_device_unregister(&dev->v4l2_dev);
1712 err_clk:
1713 clk_disable_unprepare(dev->clk);
1714
1715 return ret;
1716 }
1717
1718 static int pxp_remove(struct platform_device *pdev)
1719 {
1720 struct pxp_dev *dev = platform_get_drvdata(pdev);
1721
1722 writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_SET);
1723 writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_SET);
1724
1725 clk_disable_unprepare(dev->clk);
1726
1727 v4l2_info(&dev->v4l2_dev, "Removing " MEM2MEM_NAME);
1728 video_unregister_device(&dev->vfd);
1729 v4l2_m2m_release(dev->m2m_dev);
1730 v4l2_device_unregister(&dev->v4l2_dev);
1731
1732 return 0;
1733 }
1734
1735 static const struct of_device_id pxp_dt_ids[] = {
1736 { .compatible = "fsl,imx6ull-pxp", .data = NULL },
1737 { },
1738 };
1739 MODULE_DEVICE_TABLE(of, pxp_dt_ids);
1740
1741 static struct platform_driver pxp_driver = {
1742 .probe = pxp_probe,
1743 .remove = pxp_remove,
1744 .driver = {
1745 .name = MEM2MEM_NAME,
1746 .of_match_table = of_match_ptr(pxp_dt_ids),
1747 },
1748 };
1749
1750 module_platform_driver(pxp_driver);
1751
1752 MODULE_DESCRIPTION("i.MX PXP mem2mem scaler/CSC/rotator");
1753 MODULE_AUTHOR("Philipp Zabel <kernel@pengutronix.de>");
1754 MODULE_LICENSE("GPL");
Linux with added FPC-III support