drivers/media/rc/fintek-cir.c

   1 /*
   2  * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
   3  *
   4  * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
   5  *
   6  * Special thanks to Fintek for providing hardware and spec sheets.
   7  * This driver is based upon the nuvoton, ite and ene drivers for
   8  * similar hardware.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of the
  13  * License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/pnp.h>
  26 #include <linux/io.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/sched.h>
  29 #include <linux/slab.h>
  30 #include <media/rc-core.h>
  31
  32 #include "fintek-cir.h"
  33
  34 /* write val to config reg */
  35 static inline void fintek_cr_write(struct fintek_dev *fintek, u8 val, u8 reg)
  36 {
  37         fit_dbg("%s: reg 0x%02x, val 0x%02x  (ip/dp: %02x/%02x)",
  38                 __func__, reg, val, fintek->cr_ip, fintek->cr_dp);
  39         outb(reg, fintek->cr_ip);
  40         outb(val, fintek->cr_dp);
  41 }
  42
  43 /* read val from config reg */
  44 static inline u8 fintek_cr_read(struct fintek_dev *fintek, u8 reg)
  45 {
  46         u8 val;
  47
  48         outb(reg, fintek->cr_ip);
  49         val = inb(fintek->cr_dp);
  50
  51         fit_dbg("%s: reg 0x%02x, val 0x%02x  (ip/dp: %02x/%02x)",
  52                 __func__, reg, val, fintek->cr_ip, fintek->cr_dp);
  53         return val;
  54 }
  55
  56 /* update config register bit without changing other bits */
  57 static inline void fintek_set_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
  58 {
  59         u8 tmp = fintek_cr_read(fintek, reg) | val;
  60         fintek_cr_write(fintek, tmp, reg);
  61 }
  62
  63 /* clear config register bit without changing other bits */
  64 static inline void fintek_clear_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg)
  65 {
  66         u8 tmp = fintek_cr_read(fintek, reg) & ~val;
  67         fintek_cr_write(fintek, tmp, reg);
  68 }
  69
  70 /* enter config mode */
  71 static inline void fintek_config_mode_enable(struct fintek_dev *fintek)
  72 {
  73         /* Enabling Config Mode explicitly requires writing 2x */
  74         outb(CONFIG_REG_ENABLE, fintek->cr_ip);
  75         outb(CONFIG_REG_ENABLE, fintek->cr_ip);
  76 }
  77
  78 /* exit config mode */
  79 static inline void fintek_config_mode_disable(struct fintek_dev *fintek)
  80 {
  81         outb(CONFIG_REG_DISABLE, fintek->cr_ip);
  82 }
  83
  84 /*
  85  * When you want to address a specific logical device, write its logical
  86  * device number to GCR_LOGICAL_DEV_NO
  87  */
  88 static inline void fintek_select_logical_dev(struct fintek_dev *fintek, u8 ldev)
  89 {
  90         fintek_cr_write(fintek, ldev, GCR_LOGICAL_DEV_NO);
  91 }
  92
  93 /* write val to cir config register */
  94 static inline void fintek_cir_reg_write(struct fintek_dev *fintek, u8 val, u8 offset)
  95 {
  96         outb(val, fintek->cir_addr + offset);
  97 }
  98
  99 /* read val from cir config register */
 100 static u8 fintek_cir_reg_read(struct fintek_dev *fintek, u8 offset)
 101 {
 102         return inb(fintek->cir_addr + offset);
 103 }
 104
 105 /* dump current cir register contents */
 106 static void cir_dump_regs(struct fintek_dev *fintek)
 107 {
 108         fintek_config_mode_enable(fintek);
 109         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
 110
 111         pr_info("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME);
 112         pr_info(" * CR CIR BASE ADDR: 0x%x\n",
 113                 (fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) |
 114                 fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO));
 115         pr_info(" * CR CIR IRQ NUM:   0x%x\n",
 116                 fintek_cr_read(fintek, CIR_CR_IRQ_SEL));
 117
 118         fintek_config_mode_disable(fintek);
 119
 120         pr_info("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME);
 121         pr_info(" * STATUS:     0x%x\n",
 122                 fintek_cir_reg_read(fintek, CIR_STATUS));
 123         pr_info(" * CONTROL:    0x%x\n",
 124                 fintek_cir_reg_read(fintek, CIR_CONTROL));
 125         pr_info(" * RX_DATA:    0x%x\n",
 126                 fintek_cir_reg_read(fintek, CIR_RX_DATA));
 127         pr_info(" * TX_CONTROL: 0x%x\n",
 128                 fintek_cir_reg_read(fintek, CIR_TX_CONTROL));
 129         pr_info(" * TX_DATA:    0x%x\n",
 130                 fintek_cir_reg_read(fintek, CIR_TX_DATA));
 131 }
 132
 133 /* detect hardware features */
 134 static int fintek_hw_detect(struct fintek_dev *fintek)
 135 {
 136         unsigned long flags;
 137         u8 chip_major, chip_minor;
 138         u8 vendor_major, vendor_minor;
 139         u8 portsel, ir_class;
 140         u16 vendor, chip;
 141
 142         fintek_config_mode_enable(fintek);
 143
 144         /* Check if we're using config port 0x4e or 0x2e */
 145         portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
 146         if (portsel == 0xff) {
 147                 fit_pr(KERN_INFO, "first portsel read was bunk, trying alt");
 148                 fintek_config_mode_disable(fintek);
 149                 fintek->cr_ip = CR_INDEX_PORT2;
 150                 fintek->cr_dp = CR_DATA_PORT2;
 151                 fintek_config_mode_enable(fintek);
 152                 portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL);
 153         }
 154         fit_dbg("portsel reg: 0x%02x", portsel);
 155
 156         ir_class = fintek_cir_reg_read(fintek, CIR_CR_CLASS);
 157         fit_dbg("ir_class reg: 0x%02x", ir_class);
 158
 159         switch (ir_class) {
 160         case CLASS_RX_2TX:
 161         case CLASS_RX_1TX:
 162                 fintek->hw_tx_capable = true;
 163                 break;
 164         case CLASS_RX_ONLY:
 165         default:
 166                 fintek->hw_tx_capable = false;
 167                 break;
 168         }
 169
 170         chip_major = fintek_cr_read(fintek, GCR_CHIP_ID_HI);
 171         chip_minor = fintek_cr_read(fintek, GCR_CHIP_ID_LO);
 172         chip  = chip_major << 8 | chip_minor;
 173
 174         vendor_major = fintek_cr_read(fintek, GCR_VENDOR_ID_HI);
 175         vendor_minor = fintek_cr_read(fintek, GCR_VENDOR_ID_LO);
 176         vendor = vendor_major << 8 | vendor_minor;
 177
 178         if (vendor != VENDOR_ID_FINTEK)
 179                 fit_pr(KERN_WARNING, "Unknown vendor ID: 0x%04x", vendor);
 180         else
 181                 fit_dbg("Read Fintek vendor ID from chip");
 182
 183         fintek_config_mode_disable(fintek);
 184
 185         spin_lock_irqsave(&fintek->fintek_lock, flags);
 186         fintek->chip_major  = chip_major;
 187         fintek->chip_minor  = chip_minor;
 188         fintek->chip_vendor = vendor;
 189
 190         /*
 191          * Newer reviews of this chipset uses port 8 instead of 5
 192          */
 193         if ((chip != 0x0408) && (chip != 0x0804))
 194                 fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV2;
 195         else
 196                 fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV1;
 197
 198         spin_unlock_irqrestore(&fintek->fintek_lock, flags);
 199
 200         return 0;
 201 }
 202
 203 static void fintek_cir_ldev_init(struct fintek_dev *fintek)
 204 {
 205         /* Select CIR logical device and enable */
 206         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
 207         fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
 208
 209         /* Write allocated CIR address and IRQ information to hardware */
 210         fintek_cr_write(fintek, fintek->cir_addr >> 8, CIR_CR_BASE_ADDR_HI);
 211         fintek_cr_write(fintek, fintek->cir_addr & 0xff, CIR_CR_BASE_ADDR_LO);
 212
 213         fintek_cr_write(fintek, fintek->cir_irq, CIR_CR_IRQ_SEL);
 214
 215         fit_dbg("CIR initialized, base io address: 0x%lx, irq: %d (len: %d)",
 216                 fintek->cir_addr, fintek->cir_irq, fintek->cir_port_len);
 217 }
 218
 219 /* enable CIR interrupts */
 220 static void fintek_enable_cir_irq(struct fintek_dev *fintek)
 221 {
 222         fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
 223 }
 224
 225 static void fintek_cir_regs_init(struct fintek_dev *fintek)
 226 {
 227         /* clear any and all stray interrupts */
 228         fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
 229
 230         /* and finally, enable interrupts */
 231         fintek_enable_cir_irq(fintek);
 232 }
 233
 234 static void fintek_enable_wake(struct fintek_dev *fintek)
 235 {
 236         fintek_config_mode_enable(fintek);
 237         fintek_select_logical_dev(fintek, LOGICAL_DEV_ACPI);
 238
 239         /* Allow CIR PME's to wake system */
 240         fintek_set_reg_bit(fintek, ACPI_WAKE_EN_CIR_BIT, LDEV_ACPI_WAKE_EN_REG);
 241         /* Enable CIR PME's */
 242         fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_EN_REG);
 243         /* Clear CIR PME status register */
 244         fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_CLR_REG);
 245         /* Save state */
 246         fintek_set_reg_bit(fintek, ACPI_STATE_CIR_BIT, LDEV_ACPI_STATE_REG);
 247
 248         fintek_config_mode_disable(fintek);
 249 }
 250
 251 static int fintek_cmdsize(u8 cmd, u8 subcmd)
 252 {
 253         int datasize = 0;
 254
 255         switch (cmd) {
 256         case BUF_COMMAND_NULL:
 257                 if (subcmd == BUF_HW_CMD_HEADER)
 258                         datasize = 1;
 259                 break;
 260         case BUF_HW_CMD_HEADER:
 261                 if (subcmd == BUF_CMD_G_REVISION)
 262                         datasize = 2;
 263                 break;
 264         case BUF_COMMAND_HEADER:
 265                 switch (subcmd) {
 266                 case BUF_CMD_S_CARRIER:
 267                 case BUF_CMD_S_TIMEOUT:
 268                 case BUF_RSP_PULSE_COUNT:
 269                         datasize = 2;
 270                         break;
 271                 case BUF_CMD_SIG_END:
 272                 case BUF_CMD_S_TXMASK:
 273                 case BUF_CMD_S_RXSENSOR:
 274                         datasize = 1;
 275                         break;
 276                 }
 277         }
 278
 279         return datasize;
 280 }
 281
 282 /* process ir data stored in driver buffer */
 283 static void fintek_process_rx_ir_data(struct fintek_dev *fintek)
 284 {
 285         struct ir_raw_event rawir = {};
 286         u8 sample;
 287         bool event = false;
 288         int i;
 289
 290         for (i = 0; i < fintek->pkts; i++) {
 291                 sample = fintek->buf[i];
 292                 switch (fintek->parser_state) {
 293                 case CMD_HEADER:
 294                         fintek->cmd = sample;
 295                         if ((fintek->cmd == BUF_COMMAND_HEADER) ||
 296                             ((fintek->cmd & BUF_COMMAND_MASK) !=
 297                              BUF_PULSE_BIT)) {
 298                                 fintek->parser_state = SUBCMD;
 299                                 continue;
 300                         }
 301                         fintek->rem = (fintek->cmd & BUF_LEN_MASK);
 302                         fit_dbg("%s: rem: 0x%02x", __func__, fintek->rem);
 303                         if (fintek->rem)
 304                                 fintek->parser_state = PARSE_IRDATA;
 305                         else
 306                                 ir_raw_event_reset(fintek->rdev);
 307                         break;
 308                 case SUBCMD:
 309                         fintek->rem = fintek_cmdsize(fintek->cmd, sample);
 310                         fintek->parser_state = CMD_DATA;
 311                         break;
 312                 case CMD_DATA:
 313                         fintek->rem--;
 314                         break;
 315                 case PARSE_IRDATA:
 316                         fintek->rem--;
 317                         rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
 318                         rawir.duration = US_TO_NS((sample & BUF_SAMPLE_MASK)
 319                                           * CIR_SAMPLE_PERIOD);
 320
 321                         fit_dbg("Storing %s with duration %d",
 322                                 rawir.pulse ? "pulse" : "space",
 323                                 rawir.duration);
 324                         if (ir_raw_event_store_with_filter(fintek->rdev,
 325                                                                         &rawir))
 326                                 event = true;
 327                         break;
 328                 }
 329
 330                 if ((fintek->parser_state != CMD_HEADER) && !fintek->rem)
 331                         fintek->parser_state = CMD_HEADER;
 332         }
 333
 334         fintek->pkts = 0;
 335
 336         if (event) {
 337                 fit_dbg("Calling ir_raw_event_handle");
 338                 ir_raw_event_handle(fintek->rdev);
 339         }
 340 }
 341
 342 /* copy data from hardware rx register into driver buffer */
 343 static void fintek_get_rx_ir_data(struct fintek_dev *fintek, u8 rx_irqs)
 344 {
 345         unsigned long flags;
 346         u8 sample, status;
 347
 348         spin_lock_irqsave(&fintek->fintek_lock, flags);
 349
 350         /*
 351          * We must read data from CIR_RX_DATA until the hardware IR buffer
 352          * is empty and clears the RX_TIMEOUT and/or RX_RECEIVE flags in
 353          * the CIR_STATUS register
 354          */
 355         do {
 356                 sample = fintek_cir_reg_read(fintek, CIR_RX_DATA);
 357                 fit_dbg("%s: sample: 0x%02x", __func__, sample);
 358
 359                 fintek->buf[fintek->pkts] = sample;
 360                 fintek->pkts++;
 361
 362                 status = fintek_cir_reg_read(fintek, CIR_STATUS);
 363                 if (!(status & CIR_STATUS_IRQ_EN))
 364                         break;
 365         } while (status & rx_irqs);
 366
 367         fintek_process_rx_ir_data(fintek);
 368
 369         spin_unlock_irqrestore(&fintek->fintek_lock, flags);
 370 }
 371
 372 static void fintek_cir_log_irqs(u8 status)
 373 {
 374         fit_pr(KERN_INFO, "IRQ 0x%02x:%s%s%s%s%s", status,
 375                 status & CIR_STATUS_IRQ_EN      ? " IRQEN"      : "",
 376                 status & CIR_STATUS_TX_FINISH   ? " TXF"        : "",
 377                 status & CIR_STATUS_TX_UNDERRUN ? " TXU"        : "",
 378                 status & CIR_STATUS_RX_TIMEOUT  ? " RXTO"       : "",
 379                 status & CIR_STATUS_RX_RECEIVE  ? " RXOK"       : "");
 380 }
 381
 382 /* interrupt service routine for incoming and outgoing CIR data */
 383 static irqreturn_t fintek_cir_isr(int irq, void *data)
 384 {
 385         struct fintek_dev *fintek = data;
 386         u8 status, rx_irqs;
 387
 388         fit_dbg_verbose("%s firing", __func__);
 389
 390         fintek_config_mode_enable(fintek);
 391         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
 392         fintek_config_mode_disable(fintek);
 393
 394         /*
 395          * Get IR Status register contents. Write 1 to ack/clear
 396          *
 397          * bit: reg name    - description
 398          *   3: TX_FINISH   - TX is finished
 399          *   2: TX_UNDERRUN - TX underrun
 400          *   1: RX_TIMEOUT  - RX data timeout
 401          *   0: RX_RECEIVE  - RX data received
 402          */
 403         status = fintek_cir_reg_read(fintek, CIR_STATUS);
 404         if (!(status & CIR_STATUS_IRQ_MASK) || status == 0xff) {
 405                 fit_dbg_verbose("%s exiting, IRSTS 0x%02x", __func__, status);
 406                 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
 407                 return IRQ_RETVAL(IRQ_NONE);
 408         }
 409
 410         if (debug)
 411                 fintek_cir_log_irqs(status);
 412
 413         rx_irqs = status & (CIR_STATUS_RX_RECEIVE | CIR_STATUS_RX_TIMEOUT);
 414         if (rx_irqs)
 415                 fintek_get_rx_ir_data(fintek, rx_irqs);
 416
 417         /* ack/clear all irq flags we've got */
 418         fintek_cir_reg_write(fintek, status, CIR_STATUS);
 419
 420         fit_dbg_verbose("%s done", __func__);
 421         return IRQ_RETVAL(IRQ_HANDLED);
 422 }
 423
 424 static void fintek_enable_cir(struct fintek_dev *fintek)
 425 {
 426         /* set IRQ enabled */
 427         fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS);
 428
 429         fintek_config_mode_enable(fintek);
 430
 431         /* enable the CIR logical device */
 432         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
 433         fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
 434
 435         fintek_config_mode_disable(fintek);
 436
 437         /* clear all pending interrupts */
 438         fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
 439
 440         /* enable interrupts */
 441         fintek_enable_cir_irq(fintek);
 442 }
 443
 444 static void fintek_disable_cir(struct fintek_dev *fintek)
 445 {
 446         fintek_config_mode_enable(fintek);
 447
 448         /* disable the CIR logical device */
 449         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
 450         fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);
 451
 452         fintek_config_mode_disable(fintek);
 453 }
 454
 455 static int fintek_open(struct rc_dev *dev)
 456 {
 457         struct fintek_dev *fintek = dev->priv;
 458         unsigned long flags;
 459
 460         spin_lock_irqsave(&fintek->fintek_lock, flags);
 461         fintek_enable_cir(fintek);
 462         spin_unlock_irqrestore(&fintek->fintek_lock, flags);
 463
 464         return 0;
 465 }
 466
 467 static void fintek_close(struct rc_dev *dev)
 468 {
 469         struct fintek_dev *fintek = dev->priv;
 470         unsigned long flags;
 471
 472         spin_lock_irqsave(&fintek->fintek_lock, flags);
 473         fintek_disable_cir(fintek);
 474         spin_unlock_irqrestore(&fintek->fintek_lock, flags);
 475 }
 476
 477 /* Allocate memory, probe hardware, and initialize everything */
 478 static int fintek_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
 479 {
 480         struct fintek_dev *fintek;
 481         struct rc_dev *rdev;
 482         int ret = -ENOMEM;
 483
 484         fintek = kzalloc(sizeof(struct fintek_dev), GFP_KERNEL);
 485         if (!fintek)
 486                 return ret;
 487
 488         /* input device for IR remote (and tx) */
 489         rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
 490         if (!rdev)
 491                 goto exit_free_dev_rdev;
 492
 493         ret = -ENODEV;
 494         /* validate pnp resources */
 495         if (!pnp_port_valid(pdev, 0)) {
 496                 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
 497                 goto exit_free_dev_rdev;
 498         }
 499
 500         if (!pnp_irq_valid(pdev, 0)) {
 501                 dev_err(&pdev->dev, "IR PNP IRQ not valid!\n");
 502                 goto exit_free_dev_rdev;
 503         }
 504
 505         fintek->cir_addr = pnp_port_start(pdev, 0);
 506         fintek->cir_irq  = pnp_irq(pdev, 0);
 507         fintek->cir_port_len = pnp_port_len(pdev, 0);
 508
 509         fintek->cr_ip = CR_INDEX_PORT;
 510         fintek->cr_dp = CR_DATA_PORT;
 511
 512         spin_lock_init(&fintek->fintek_lock);
 513
 514         pnp_set_drvdata(pdev, fintek);
 515         fintek->pdev = pdev;
 516
 517         ret = fintek_hw_detect(fintek);
 518         if (ret)
 519                 goto exit_free_dev_rdev;
 520
 521         /* Initialize CIR & CIR Wake Logical Devices */
 522         fintek_config_mode_enable(fintek);
 523         fintek_cir_ldev_init(fintek);
 524         fintek_config_mode_disable(fintek);
 525
 526         /* Initialize CIR & CIR Wake Config Registers */
 527         fintek_cir_regs_init(fintek);
 528
 529         /* Set up the rc device */
 530         rdev->priv = fintek;
 531         rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
 532         rdev->open = fintek_open;
 533         rdev->close = fintek_close;
 534         rdev->device_name = FINTEK_DESCRIPTION;
 535         rdev->input_phys = "fintek/cir0";
 536         rdev->input_id.bustype = BUS_HOST;
 537         rdev->input_id.vendor = VENDOR_ID_FINTEK;
 538         rdev->input_id.product = fintek->chip_major;
 539         rdev->input_id.version = fintek->chip_minor;
 540         rdev->dev.parent = &pdev->dev;
 541         rdev->driver_name = FINTEK_DRIVER_NAME;
 542         rdev->map_name = RC_MAP_RC6_MCE;
 543         rdev->timeout = US_TO_NS(1000);
 544         /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
 545         rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
 546
 547         fintek->rdev = rdev;
 548
 549         ret = -EBUSY;
 550         /* now claim resources */
 551         if (!request_region(fintek->cir_addr,
 552                             fintek->cir_port_len, FINTEK_DRIVER_NAME))
 553                 goto exit_free_dev_rdev;
 554
 555         if (request_irq(fintek->cir_irq, fintek_cir_isr, IRQF_SHARED,
 556                         FINTEK_DRIVER_NAME, (void *)fintek))
 557                 goto exit_free_cir_addr;
 558
 559         ret = rc_register_device(rdev);
 560         if (ret)
 561                 goto exit_free_irq;
 562
 563         device_init_wakeup(&pdev->dev, true);
 564
 565         fit_pr(KERN_NOTICE, "driver has been successfully loaded\n");
 566         if (debug)
 567                 cir_dump_regs(fintek);
 568
 569         return 0;
 570
 571 exit_free_irq:
 572         free_irq(fintek->cir_irq, fintek);
 573 exit_free_cir_addr:
 574         release_region(fintek->cir_addr, fintek->cir_port_len);
 575 exit_free_dev_rdev:
 576         rc_free_device(rdev);
 577         kfree(fintek);
 578
 579         return ret;
 580 }
 581
 582 static void fintek_remove(struct pnp_dev *pdev)
 583 {
 584         struct fintek_dev *fintek = pnp_get_drvdata(pdev);
 585         unsigned long flags;
 586
 587         spin_lock_irqsave(&fintek->fintek_lock, flags);
 588         /* disable CIR */
 589         fintek_disable_cir(fintek);
 590         fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
 591         /* enable CIR Wake (for IR power-on) */
 592         fintek_enable_wake(fintek);
 593         spin_unlock_irqrestore(&fintek->fintek_lock, flags);
 594
 595         /* free resources */
 596         free_irq(fintek->cir_irq, fintek);
 597         release_region(fintek->cir_addr, fintek->cir_port_len);
 598
 599         rc_unregister_device(fintek->rdev);
 600
 601         kfree(fintek);
 602 }
 603
 604 static int fintek_suspend(struct pnp_dev *pdev, pm_message_t state)
 605 {
 606         struct fintek_dev *fintek = pnp_get_drvdata(pdev);
 607         unsigned long flags;
 608
 609         fit_dbg("%s called", __func__);
 610
 611         spin_lock_irqsave(&fintek->fintek_lock, flags);
 612
 613         /* disable all CIR interrupts */
 614         fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS);
 615
 616         spin_unlock_irqrestore(&fintek->fintek_lock, flags);
 617
 618         fintek_config_mode_enable(fintek);
 619
 620         /* disable cir logical dev */
 621         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
 622         fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN);
 623
 624         fintek_config_mode_disable(fintek);
 625
 626         /* make sure wake is enabled */
 627         fintek_enable_wake(fintek);
 628
 629         return 0;
 630 }
 631
 632 static int fintek_resume(struct pnp_dev *pdev)
 633 {
 634         struct fintek_dev *fintek = pnp_get_drvdata(pdev);
 635
 636         fit_dbg("%s called", __func__);
 637
 638         /* open interrupt */
 639         fintek_enable_cir_irq(fintek);
 640
 641         /* Enable CIR logical device */
 642         fintek_config_mode_enable(fintek);
 643         fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
 644         fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN);
 645
 646         fintek_config_mode_disable(fintek);
 647
 648         fintek_cir_regs_init(fintek);
 649
 650         return 0;
 651 }
 652
 653 static void fintek_shutdown(struct pnp_dev *pdev)
 654 {
 655         struct fintek_dev *fintek = pnp_get_drvdata(pdev);
 656         fintek_enable_wake(fintek);
 657 }
 658
 659 static const struct pnp_device_id fintek_ids[] = {
 660         { "FIT0002", 0 },   /* CIR */
 661         { "", 0 },
 662 };
 663
 664 static struct pnp_driver fintek_driver = {
 665         .name           = FINTEK_DRIVER_NAME,
 666         .id_table       = fintek_ids,
 667         .flags          = PNP_DRIVER_RES_DO_NOT_CHANGE,
 668         .probe          = fintek_probe,
 669         .remove         = fintek_remove,
 670         .suspend        = fintek_suspend,
 671         .resume         = fintek_resume,
 672         .shutdown       = fintek_shutdown,
 673 };
 674
 675 module_param(debug, int, S_IRUGO | S_IWUSR);
 676 MODULE_PARM_DESC(debug, "Enable debugging output");
 677
 678 MODULE_DEVICE_TABLE(pnp, fintek_ids);
 679 MODULE_DESCRIPTION(FINTEK_DESCRIPTION " driver");
 680
 681 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
 682 MODULE_LICENSE("GPL");
 683
 684 module_pnp_driver(fintek_driver);