drivers/spi/spi-dw.c

   1 /*
   2  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/highmem.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/gpio.h>
  24
  25 #include "spi-dw.h"
  26
  27 #ifdef CONFIG_DEBUG_FS
  28 #include <linux/debugfs.h>
  29 #endif
  30
  31 /* Slave spi_dev related */
  32 struct chip_data {
  33         u8 tmode;               /* TR/TO/RO/EEPROM */
  34         u8 type;                /* SPI/SSP/MicroWire */
  35
  36         u8 poll_mode;           /* 1 means use poll mode */
  37
  38         u16 clk_div;            /* baud rate divider */
  39         u32 speed_hz;           /* baud rate */
  40         void (*cs_control)(u32 command);
  41 };
  42
  43 #ifdef CONFIG_DEBUG_FS
  44 #define SPI_REGS_BUFSIZE        1024
  45 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
  46                 size_t count, loff_t *ppos)
  47 {
  48         struct dw_spi *dws = file->private_data;
  49         char *buf;
  50         u32 len = 0;
  51         ssize_t ret;
  52
  53         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  54         if (!buf)
  55                 return 0;
  56
  57         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  58                         "%s registers:\n", dev_name(&dws->master->dev));
  59         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  60                         "=================================\n");
  61         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  62                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  63         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  64                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  65         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  66                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  67         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  68                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  69         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  70                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  71         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  72                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  73         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  74                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  75         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  76                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
  77         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  78                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
  79         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  80                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
  81         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  82                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
  83         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  84                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
  85         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  86                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
  87         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  88                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
  89         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  90                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
  91         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  92                         "=================================\n");
  93
  94         ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  95         kfree(buf);
  96         return ret;
  97 }
  98
  99 static const struct file_operations dw_spi_regs_ops = {
 100         .owner          = THIS_MODULE,
 101         .open           = simple_open,
 102         .read           = dw_spi_show_regs,
 103         .llseek         = default_llseek,
 104 };
 105
 106 static int dw_spi_debugfs_init(struct dw_spi *dws)
 107 {
 108         char name[32];
 109
 110         snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
 111         dws->debugfs = debugfs_create_dir(name, NULL);
 112         if (!dws->debugfs)
 113                 return -ENOMEM;
 114
 115         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 116                 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
 117         return 0;
 118 }
 119
 120 static void dw_spi_debugfs_remove(struct dw_spi *dws)
 121 {
 122         debugfs_remove_recursive(dws->debugfs);
 123 }
 124
 125 #else
 126 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
 127 {
 128         return 0;
 129 }
 130
 131 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
 132 {
 133 }
 134 #endif /* CONFIG_DEBUG_FS */
 135
 136 void dw_spi_set_cs(struct spi_device *spi, bool enable)
 137 {
 138         struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
 139         struct chip_data *chip = spi_get_ctldata(spi);
 140
 141         /* Chip select logic is inverted from spi_set_cs() */
 142         if (chip && chip->cs_control)
 143                 chip->cs_control(!enable);
 144
 145         if (!enable)
 146                 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
 147         else if (dws->cs_override)
 148                 dw_writel(dws, DW_SPI_SER, 0);
 149 }
 150 EXPORT_SYMBOL_GPL(dw_spi_set_cs);
 151
 152 /* Return the max entries we can fill into tx fifo */
 153 static inline u32 tx_max(struct dw_spi *dws)
 154 {
 155         u32 tx_left, tx_room, rxtx_gap;
 156
 157         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 158         tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
 159
 160         /*
 161          * Another concern is about the tx/rx mismatch, we
 162          * though to use (dws->fifo_len - rxflr - txflr) as
 163          * one maximum value for tx, but it doesn't cover the
 164          * data which is out of tx/rx fifo and inside the
 165          * shift registers. So a control from sw point of
 166          * view is taken.
 167          */
 168         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 169                         / dws->n_bytes;
 170
 171         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 172 }
 173
 174 /* Return the max entries we should read out of rx fifo */
 175 static inline u32 rx_max(struct dw_spi *dws)
 176 {
 177         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 178
 179         return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
 180 }
 181
 182 static void dw_writer(struct dw_spi *dws)
 183 {
 184         u32 max = tx_max(dws);
 185         u16 txw = 0;
 186
 187         while (max--) {
 188                 /* Set the tx word if the transfer's original "tx" is not null */
 189                 if (dws->tx_end - dws->len) {
 190                         if (dws->n_bytes == 1)
 191                                 txw = *(u8 *)(dws->tx);
 192                         else
 193                                 txw = *(u16 *)(dws->tx);
 194                 }
 195                 dw_write_io_reg(dws, DW_SPI_DR, txw);
 196                 dws->tx += dws->n_bytes;
 197         }
 198 }
 199
 200 static void dw_reader(struct dw_spi *dws)
 201 {
 202         u32 max = rx_max(dws);
 203         u16 rxw;
 204
 205         while (max--) {
 206                 rxw = dw_read_io_reg(dws, DW_SPI_DR);
 207                 /* Care rx only if the transfer's original "rx" is not null */
 208                 if (dws->rx_end - dws->len) {
 209                         if (dws->n_bytes == 1)
 210                                 *(u8 *)(dws->rx) = rxw;
 211                         else
 212                                 *(u16 *)(dws->rx) = rxw;
 213                 }
 214                 dws->rx += dws->n_bytes;
 215         }
 216 }
 217
 218 static void int_error_stop(struct dw_spi *dws, const char *msg)
 219 {
 220         spi_reset_chip(dws);
 221
 222         dev_err(&dws->master->dev, "%s\n", msg);
 223         dws->master->cur_msg->status = -EIO;
 224         spi_finalize_current_transfer(dws->master);
 225 }
 226
 227 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 228 {
 229         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 230
 231         /* Error handling */
 232         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 233                 dw_readl(dws, DW_SPI_ICR);
 234                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 235                 return IRQ_HANDLED;
 236         }
 237
 238         dw_reader(dws);
 239         if (dws->rx_end == dws->rx) {
 240                 spi_mask_intr(dws, SPI_INT_TXEI);
 241                 spi_finalize_current_transfer(dws->master);
 242                 return IRQ_HANDLED;
 243         }
 244         if (irq_status & SPI_INT_TXEI) {
 245                 spi_mask_intr(dws, SPI_INT_TXEI);
 246                 dw_writer(dws);
 247                 /* Enable TX irq always, it will be disabled when RX finished */
 248                 spi_umask_intr(dws, SPI_INT_TXEI);
 249         }
 250
 251         return IRQ_HANDLED;
 252 }
 253
 254 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 255 {
 256         struct spi_controller *master = dev_id;
 257         struct dw_spi *dws = spi_controller_get_devdata(master);
 258         u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
 259
 260         if (!irq_status)
 261                 return IRQ_NONE;
 262
 263         if (!master->cur_msg) {
 264                 spi_mask_intr(dws, SPI_INT_TXEI);
 265                 return IRQ_HANDLED;
 266         }
 267
 268         return dws->transfer_handler(dws);
 269 }
 270
 271 /* Must be called inside pump_transfers() */
 272 static int poll_transfer(struct dw_spi *dws)
 273 {
 274         do {
 275                 dw_writer(dws);
 276                 dw_reader(dws);
 277                 cpu_relax();
 278         } while (dws->rx_end > dws->rx);
 279
 280         return 0;
 281 }
 282
 283 static int dw_spi_transfer_one(struct spi_controller *master,
 284                 struct spi_device *spi, struct spi_transfer *transfer)
 285 {
 286         struct dw_spi *dws = spi_controller_get_devdata(master);
 287         struct chip_data *chip = spi_get_ctldata(spi);
 288         u8 imask = 0;
 289         u16 txlevel = 0;
 290         u32 cr0;
 291         int ret;
 292
 293         dws->dma_mapped = 0;
 294
 295         dws->tx = (void *)transfer->tx_buf;
 296         dws->tx_end = dws->tx + transfer->len;
 297         dws->rx = transfer->rx_buf;
 298         dws->rx_end = dws->rx + transfer->len;
 299         dws->len = transfer->len;
 300
 301         spi_enable_chip(dws, 0);
 302
 303         /* Handle per transfer options for bpw and speed */
 304         if (transfer->speed_hz != dws->current_freq) {
 305                 if (transfer->speed_hz != chip->speed_hz) {
 306                         /* clk_div doesn't support odd number */
 307                         chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
 308                         chip->speed_hz = transfer->speed_hz;
 309                 }
 310                 dws->current_freq = transfer->speed_hz;
 311                 spi_set_clk(dws, chip->clk_div);
 312         }
 313
 314         dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
 315         dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
 316
 317         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 318         cr0 = (transfer->bits_per_word - 1)
 319                 | (chip->type << SPI_FRF_OFFSET)
 320                 | (spi->mode << SPI_MODE_OFFSET)
 321                 | (chip->tmode << SPI_TMOD_OFFSET);
 322
 323         /*
 324          * Adjust transfer mode if necessary. Requires platform dependent
 325          * chipselect mechanism.
 326          */
 327         if (chip->cs_control) {
 328                 if (dws->rx && dws->tx)
 329                         chip->tmode = SPI_TMOD_TR;
 330                 else if (dws->rx)
 331                         chip->tmode = SPI_TMOD_RO;
 332                 else
 333                         chip->tmode = SPI_TMOD_TO;
 334
 335                 cr0 &= ~SPI_TMOD_MASK;
 336                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 337         }
 338
 339         dw_writel(dws, DW_SPI_CTRL0, cr0);
 340
 341         /* Check if current transfer is a DMA transaction */
 342         if (master->can_dma && master->can_dma(master, spi, transfer))
 343                 dws->dma_mapped = master->cur_msg_mapped;
 344
 345         /* For poll mode just disable all interrupts */
 346         spi_mask_intr(dws, 0xff);
 347
 348         /*
 349          * Interrupt mode
 350          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 351          */
 352         if (dws->dma_mapped) {
 353                 ret = dws->dma_ops->dma_setup(dws, transfer);
 354                 if (ret < 0) {
 355                         spi_enable_chip(dws, 1);
 356                         return ret;
 357                 }
 358         } else if (!chip->poll_mode) {
 359                 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
 360                 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
 361
 362                 /* Set the interrupt mask */
 363                 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
 364                          SPI_INT_RXUI | SPI_INT_RXOI;
 365                 spi_umask_intr(dws, imask);
 366
 367                 dws->transfer_handler = interrupt_transfer;
 368         }
 369
 370         spi_enable_chip(dws, 1);
 371
 372         if (dws->dma_mapped) {
 373                 ret = dws->dma_ops->dma_transfer(dws, transfer);
 374                 if (ret < 0)
 375                         return ret;
 376         }
 377
 378         if (chip->poll_mode)
 379                 return poll_transfer(dws);
 380
 381         return 1;
 382 }
 383
 384 static void dw_spi_handle_err(struct spi_controller *master,
 385                 struct spi_message *msg)
 386 {
 387         struct dw_spi *dws = spi_controller_get_devdata(master);
 388
 389         if (dws->dma_mapped)
 390                 dws->dma_ops->dma_stop(dws);
 391
 392         spi_reset_chip(dws);
 393 }
 394
 395 /* This may be called twice for each spi dev */
 396 static int dw_spi_setup(struct spi_device *spi)
 397 {
 398         struct dw_spi_chip *chip_info = NULL;
 399         struct chip_data *chip;
 400         int ret;
 401
 402         /* Only alloc on first setup */
 403         chip = spi_get_ctldata(spi);
 404         if (!chip) {
 405                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 406                 if (!chip)
 407                         return -ENOMEM;
 408                 spi_set_ctldata(spi, chip);
 409         }
 410
 411         /*
 412          * Protocol drivers may change the chip settings, so...
 413          * if chip_info exists, use it
 414          */
 415         chip_info = spi->controller_data;
 416
 417         /* chip_info doesn't always exist */
 418         if (chip_info) {
 419                 if (chip_info->cs_control)
 420                         chip->cs_control = chip_info->cs_control;
 421
 422                 chip->poll_mode = chip_info->poll_mode;
 423                 chip->type = chip_info->type;
 424         }
 425
 426         chip->tmode = SPI_TMOD_TR;
 427
 428         if (gpio_is_valid(spi->cs_gpio)) {
 429                 ret = gpio_direction_output(spi->cs_gpio,
 430                                 !(spi->mode & SPI_CS_HIGH));
 431                 if (ret)
 432                         return ret;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static void dw_spi_cleanup(struct spi_device *spi)
 439 {
 440         struct chip_data *chip = spi_get_ctldata(spi);
 441
 442         kfree(chip);
 443         spi_set_ctldata(spi, NULL);
 444 }
 445
 446 /* Restart the controller, disable all interrupts, clean rx fifo */
 447 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
 448 {
 449         spi_reset_chip(dws);
 450
 451         /*
 452          * Try to detect the FIFO depth if not set by interface driver,
 453          * the depth could be from 2 to 256 from HW spec
 454          */
 455         if (!dws->fifo_len) {
 456                 u32 fifo;
 457
 458                 for (fifo = 1; fifo < 256; fifo++) {
 459                         dw_writel(dws, DW_SPI_TXFLTR, fifo);
 460                         if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
 461                                 break;
 462                 }
 463                 dw_writel(dws, DW_SPI_TXFLTR, 0);
 464
 465                 dws->fifo_len = (fifo == 1) ? 0 : fifo;
 466                 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
 467         }
 468
 469         /* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
 470         if (dws->cs_override)
 471                 dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
 472 }
 473
 474 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
 475 {
 476         struct spi_controller *master;
 477         int ret;
 478
 479         BUG_ON(dws == NULL);
 480
 481         master = spi_alloc_master(dev, 0);
 482         if (!master)
 483                 return -ENOMEM;
 484
 485         dws->master = master;
 486         dws->type = SSI_MOTO_SPI;
 487         dws->dma_inited = 0;
 488         dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
 489
 490         spi_controller_set_devdata(master, dws);
 491
 492         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
 493                           master);
 494         if (ret < 0) {
 495                 dev_err(dev, "can not get IRQ\n");
 496                 goto err_free_master;
 497         }
 498
 499         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 500         master->bits_per_word_mask =  SPI_BPW_RANGE_MASK(4, 16);
 501         master->bus_num = dws->bus_num;
 502         master->num_chipselect = dws->num_cs;
 503         master->setup = dw_spi_setup;
 504         master->cleanup = dw_spi_cleanup;
 505         master->set_cs = dw_spi_set_cs;
 506         master->transfer_one = dw_spi_transfer_one;
 507         master->handle_err = dw_spi_handle_err;
 508         master->max_speed_hz = dws->max_freq;
 509         master->dev.of_node = dev->of_node;
 510         master->flags = SPI_MASTER_GPIO_SS;
 511
 512         if (dws->set_cs)
 513                 master->set_cs = dws->set_cs;
 514
 515         /* Basic HW init */
 516         spi_hw_init(dev, dws);
 517
 518         if (dws->dma_ops && dws->dma_ops->dma_init) {
 519                 ret = dws->dma_ops->dma_init(dws);
 520                 if (ret) {
 521                         dev_warn(dev, "DMA init failed\n");
 522                         dws->dma_inited = 0;
 523                 } else {
 524                         master->can_dma = dws->dma_ops->can_dma;
 525                 }
 526         }
 527
 528         ret = devm_spi_register_controller(dev, master);
 529         if (ret) {
 530                 dev_err(&master->dev, "problem registering spi master\n");
 531                 goto err_dma_exit;
 532         }
 533
 534         dw_spi_debugfs_init(dws);
 535         return 0;
 536
 537 err_dma_exit:
 538         if (dws->dma_ops && dws->dma_ops->dma_exit)
 539                 dws->dma_ops->dma_exit(dws);
 540         spi_enable_chip(dws, 0);
 541         free_irq(dws->irq, master);
 542 err_free_master:
 543         spi_controller_put(master);
 544         return ret;
 545 }
 546 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 547
 548 void dw_spi_remove_host(struct dw_spi *dws)
 549 {
 550         dw_spi_debugfs_remove(dws);
 551
 552         if (dws->dma_ops && dws->dma_ops->dma_exit)
 553                 dws->dma_ops->dma_exit(dws);
 554
 555         spi_shutdown_chip(dws);
 556
 557         free_irq(dws->irq, dws->master);
 558 }
 559 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 560
 561 int dw_spi_suspend_host(struct dw_spi *dws)
 562 {
 563         int ret;
 564
 565         ret = spi_controller_suspend(dws->master);
 566         if (ret)
 567                 return ret;
 568
 569         spi_shutdown_chip(dws);
 570         return 0;
 571 }
 572 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 573
 574 int dw_spi_resume_host(struct dw_spi *dws)
 575 {
 576         spi_hw_init(&dws->master->dev, dws);
 577         return spi_controller_resume(dws->master);
 578 }
 579 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 580
 581 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 582 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 583 MODULE_LICENSE("GPL v2");