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perf bpf: Move perf_event_output() from stdio.h to bpf.h
[linux/fpc-iii.git] / drivers / spi / spi-imx.c
blobdd1ce12aa386a75c1747d6081881feacc356a231
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 // Copyright (C) 2008 Juergen Beisert
4
5 #include <linux/clk.h>
6 #include <linux/completion.h>
7 #include <linux/delay.h>
8 #include <linux/dmaengine.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/gpio.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/irq.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi_bitbang.h>
21 #include <linux/types.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/of_gpio.h>
25
26 #include <linux/platform_data/dma-imx.h>
27 #include <linux/platform_data/spi-imx.h>
28
29 #define DRIVER_NAME "spi_imx"
30
31 #define MXC_CSPIRXDATA 0x00
32 #define MXC_CSPITXDATA 0x04
33 #define MXC_CSPICTRL 0x08
34 #define MXC_CSPIINT 0x0c
35 #define MXC_RESET 0x1c
36
37 /* generic defines to abstract from the different register layouts */
38 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
39 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
40 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
41
42 /* The maximum bytes that a sdma BD can transfer.*/
43 #define MAX_SDMA_BD_BYTES (1 << 15)
44 #define MX51_ECSPI_CTRL_MAX_BURST 512
45 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
46 #define MX53_MAX_TRANSFER_BYTES 512
47
48 enum spi_imx_devtype {
49 IMX1_CSPI,
50 IMX21_CSPI,
51 IMX27_CSPI,
52 IMX31_CSPI,
53 IMX35_CSPI, /* CSPI on all i.mx except above */
54 IMX51_ECSPI, /* ECSPI on i.mx51 */
55 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
56 };
57
58 struct spi_imx_data;
59
60 struct spi_imx_devtype_data {
61 void (*intctrl)(struct spi_imx_data *, int);
62 int (*config)(struct spi_device *);
63 void (*trigger)(struct spi_imx_data *);
64 int (*rx_available)(struct spi_imx_data *);
65 void (*reset)(struct spi_imx_data *);
66 void (*setup_wml)(struct spi_imx_data *);
67 void (*disable)(struct spi_imx_data *);
68 bool has_dmamode;
69 bool has_slavemode;
70 unsigned int fifo_size;
71 bool dynamic_burst;
72 enum spi_imx_devtype devtype;
73 };
74
75 struct spi_imx_data {
76 struct spi_bitbang bitbang;
77 struct device *dev;
78
79 struct completion xfer_done;
80 void __iomem *base;
81 unsigned long base_phys;
82
83 struct clk *clk_per;
84 struct clk *clk_ipg;
85 unsigned long spi_clk;
86 unsigned int spi_bus_clk;
87
88 unsigned int speed_hz;
89 unsigned int bits_per_word;
90 unsigned int spi_drctl;
91
92 unsigned int count, remainder;
93 void (*tx)(struct spi_imx_data *);
94 void (*rx)(struct spi_imx_data *);
95 void *rx_buf;
96 const void *tx_buf;
97 unsigned int txfifo; /* number of words pushed in tx FIFO */
98 unsigned int dynamic_burst;
99
100 /* Slave mode */
101 bool slave_mode;
102 bool slave_aborted;
103 unsigned int slave_burst;
104
105 /* DMA */
106 bool usedma;
107 u32 wml;
108 struct completion dma_rx_completion;
109 struct completion dma_tx_completion;
110
111 const struct spi_imx_devtype_data *devtype_data;
112 };
113
114 static inline int is_imx27_cspi(struct spi_imx_data *d)
115 {
116 return d->devtype_data->devtype == IMX27_CSPI;
117 }
118
119 static inline int is_imx35_cspi(struct spi_imx_data *d)
120 {
121 return d->devtype_data->devtype == IMX35_CSPI;
122 }
123
124 static inline int is_imx51_ecspi(struct spi_imx_data *d)
125 {
126 return d->devtype_data->devtype == IMX51_ECSPI;
127 }
128
129 static inline int is_imx53_ecspi(struct spi_imx_data *d)
130 {
131 return d->devtype_data->devtype == IMX53_ECSPI;
132 }
133
134 #define MXC_SPI_BUF_RX(type) \
135 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
136 { \
137 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
138 \
139 if (spi_imx->rx_buf) { \
140 *(type *)spi_imx->rx_buf = val; \
141 spi_imx->rx_buf += sizeof(type); \
142 } \
143 \
144 spi_imx->remainder -= sizeof(type); \
145 }
146
147 #define MXC_SPI_BUF_TX(type) \
148 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
149 { \
150 type val = 0; \
151 \
152 if (spi_imx->tx_buf) { \
153 val = *(type *)spi_imx->tx_buf; \
154 spi_imx->tx_buf += sizeof(type); \
155 } \
156 \
157 spi_imx->count -= sizeof(type); \
158 \
159 writel(val, spi_imx->base + MXC_CSPITXDATA); \
160 }
161
162 MXC_SPI_BUF_RX(u8)
163 MXC_SPI_BUF_TX(u8)
164 MXC_SPI_BUF_RX(u16)
165 MXC_SPI_BUF_TX(u16)
166 MXC_SPI_BUF_RX(u32)
167 MXC_SPI_BUF_TX(u32)
168
169 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
170 * (which is currently not the case in this driver)
171 */
172 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
173 256, 384, 512, 768, 1024};
174
175 /* MX21, MX27 */
176 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
177 unsigned int fspi, unsigned int max, unsigned int *fres)
178 {
179 int i;
180
181 for (i = 2; i < max; i++)
182 if (fspi * mxc_clkdivs[i] >= fin)
183 break;
184
185 *fres = fin / mxc_clkdivs[i];
186 return i;
187 }
188
189 /* MX1, MX31, MX35, MX51 CSPI */
190 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
191 unsigned int fspi, unsigned int *fres)
192 {
193 int i, div = 4;
194
195 for (i = 0; i < 7; i++) {
196 if (fspi * div >= fin)
197 goto out;
198 div <<= 1;
199 }
200
201 out:
202 *fres = fin / div;
203 return i;
204 }
205
206 static int spi_imx_bytes_per_word(const int bits_per_word)
207 {
208 if (bits_per_word <= 8)
209 return 1;
210 else if (bits_per_word <= 16)
211 return 2;
212 else
213 return 4;
214 }
215
216 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
217 struct spi_transfer *transfer)
218 {
219 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
220
221 if (!master->dma_rx)
222 return false;
223
224 if (spi_imx->slave_mode)
225 return false;
226
227 if (transfer->len < spi_imx->devtype_data->fifo_size)
228 return false;
229
230 spi_imx->dynamic_burst = 0;
231
232 return true;
233 }
234
235 #define MX51_ECSPI_CTRL 0x08
236 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
237 #define MX51_ECSPI_CTRL_XCH (1 << 2)
238 #define MX51_ECSPI_CTRL_SMC (1 << 3)
239 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
240 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
241 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
242 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
243 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
244 #define MX51_ECSPI_CTRL_BL_OFFSET 20
245 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
246
247 #define MX51_ECSPI_CONFIG 0x0c
248 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
249 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
250 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
251 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
252 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
253
254 #define MX51_ECSPI_INT 0x10
255 #define MX51_ECSPI_INT_TEEN (1 << 0)
256 #define MX51_ECSPI_INT_RREN (1 << 3)
257 #define MX51_ECSPI_INT_RDREN (1 << 4)
258
259 #define MX51_ECSPI_DMA 0x14
260 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
261 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
262 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
263
264 #define MX51_ECSPI_DMA_TEDEN (1 << 7)
265 #define MX51_ECSPI_DMA_RXDEN (1 << 23)
266 #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
267
268 #define MX51_ECSPI_STAT 0x18
269 #define MX51_ECSPI_STAT_RR (1 << 3)
270
271 #define MX51_ECSPI_TESTREG 0x20
272 #define MX51_ECSPI_TESTREG_LBC BIT(31)
273
274 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
275 {
276 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
277 #ifdef __LITTLE_ENDIAN
278 unsigned int bytes_per_word;
279 #endif
280
281 if (spi_imx->rx_buf) {
282 #ifdef __LITTLE_ENDIAN
283 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
284 if (bytes_per_word == 1)
285 val = cpu_to_be32(val);
286 else if (bytes_per_word == 2)
287 val = (val << 16) | (val >> 16);
288 #endif
289 *(u32 *)spi_imx->rx_buf = val;
290 spi_imx->rx_buf += sizeof(u32);
291 }
292
293 spi_imx->remainder -= sizeof(u32);
294 }
295
296 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
297 {
298 int unaligned;
299 u32 val;
300
301 unaligned = spi_imx->remainder % 4;
302
303 if (!unaligned) {
304 spi_imx_buf_rx_swap_u32(spi_imx);
305 return;
306 }
307
308 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
309 spi_imx_buf_rx_u16(spi_imx);
310 return;
311 }
312
313 val = readl(spi_imx->base + MXC_CSPIRXDATA);
314
315 while (unaligned--) {
316 if (spi_imx->rx_buf) {
317 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
318 spi_imx->rx_buf++;
319 }
320 spi_imx->remainder--;
321 }
322 }
323
324 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
325 {
326 u32 val = 0;
327 #ifdef __LITTLE_ENDIAN
328 unsigned int bytes_per_word;
329 #endif
330
331 if (spi_imx->tx_buf) {
332 val = *(u32 *)spi_imx->tx_buf;
333 spi_imx->tx_buf += sizeof(u32);
334 }
335
336 spi_imx->count -= sizeof(u32);
337 #ifdef __LITTLE_ENDIAN
338 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
339
340 if (bytes_per_word == 1)
341 val = cpu_to_be32(val);
342 else if (bytes_per_word == 2)
343 val = (val << 16) | (val >> 16);
344 #endif
345 writel(val, spi_imx->base + MXC_CSPITXDATA);
346 }
347
348 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
349 {
350 int unaligned;
351 u32 val = 0;
352
353 unaligned = spi_imx->count % 4;
354
355 if (!unaligned) {
356 spi_imx_buf_tx_swap_u32(spi_imx);
357 return;
358 }
359
360 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
361 spi_imx_buf_tx_u16(spi_imx);
362 return;
363 }
364
365 while (unaligned--) {
366 if (spi_imx->tx_buf) {
367 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
368 spi_imx->tx_buf++;
369 }
370 spi_imx->count--;
371 }
372
373 writel(val, spi_imx->base + MXC_CSPITXDATA);
374 }
375
376 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
377 {
378 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
379
380 if (spi_imx->rx_buf) {
381 int n_bytes = spi_imx->slave_burst % sizeof(val);
382
383 if (!n_bytes)
384 n_bytes = sizeof(val);
385
386 memcpy(spi_imx->rx_buf,
387 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
388
389 spi_imx->rx_buf += n_bytes;
390 spi_imx->slave_burst -= n_bytes;
391 }
392
393 spi_imx->remainder -= sizeof(u32);
394 }
395
396 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
397 {
398 u32 val = 0;
399 int n_bytes = spi_imx->count % sizeof(val);
400
401 if (!n_bytes)
402 n_bytes = sizeof(val);
403
404 if (spi_imx->tx_buf) {
405 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
406 spi_imx->tx_buf, n_bytes);
407 val = cpu_to_be32(val);
408 spi_imx->tx_buf += n_bytes;
409 }
410
411 spi_imx->count -= n_bytes;
412
413 writel(val, spi_imx->base + MXC_CSPITXDATA);
414 }
415
416 /* MX51 eCSPI */
417 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
418 unsigned int fspi, unsigned int *fres)
419 {
420 /*
421 * there are two 4-bit dividers, the pre-divider divides by
422 * $pre, the post-divider by 2^$post
423 */
424 unsigned int pre, post;
425 unsigned int fin = spi_imx->spi_clk;
426
427 if (unlikely(fspi > fin))
428 return 0;
429
430 post = fls(fin) - fls(fspi);
431 if (fin > fspi << post)
432 post++;
433
434 /* now we have: (fin <= fspi << post) with post being minimal */
435
436 post = max(4U, post) - 4;
437 if (unlikely(post > 0xf)) {
438 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
439 fspi, fin);
440 return 0xff;
441 }
442
443 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
444
445 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
446 __func__, fin, fspi, post, pre);
447
448 /* Resulting frequency for the SCLK line. */
449 *fres = (fin / (pre + 1)) >> post;
450
451 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
452 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
453 }
454
455 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
456 {
457 unsigned val = 0;
458
459 if (enable & MXC_INT_TE)
460 val |= MX51_ECSPI_INT_TEEN;
461
462 if (enable & MXC_INT_RR)
463 val |= MX51_ECSPI_INT_RREN;
464
465 if (enable & MXC_INT_RDR)
466 val |= MX51_ECSPI_INT_RDREN;
467
468 writel(val, spi_imx->base + MX51_ECSPI_INT);
469 }
470
471 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
472 {
473 u32 reg;
474
475 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
476 reg |= MX51_ECSPI_CTRL_XCH;
477 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
478 }
479
480 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
481 {
482 u32 ctrl;
483
484 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
485 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
486 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
487 }
488
489 static int mx51_ecspi_config(struct spi_device *spi)
490 {
491 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
492 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
493 u32 clk = spi_imx->speed_hz, delay, reg;
494 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
495
496 /* set Master or Slave mode */
497 if (spi_imx->slave_mode)
498 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
499 else
500 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
501
502 /*
503 * Enable SPI_RDY handling (falling edge/level triggered).
504 */
505 if (spi->mode & SPI_READY)
506 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
507
508 /* set clock speed */
509 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->speed_hz, &clk);
510 spi_imx->spi_bus_clk = clk;
511
512 /* set chip select to use */
513 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
514
515 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
516 ctrl |= (spi_imx->slave_burst * 8 - 1)
517 << MX51_ECSPI_CTRL_BL_OFFSET;
518 else
519 ctrl |= (spi_imx->bits_per_word - 1)
520 << MX51_ECSPI_CTRL_BL_OFFSET;
521
522 /*
523 * eCSPI burst completion by Chip Select signal in Slave mode
524 * is not functional for imx53 Soc, config SPI burst completed when
525 * BURST_LENGTH + 1 bits are received
526 */
527 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
528 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
529 else
530 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
531
532 if (spi->mode & SPI_CPHA)
533 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
534 else
535 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
536
537 if (spi->mode & SPI_CPOL) {
538 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
539 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
540 } else {
541 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
542 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
543 }
544 if (spi->mode & SPI_CS_HIGH)
545 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
546 else
547 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
548
549 if (spi_imx->usedma)
550 ctrl |= MX51_ECSPI_CTRL_SMC;
551
552 /* CTRL register always go first to bring out controller from reset */
553 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
554
555 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
556 if (spi->mode & SPI_LOOP)
557 reg |= MX51_ECSPI_TESTREG_LBC;
558 else
559 reg &= ~MX51_ECSPI_TESTREG_LBC;
560 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
561
562 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
563
564 /*
565 * Wait until the changes in the configuration register CONFIGREG
566 * propagate into the hardware. It takes exactly one tick of the
567 * SCLK clock, but we will wait two SCLK clock just to be sure. The
568 * effect of the delay it takes for the hardware to apply changes
569 * is noticable if the SCLK clock run very slow. In such a case, if
570 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
571 * be asserted before the SCLK polarity changes, which would disrupt
572 * the SPI communication as the device on the other end would consider
573 * the change of SCLK polarity as a clock tick already.
574 */
575 delay = (2 * 1000000) / clk;
576 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
577 udelay(delay);
578 else /* SCLK is _very_ slow */
579 usleep_range(delay, delay + 10);
580
581 return 0;
582 }
583
584 static void mx51_setup_wml(struct spi_imx_data *spi_imx)
585 {
586 /*
587 * Configure the DMA register: setup the watermark
588 * and enable DMA request.
589 */
590
591 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
592 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
593 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
594 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
595 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
596 }
597
598 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
599 {
600 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
601 }
602
603 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
604 {
605 /* drain receive buffer */
606 while (mx51_ecspi_rx_available(spi_imx))
607 readl(spi_imx->base + MXC_CSPIRXDATA);
608 }
609
610 #define MX31_INTREG_TEEN (1 << 0)
611 #define MX31_INTREG_RREN (1 << 3)
612
613 #define MX31_CSPICTRL_ENABLE (1 << 0)
614 #define MX31_CSPICTRL_MASTER (1 << 1)
615 #define MX31_CSPICTRL_XCH (1 << 2)
616 #define MX31_CSPICTRL_SMC (1 << 3)
617 #define MX31_CSPICTRL_POL (1 << 4)
618 #define MX31_CSPICTRL_PHA (1 << 5)
619 #define MX31_CSPICTRL_SSCTL (1 << 6)
620 #define MX31_CSPICTRL_SSPOL (1 << 7)
621 #define MX31_CSPICTRL_BC_SHIFT 8
622 #define MX35_CSPICTRL_BL_SHIFT 20
623 #define MX31_CSPICTRL_CS_SHIFT 24
624 #define MX35_CSPICTRL_CS_SHIFT 12
625 #define MX31_CSPICTRL_DR_SHIFT 16
626
627 #define MX31_CSPI_DMAREG 0x10
628 #define MX31_DMAREG_RH_DEN (1<<4)
629 #define MX31_DMAREG_TH_DEN (1<<1)
630
631 #define MX31_CSPISTATUS 0x14
632 #define MX31_STATUS_RR (1 << 3)
633
634 #define MX31_CSPI_TESTREG 0x1C
635 #define MX31_TEST_LBC (1 << 14)
636
637 /* These functions also work for the i.MX35, but be aware that
638 * the i.MX35 has a slightly different register layout for bits
639 * we do not use here.
640 */
641 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
642 {
643 unsigned int val = 0;
644
645 if (enable & MXC_INT_TE)
646 val |= MX31_INTREG_TEEN;
647 if (enable & MXC_INT_RR)
648 val |= MX31_INTREG_RREN;
649
650 writel(val, spi_imx->base + MXC_CSPIINT);
651 }
652
653 static void mx31_trigger(struct spi_imx_data *spi_imx)
654 {
655 unsigned int reg;
656
657 reg = readl(spi_imx->base + MXC_CSPICTRL);
658 reg |= MX31_CSPICTRL_XCH;
659 writel(reg, spi_imx->base + MXC_CSPICTRL);
660 }
661
662 static int mx31_config(struct spi_device *spi)
663 {
664 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
665 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
666 unsigned int clk;
667
668 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
669 MX31_CSPICTRL_DR_SHIFT;
670 spi_imx->spi_bus_clk = clk;
671
672 if (is_imx35_cspi(spi_imx)) {
673 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
674 reg |= MX31_CSPICTRL_SSCTL;
675 } else {
676 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
677 }
678
679 if (spi->mode & SPI_CPHA)
680 reg |= MX31_CSPICTRL_PHA;
681 if (spi->mode & SPI_CPOL)
682 reg |= MX31_CSPICTRL_POL;
683 if (spi->mode & SPI_CS_HIGH)
684 reg |= MX31_CSPICTRL_SSPOL;
685 if (!gpio_is_valid(spi->cs_gpio))
686 reg |= (spi->chip_select) <<
687 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
688 MX31_CSPICTRL_CS_SHIFT);
689
690 if (spi_imx->usedma)
691 reg |= MX31_CSPICTRL_SMC;
692
693 writel(reg, spi_imx->base + MXC_CSPICTRL);
694
695 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
696 if (spi->mode & SPI_LOOP)
697 reg |= MX31_TEST_LBC;
698 else
699 reg &= ~MX31_TEST_LBC;
700 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
701
702 if (spi_imx->usedma) {
703 /* configure DMA requests when RXFIFO is half full and
704 when TXFIFO is half empty */
705 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
706 spi_imx->base + MX31_CSPI_DMAREG);
707 }
708
709 return 0;
710 }
711
712 static int mx31_rx_available(struct spi_imx_data *spi_imx)
713 {
714 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
715 }
716
717 static void mx31_reset(struct spi_imx_data *spi_imx)
718 {
719 /* drain receive buffer */
720 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
721 readl(spi_imx->base + MXC_CSPIRXDATA);
722 }
723
724 #define MX21_INTREG_RR (1 << 4)
725 #define MX21_INTREG_TEEN (1 << 9)
726 #define MX21_INTREG_RREN (1 << 13)
727
728 #define MX21_CSPICTRL_POL (1 << 5)
729 #define MX21_CSPICTRL_PHA (1 << 6)
730 #define MX21_CSPICTRL_SSPOL (1 << 8)
731 #define MX21_CSPICTRL_XCH (1 << 9)
732 #define MX21_CSPICTRL_ENABLE (1 << 10)
733 #define MX21_CSPICTRL_MASTER (1 << 11)
734 #define MX21_CSPICTRL_DR_SHIFT 14
735 #define MX21_CSPICTRL_CS_SHIFT 19
736
737 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
738 {
739 unsigned int val = 0;
740
741 if (enable & MXC_INT_TE)
742 val |= MX21_INTREG_TEEN;
743 if (enable & MXC_INT_RR)
744 val |= MX21_INTREG_RREN;
745
746 writel(val, spi_imx->base + MXC_CSPIINT);
747 }
748
749 static void mx21_trigger(struct spi_imx_data *spi_imx)
750 {
751 unsigned int reg;
752
753 reg = readl(spi_imx->base + MXC_CSPICTRL);
754 reg |= MX21_CSPICTRL_XCH;
755 writel(reg, spi_imx->base + MXC_CSPICTRL);
756 }
757
758 static int mx21_config(struct spi_device *spi)
759 {
760 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
761 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
762 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
763 unsigned int clk;
764
765 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->speed_hz, max, &clk)
766 << MX21_CSPICTRL_DR_SHIFT;
767 spi_imx->spi_bus_clk = clk;
768
769 reg |= spi_imx->bits_per_word - 1;
770
771 if (spi->mode & SPI_CPHA)
772 reg |= MX21_CSPICTRL_PHA;
773 if (spi->mode & SPI_CPOL)
774 reg |= MX21_CSPICTRL_POL;
775 if (spi->mode & SPI_CS_HIGH)
776 reg |= MX21_CSPICTRL_SSPOL;
777 if (!gpio_is_valid(spi->cs_gpio))
778 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
779
780 writel(reg, spi_imx->base + MXC_CSPICTRL);
781
782 return 0;
783 }
784
785 static int mx21_rx_available(struct spi_imx_data *spi_imx)
786 {
787 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
788 }
789
790 static void mx21_reset(struct spi_imx_data *spi_imx)
791 {
792 writel(1, spi_imx->base + MXC_RESET);
793 }
794
795 #define MX1_INTREG_RR (1 << 3)
796 #define MX1_INTREG_TEEN (1 << 8)
797 #define MX1_INTREG_RREN (1 << 11)
798
799 #define MX1_CSPICTRL_POL (1 << 4)
800 #define MX1_CSPICTRL_PHA (1 << 5)
801 #define MX1_CSPICTRL_XCH (1 << 8)
802 #define MX1_CSPICTRL_ENABLE (1 << 9)
803 #define MX1_CSPICTRL_MASTER (1 << 10)
804 #define MX1_CSPICTRL_DR_SHIFT 13
805
806 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
807 {
808 unsigned int val = 0;
809
810 if (enable & MXC_INT_TE)
811 val |= MX1_INTREG_TEEN;
812 if (enable & MXC_INT_RR)
813 val |= MX1_INTREG_RREN;
814
815 writel(val, spi_imx->base + MXC_CSPIINT);
816 }
817
818 static void mx1_trigger(struct spi_imx_data *spi_imx)
819 {
820 unsigned int reg;
821
822 reg = readl(spi_imx->base + MXC_CSPICTRL);
823 reg |= MX1_CSPICTRL_XCH;
824 writel(reg, spi_imx->base + MXC_CSPICTRL);
825 }
826
827 static int mx1_config(struct spi_device *spi)
828 {
829 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
830 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
831 unsigned int clk;
832
833 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
834 MX1_CSPICTRL_DR_SHIFT;
835 spi_imx->spi_bus_clk = clk;
836
837 reg |= spi_imx->bits_per_word - 1;
838
839 if (spi->mode & SPI_CPHA)
840 reg |= MX1_CSPICTRL_PHA;
841 if (spi->mode & SPI_CPOL)
842 reg |= MX1_CSPICTRL_POL;
843
844 writel(reg, spi_imx->base + MXC_CSPICTRL);
845
846 return 0;
847 }
848
849 static int mx1_rx_available(struct spi_imx_data *spi_imx)
850 {
851 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
852 }
853
854 static void mx1_reset(struct spi_imx_data *spi_imx)
855 {
856 writel(1, spi_imx->base + MXC_RESET);
857 }
858
859 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
860 .intctrl = mx1_intctrl,
861 .config = mx1_config,
862 .trigger = mx1_trigger,
863 .rx_available = mx1_rx_available,
864 .reset = mx1_reset,
865 .fifo_size = 8,
866 .has_dmamode = false,
867 .dynamic_burst = false,
868 .has_slavemode = false,
869 .devtype = IMX1_CSPI,
870 };
871
872 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
873 .intctrl = mx21_intctrl,
874 .config = mx21_config,
875 .trigger = mx21_trigger,
876 .rx_available = mx21_rx_available,
877 .reset = mx21_reset,
878 .fifo_size = 8,
879 .has_dmamode = false,
880 .dynamic_burst = false,
881 .has_slavemode = false,
882 .devtype = IMX21_CSPI,
883 };
884
885 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
886 /* i.mx27 cspi shares the functions with i.mx21 one */
887 .intctrl = mx21_intctrl,
888 .config = mx21_config,
889 .trigger = mx21_trigger,
890 .rx_available = mx21_rx_available,
891 .reset = mx21_reset,
892 .fifo_size = 8,
893 .has_dmamode = false,
894 .dynamic_burst = false,
895 .has_slavemode = false,
896 .devtype = IMX27_CSPI,
897 };
898
899 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
900 .intctrl = mx31_intctrl,
901 .config = mx31_config,
902 .trigger = mx31_trigger,
903 .rx_available = mx31_rx_available,
904 .reset = mx31_reset,
905 .fifo_size = 8,
906 .has_dmamode = false,
907 .dynamic_burst = false,
908 .has_slavemode = false,
909 .devtype = IMX31_CSPI,
910 };
911
912 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
913 /* i.mx35 and later cspi shares the functions with i.mx31 one */
914 .intctrl = mx31_intctrl,
915 .config = mx31_config,
916 .trigger = mx31_trigger,
917 .rx_available = mx31_rx_available,
918 .reset = mx31_reset,
919 .fifo_size = 8,
920 .has_dmamode = true,
921 .dynamic_burst = false,
922 .has_slavemode = false,
923 .devtype = IMX35_CSPI,
924 };
925
926 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
927 .intctrl = mx51_ecspi_intctrl,
928 .config = mx51_ecspi_config,
929 .trigger = mx51_ecspi_trigger,
930 .rx_available = mx51_ecspi_rx_available,
931 .reset = mx51_ecspi_reset,
932 .setup_wml = mx51_setup_wml,
933 .fifo_size = 64,
934 .has_dmamode = true,
935 .dynamic_burst = true,
936 .has_slavemode = true,
937 .disable = mx51_ecspi_disable,
938 .devtype = IMX51_ECSPI,
939 };
940
941 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
942 .intctrl = mx51_ecspi_intctrl,
943 .config = mx51_ecspi_config,
944 .trigger = mx51_ecspi_trigger,
945 .rx_available = mx51_ecspi_rx_available,
946 .reset = mx51_ecspi_reset,
947 .fifo_size = 64,
948 .has_dmamode = true,
949 .has_slavemode = true,
950 .disable = mx51_ecspi_disable,
951 .devtype = IMX53_ECSPI,
952 };
953
954 static const struct platform_device_id spi_imx_devtype[] = {
955 {
956 .name = "imx1-cspi",
957 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
958 }, {
959 .name = "imx21-cspi",
960 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
961 }, {
962 .name = "imx27-cspi",
963 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
964 }, {
965 .name = "imx31-cspi",
966 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
967 }, {
968 .name = "imx35-cspi",
969 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
970 }, {
971 .name = "imx51-ecspi",
972 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
973 }, {
974 .name = "imx53-ecspi",
975 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
976 }, {
977 /* sentinel */
978 }
979 };
980
981 static const struct of_device_id spi_imx_dt_ids[] = {
982 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
983 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
984 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
985 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
986 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
987 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
988 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
989 { /* sentinel */ }
990 };
991 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
992
993 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
994 {
995 int active = is_active != BITBANG_CS_INACTIVE;
996 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
997
998 if (spi->mode & SPI_NO_CS)
999 return;
1000
1001 if (!gpio_is_valid(spi->cs_gpio))
1002 return;
1003
1004 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
1005 }
1006
1007 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1008 {
1009 u32 ctrl;
1010
1011 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1012 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1013 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1014 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1015 }
1016
1017 static void spi_imx_push(struct spi_imx_data *spi_imx)
1018 {
1019 unsigned int burst_len, fifo_words;
1020
1021 if (spi_imx->dynamic_burst)
1022 fifo_words = 4;
1023 else
1024 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1025 /*
1026 * Reload the FIFO when the remaining bytes to be transferred in the
1027 * current burst is 0. This only applies when bits_per_word is a
1028 * multiple of 8.
1029 */
1030 if (!spi_imx->remainder) {
1031 if (spi_imx->dynamic_burst) {
1032
1033 /* We need to deal unaligned data first */
1034 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1035
1036 if (!burst_len)
1037 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1038
1039 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1040
1041 spi_imx->remainder = burst_len;
1042 } else {
1043 spi_imx->remainder = fifo_words;
1044 }
1045 }
1046
1047 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1048 if (!spi_imx->count)
1049 break;
1050 if (spi_imx->dynamic_burst &&
1051 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
1052 fifo_words))
1053 break;
1054 spi_imx->tx(spi_imx);
1055 spi_imx->txfifo++;
1056 }
1057
1058 if (!spi_imx->slave_mode)
1059 spi_imx->devtype_data->trigger(spi_imx);
1060 }
1061
1062 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1063 {
1064 struct spi_imx_data *spi_imx = dev_id;
1065
1066 while (spi_imx->txfifo &&
1067 spi_imx->devtype_data->rx_available(spi_imx)) {
1068 spi_imx->rx(spi_imx);
1069 spi_imx->txfifo--;
1070 }
1071
1072 if (spi_imx->count) {
1073 spi_imx_push(spi_imx);
1074 return IRQ_HANDLED;
1075 }
1076
1077 if (spi_imx->txfifo) {
1078 /* No data left to push, but still waiting for rx data,
1079 * enable receive data available interrupt.
1080 */
1081 spi_imx->devtype_data->intctrl(
1082 spi_imx, MXC_INT_RR);
1083 return IRQ_HANDLED;
1084 }
1085
1086 spi_imx->devtype_data->intctrl(spi_imx, 0);
1087 complete(&spi_imx->xfer_done);
1088
1089 return IRQ_HANDLED;
1090 }
1091
1092 static int spi_imx_dma_configure(struct spi_master *master)
1093 {
1094 int ret;
1095 enum dma_slave_buswidth buswidth;
1096 struct dma_slave_config rx = {}, tx = {};
1097 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1098
1099 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1100 case 4:
1101 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1102 break;
1103 case 2:
1104 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1105 break;
1106 case 1:
1107 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1108 break;
1109 default:
1110 return -EINVAL;
1111 }
1112
1113 tx.direction = DMA_MEM_TO_DEV;
1114 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1115 tx.dst_addr_width = buswidth;
1116 tx.dst_maxburst = spi_imx->wml;
1117 ret = dmaengine_slave_config(master->dma_tx, &tx);
1118 if (ret) {
1119 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1120 return ret;
1121 }
1122
1123 rx.direction = DMA_DEV_TO_MEM;
1124 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1125 rx.src_addr_width = buswidth;
1126 rx.src_maxburst = spi_imx->wml;
1127 ret = dmaengine_slave_config(master->dma_rx, &rx);
1128 if (ret) {
1129 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1130 return ret;
1131 }
1132
1133 return 0;
1134 }
1135
1136 static int spi_imx_setupxfer(struct spi_device *spi,
1137 struct spi_transfer *t)
1138 {
1139 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1140
1141 if (!t)
1142 return 0;
1143
1144 spi_imx->bits_per_word = t->bits_per_word;
1145 spi_imx->speed_hz = t->speed_hz;
1146
1147 /*
1148 * Initialize the functions for transfer. To transfer non byte-aligned
1149 * words, we have to use multiple word-size bursts, we can't use
1150 * dynamic_burst in that case.
1151 */
1152 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
1153 (spi_imx->bits_per_word == 8 ||
1154 spi_imx->bits_per_word == 16 ||
1155 spi_imx->bits_per_word == 32)) {
1156
1157 spi_imx->rx = spi_imx_buf_rx_swap;
1158 spi_imx->tx = spi_imx_buf_tx_swap;
1159 spi_imx->dynamic_burst = 1;
1160
1161 } else {
1162 if (spi_imx->bits_per_word <= 8) {
1163 spi_imx->rx = spi_imx_buf_rx_u8;
1164 spi_imx->tx = spi_imx_buf_tx_u8;
1165 } else if (spi_imx->bits_per_word <= 16) {
1166 spi_imx->rx = spi_imx_buf_rx_u16;
1167 spi_imx->tx = spi_imx_buf_tx_u16;
1168 } else {
1169 spi_imx->rx = spi_imx_buf_rx_u32;
1170 spi_imx->tx = spi_imx_buf_tx_u32;
1171 }
1172 spi_imx->dynamic_burst = 0;
1173 }
1174
1175 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1176 spi_imx->usedma = 1;
1177 else
1178 spi_imx->usedma = 0;
1179
1180 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1181 spi_imx->rx = mx53_ecspi_rx_slave;
1182 spi_imx->tx = mx53_ecspi_tx_slave;
1183 spi_imx->slave_burst = t->len;
1184 }
1185
1186 spi_imx->devtype_data->config(spi);
1187
1188 return 0;
1189 }
1190
1191 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1192 {
1193 struct spi_master *master = spi_imx->bitbang.master;
1194
1195 if (master->dma_rx) {
1196 dma_release_channel(master->dma_rx);
1197 master->dma_rx = NULL;
1198 }
1199
1200 if (master->dma_tx) {
1201 dma_release_channel(master->dma_tx);
1202 master->dma_tx = NULL;
1203 }
1204 }
1205
1206 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1207 struct spi_master *master)
1208 {
1209 int ret;
1210
1211 /* use pio mode for i.mx6dl chip TKT238285 */
1212 if (of_machine_is_compatible("fsl,imx6dl"))
1213 return 0;
1214
1215 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1216
1217 /* Prepare for TX DMA: */
1218 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
1219 if (IS_ERR(master->dma_tx)) {
1220 ret = PTR_ERR(master->dma_tx);
1221 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1222 master->dma_tx = NULL;
1223 goto err;
1224 }
1225
1226 /* Prepare for RX : */
1227 master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
1228 if (IS_ERR(master->dma_rx)) {
1229 ret = PTR_ERR(master->dma_rx);
1230 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1231 master->dma_rx = NULL;
1232 goto err;
1233 }
1234
1235 init_completion(&spi_imx->dma_rx_completion);
1236 init_completion(&spi_imx->dma_tx_completion);
1237 master->can_dma = spi_imx_can_dma;
1238 master->max_dma_len = MAX_SDMA_BD_BYTES;
1239 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1240 SPI_MASTER_MUST_TX;
1241
1242 return 0;
1243 err:
1244 spi_imx_sdma_exit(spi_imx);
1245 return ret;
1246 }
1247
1248 static void spi_imx_dma_rx_callback(void *cookie)
1249 {
1250 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1251
1252 complete(&spi_imx->dma_rx_completion);
1253 }
1254
1255 static void spi_imx_dma_tx_callback(void *cookie)
1256 {
1257 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1258
1259 complete(&spi_imx->dma_tx_completion);
1260 }
1261
1262 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1263 {
1264 unsigned long timeout = 0;
1265
1266 /* Time with actual data transfer and CS change delay related to HW */
1267 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1268
1269 /* Add extra second for scheduler related activities */
1270 timeout += 1;
1271
1272 /* Double calculated timeout */
1273 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1274 }
1275
1276 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1277 struct spi_transfer *transfer)
1278 {
1279 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1280 unsigned long transfer_timeout;
1281 unsigned long timeout;
1282 struct spi_master *master = spi_imx->bitbang.master;
1283 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1284 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1285 unsigned int bytes_per_word, i;
1286 int ret;
1287
1288 /* Get the right burst length from the last sg to ensure no tail data */
1289 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1290 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1291 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1292 break;
1293 }
1294 /* Use 1 as wml in case no available burst length got */
1295 if (i == 0)
1296 i = 1;
1297
1298 spi_imx->wml = i;
1299
1300 ret = spi_imx_dma_configure(master);
1301 if (ret)
1302 return ret;
1303
1304 if (!spi_imx->devtype_data->setup_wml) {
1305 dev_err(spi_imx->dev, "No setup_wml()?\n");
1306 return -EINVAL;
1307 }
1308 spi_imx->devtype_data->setup_wml(spi_imx);
1309
1310 /*
1311 * The TX DMA setup starts the transfer, so make sure RX is configured
1312 * before TX.
1313 */
1314 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1315 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1316 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1317 if (!desc_rx)
1318 return -EINVAL;
1319
1320 desc_rx->callback = spi_imx_dma_rx_callback;
1321 desc_rx->callback_param = (void *)spi_imx;
1322 dmaengine_submit(desc_rx);
1323 reinit_completion(&spi_imx->dma_rx_completion);
1324 dma_async_issue_pending(master->dma_rx);
1325
1326 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1327 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1328 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1329 if (!desc_tx) {
1330 dmaengine_terminate_all(master->dma_tx);
1331 return -EINVAL;
1332 }
1333
1334 desc_tx->callback = spi_imx_dma_tx_callback;
1335 desc_tx->callback_param = (void *)spi_imx;
1336 dmaengine_submit(desc_tx);
1337 reinit_completion(&spi_imx->dma_tx_completion);
1338 dma_async_issue_pending(master->dma_tx);
1339
1340 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1341
1342 /* Wait SDMA to finish the data transfer.*/
1343 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1344 transfer_timeout);
1345 if (!timeout) {
1346 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1347 dmaengine_terminate_all(master->dma_tx);
1348 dmaengine_terminate_all(master->dma_rx);
1349 return -ETIMEDOUT;
1350 }
1351
1352 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1353 transfer_timeout);
1354 if (!timeout) {
1355 dev_err(&master->dev, "I/O Error in DMA RX\n");
1356 spi_imx->devtype_data->reset(spi_imx);
1357 dmaengine_terminate_all(master->dma_rx);
1358 return -ETIMEDOUT;
1359 }
1360
1361 return transfer->len;
1362 }
1363
1364 static int spi_imx_pio_transfer(struct spi_device *spi,
1365 struct spi_transfer *transfer)
1366 {
1367 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1368 unsigned long transfer_timeout;
1369 unsigned long timeout;
1370
1371 spi_imx->tx_buf = transfer->tx_buf;
1372 spi_imx->rx_buf = transfer->rx_buf;
1373 spi_imx->count = transfer->len;
1374 spi_imx->txfifo = 0;
1375 spi_imx->remainder = 0;
1376
1377 reinit_completion(&spi_imx->xfer_done);
1378
1379 spi_imx_push(spi_imx);
1380
1381 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1382
1383 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1384
1385 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1386 transfer_timeout);
1387 if (!timeout) {
1388 dev_err(&spi->dev, "I/O Error in PIO\n");
1389 spi_imx->devtype_data->reset(spi_imx);
1390 return -ETIMEDOUT;
1391 }
1392
1393 return transfer->len;
1394 }
1395
1396 static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1397 struct spi_transfer *transfer)
1398 {
1399 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1400 int ret = transfer->len;
1401
1402 if (is_imx53_ecspi(spi_imx) &&
1403 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1404 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1405 MX53_MAX_TRANSFER_BYTES);
1406 return -EMSGSIZE;
1407 }
1408
1409 spi_imx->tx_buf = transfer->tx_buf;
1410 spi_imx->rx_buf = transfer->rx_buf;
1411 spi_imx->count = transfer->len;
1412 spi_imx->txfifo = 0;
1413 spi_imx->remainder = 0;
1414
1415 reinit_completion(&spi_imx->xfer_done);
1416 spi_imx->slave_aborted = false;
1417
1418 spi_imx_push(spi_imx);
1419
1420 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1421
1422 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1423 spi_imx->slave_aborted) {
1424 dev_dbg(&spi->dev, "interrupted\n");
1425 ret = -EINTR;
1426 }
1427
1428 /* ecspi has a HW issue when works in Slave mode,
1429 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1430 * ECSPI_TXDATA keeps shift out the last word data,
1431 * so we have to disable ECSPI when in slave mode after the
1432 * transfer completes
1433 */
1434 if (spi_imx->devtype_data->disable)
1435 spi_imx->devtype_data->disable(spi_imx);
1436
1437 return ret;
1438 }
1439
1440 static int spi_imx_transfer(struct spi_device *spi,
1441 struct spi_transfer *transfer)
1442 {
1443 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1444
1445 /* flush rxfifo before transfer */
1446 while (spi_imx->devtype_data->rx_available(spi_imx))
1447 spi_imx->rx(spi_imx);
1448
1449 if (spi_imx->slave_mode)
1450 return spi_imx_pio_transfer_slave(spi, transfer);
1451
1452 if (spi_imx->usedma)
1453 return spi_imx_dma_transfer(spi_imx, transfer);
1454 else
1455 return spi_imx_pio_transfer(spi, transfer);
1456 }
1457
1458 static int spi_imx_setup(struct spi_device *spi)
1459 {
1460 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1461 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1462
1463 if (spi->mode & SPI_NO_CS)
1464 return 0;
1465
1466 if (gpio_is_valid(spi->cs_gpio))
1467 gpio_direction_output(spi->cs_gpio,
1468 spi->mode & SPI_CS_HIGH ? 0 : 1);
1469
1470 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1471
1472 return 0;
1473 }
1474
1475 static void spi_imx_cleanup(struct spi_device *spi)
1476 {
1477 }
1478
1479 static int
1480 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1481 {
1482 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1483 int ret;
1484
1485 ret = clk_enable(spi_imx->clk_per);
1486 if (ret)
1487 return ret;
1488
1489 ret = clk_enable(spi_imx->clk_ipg);
1490 if (ret) {
1491 clk_disable(spi_imx->clk_per);
1492 return ret;
1493 }
1494
1495 return 0;
1496 }
1497
1498 static int
1499 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1500 {
1501 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1502
1503 clk_disable(spi_imx->clk_ipg);
1504 clk_disable(spi_imx->clk_per);
1505 return 0;
1506 }
1507
1508 static int spi_imx_slave_abort(struct spi_master *master)
1509 {
1510 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1511
1512 spi_imx->slave_aborted = true;
1513 complete(&spi_imx->xfer_done);
1514
1515 return 0;
1516 }
1517
1518 static int spi_imx_probe(struct platform_device *pdev)
1519 {
1520 struct device_node *np = pdev->dev.of_node;
1521 const struct of_device_id *of_id =
1522 of_match_device(spi_imx_dt_ids, &pdev->dev);
1523 struct spi_imx_master *mxc_platform_info =
1524 dev_get_platdata(&pdev->dev);
1525 struct spi_master *master;
1526 struct spi_imx_data *spi_imx;
1527 struct resource *res;
1528 int i, ret, irq, spi_drctl;
1529 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1530 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1531 bool slave_mode;
1532
1533 if (!np && !mxc_platform_info) {
1534 dev_err(&pdev->dev, "can't get the platform data\n");
1535 return -EINVAL;
1536 }
1537
1538 slave_mode = devtype_data->has_slavemode &&
1539 of_property_read_bool(np, "spi-slave");
1540 if (slave_mode)
1541 master = spi_alloc_slave(&pdev->dev,
1542 sizeof(struct spi_imx_data));
1543 else
1544 master = spi_alloc_master(&pdev->dev,
1545 sizeof(struct spi_imx_data));
1546 if (!master)
1547 return -ENOMEM;
1548
1549 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1550 if ((ret < 0) || (spi_drctl >= 0x3)) {
1551 /* '11' is reserved */
1552 spi_drctl = 0;
1553 }
1554
1555 platform_set_drvdata(pdev, master);
1556
1557 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1558 master->bus_num = np ? -1 : pdev->id;
1559
1560 spi_imx = spi_master_get_devdata(master);
1561 spi_imx->bitbang.master = master;
1562 spi_imx->dev = &pdev->dev;
1563 spi_imx->slave_mode = slave_mode;
1564
1565 spi_imx->devtype_data = devtype_data;
1566
1567 /* Get number of chip selects, either platform data or OF */
1568 if (mxc_platform_info) {
1569 master->num_chipselect = mxc_platform_info->num_chipselect;
1570 if (mxc_platform_info->chipselect) {
1571 master->cs_gpios = devm_kcalloc(&master->dev,
1572 master->num_chipselect, sizeof(int),
1573 GFP_KERNEL);
1574 if (!master->cs_gpios)
1575 return -ENOMEM;
1576
1577 for (i = 0; i < master->num_chipselect; i++)
1578 master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1579 }
1580 } else {
1581 u32 num_cs;
1582
1583 if (!of_property_read_u32(np, "num-cs", &num_cs))
1584 master->num_chipselect = num_cs;
1585 /* If not preset, default value of 1 is used */
1586 }
1587
1588 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1589 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1590 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1591 spi_imx->bitbang.master->setup = spi_imx_setup;
1592 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1593 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1594 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1595 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1596 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1597 | SPI_NO_CS;
1598 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1599 is_imx53_ecspi(spi_imx))
1600 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1601
1602 spi_imx->spi_drctl = spi_drctl;
1603
1604 init_completion(&spi_imx->xfer_done);
1605
1606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1607 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1608 if (IS_ERR(spi_imx->base)) {
1609 ret = PTR_ERR(spi_imx->base);
1610 goto out_master_put;
1611 }
1612 spi_imx->base_phys = res->start;
1613
1614 irq = platform_get_irq(pdev, 0);
1615 if (irq < 0) {
1616 ret = irq;
1617 goto out_master_put;
1618 }
1619
1620 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1621 dev_name(&pdev->dev), spi_imx);
1622 if (ret) {
1623 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1624 goto out_master_put;
1625 }
1626
1627 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1628 if (IS_ERR(spi_imx->clk_ipg)) {
1629 ret = PTR_ERR(spi_imx->clk_ipg);
1630 goto out_master_put;
1631 }
1632
1633 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1634 if (IS_ERR(spi_imx->clk_per)) {
1635 ret = PTR_ERR(spi_imx->clk_per);
1636 goto out_master_put;
1637 }
1638
1639 ret = clk_prepare_enable(spi_imx->clk_per);
1640 if (ret)
1641 goto out_master_put;
1642
1643 ret = clk_prepare_enable(spi_imx->clk_ipg);
1644 if (ret)
1645 goto out_put_per;
1646
1647 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1648 /*
1649 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1650 * if validated on other chips.
1651 */
1652 if (spi_imx->devtype_data->has_dmamode) {
1653 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1654 if (ret == -EPROBE_DEFER)
1655 goto out_clk_put;
1656
1657 if (ret < 0)
1658 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1659 ret);
1660 }
1661
1662 spi_imx->devtype_data->reset(spi_imx);
1663
1664 spi_imx->devtype_data->intctrl(spi_imx, 0);
1665
1666 master->dev.of_node = pdev->dev.of_node;
1667 ret = spi_bitbang_start(&spi_imx->bitbang);
1668 if (ret) {
1669 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1670 goto out_clk_put;
1671 }
1672
1673 /* Request GPIO CS lines, if any */
1674 if (!spi_imx->slave_mode && master->cs_gpios) {
1675 for (i = 0; i < master->num_chipselect; i++) {
1676 if (!gpio_is_valid(master->cs_gpios[i]))
1677 continue;
1678
1679 ret = devm_gpio_request(&pdev->dev,
1680 master->cs_gpios[i],
1681 DRIVER_NAME);
1682 if (ret) {
1683 dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1684 master->cs_gpios[i]);
1685 goto out_spi_bitbang;
1686 }
1687 }
1688 }
1689
1690 dev_info(&pdev->dev, "probed\n");
1691
1692 clk_disable(spi_imx->clk_ipg);
1693 clk_disable(spi_imx->clk_per);
1694 return ret;
1695
1696 out_spi_bitbang:
1697 spi_bitbang_stop(&spi_imx->bitbang);
1698 out_clk_put:
1699 clk_disable_unprepare(spi_imx->clk_ipg);
1700 out_put_per:
1701 clk_disable_unprepare(spi_imx->clk_per);
1702 out_master_put:
1703 spi_master_put(master);
1704
1705 return ret;
1706 }
1707
1708 static int spi_imx_remove(struct platform_device *pdev)
1709 {
1710 struct spi_master *master = platform_get_drvdata(pdev);
1711 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1712 int ret;
1713
1714 spi_bitbang_stop(&spi_imx->bitbang);
1715
1716 ret = clk_enable(spi_imx->clk_per);
1717 if (ret)
1718 return ret;
1719
1720 ret = clk_enable(spi_imx->clk_ipg);
1721 if (ret) {
1722 clk_disable(spi_imx->clk_per);
1723 return ret;
1724 }
1725
1726 writel(0, spi_imx->base + MXC_CSPICTRL);
1727 clk_disable_unprepare(spi_imx->clk_ipg);
1728 clk_disable_unprepare(spi_imx->clk_per);
1729 spi_imx_sdma_exit(spi_imx);
1730 spi_master_put(master);
1731
1732 return 0;
1733 }
1734
1735 static struct platform_driver spi_imx_driver = {
1736 .driver = {
1737 .name = DRIVER_NAME,
1738 .of_match_table = spi_imx_dt_ids,
1739 },
1740 .id_table = spi_imx_devtype,
1741 .probe = spi_imx_probe,
1742 .remove = spi_imx_remove,
1743 };
1744 module_platform_driver(spi_imx_driver);
1745
1746 MODULE_DESCRIPTION("SPI Controller driver");
1747 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1748 MODULE_LICENSE("GPL");
1749 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support