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[SCSI] qla2xxx: Do link initialization on get loop id failure.
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_dbg.c
blob65e95bdce704ff792876e7e46b2b66e7da6ab88c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2012 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7
8 /*
9 * Table for showing the current message id in use for particular level
10 * Change this table for addition of log/debug messages.
11 * ----------------------------------------------------------------------
12 * | Level | Last Value Used | Holes |
13 * ----------------------------------------------------------------------
14 * | Module Init and Probe | 0x0126 | 0x4b,0xba,0xfa |
15 * | Mailbox commands | 0x1154 | 0x111a-0x111b |
16 * | | | 0x112c-0x112e |
17 * | | | 0x113a |
18 * | Device Discovery | 0x2087 | 0x2020-0x2022, |
19 * | | | 0x2016 |
20 * | Queue Command and IO tracing | 0x3031 | 0x3006-0x300b |
21 * | | | 0x3027-0x3028 |
22 * | | | 0x302d-0x302e |
23 * | DPC Thread | 0x401d | 0x4002,0x4013 |
24 * | Async Events | 0x5071 | 0x502b-0x502f |
25 * | | | 0x5047,0x5052 |
26 * | Timer Routines | 0x6011 | |
27 * | User Space Interactions | 0x70c4 | 0x7018,0x702e, |
28 * | | | 0x7020,0x7024, |
29 * | | | 0x7039,0x7045, |
30 * | | | 0x7073-0x7075, |
31 * | | | 0x708c, |
32 * | | | 0x70a5,0x70a6, |
33 * | | | 0x70a8,0x70ab, |
34 * | | | 0x70ad-0x70ae |
35 * | Task Management | 0x803c | 0x8025-0x8026 |
36 * | | | 0x800b,0x8039 |
37 * | AER/EEH | 0x9011 | |
38 * | Virtual Port | 0xa007 | |
39 * | ISP82XX Specific | 0xb084 | 0xb002,0xb024 |
40 * | MultiQ | 0xc00c | |
41 * | Misc | 0xd010 | |
42 * | Target Mode | 0xe070 | |
43 * | Target Mode Management | 0xf072 | |
44 * | Target Mode Task Management | 0x1000b | |
45 * ----------------------------------------------------------------------
46 */
47
48 #include "qla_def.h"
49
50 #include <linux/delay.h>
51
52 static uint32_t ql_dbg_offset = 0x800;
53
54 static inline void
55 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
56 {
57 fw_dump->fw_major_version = htonl(ha->fw_major_version);
58 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
59 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
60 fw_dump->fw_attributes = htonl(ha->fw_attributes);
61
62 fw_dump->vendor = htonl(ha->pdev->vendor);
63 fw_dump->device = htonl(ha->pdev->device);
64 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
65 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
66 }
67
68 static inline void *
69 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
70 {
71 struct req_que *req = ha->req_q_map[0];
72 struct rsp_que *rsp = ha->rsp_q_map[0];
73 /* Request queue. */
74 memcpy(ptr, req->ring, req->length *
75 sizeof(request_t));
76
77 /* Response queue. */
78 ptr += req->length * sizeof(request_t);
79 memcpy(ptr, rsp->ring, rsp->length *
80 sizeof(response_t));
81
82 return ptr + (rsp->length * sizeof(response_t));
83 }
84
85 static int
86 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
87 uint32_t ram_dwords, void **nxt)
88 {
89 int rval;
90 uint32_t cnt, stat, timer, dwords, idx;
91 uint16_t mb0;
92 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
93 dma_addr_t dump_dma = ha->gid_list_dma;
94 uint32_t *dump = (uint32_t *)ha->gid_list;
95
96 rval = QLA_SUCCESS;
97 mb0 = 0;
98
99 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
100 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
101
102 dwords = qla2x00_gid_list_size(ha) / 4;
103 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
104 cnt += dwords, addr += dwords) {
105 if (cnt + dwords > ram_dwords)
106 dwords = ram_dwords - cnt;
107
108 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
109 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
110
111 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
112 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
113 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
114 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
115
116 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
117 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
118 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
119
120 for (timer = 6000000; timer; timer--) {
121 /* Check for pending interrupts. */
122 stat = RD_REG_DWORD(&reg->host_status);
123 if (stat & HSRX_RISC_INT) {
124 stat &= 0xff;
125
126 if (stat == 0x1 || stat == 0x2 ||
127 stat == 0x10 || stat == 0x11) {
128 set_bit(MBX_INTERRUPT,
129 &ha->mbx_cmd_flags);
130
131 mb0 = RD_REG_WORD(&reg->mailbox0);
132
133 WRT_REG_DWORD(&reg->hccr,
134 HCCRX_CLR_RISC_INT);
135 RD_REG_DWORD(&reg->hccr);
136 break;
137 }
138
139 /* Clear this intr; it wasn't a mailbox intr */
140 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
141 RD_REG_DWORD(&reg->hccr);
142 }
143 udelay(5);
144 }
145
146 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
147 rval = mb0 & MBS_MASK;
148 for (idx = 0; idx < dwords; idx++)
149 ram[cnt + idx] = swab32(dump[idx]);
150 } else {
151 rval = QLA_FUNCTION_FAILED;
152 }
153 }
154
155 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
156 return rval;
157 }
158
159 static int
160 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
161 uint32_t cram_size, void **nxt)
162 {
163 int rval;
164
165 /* Code RAM. */
166 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
167 if (rval != QLA_SUCCESS)
168 return rval;
169
170 /* External Memory. */
171 return qla24xx_dump_ram(ha, 0x100000, *nxt,
172 ha->fw_memory_size - 0x100000 + 1, nxt);
173 }
174
175 static uint32_t *
176 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
177 uint32_t count, uint32_t *buf)
178 {
179 uint32_t __iomem *dmp_reg;
180
181 WRT_REG_DWORD(&reg->iobase_addr, iobase);
182 dmp_reg = &reg->iobase_window;
183 while (count--)
184 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
185
186 return buf;
187 }
188
189 static inline int
190 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
191 {
192 int rval = QLA_SUCCESS;
193 uint32_t cnt;
194
195 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
196 for (cnt = 30000;
197 ((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
198 rval == QLA_SUCCESS; cnt--) {
199 if (cnt)
200 udelay(100);
201 else
202 rval = QLA_FUNCTION_TIMEOUT;
203 }
204
205 return rval;
206 }
207
208 static int
209 qla24xx_soft_reset(struct qla_hw_data *ha)
210 {
211 int rval = QLA_SUCCESS;
212 uint32_t cnt;
213 uint16_t mb0, wd;
214 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
215
216 /* Reset RISC. */
217 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
218 for (cnt = 0; cnt < 30000; cnt++) {
219 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
220 break;
221
222 udelay(10);
223 }
224
225 WRT_REG_DWORD(&reg->ctrl_status,
226 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
227 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
228
229 udelay(100);
230 /* Wait for firmware to complete NVRAM accesses. */
231 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
232 for (cnt = 10000 ; cnt && mb0; cnt--) {
233 udelay(5);
234 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
235 barrier();
236 }
237
238 /* Wait for soft-reset to complete. */
239 for (cnt = 0; cnt < 30000; cnt++) {
240 if ((RD_REG_DWORD(&reg->ctrl_status) &
241 CSRX_ISP_SOFT_RESET) == 0)
242 break;
243
244 udelay(10);
245 }
246 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
247 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
248
249 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
250 rval == QLA_SUCCESS; cnt--) {
251 if (cnt)
252 udelay(100);
253 else
254 rval = QLA_FUNCTION_TIMEOUT;
255 }
256
257 return rval;
258 }
259
260 static int
261 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
262 uint32_t ram_words, void **nxt)
263 {
264 int rval;
265 uint32_t cnt, stat, timer, words, idx;
266 uint16_t mb0;
267 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
268 dma_addr_t dump_dma = ha->gid_list_dma;
269 uint16_t *dump = (uint16_t *)ha->gid_list;
270
271 rval = QLA_SUCCESS;
272 mb0 = 0;
273
274 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
275 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
276
277 words = qla2x00_gid_list_size(ha) / 2;
278 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
279 cnt += words, addr += words) {
280 if (cnt + words > ram_words)
281 words = ram_words - cnt;
282
283 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
284 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
285
286 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
287 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
288 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
289 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
290
291 WRT_MAILBOX_REG(ha, reg, 4, words);
292 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
293
294 for (timer = 6000000; timer; timer--) {
295 /* Check for pending interrupts. */
296 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
297 if (stat & HSR_RISC_INT) {
298 stat &= 0xff;
299
300 if (stat == 0x1 || stat == 0x2) {
301 set_bit(MBX_INTERRUPT,
302 &ha->mbx_cmd_flags);
303
304 mb0 = RD_MAILBOX_REG(ha, reg, 0);
305
306 /* Release mailbox registers. */
307 WRT_REG_WORD(&reg->semaphore, 0);
308 WRT_REG_WORD(&reg->hccr,
309 HCCR_CLR_RISC_INT);
310 RD_REG_WORD(&reg->hccr);
311 break;
312 } else if (stat == 0x10 || stat == 0x11) {
313 set_bit(MBX_INTERRUPT,
314 &ha->mbx_cmd_flags);
315
316 mb0 = RD_MAILBOX_REG(ha, reg, 0);
317
318 WRT_REG_WORD(&reg->hccr,
319 HCCR_CLR_RISC_INT);
320 RD_REG_WORD(&reg->hccr);
321 break;
322 }
323
324 /* clear this intr; it wasn't a mailbox intr */
325 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
326 RD_REG_WORD(&reg->hccr);
327 }
328 udelay(5);
329 }
330
331 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
332 rval = mb0 & MBS_MASK;
333 for (idx = 0; idx < words; idx++)
334 ram[cnt + idx] = swab16(dump[idx]);
335 } else {
336 rval = QLA_FUNCTION_FAILED;
337 }
338 }
339
340 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
341 return rval;
342 }
343
344 static inline void
345 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
346 uint16_t *buf)
347 {
348 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
349
350 while (count--)
351 *buf++ = htons(RD_REG_WORD(dmp_reg++));
352 }
353
354 static inline void *
355 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
356 {
357 if (!ha->eft)
358 return ptr;
359
360 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
361 return ptr + ntohl(ha->fw_dump->eft_size);
362 }
363
364 static inline void *
365 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
366 {
367 uint32_t cnt;
368 uint32_t *iter_reg;
369 struct qla2xxx_fce_chain *fcec = ptr;
370
371 if (!ha->fce)
372 return ptr;
373
374 *last_chain = &fcec->type;
375 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
376 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
377 fce_calc_size(ha->fce_bufs));
378 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
379 fcec->addr_l = htonl(LSD(ha->fce_dma));
380 fcec->addr_h = htonl(MSD(ha->fce_dma));
381
382 iter_reg = fcec->eregs;
383 for (cnt = 0; cnt < 8; cnt++)
384 *iter_reg++ = htonl(ha->fce_mb[cnt]);
385
386 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
387
388 return (char *)iter_reg + ntohl(fcec->size);
389 }
390
391 static inline void *
392 qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr,
393 uint32_t **last_chain)
394 {
395 struct qla2xxx_mqueue_chain *q;
396 struct qla2xxx_mqueue_header *qh;
397 uint32_t num_queues;
398 int que;
399 struct {
400 int length;
401 void *ring;
402 } aq, *aqp;
403
404 if (!ha->tgt.atio_q_length)
405 return ptr;
406
407 num_queues = 1;
408 aqp = &aq;
409 aqp->length = ha->tgt.atio_q_length;
410 aqp->ring = ha->tgt.atio_ring;
411
412 for (que = 0; que < num_queues; que++) {
413 /* aqp = ha->atio_q_map[que]; */
414 q = ptr;
415 *last_chain = &q->type;
416 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
417 q->chain_size = htonl(
418 sizeof(struct qla2xxx_mqueue_chain) +
419 sizeof(struct qla2xxx_mqueue_header) +
420 (aqp->length * sizeof(request_t)));
421 ptr += sizeof(struct qla2xxx_mqueue_chain);
422
423 /* Add header. */
424 qh = ptr;
425 qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
426 qh->number = htonl(que);
427 qh->size = htonl(aqp->length * sizeof(request_t));
428 ptr += sizeof(struct qla2xxx_mqueue_header);
429
430 /* Add data. */
431 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
432
433 ptr += aqp->length * sizeof(request_t);
434 }
435
436 return ptr;
437 }
438
439 static inline void *
440 qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
441 {
442 struct qla2xxx_mqueue_chain *q;
443 struct qla2xxx_mqueue_header *qh;
444 struct req_que *req;
445 struct rsp_que *rsp;
446 int que;
447
448 if (!ha->mqenable)
449 return ptr;
450
451 /* Request queues */
452 for (que = 1; que < ha->max_req_queues; que++) {
453 req = ha->req_q_map[que];
454 if (!req)
455 break;
456
457 /* Add chain. */
458 q = ptr;
459 *last_chain = &q->type;
460 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
461 q->chain_size = htonl(
462 sizeof(struct qla2xxx_mqueue_chain) +
463 sizeof(struct qla2xxx_mqueue_header) +
464 (req->length * sizeof(request_t)));
465 ptr += sizeof(struct qla2xxx_mqueue_chain);
466
467 /* Add header. */
468 qh = ptr;
469 qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
470 qh->number = htonl(que);
471 qh->size = htonl(req->length * sizeof(request_t));
472 ptr += sizeof(struct qla2xxx_mqueue_header);
473
474 /* Add data. */
475 memcpy(ptr, req->ring, req->length * sizeof(request_t));
476 ptr += req->length * sizeof(request_t);
477 }
478
479 /* Response queues */
480 for (que = 1; que < ha->max_rsp_queues; que++) {
481 rsp = ha->rsp_q_map[que];
482 if (!rsp)
483 break;
484
485 /* Add chain. */
486 q = ptr;
487 *last_chain = &q->type;
488 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
489 q->chain_size = htonl(
490 sizeof(struct qla2xxx_mqueue_chain) +
491 sizeof(struct qla2xxx_mqueue_header) +
492 (rsp->length * sizeof(response_t)));
493 ptr += sizeof(struct qla2xxx_mqueue_chain);
494
495 /* Add header. */
496 qh = ptr;
497 qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
498 qh->number = htonl(que);
499 qh->size = htonl(rsp->length * sizeof(response_t));
500 ptr += sizeof(struct qla2xxx_mqueue_header);
501
502 /* Add data. */
503 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
504 ptr += rsp->length * sizeof(response_t);
505 }
506
507 return ptr;
508 }
509
510 static inline void *
511 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
512 {
513 uint32_t cnt, que_idx;
514 uint8_t que_cnt;
515 struct qla2xxx_mq_chain *mq = ptr;
516 struct device_reg_25xxmq __iomem *reg;
517
518 if (!ha->mqenable || IS_QLA83XX(ha))
519 return ptr;
520
521 mq = ptr;
522 *last_chain = &mq->type;
523 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
524 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
525
526 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
527 ha->max_req_queues : ha->max_rsp_queues;
528 mq->count = htonl(que_cnt);
529 for (cnt = 0; cnt < que_cnt; cnt++) {
530 reg = (struct device_reg_25xxmq __iomem *)
531 (ha->mqiobase + cnt * QLA_QUE_PAGE);
532 que_idx = cnt * 4;
533 mq->qregs[que_idx] = htonl(RD_REG_DWORD(&reg->req_q_in));
534 mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(&reg->req_q_out));
535 mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(&reg->rsp_q_in));
536 mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(&reg->rsp_q_out));
537 }
538
539 return ptr + sizeof(struct qla2xxx_mq_chain);
540 }
541
542 void
543 qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
544 {
545 struct qla_hw_data *ha = vha->hw;
546
547 if (rval != QLA_SUCCESS) {
548 ql_log(ql_log_warn, vha, 0xd000,
549 "Failed to dump firmware (%x).\n", rval);
550 ha->fw_dumped = 0;
551 } else {
552 ql_log(ql_log_info, vha, 0xd001,
553 "Firmware dump saved to temp buffer (%ld/%p).\n",
554 vha->host_no, ha->fw_dump);
555 ha->fw_dumped = 1;
556 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
557 }
558 }
559
560 /**
561 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
562 * @ha: HA context
563 * @hardware_locked: Called with the hardware_lock
564 */
565 void
566 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
567 {
568 int rval;
569 uint32_t cnt;
570 struct qla_hw_data *ha = vha->hw;
571 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
572 uint16_t __iomem *dmp_reg;
573 unsigned long flags;
574 struct qla2300_fw_dump *fw;
575 void *nxt;
576 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
577
578 flags = 0;
579
580 if (!hardware_locked)
581 spin_lock_irqsave(&ha->hardware_lock, flags);
582
583 if (!ha->fw_dump) {
584 ql_log(ql_log_warn, vha, 0xd002,
585 "No buffer available for dump.\n");
586 goto qla2300_fw_dump_failed;
587 }
588
589 if (ha->fw_dumped) {
590 ql_log(ql_log_warn, vha, 0xd003,
591 "Firmware has been previously dumped (%p) "
592 "-- ignoring request.\n",
593 ha->fw_dump);
594 goto qla2300_fw_dump_failed;
595 }
596 fw = &ha->fw_dump->isp.isp23;
597 qla2xxx_prep_dump(ha, ha->fw_dump);
598
599 rval = QLA_SUCCESS;
600 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
601
602 /* Pause RISC. */
603 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
604 if (IS_QLA2300(ha)) {
605 for (cnt = 30000;
606 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
607 rval == QLA_SUCCESS; cnt--) {
608 if (cnt)
609 udelay(100);
610 else
611 rval = QLA_FUNCTION_TIMEOUT;
612 }
613 } else {
614 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
615 udelay(10);
616 }
617
618 if (rval == QLA_SUCCESS) {
619 dmp_reg = &reg->flash_address;
620 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
621 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
622
623 dmp_reg = &reg->u.isp2300.req_q_in;
624 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
625 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
626
627 dmp_reg = &reg->u.isp2300.mailbox0;
628 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
629 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
630
631 WRT_REG_WORD(&reg->ctrl_status, 0x40);
632 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
633
634 WRT_REG_WORD(&reg->ctrl_status, 0x50);
635 qla2xxx_read_window(reg, 48, fw->dma_reg);
636
637 WRT_REG_WORD(&reg->ctrl_status, 0x00);
638 dmp_reg = &reg->risc_hw;
639 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
640 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
641
642 WRT_REG_WORD(&reg->pcr, 0x2000);
643 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
644
645 WRT_REG_WORD(&reg->pcr, 0x2200);
646 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
647
648 WRT_REG_WORD(&reg->pcr, 0x2400);
649 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
650
651 WRT_REG_WORD(&reg->pcr, 0x2600);
652 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
653
654 WRT_REG_WORD(&reg->pcr, 0x2800);
655 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
656
657 WRT_REG_WORD(&reg->pcr, 0x2A00);
658 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
659
660 WRT_REG_WORD(&reg->pcr, 0x2C00);
661 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
662
663 WRT_REG_WORD(&reg->pcr, 0x2E00);
664 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
665
666 WRT_REG_WORD(&reg->ctrl_status, 0x10);
667 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
668
669 WRT_REG_WORD(&reg->ctrl_status, 0x20);
670 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
671
672 WRT_REG_WORD(&reg->ctrl_status, 0x30);
673 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
674
675 /* Reset RISC. */
676 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
677 for (cnt = 0; cnt < 30000; cnt++) {
678 if ((RD_REG_WORD(&reg->ctrl_status) &
679 CSR_ISP_SOFT_RESET) == 0)
680 break;
681
682 udelay(10);
683 }
684 }
685
686 if (!IS_QLA2300(ha)) {
687 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
688 rval == QLA_SUCCESS; cnt--) {
689 if (cnt)
690 udelay(100);
691 else
692 rval = QLA_FUNCTION_TIMEOUT;
693 }
694 }
695
696 /* Get RISC SRAM. */
697 if (rval == QLA_SUCCESS)
698 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
699 sizeof(fw->risc_ram) / 2, &nxt);
700
701 /* Get stack SRAM. */
702 if (rval == QLA_SUCCESS)
703 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
704 sizeof(fw->stack_ram) / 2, &nxt);
705
706 /* Get data SRAM. */
707 if (rval == QLA_SUCCESS)
708 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
709 ha->fw_memory_size - 0x11000 + 1, &nxt);
710
711 if (rval == QLA_SUCCESS)
712 qla2xxx_copy_queues(ha, nxt);
713
714 qla2xxx_dump_post_process(base_vha, rval);
715
716 qla2300_fw_dump_failed:
717 if (!hardware_locked)
718 spin_unlock_irqrestore(&ha->hardware_lock, flags);
719 }
720
721 /**
722 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
723 * @ha: HA context
724 * @hardware_locked: Called with the hardware_lock
725 */
726 void
727 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
728 {
729 int rval;
730 uint32_t cnt, timer;
731 uint16_t risc_address;
732 uint16_t mb0, mb2;
733 struct qla_hw_data *ha = vha->hw;
734 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
735 uint16_t __iomem *dmp_reg;
736 unsigned long flags;
737 struct qla2100_fw_dump *fw;
738 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
739
740 risc_address = 0;
741 mb0 = mb2 = 0;
742 flags = 0;
743
744 if (!hardware_locked)
745 spin_lock_irqsave(&ha->hardware_lock, flags);
746
747 if (!ha->fw_dump) {
748 ql_log(ql_log_warn, vha, 0xd004,
749 "No buffer available for dump.\n");
750 goto qla2100_fw_dump_failed;
751 }
752
753 if (ha->fw_dumped) {
754 ql_log(ql_log_warn, vha, 0xd005,
755 "Firmware has been previously dumped (%p) "
756 "-- ignoring request.\n",
757 ha->fw_dump);
758 goto qla2100_fw_dump_failed;
759 }
760 fw = &ha->fw_dump->isp.isp21;
761 qla2xxx_prep_dump(ha, ha->fw_dump);
762
763 rval = QLA_SUCCESS;
764 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
765
766 /* Pause RISC. */
767 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
768 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
769 rval == QLA_SUCCESS; cnt--) {
770 if (cnt)
771 udelay(100);
772 else
773 rval = QLA_FUNCTION_TIMEOUT;
774 }
775 if (rval == QLA_SUCCESS) {
776 dmp_reg = &reg->flash_address;
777 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
778 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
779
780 dmp_reg = &reg->u.isp2100.mailbox0;
781 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
782 if (cnt == 8)
783 dmp_reg = &reg->u_end.isp2200.mailbox8;
784
785 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
786 }
787
788 dmp_reg = &reg->u.isp2100.unused_2[0];
789 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
790 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
791
792 WRT_REG_WORD(&reg->ctrl_status, 0x00);
793 dmp_reg = &reg->risc_hw;
794 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
795 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
796
797 WRT_REG_WORD(&reg->pcr, 0x2000);
798 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
799
800 WRT_REG_WORD(&reg->pcr, 0x2100);
801 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
802
803 WRT_REG_WORD(&reg->pcr, 0x2200);
804 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
805
806 WRT_REG_WORD(&reg->pcr, 0x2300);
807 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
808
809 WRT_REG_WORD(&reg->pcr, 0x2400);
810 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
811
812 WRT_REG_WORD(&reg->pcr, 0x2500);
813 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
814
815 WRT_REG_WORD(&reg->pcr, 0x2600);
816 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
817
818 WRT_REG_WORD(&reg->pcr, 0x2700);
819 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
820
821 WRT_REG_WORD(&reg->ctrl_status, 0x10);
822 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
823
824 WRT_REG_WORD(&reg->ctrl_status, 0x20);
825 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
826
827 WRT_REG_WORD(&reg->ctrl_status, 0x30);
828 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
829
830 /* Reset the ISP. */
831 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
832 }
833
834 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
835 rval == QLA_SUCCESS; cnt--) {
836 if (cnt)
837 udelay(100);
838 else
839 rval = QLA_FUNCTION_TIMEOUT;
840 }
841
842 /* Pause RISC. */
843 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
844 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
845
846 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
847 for (cnt = 30000;
848 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
849 rval == QLA_SUCCESS; cnt--) {
850 if (cnt)
851 udelay(100);
852 else
853 rval = QLA_FUNCTION_TIMEOUT;
854 }
855 if (rval == QLA_SUCCESS) {
856 /* Set memory configuration and timing. */
857 if (IS_QLA2100(ha))
858 WRT_REG_WORD(&reg->mctr, 0xf1);
859 else
860 WRT_REG_WORD(&reg->mctr, 0xf2);
861 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
862
863 /* Release RISC. */
864 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
865 }
866 }
867
868 if (rval == QLA_SUCCESS) {
869 /* Get RISC SRAM. */
870 risc_address = 0x1000;
871 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
872 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
873 }
874 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
875 cnt++, risc_address++) {
876 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
877 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
878
879 for (timer = 6000000; timer != 0; timer--) {
880 /* Check for pending interrupts. */
881 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
882 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
883 set_bit(MBX_INTERRUPT,
884 &ha->mbx_cmd_flags);
885
886 mb0 = RD_MAILBOX_REG(ha, reg, 0);
887 mb2 = RD_MAILBOX_REG(ha, reg, 2);
888
889 WRT_REG_WORD(&reg->semaphore, 0);
890 WRT_REG_WORD(&reg->hccr,
891 HCCR_CLR_RISC_INT);
892 RD_REG_WORD(&reg->hccr);
893 break;
894 }
895 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
896 RD_REG_WORD(&reg->hccr);
897 }
898 udelay(5);
899 }
900
901 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
902 rval = mb0 & MBS_MASK;
903 fw->risc_ram[cnt] = htons(mb2);
904 } else {
905 rval = QLA_FUNCTION_FAILED;
906 }
907 }
908
909 if (rval == QLA_SUCCESS)
910 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
911
912 qla2xxx_dump_post_process(base_vha, rval);
913
914 qla2100_fw_dump_failed:
915 if (!hardware_locked)
916 spin_unlock_irqrestore(&ha->hardware_lock, flags);
917 }
918
919 void
920 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
921 {
922 int rval;
923 uint32_t cnt;
924 uint32_t risc_address;
925 struct qla_hw_data *ha = vha->hw;
926 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
927 uint32_t __iomem *dmp_reg;
928 uint32_t *iter_reg;
929 uint16_t __iomem *mbx_reg;
930 unsigned long flags;
931 struct qla24xx_fw_dump *fw;
932 uint32_t ext_mem_cnt;
933 void *nxt;
934 void *nxt_chain;
935 uint32_t *last_chain = NULL;
936 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
937
938 if (IS_QLA82XX(ha))
939 return;
940
941 risc_address = ext_mem_cnt = 0;
942 flags = 0;
943
944 if (!hardware_locked)
945 spin_lock_irqsave(&ha->hardware_lock, flags);
946
947 if (!ha->fw_dump) {
948 ql_log(ql_log_warn, vha, 0xd006,
949 "No buffer available for dump.\n");
950 goto qla24xx_fw_dump_failed;
951 }
952
953 if (ha->fw_dumped) {
954 ql_log(ql_log_warn, vha, 0xd007,
955 "Firmware has been previously dumped (%p) "
956 "-- ignoring request.\n",
957 ha->fw_dump);
958 goto qla24xx_fw_dump_failed;
959 }
960 fw = &ha->fw_dump->isp.isp24;
961 qla2xxx_prep_dump(ha, ha->fw_dump);
962
963 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
964
965 /* Pause RISC. */
966 rval = qla24xx_pause_risc(reg);
967 if (rval != QLA_SUCCESS)
968 goto qla24xx_fw_dump_failed_0;
969
970 /* Host interface registers. */
971 dmp_reg = &reg->flash_addr;
972 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
973 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
974
975 /* Disable interrupts. */
976 WRT_REG_DWORD(&reg->ictrl, 0);
977 RD_REG_DWORD(&reg->ictrl);
978
979 /* Shadow registers. */
980 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
981 RD_REG_DWORD(&reg->iobase_addr);
982 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
983 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
984
985 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
986 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
987
988 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
989 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
990
991 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
992 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
993
994 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
995 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
996
997 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
998 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
999
1000 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1001 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1002
1003 /* Mailbox registers. */
1004 mbx_reg = &reg->mailbox0;
1005 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1006 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1007
1008 /* Transfer sequence registers. */
1009 iter_reg = fw->xseq_gp_reg;
1010 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1011 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1012 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1013 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1014 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1015 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1016 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1017 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1018
1019 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
1020 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1021
1022 /* Receive sequence registers. */
1023 iter_reg = fw->rseq_gp_reg;
1024 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1025 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1026 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1027 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1028 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1029 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1030 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1031 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1032
1033 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
1034 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1035 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1036
1037 /* Command DMA registers. */
1038 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1039
1040 /* Queues. */
1041 iter_reg = fw->req0_dma_reg;
1042 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1043 dmp_reg = &reg->iobase_q;
1044 for (cnt = 0; cnt < 7; cnt++)
1045 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1046
1047 iter_reg = fw->resp0_dma_reg;
1048 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1049 dmp_reg = &reg->iobase_q;
1050 for (cnt = 0; cnt < 7; cnt++)
1051 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1052
1053 iter_reg = fw->req1_dma_reg;
1054 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1055 dmp_reg = &reg->iobase_q;
1056 for (cnt = 0; cnt < 7; cnt++)
1057 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1058
1059 /* Transmit DMA registers. */
1060 iter_reg = fw->xmt0_dma_reg;
1061 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1062 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1063
1064 iter_reg = fw->xmt1_dma_reg;
1065 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1066 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1067
1068 iter_reg = fw->xmt2_dma_reg;
1069 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1070 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1071
1072 iter_reg = fw->xmt3_dma_reg;
1073 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1074 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1075
1076 iter_reg = fw->xmt4_dma_reg;
1077 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1078 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1079
1080 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1081
1082 /* Receive DMA registers. */
1083 iter_reg = fw->rcvt0_data_dma_reg;
1084 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1085 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1086
1087 iter_reg = fw->rcvt1_data_dma_reg;
1088 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1089 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1090
1091 /* RISC registers. */
1092 iter_reg = fw->risc_gp_reg;
1093 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1094 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1095 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1096 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1097 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1098 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1099 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1100 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1101
1102 /* Local memory controller registers. */
1103 iter_reg = fw->lmc_reg;
1104 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1105 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1106 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1107 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1108 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1109 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1110 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1111
1112 /* Fibre Protocol Module registers. */
1113 iter_reg = fw->fpm_hdw_reg;
1114 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1115 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1116 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1117 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1118 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1119 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1120 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1121 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1122 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1123 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1124 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1125 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1126
1127 /* Frame Buffer registers. */
1128 iter_reg = fw->fb_hdw_reg;
1129 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1130 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1131 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1132 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1133 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1134 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1135 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1136 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1137 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1138 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1139 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1140
1141 rval = qla24xx_soft_reset(ha);
1142 if (rval != QLA_SUCCESS)
1143 goto qla24xx_fw_dump_failed_0;
1144
1145 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1146 &nxt);
1147 if (rval != QLA_SUCCESS)
1148 goto qla24xx_fw_dump_failed_0;
1149
1150 nxt = qla2xxx_copy_queues(ha, nxt);
1151
1152 qla24xx_copy_eft(ha, nxt);
1153
1154 nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
1155 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1156 if (last_chain) {
1157 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1158 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1159 }
1160
1161 /* Adjust valid length. */
1162 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1163
1164 qla24xx_fw_dump_failed_0:
1165 qla2xxx_dump_post_process(base_vha, rval);
1166
1167 qla24xx_fw_dump_failed:
1168 if (!hardware_locked)
1169 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1170 }
1171
1172 void
1173 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1174 {
1175 int rval;
1176 uint32_t cnt;
1177 uint32_t risc_address;
1178 struct qla_hw_data *ha = vha->hw;
1179 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1180 uint32_t __iomem *dmp_reg;
1181 uint32_t *iter_reg;
1182 uint16_t __iomem *mbx_reg;
1183 unsigned long flags;
1184 struct qla25xx_fw_dump *fw;
1185 uint32_t ext_mem_cnt;
1186 void *nxt, *nxt_chain;
1187 uint32_t *last_chain = NULL;
1188 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1189
1190 risc_address = ext_mem_cnt = 0;
1191 flags = 0;
1192
1193 if (!hardware_locked)
1194 spin_lock_irqsave(&ha->hardware_lock, flags);
1195
1196 if (!ha->fw_dump) {
1197 ql_log(ql_log_warn, vha, 0xd008,
1198 "No buffer available for dump.\n");
1199 goto qla25xx_fw_dump_failed;
1200 }
1201
1202 if (ha->fw_dumped) {
1203 ql_log(ql_log_warn, vha, 0xd009,
1204 "Firmware has been previously dumped (%p) "
1205 "-- ignoring request.\n",
1206 ha->fw_dump);
1207 goto qla25xx_fw_dump_failed;
1208 }
1209 fw = &ha->fw_dump->isp.isp25;
1210 qla2xxx_prep_dump(ha, ha->fw_dump);
1211 ha->fw_dump->version = __constant_htonl(2);
1212
1213 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1214
1215 /* Pause RISC. */
1216 rval = qla24xx_pause_risc(reg);
1217 if (rval != QLA_SUCCESS)
1218 goto qla25xx_fw_dump_failed_0;
1219
1220 /* Host/Risc registers. */
1221 iter_reg = fw->host_risc_reg;
1222 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1223 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1224
1225 /* PCIe registers. */
1226 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1227 RD_REG_DWORD(&reg->iobase_addr);
1228 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1229 dmp_reg = &reg->iobase_c4;
1230 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1231 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1232 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1233 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1234
1235 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1236 RD_REG_DWORD(&reg->iobase_window);
1237
1238 /* Host interface registers. */
1239 dmp_reg = &reg->flash_addr;
1240 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1241 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1242
1243 /* Disable interrupts. */
1244 WRT_REG_DWORD(&reg->ictrl, 0);
1245 RD_REG_DWORD(&reg->ictrl);
1246
1247 /* Shadow registers. */
1248 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1249 RD_REG_DWORD(&reg->iobase_addr);
1250 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1251 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1252
1253 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1254 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1255
1256 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1257 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1258
1259 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1260 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1261
1262 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1263 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1264
1265 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1266 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1267
1268 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1269 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1270
1271 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1272 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1273
1274 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1275 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1276
1277 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1278 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1279
1280 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1281 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1282
1283 /* RISC I/O register. */
1284 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1285 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1286
1287 /* Mailbox registers. */
1288 mbx_reg = &reg->mailbox0;
1289 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1290 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1291
1292 /* Transfer sequence registers. */
1293 iter_reg = fw->xseq_gp_reg;
1294 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1295 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1296 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1297 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1298 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1299 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1300 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1301 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1302
1303 iter_reg = fw->xseq_0_reg;
1304 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1305 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1306 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1307
1308 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1309
1310 /* Receive sequence registers. */
1311 iter_reg = fw->rseq_gp_reg;
1312 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1313 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1314 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1315 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1316 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1317 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1318 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1319 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1320
1321 iter_reg = fw->rseq_0_reg;
1322 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1323 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1324
1325 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1326 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1327
1328 /* Auxiliary sequence registers. */
1329 iter_reg = fw->aseq_gp_reg;
1330 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1331 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1332 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1333 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1334 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1335 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1336 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1337 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1338
1339 iter_reg = fw->aseq_0_reg;
1340 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1341 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1342
1343 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1344 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1345
1346 /* Command DMA registers. */
1347 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1348
1349 /* Queues. */
1350 iter_reg = fw->req0_dma_reg;
1351 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1352 dmp_reg = &reg->iobase_q;
1353 for (cnt = 0; cnt < 7; cnt++)
1354 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1355
1356 iter_reg = fw->resp0_dma_reg;
1357 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1358 dmp_reg = &reg->iobase_q;
1359 for (cnt = 0; cnt < 7; cnt++)
1360 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1361
1362 iter_reg = fw->req1_dma_reg;
1363 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1364 dmp_reg = &reg->iobase_q;
1365 for (cnt = 0; cnt < 7; cnt++)
1366 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1367
1368 /* Transmit DMA registers. */
1369 iter_reg = fw->xmt0_dma_reg;
1370 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1371 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1372
1373 iter_reg = fw->xmt1_dma_reg;
1374 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1375 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1376
1377 iter_reg = fw->xmt2_dma_reg;
1378 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1379 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1380
1381 iter_reg = fw->xmt3_dma_reg;
1382 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1383 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1384
1385 iter_reg = fw->xmt4_dma_reg;
1386 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1387 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1388
1389 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1390
1391 /* Receive DMA registers. */
1392 iter_reg = fw->rcvt0_data_dma_reg;
1393 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1394 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1395
1396 iter_reg = fw->rcvt1_data_dma_reg;
1397 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1398 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1399
1400 /* RISC registers. */
1401 iter_reg = fw->risc_gp_reg;
1402 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1403 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1404 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1405 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1406 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1407 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1408 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1409 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1410
1411 /* Local memory controller registers. */
1412 iter_reg = fw->lmc_reg;
1413 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1414 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1415 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1416 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1417 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1418 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1419 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1420 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1421
1422 /* Fibre Protocol Module registers. */
1423 iter_reg = fw->fpm_hdw_reg;
1424 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1425 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1426 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1427 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1428 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1429 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1430 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1431 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1432 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1433 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1434 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1435 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1436
1437 /* Frame Buffer registers. */
1438 iter_reg = fw->fb_hdw_reg;
1439 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1440 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1441 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1442 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1443 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1444 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1445 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1446 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1447 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1448 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1449 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1450 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1451
1452 /* Multi queue registers */
1453 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1454 &last_chain);
1455
1456 rval = qla24xx_soft_reset(ha);
1457 if (rval != QLA_SUCCESS)
1458 goto qla25xx_fw_dump_failed_0;
1459
1460 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1461 &nxt);
1462 if (rval != QLA_SUCCESS)
1463 goto qla25xx_fw_dump_failed_0;
1464
1465 nxt = qla2xxx_copy_queues(ha, nxt);
1466
1467 nxt = qla24xx_copy_eft(ha, nxt);
1468
1469 /* Chain entries -- started with MQ. */
1470 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1471 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1472 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1473 if (last_chain) {
1474 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1475 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1476 }
1477
1478 /* Adjust valid length. */
1479 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1480
1481 qla25xx_fw_dump_failed_0:
1482 qla2xxx_dump_post_process(base_vha, rval);
1483
1484 qla25xx_fw_dump_failed:
1485 if (!hardware_locked)
1486 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1487 }
1488
1489 void
1490 qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1491 {
1492 int rval;
1493 uint32_t cnt;
1494 uint32_t risc_address;
1495 struct qla_hw_data *ha = vha->hw;
1496 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1497 uint32_t __iomem *dmp_reg;
1498 uint32_t *iter_reg;
1499 uint16_t __iomem *mbx_reg;
1500 unsigned long flags;
1501 struct qla81xx_fw_dump *fw;
1502 uint32_t ext_mem_cnt;
1503 void *nxt, *nxt_chain;
1504 uint32_t *last_chain = NULL;
1505 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1506
1507 risc_address = ext_mem_cnt = 0;
1508 flags = 0;
1509
1510 if (!hardware_locked)
1511 spin_lock_irqsave(&ha->hardware_lock, flags);
1512
1513 if (!ha->fw_dump) {
1514 ql_log(ql_log_warn, vha, 0xd00a,
1515 "No buffer available for dump.\n");
1516 goto qla81xx_fw_dump_failed;
1517 }
1518
1519 if (ha->fw_dumped) {
1520 ql_log(ql_log_warn, vha, 0xd00b,
1521 "Firmware has been previously dumped (%p) "
1522 "-- ignoring request.\n",
1523 ha->fw_dump);
1524 goto qla81xx_fw_dump_failed;
1525 }
1526 fw = &ha->fw_dump->isp.isp81;
1527 qla2xxx_prep_dump(ha, ha->fw_dump);
1528
1529 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1530
1531 /* Pause RISC. */
1532 rval = qla24xx_pause_risc(reg);
1533 if (rval != QLA_SUCCESS)
1534 goto qla81xx_fw_dump_failed_0;
1535
1536 /* Host/Risc registers. */
1537 iter_reg = fw->host_risc_reg;
1538 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1539 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1540
1541 /* PCIe registers. */
1542 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1543 RD_REG_DWORD(&reg->iobase_addr);
1544 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1545 dmp_reg = &reg->iobase_c4;
1546 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1547 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1548 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1549 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1550
1551 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1552 RD_REG_DWORD(&reg->iobase_window);
1553
1554 /* Host interface registers. */
1555 dmp_reg = &reg->flash_addr;
1556 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1557 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1558
1559 /* Disable interrupts. */
1560 WRT_REG_DWORD(&reg->ictrl, 0);
1561 RD_REG_DWORD(&reg->ictrl);
1562
1563 /* Shadow registers. */
1564 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1565 RD_REG_DWORD(&reg->iobase_addr);
1566 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1567 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1568
1569 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1570 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1571
1572 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1573 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1574
1575 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1576 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1577
1578 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1579 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1580
1581 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1582 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1583
1584 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1585 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1586
1587 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1588 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1589
1590 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1591 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1592
1593 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1594 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1595
1596 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1597 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1598
1599 /* RISC I/O register. */
1600 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1601 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1602
1603 /* Mailbox registers. */
1604 mbx_reg = &reg->mailbox0;
1605 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1606 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1607
1608 /* Transfer sequence registers. */
1609 iter_reg = fw->xseq_gp_reg;
1610 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1611 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1612 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1613 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1614 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1615 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1616 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1617 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1618
1619 iter_reg = fw->xseq_0_reg;
1620 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1621 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1622 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1623
1624 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1625
1626 /* Receive sequence registers. */
1627 iter_reg = fw->rseq_gp_reg;
1628 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1629 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1630 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1631 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1632 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1633 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1634 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1635 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1636
1637 iter_reg = fw->rseq_0_reg;
1638 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1639 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1640
1641 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1642 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1643
1644 /* Auxiliary sequence registers. */
1645 iter_reg = fw->aseq_gp_reg;
1646 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1647 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1648 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1649 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1650 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1651 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1652 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1653 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1654
1655 iter_reg = fw->aseq_0_reg;
1656 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1657 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1658
1659 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1660 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1661
1662 /* Command DMA registers. */
1663 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1664
1665 /* Queues. */
1666 iter_reg = fw->req0_dma_reg;
1667 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1668 dmp_reg = &reg->iobase_q;
1669 for (cnt = 0; cnt < 7; cnt++)
1670 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1671
1672 iter_reg = fw->resp0_dma_reg;
1673 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1674 dmp_reg = &reg->iobase_q;
1675 for (cnt = 0; cnt < 7; cnt++)
1676 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1677
1678 iter_reg = fw->req1_dma_reg;
1679 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1680 dmp_reg = &reg->iobase_q;
1681 for (cnt = 0; cnt < 7; cnt++)
1682 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1683
1684 /* Transmit DMA registers. */
1685 iter_reg = fw->xmt0_dma_reg;
1686 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1687 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1688
1689 iter_reg = fw->xmt1_dma_reg;
1690 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1691 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1692
1693 iter_reg = fw->xmt2_dma_reg;
1694 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1695 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1696
1697 iter_reg = fw->xmt3_dma_reg;
1698 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1699 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1700
1701 iter_reg = fw->xmt4_dma_reg;
1702 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1703 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1704
1705 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1706
1707 /* Receive DMA registers. */
1708 iter_reg = fw->rcvt0_data_dma_reg;
1709 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1710 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1711
1712 iter_reg = fw->rcvt1_data_dma_reg;
1713 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1714 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1715
1716 /* RISC registers. */
1717 iter_reg = fw->risc_gp_reg;
1718 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1719 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1720 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1721 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1722 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1723 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1724 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1725 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1726
1727 /* Local memory controller registers. */
1728 iter_reg = fw->lmc_reg;
1729 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1730 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1731 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1732 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1733 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1734 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1735 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1736 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1737
1738 /* Fibre Protocol Module registers. */
1739 iter_reg = fw->fpm_hdw_reg;
1740 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1741 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1742 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1743 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1744 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1745 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1746 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1747 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1748 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1749 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1750 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1751 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1752 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1753 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1754
1755 /* Frame Buffer registers. */
1756 iter_reg = fw->fb_hdw_reg;
1757 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1758 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1759 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1760 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1761 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1762 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1763 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1764 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1765 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1766 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1767 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1768 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1769 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1770
1771 /* Multi queue registers */
1772 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1773 &last_chain);
1774
1775 rval = qla24xx_soft_reset(ha);
1776 if (rval != QLA_SUCCESS)
1777 goto qla81xx_fw_dump_failed_0;
1778
1779 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1780 &nxt);
1781 if (rval != QLA_SUCCESS)
1782 goto qla81xx_fw_dump_failed_0;
1783
1784 nxt = qla2xxx_copy_queues(ha, nxt);
1785
1786 nxt = qla24xx_copy_eft(ha, nxt);
1787
1788 /* Chain entries -- started with MQ. */
1789 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1790 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1791 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1792 if (last_chain) {
1793 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1794 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1795 }
1796
1797 /* Adjust valid length. */
1798 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1799
1800 qla81xx_fw_dump_failed_0:
1801 qla2xxx_dump_post_process(base_vha, rval);
1802
1803 qla81xx_fw_dump_failed:
1804 if (!hardware_locked)
1805 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1806 }
1807
1808 void
1809 qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1810 {
1811 int rval;
1812 uint32_t cnt, reg_data;
1813 uint32_t risc_address;
1814 struct qla_hw_data *ha = vha->hw;
1815 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1816 uint32_t __iomem *dmp_reg;
1817 uint32_t *iter_reg;
1818 uint16_t __iomem *mbx_reg;
1819 unsigned long flags;
1820 struct qla83xx_fw_dump *fw;
1821 uint32_t ext_mem_cnt;
1822 void *nxt, *nxt_chain;
1823 uint32_t *last_chain = NULL;
1824 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1825
1826 risc_address = ext_mem_cnt = 0;
1827 flags = 0;
1828
1829 if (!hardware_locked)
1830 spin_lock_irqsave(&ha->hardware_lock, flags);
1831
1832 if (!ha->fw_dump) {
1833 ql_log(ql_log_warn, vha, 0xd00c,
1834 "No buffer available for dump!!!\n");
1835 goto qla83xx_fw_dump_failed;
1836 }
1837
1838 if (ha->fw_dumped) {
1839 ql_log(ql_log_warn, vha, 0xd00d,
1840 "Firmware has been previously dumped (%p) -- ignoring "
1841 "request...\n", ha->fw_dump);
1842 goto qla83xx_fw_dump_failed;
1843 }
1844 fw = &ha->fw_dump->isp.isp83;
1845 qla2xxx_prep_dump(ha, ha->fw_dump);
1846
1847 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1848
1849 /* Pause RISC. */
1850 rval = qla24xx_pause_risc(reg);
1851 if (rval != QLA_SUCCESS)
1852 goto qla83xx_fw_dump_failed_0;
1853
1854 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1855 dmp_reg = &reg->iobase_window;
1856 reg_data = RD_REG_DWORD(dmp_reg);
1857 WRT_REG_DWORD(dmp_reg, 0);
1858
1859 dmp_reg = &reg->unused_4_1[0];
1860 reg_data = RD_REG_DWORD(dmp_reg);
1861 WRT_REG_DWORD(dmp_reg, 0);
1862
1863 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1864 dmp_reg = &reg->unused_4_1[2];
1865 reg_data = RD_REG_DWORD(dmp_reg);
1866 WRT_REG_DWORD(dmp_reg, 0);
1867
1868 /* select PCR and disable ecc checking and correction */
1869 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1870 RD_REG_DWORD(&reg->iobase_addr);
1871 WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
1872
1873 /* Host/Risc registers. */
1874 iter_reg = fw->host_risc_reg;
1875 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1876 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1877 qla24xx_read_window(reg, 0x7040, 16, iter_reg);
1878
1879 /* PCIe registers. */
1880 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1881 RD_REG_DWORD(&reg->iobase_addr);
1882 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1883 dmp_reg = &reg->iobase_c4;
1884 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1885 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1886 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1887 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1888
1889 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1890 RD_REG_DWORD(&reg->iobase_window);
1891
1892 /* Host interface registers. */
1893 dmp_reg = &reg->flash_addr;
1894 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1895 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1896
1897 /* Disable interrupts. */
1898 WRT_REG_DWORD(&reg->ictrl, 0);
1899 RD_REG_DWORD(&reg->ictrl);
1900
1901 /* Shadow registers. */
1902 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1903 RD_REG_DWORD(&reg->iobase_addr);
1904 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1905 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1906
1907 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1908 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1909
1910 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1911 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1912
1913 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1914 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1915
1916 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1917 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1918
1919 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1920 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1921
1922 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1923 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1924
1925 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1926 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1927
1928 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1929 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1930
1931 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1932 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1933
1934 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1935 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1936
1937 /* RISC I/O register. */
1938 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1939 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1940
1941 /* Mailbox registers. */
1942 mbx_reg = &reg->mailbox0;
1943 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1944 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1945
1946 /* Transfer sequence registers. */
1947 iter_reg = fw->xseq_gp_reg;
1948 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
1949 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
1950 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
1951 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
1952 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
1953 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
1954 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
1955 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
1956 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1957 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1958 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1959 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1960 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1961 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1962 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1963 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1964
1965 iter_reg = fw->xseq_0_reg;
1966 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1967 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1968 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1969
1970 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1971
1972 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
1973
1974 /* Receive sequence registers. */
1975 iter_reg = fw->rseq_gp_reg;
1976 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
1977 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
1978 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
1979 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
1980 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
1981 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
1982 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
1983 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
1984 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1985 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1986 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1987 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1988 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1989 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1990 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1991 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1992
1993 iter_reg = fw->rseq_0_reg;
1994 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1995 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1996
1997 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1998 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1999 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
2000
2001 /* Auxiliary sequence registers. */
2002 iter_reg = fw->aseq_gp_reg;
2003 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
2004 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
2005 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
2006 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
2007 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
2008 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
2009 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
2010 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
2011 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
2012 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
2013 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
2014 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
2015 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
2016 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
2017 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
2018 qla24xx_read_window(reg, 0xB170, 16, iter_reg);
2019
2020 iter_reg = fw->aseq_0_reg;
2021 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
2022 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
2023
2024 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
2025 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
2026 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
2027
2028 /* Command DMA registers. */
2029 iter_reg = fw->cmd_dma_reg;
2030 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
2031 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
2032 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
2033 qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
2034
2035 /* Queues. */
2036 iter_reg = fw->req0_dma_reg;
2037 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
2038 dmp_reg = &reg->iobase_q;
2039 for (cnt = 0; cnt < 7; cnt++)
2040 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2041
2042 iter_reg = fw->resp0_dma_reg;
2043 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
2044 dmp_reg = &reg->iobase_q;
2045 for (cnt = 0; cnt < 7; cnt++)
2046 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2047
2048 iter_reg = fw->req1_dma_reg;
2049 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
2050 dmp_reg = &reg->iobase_q;
2051 for (cnt = 0; cnt < 7; cnt++)
2052 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2053
2054 /* Transmit DMA registers. */
2055 iter_reg = fw->xmt0_dma_reg;
2056 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
2057 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
2058
2059 iter_reg = fw->xmt1_dma_reg;
2060 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
2061 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
2062
2063 iter_reg = fw->xmt2_dma_reg;
2064 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
2065 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
2066
2067 iter_reg = fw->xmt3_dma_reg;
2068 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
2069 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
2070
2071 iter_reg = fw->xmt4_dma_reg;
2072 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
2073 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
2074
2075 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
2076
2077 /* Receive DMA registers. */
2078 iter_reg = fw->rcvt0_data_dma_reg;
2079 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
2080 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
2081
2082 iter_reg = fw->rcvt1_data_dma_reg;
2083 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
2084 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
2085
2086 /* RISC registers. */
2087 iter_reg = fw->risc_gp_reg;
2088 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
2089 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
2090 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
2091 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
2092 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
2093 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
2094 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
2095 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
2096
2097 /* Local memory controller registers. */
2098 iter_reg = fw->lmc_reg;
2099 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
2100 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
2101 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
2102 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
2103 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
2104 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
2105 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
2106 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
2107
2108 /* Fibre Protocol Module registers. */
2109 iter_reg = fw->fpm_hdw_reg;
2110 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
2111 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
2112 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
2113 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
2114 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
2115 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
2116 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
2117 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
2118 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
2119 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
2120 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
2121 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
2122 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
2123 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
2124 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
2125 qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
2126
2127 /* RQ0 Array registers. */
2128 iter_reg = fw->rq0_array_reg;
2129 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
2130 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
2131 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
2132 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
2133 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
2134 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
2135 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
2136 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
2137 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
2138 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
2139 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
2140 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
2141 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
2142 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
2143 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
2144 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
2145
2146 /* RQ1 Array registers. */
2147 iter_reg = fw->rq1_array_reg;
2148 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
2149 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
2150 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
2151 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
2152 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
2153 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
2154 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
2155 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
2156 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
2157 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
2158 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
2159 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
2160 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
2161 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
2162 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
2163 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
2164
2165 /* RP0 Array registers. */
2166 iter_reg = fw->rp0_array_reg;
2167 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
2168 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
2169 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
2170 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
2171 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
2172 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
2173 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
2174 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
2175 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
2176 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
2177 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
2178 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
2179 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
2180 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
2181 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
2182 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
2183
2184 /* RP1 Array registers. */
2185 iter_reg = fw->rp1_array_reg;
2186 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
2187 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
2188 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
2189 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
2190 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
2191 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
2192 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
2193 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
2194 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
2195 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
2196 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
2197 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
2198 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
2199 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
2200 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
2201 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
2202
2203 iter_reg = fw->at0_array_reg;
2204 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
2205 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
2206 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
2207 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
2208 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
2209 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
2210 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
2211 qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
2212
2213 /* I/O Queue Control registers. */
2214 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
2215
2216 /* Frame Buffer registers. */
2217 iter_reg = fw->fb_hdw_reg;
2218 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
2219 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
2220 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
2221 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
2222 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
2223 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
2224 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
2225 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
2226 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
2227 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
2228 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
2229 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
2230 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
2231 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
2232 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
2233 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
2234 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
2235 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
2236 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
2237 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
2238 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
2239 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
2240 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
2241 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
2242 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
2243 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
2244 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
2245
2246 /* Multi queue registers */
2247 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
2248 &last_chain);
2249
2250 rval = qla24xx_soft_reset(ha);
2251 if (rval != QLA_SUCCESS) {
2252 ql_log(ql_log_warn, vha, 0xd00e,
2253 "SOFT RESET FAILED, forcing continuation of dump!!!\n");
2254 rval = QLA_SUCCESS;
2255
2256 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2257
2258 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2259 RD_REG_DWORD(&reg->hccr);
2260
2261 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2262 RD_REG_DWORD(&reg->hccr);
2263
2264 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2265 RD_REG_DWORD(&reg->hccr);
2266
2267 for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
2268 udelay(5);
2269
2270 if (!cnt) {
2271 nxt = fw->code_ram;
2272 nxt += sizeof(fw->code_ram);
2273 nxt += (ha->fw_memory_size - 0x100000 + 1);
2274 goto copy_queue;
2275 } else
2276 ql_log(ql_log_warn, vha, 0xd010,
2277 "bigger hammer success?\n");
2278 }
2279
2280 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
2281 &nxt);
2282 if (rval != QLA_SUCCESS)
2283 goto qla83xx_fw_dump_failed_0;
2284
2285 copy_queue:
2286 nxt = qla2xxx_copy_queues(ha, nxt);
2287
2288 nxt = qla24xx_copy_eft(ha, nxt);
2289
2290 /* Chain entries -- started with MQ. */
2291 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
2292 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2293 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
2294 if (last_chain) {
2295 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
2296 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
2297 }
2298
2299 /* Adjust valid length. */
2300 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
2301
2302 qla83xx_fw_dump_failed_0:
2303 qla2xxx_dump_post_process(base_vha, rval);
2304
2305 qla83xx_fw_dump_failed:
2306 if (!hardware_locked)
2307 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2308 }
2309
2310 /****************************************************************************/
2311 /* Driver Debug Functions. */
2312 /****************************************************************************/
2313
2314 static inline int
2315 ql_mask_match(uint32_t level)
2316 {
2317 if (ql2xextended_error_logging == 1)
2318 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2319 return (level & ql2xextended_error_logging) == level;
2320 }
2321
2322 /*
2323 * This function is for formatting and logging debug information.
2324 * It is to be used when vha is available. It formats the message
2325 * and logs it to the messages file.
2326 * parameters:
2327 * level: The level of the debug messages to be printed.
2328 * If ql2xextended_error_logging value is correctly set,
2329 * this message will appear in the messages file.
2330 * vha: Pointer to the scsi_qla_host_t.
2331 * id: This is a unique identifier for the level. It identifies the
2332 * part of the code from where the message originated.
2333 * msg: The message to be displayed.
2334 */
2335 void
2336 ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2337 {
2338 va_list va;
2339 struct va_format vaf;
2340
2341 if (!ql_mask_match(level))
2342 return;
2343
2344 va_start(va, fmt);
2345
2346 vaf.fmt = fmt;
2347 vaf.va = &va;
2348
2349 if (vha != NULL) {
2350 const struct pci_dev *pdev = vha->hw->pdev;
2351 /* <module-name> <pci-name> <msg-id>:<host> Message */
2352 pr_warn("%s [%s]-%04x:%ld: %pV",
2353 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2354 vha->host_no, &vaf);
2355 } else {
2356 pr_warn("%s [%s]-%04x: : %pV",
2357 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
2358 }
2359
2360 va_end(va);
2361
2362 }
2363
2364 /*
2365 * This function is for formatting and logging debug information.
2366 * It is to be used when vha is not available and pci is available,
2367 * i.e., before host allocation. It formats the message and logs it
2368 * to the messages file.
2369 * parameters:
2370 * level: The level of the debug messages to be printed.
2371 * If ql2xextended_error_logging value is correctly set,
2372 * this message will appear in the messages file.
2373 * pdev: Pointer to the struct pci_dev.
2374 * id: This is a unique id for the level. It identifies the part
2375 * of the code from where the message originated.
2376 * msg: The message to be displayed.
2377 */
2378 void
2379 ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2380 const char *fmt, ...)
2381 {
2382 va_list va;
2383 struct va_format vaf;
2384
2385 if (pdev == NULL)
2386 return;
2387 if (!ql_mask_match(level))
2388 return;
2389
2390 va_start(va, fmt);
2391
2392 vaf.fmt = fmt;
2393 vaf.va = &va;
2394
2395 /* <module-name> <dev-name>:<msg-id> Message */
2396 pr_warn("%s [%s]-%04x: : %pV",
2397 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
2398
2399 va_end(va);
2400 }
2401
2402 /*
2403 * This function is for formatting and logging log messages.
2404 * It is to be used when vha is available. It formats the message
2405 * and logs it to the messages file. All the messages will be logged
2406 * irrespective of value of ql2xextended_error_logging.
2407 * parameters:
2408 * level: The level of the log messages to be printed in the
2409 * messages file.
2410 * vha: Pointer to the scsi_qla_host_t
2411 * id: This is a unique id for the level. It identifies the
2412 * part of the code from where the message originated.
2413 * msg: The message to be displayed.
2414 */
2415 void
2416 ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2417 {
2418 va_list va;
2419 struct va_format vaf;
2420 char pbuf[128];
2421
2422 if (level > ql_errlev)
2423 return;
2424
2425 if (vha != NULL) {
2426 const struct pci_dev *pdev = vha->hw->pdev;
2427 /* <module-name> <msg-id>:<host> Message */
2428 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
2429 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
2430 } else {
2431 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2432 QL_MSGHDR, "0000:00:00.0", id);
2433 }
2434 pbuf[sizeof(pbuf) - 1] = 0;
2435
2436 va_start(va, fmt);
2437
2438 vaf.fmt = fmt;
2439 vaf.va = &va;
2440
2441 switch (level) {
2442 case ql_log_fatal: /* FATAL LOG */
2443 pr_crit("%s%pV", pbuf, &vaf);
2444 break;
2445 case ql_log_warn:
2446 pr_err("%s%pV", pbuf, &vaf);
2447 break;
2448 case ql_log_info:
2449 pr_warn("%s%pV", pbuf, &vaf);
2450 break;
2451 default:
2452 pr_info("%s%pV", pbuf, &vaf);
2453 break;
2454 }
2455
2456 va_end(va);
2457 }
2458
2459 /*
2460 * This function is for formatting and logging log messages.
2461 * It is to be used when vha is not available and pci is available,
2462 * i.e., before host allocation. It formats the message and logs
2463 * it to the messages file. All the messages are logged irrespective
2464 * of the value of ql2xextended_error_logging.
2465 * parameters:
2466 * level: The level of the log messages to be printed in the
2467 * messages file.
2468 * pdev: Pointer to the struct pci_dev.
2469 * id: This is a unique id for the level. It identifies the
2470 * part of the code from where the message originated.
2471 * msg: The message to be displayed.
2472 */
2473 void
2474 ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2475 const char *fmt, ...)
2476 {
2477 va_list va;
2478 struct va_format vaf;
2479 char pbuf[128];
2480
2481 if (pdev == NULL)
2482 return;
2483 if (level > ql_errlev)
2484 return;
2485
2486 /* <module-name> <dev-name>:<msg-id> Message */
2487 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2488 QL_MSGHDR, dev_name(&(pdev->dev)), id);
2489 pbuf[sizeof(pbuf) - 1] = 0;
2490
2491 va_start(va, fmt);
2492
2493 vaf.fmt = fmt;
2494 vaf.va = &va;
2495
2496 switch (level) {
2497 case ql_log_fatal: /* FATAL LOG */
2498 pr_crit("%s%pV", pbuf, &vaf);
2499 break;
2500 case ql_log_warn:
2501 pr_err("%s%pV", pbuf, &vaf);
2502 break;
2503 case ql_log_info:
2504 pr_warn("%s%pV", pbuf, &vaf);
2505 break;
2506 default:
2507 pr_info("%s%pV", pbuf, &vaf);
2508 break;
2509 }
2510
2511 va_end(va);
2512 }
2513
2514 void
2515 ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
2516 {
2517 int i;
2518 struct qla_hw_data *ha = vha->hw;
2519 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2520 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2521 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2522 uint16_t __iomem *mbx_reg;
2523
2524 if (!ql_mask_match(level))
2525 return;
2526
2527 if (IS_QLA82XX(ha))
2528 mbx_reg = &reg82->mailbox_in[0];
2529 else if (IS_FWI2_CAPABLE(ha))
2530 mbx_reg = &reg24->mailbox0;
2531 else
2532 mbx_reg = MAILBOX_REG(ha, reg, 0);
2533
2534 ql_dbg(level, vha, id, "Mailbox registers:\n");
2535 for (i = 0; i < 6; i++)
2536 ql_dbg(level, vha, id,
2537 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
2538 }
2539
2540
2541 void
2542 ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
2543 uint8_t *b, uint32_t size)
2544 {
2545 uint32_t cnt;
2546 uint8_t c;
2547
2548 if (!ql_mask_match(level))
2549 return;
2550
2551 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
2552 "9 Ah Bh Ch Dh Eh Fh\n");
2553 ql_dbg(level, vha, id, "----------------------------------"
2554 "----------------------------\n");
2555
2556 ql_dbg(level, vha, id, " ");
2557 for (cnt = 0; cnt < size;) {
2558 c = *b++;
2559 printk("%02x", (uint32_t) c);
2560 cnt++;
2561 if (!(cnt % 16))
2562 printk("\n");
2563 else
2564 printk(" ");
2565 }
2566 if (cnt % 16)
2567 ql_dbg(level, vha, id, "\n");
2568 }
Linux with added FPC-III support