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HID: hiddev: Fix slab-out-of-bounds write in hiddev_ioctl_usage()
[linux/fpc-iii.git] / drivers / bus / arm-ccn.c
blobe764e8ebb86b6396b0a8529faefa1c70adc5abe3
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2014 ARM Limited
12 */
13
14 #include <linux/ctype.h>
15 #include <linux/hrtimer.h>
16 #include <linux/idr.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/perf_event.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23
24 #define CCN_NUM_XP_PORTS 2
25 #define CCN_NUM_VCS 4
26 #define CCN_NUM_REGIONS 256
27 #define CCN_REGION_SIZE 0x10000
28
29 #define CCN_ALL_OLY_ID 0xff00
30 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0
31 #define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f
32 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8
33 #define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f
34
35 #define CCN_MN_ERRINT_STATUS 0x0008
36 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11
37 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02
38 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20
39 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22
40 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04
41 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
42 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44
43 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08
44 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80
45 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88
46 #define CCN_MN_OLY_COMP_LIST_63_0 0x01e0
47 #define CCN_MN_ERR_SIG_VAL_63_0 0x0300
48 #define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1)
49
50 #define CCN_DT_ACTIVE_DSM 0x0000
51 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8)
52 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff
53 #define CCN_DT_CTL 0x0028
54 #define CCN_DT_CTL__DT_EN (1 << 0)
55 #define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8)
56 #define CCN_DT_PMCCNTR 0x0140
57 #define CCN_DT_PMCCNTRSR 0x0190
58 #define CCN_DT_PMOVSR 0x0198
59 #define CCN_DT_PMOVSR_CLR 0x01a0
60 #define CCN_DT_PMOVSR_CLR__MASK 0x1f
61 #define CCN_DT_PMCR 0x01a8
62 #define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6)
63 #define CCN_DT_PMCR__PMU_EN (1 << 0)
64 #define CCN_DT_PMSR 0x01b0
65 #define CCN_DT_PMSR_REQ 0x01b8
66 #define CCN_DT_PMSR_CLR 0x01c0
67
68 #define CCN_HNF_PMU_EVENT_SEL 0x0600
69 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
70 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf
71
72 #define CCN_XP_DT_CONFIG 0x0300
73 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4)
74 #define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf
75 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0
76 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1
77 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n))
78 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n))
79 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
80 #define CCN_XP_DT_INTERFACE_SEL 0x0308
81 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8)
82 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1
83 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8)
84 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1
85 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8)
86 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3
87 #define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40)
88 #define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40)
89 #define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40)
90 #define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40)
91 #define CCN_XP_DT_CONTROL 0x0370
92 #define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0)
93 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4)
94 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf
95 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf
96 #define CCN_XP_PMU_EVENT_SEL 0x0600
97 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7)
98 #define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f
99
100 #define CCN_SBAS_PMU_EVENT_SEL 0x0600
101 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
102 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf
103
104 #define CCN_RNI_PMU_EVENT_SEL 0x0600
105 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
106 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf
107
108 #define CCN_TYPE_MN 0x01
109 #define CCN_TYPE_DT 0x02
110 #define CCN_TYPE_HNF 0x04
111 #define CCN_TYPE_HNI 0x05
112 #define CCN_TYPE_XP 0x08
113 #define CCN_TYPE_SBSX 0x0c
114 #define CCN_TYPE_SBAS 0x10
115 #define CCN_TYPE_RNI_1P 0x14
116 #define CCN_TYPE_RNI_2P 0x15
117 #define CCN_TYPE_RNI_3P 0x16
118 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
119 #define CCN_TYPE_RND_2P 0x19
120 #define CCN_TYPE_RND_3P 0x1a
121 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */
122
123 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
124
125 #define CCN_NUM_PMU_EVENTS 4
126 #define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */
127 #define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */
128 #define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS
129
130 #define CCN_NUM_PREDEFINED_MASKS 4
131 #define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0)
132 #define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1)
133 #define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2)
134 #define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3)
135
136 struct arm_ccn_component {
137 void __iomem *base;
138 u32 type;
139
140 DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
141 union {
142 struct {
143 DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
144 } xp;
145 };
146 };
147
148 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
149 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
150
151 struct arm_ccn_dt {
152 int id;
153 void __iomem *base;
154
155 spinlock_t config_lock;
156
157 DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
158 struct {
159 struct arm_ccn_component *source;
160 struct perf_event *event;
161 } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
162
163 struct {
164 u64 l, h;
165 } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
166
167 struct hrtimer hrtimer;
168
169 cpumask_t cpu;
170 struct notifier_block cpu_nb;
171
172 struct pmu pmu;
173 };
174
175 struct arm_ccn {
176 struct device *dev;
177 void __iomem *base;
178 unsigned int irq;
179
180 unsigned sbas_present:1;
181 unsigned sbsx_present:1;
182
183 int num_nodes;
184 struct arm_ccn_component *node;
185
186 int num_xps;
187 struct arm_ccn_component *xp;
188
189 struct arm_ccn_dt dt;
190 int mn_id;
191 };
192
193
194 static int arm_ccn_node_to_xp(int node)
195 {
196 return node / CCN_NUM_XP_PORTS;
197 }
198
199 static int arm_ccn_node_to_xp_port(int node)
200 {
201 return node % CCN_NUM_XP_PORTS;
202 }
203
204
205 /*
206 * Bit shifts and masks in these defines must be kept in sync with
207 * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
208 */
209 #define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff)
210 #define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff)
211 #define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
212 #define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
213 #define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
214 #define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
215 #define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
216 #define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
217
218 static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
219 {
220 *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
221 *config |= (node_xp << 0) | (type << 8) | (port << 24);
222 }
223
224 static ssize_t arm_ccn_pmu_format_show(struct device *dev,
225 struct device_attribute *attr, char *buf)
226 {
227 struct dev_ext_attribute *ea = container_of(attr,
228 struct dev_ext_attribute, attr);
229
230 return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var);
231 }
232
233 #define CCN_FORMAT_ATTR(_name, _config) \
234 struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
235 { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \
236 NULL), _config }
237
238 static CCN_FORMAT_ATTR(node, "config:0-7");
239 static CCN_FORMAT_ATTR(xp, "config:0-7");
240 static CCN_FORMAT_ATTR(type, "config:8-15");
241 static CCN_FORMAT_ATTR(event, "config:16-23");
242 static CCN_FORMAT_ATTR(port, "config:24-25");
243 static CCN_FORMAT_ATTR(vc, "config:26-28");
244 static CCN_FORMAT_ATTR(dir, "config:29-29");
245 static CCN_FORMAT_ATTR(mask, "config:30-33");
246 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
247 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
248
249 static struct attribute *arm_ccn_pmu_format_attrs[] = {
250 &arm_ccn_pmu_format_attr_node.attr.attr,
251 &arm_ccn_pmu_format_attr_xp.attr.attr,
252 &arm_ccn_pmu_format_attr_type.attr.attr,
253 &arm_ccn_pmu_format_attr_event.attr.attr,
254 &arm_ccn_pmu_format_attr_port.attr.attr,
255 &arm_ccn_pmu_format_attr_vc.attr.attr,
256 &arm_ccn_pmu_format_attr_dir.attr.attr,
257 &arm_ccn_pmu_format_attr_mask.attr.attr,
258 &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
259 &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
260 NULL
261 };
262
263 static struct attribute_group arm_ccn_pmu_format_attr_group = {
264 .name = "format",
265 .attrs = arm_ccn_pmu_format_attrs,
266 };
267
268
269 struct arm_ccn_pmu_event {
270 struct device_attribute attr;
271 u32 type;
272 u32 event;
273 int num_ports;
274 int num_vcs;
275 const char *def;
276 int mask;
277 };
278
279 #define CCN_EVENT_ATTR(_name) \
280 __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
281
282 /*
283 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
284 * their ports in XP they are connected to. For the sake of usability they are
285 * explicitly defined here (and translated into a relevant watchpoint in
286 * arm_ccn_pmu_event_init()) so the user can easily request them without deep
287 * knowledge of the flit format.
288 */
289
290 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
291 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
292 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
293 .def = _def, .mask = _mask, }
294
295 #define CCN_EVENT_HNI(_name, _def, _mask) { \
296 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
297 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
298 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
299
300 #define CCN_EVENT_SBSX(_name, _def, _mask) { \
301 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
302 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
303 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
304
305 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
306 .type = CCN_TYPE_HNF, .event = _event, }
307
308 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
309 .type = CCN_TYPE_XP, .event = _event, \
310 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
311
312 /*
313 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
314 * on configuration. One of them is picked to represent the whole group,
315 * as they all share the same event types.
316 */
317 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
318 .type = CCN_TYPE_RNI_3P, .event = _event, }
319
320 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
321 .type = CCN_TYPE_SBAS, .event = _event, }
322
323 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
324 .type = CCN_TYPE_CYCLES }
325
326
327 static ssize_t arm_ccn_pmu_event_show(struct device *dev,
328 struct device_attribute *attr, char *buf)
329 {
330 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
331 struct arm_ccn_pmu_event *event = container_of(attr,
332 struct arm_ccn_pmu_event, attr);
333 ssize_t res;
334
335 res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type);
336 if (event->event)
337 res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x",
338 event->event);
339 if (event->def)
340 res += snprintf(buf + res, PAGE_SIZE - res, ",%s",
341 event->def);
342 if (event->mask)
343 res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x",
344 event->mask);
345
346 /* Arguments required by an event */
347 switch (event->type) {
348 case CCN_TYPE_CYCLES:
349 break;
350 case CCN_TYPE_XP:
351 res += snprintf(buf + res, PAGE_SIZE - res,
352 ",xp=?,port=?,vc=?,dir=?");
353 if (event->event == CCN_EVENT_WATCHPOINT)
354 res += snprintf(buf + res, PAGE_SIZE - res,
355 ",cmp_l=?,cmp_h=?,mask=?");
356 break;
357 case CCN_TYPE_MN:
358 res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id);
359 break;
360 default:
361 res += snprintf(buf + res, PAGE_SIZE - res, ",node=?");
362 break;
363 }
364
365 res += snprintf(buf + res, PAGE_SIZE - res, "\n");
366
367 return res;
368 }
369
370 static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
371 struct attribute *attr, int index)
372 {
373 struct device *dev = kobj_to_dev(kobj);
374 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
375 struct device_attribute *dev_attr = container_of(attr,
376 struct device_attribute, attr);
377 struct arm_ccn_pmu_event *event = container_of(dev_attr,
378 struct arm_ccn_pmu_event, attr);
379
380 if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
381 return 0;
382 if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
383 return 0;
384
385 return attr->mode;
386 }
387
388 static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
389 CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
390 CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
391 CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
392 CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
393 CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
394 CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
395 CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
396 CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
397 CCN_IDX_MASK_ORDER),
398 CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
399 CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
400 CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
401 CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
402 CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
403 CCN_IDX_MASK_ORDER),
404 CCN_EVENT_HNF(cache_miss, 0x1),
405 CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
406 CCN_EVENT_HNF(cache_fill, 0x3),
407 CCN_EVENT_HNF(pocq_retry, 0x4),
408 CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
409 CCN_EVENT_HNF(sf_hit, 0x6),
410 CCN_EVENT_HNF(sf_evictions, 0x7),
411 CCN_EVENT_HNF(snoops_sent, 0x8),
412 CCN_EVENT_HNF(snoops_broadcast, 0x9),
413 CCN_EVENT_HNF(l3_eviction, 0xa),
414 CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
415 CCN_EVENT_HNF(mc_retries, 0xc),
416 CCN_EVENT_HNF(mc_reqs, 0xd),
417 CCN_EVENT_HNF(qos_hh_retry, 0xe),
418 CCN_EVENT_RNI(rdata_beats_p0, 0x1),
419 CCN_EVENT_RNI(rdata_beats_p1, 0x2),
420 CCN_EVENT_RNI(rdata_beats_p2, 0x3),
421 CCN_EVENT_RNI(rxdat_flits, 0x4),
422 CCN_EVENT_RNI(txdat_flits, 0x5),
423 CCN_EVENT_RNI(txreq_flits, 0x6),
424 CCN_EVENT_RNI(txreq_flits_retried, 0x7),
425 CCN_EVENT_RNI(rrt_full, 0x8),
426 CCN_EVENT_RNI(wrt_full, 0x9),
427 CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
428 CCN_EVENT_XP(upload_starvation, 0x1),
429 CCN_EVENT_XP(download_starvation, 0x2),
430 CCN_EVENT_XP(respin, 0x3),
431 CCN_EVENT_XP(valid_flit, 0x4),
432 CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
433 CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
434 CCN_EVENT_SBAS(rxdat_flits, 0x4),
435 CCN_EVENT_SBAS(txdat_flits, 0x5),
436 CCN_EVENT_SBAS(txreq_flits, 0x6),
437 CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
438 CCN_EVENT_SBAS(rrt_full, 0x8),
439 CCN_EVENT_SBAS(wrt_full, 0x9),
440 CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
441 CCN_EVENT_CYCLES(cycles),
442 };
443
444 /* Populated in arm_ccn_init() */
445 static struct attribute
446 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
447
448 static struct attribute_group arm_ccn_pmu_events_attr_group = {
449 .name = "events",
450 .is_visible = arm_ccn_pmu_events_is_visible,
451 .attrs = arm_ccn_pmu_events_attrs,
452 };
453
454
455 static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
456 {
457 unsigned long i;
458
459 if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
460 return NULL;
461 i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
462
463 switch (name[1]) {
464 case 'l':
465 return &ccn->dt.cmp_mask[i].l;
466 case 'h':
467 return &ccn->dt.cmp_mask[i].h;
468 default:
469 return NULL;
470 }
471 }
472
473 static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
474 struct device_attribute *attr, char *buf)
475 {
476 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
477 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
478
479 return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL;
480 }
481
482 static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
483 struct device_attribute *attr, const char *buf, size_t count)
484 {
485 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
486 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
487 int err = -EINVAL;
488
489 if (mask)
490 err = kstrtoull(buf, 0, mask);
491
492 return err ? err : count;
493 }
494
495 #define CCN_CMP_MASK_ATTR(_name) \
496 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
497 __ATTR(_name, S_IRUGO | S_IWUSR, \
498 arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
499
500 #define CCN_CMP_MASK_ATTR_RO(_name) \
501 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
502 __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
503
504 static CCN_CMP_MASK_ATTR(0l);
505 static CCN_CMP_MASK_ATTR(0h);
506 static CCN_CMP_MASK_ATTR(1l);
507 static CCN_CMP_MASK_ATTR(1h);
508 static CCN_CMP_MASK_ATTR(2l);
509 static CCN_CMP_MASK_ATTR(2h);
510 static CCN_CMP_MASK_ATTR(3l);
511 static CCN_CMP_MASK_ATTR(3h);
512 static CCN_CMP_MASK_ATTR(4l);
513 static CCN_CMP_MASK_ATTR(4h);
514 static CCN_CMP_MASK_ATTR(5l);
515 static CCN_CMP_MASK_ATTR(5h);
516 static CCN_CMP_MASK_ATTR(6l);
517 static CCN_CMP_MASK_ATTR(6h);
518 static CCN_CMP_MASK_ATTR(7l);
519 static CCN_CMP_MASK_ATTR(7h);
520 static CCN_CMP_MASK_ATTR_RO(8l);
521 static CCN_CMP_MASK_ATTR_RO(8h);
522 static CCN_CMP_MASK_ATTR_RO(9l);
523 static CCN_CMP_MASK_ATTR_RO(9h);
524 static CCN_CMP_MASK_ATTR_RO(al);
525 static CCN_CMP_MASK_ATTR_RO(ah);
526 static CCN_CMP_MASK_ATTR_RO(bl);
527 static CCN_CMP_MASK_ATTR_RO(bh);
528
529 static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
530 &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
531 &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
532 &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
533 &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
534 &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
535 &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
536 &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
537 &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
538 &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
539 &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
540 &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
541 &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
542 NULL
543 };
544
545 static struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
546 .name = "cmp_mask",
547 .attrs = arm_ccn_pmu_cmp_mask_attrs,
548 };
549
550 static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev,
551 struct device_attribute *attr, char *buf)
552 {
553 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
554
555 return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu);
556 }
557
558 static struct device_attribute arm_ccn_pmu_cpumask_attr =
559 __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL);
560
561 static struct attribute *arm_ccn_pmu_cpumask_attrs[] = {
562 &arm_ccn_pmu_cpumask_attr.attr,
563 NULL,
564 };
565
566 static struct attribute_group arm_ccn_pmu_cpumask_attr_group = {
567 .attrs = arm_ccn_pmu_cpumask_attrs,
568 };
569
570 /*
571 * Default poll period is 10ms, which is way over the top anyway,
572 * as in the worst case scenario (an event every cycle), with 1GHz
573 * clocked bus, the smallest, 32 bit counter will overflow in
574 * more than 4s.
575 */
576 static unsigned int arm_ccn_pmu_poll_period_us = 10000;
577 module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
578 S_IRUGO | S_IWUSR);
579
580 static ktime_t arm_ccn_pmu_timer_period(void)
581 {
582 return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000);
583 }
584
585
586 static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
587 &arm_ccn_pmu_events_attr_group,
588 &arm_ccn_pmu_format_attr_group,
589 &arm_ccn_pmu_cmp_mask_attr_group,
590 &arm_ccn_pmu_cpumask_attr_group,
591 NULL
592 };
593
594
595 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
596 {
597 int bit;
598
599 do {
600 bit = find_first_zero_bit(bitmap, size);
601 if (bit >= size)
602 return -EAGAIN;
603 } while (test_and_set_bit(bit, bitmap));
604
605 return bit;
606 }
607
608 /* All RN-I and RN-D nodes have identical PMUs */
609 static int arm_ccn_pmu_type_eq(u32 a, u32 b)
610 {
611 if (a == b)
612 return 1;
613
614 switch (a) {
615 case CCN_TYPE_RNI_1P:
616 case CCN_TYPE_RNI_2P:
617 case CCN_TYPE_RNI_3P:
618 case CCN_TYPE_RND_1P:
619 case CCN_TYPE_RND_2P:
620 case CCN_TYPE_RND_3P:
621 switch (b) {
622 case CCN_TYPE_RNI_1P:
623 case CCN_TYPE_RNI_2P:
624 case CCN_TYPE_RNI_3P:
625 case CCN_TYPE_RND_1P:
626 case CCN_TYPE_RND_2P:
627 case CCN_TYPE_RND_3P:
628 return 1;
629 }
630 break;
631 }
632
633 return 0;
634 }
635
636 static int arm_ccn_pmu_event_alloc(struct perf_event *event)
637 {
638 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
639 struct hw_perf_event *hw = &event->hw;
640 u32 node_xp, type, event_id;
641 struct arm_ccn_component *source;
642 int bit;
643
644 node_xp = CCN_CONFIG_NODE(event->attr.config);
645 type = CCN_CONFIG_TYPE(event->attr.config);
646 event_id = CCN_CONFIG_EVENT(event->attr.config);
647
648 /* Allocate the cycle counter */
649 if (type == CCN_TYPE_CYCLES) {
650 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
651 ccn->dt.pmu_counters_mask))
652 return -EAGAIN;
653
654 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
655 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
656
657 return 0;
658 }
659
660 /* Allocate an event counter */
661 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
662 CCN_NUM_PMU_EVENT_COUNTERS);
663 if (hw->idx < 0) {
664 dev_dbg(ccn->dev, "No more counters available!\n");
665 return -EAGAIN;
666 }
667
668 if (type == CCN_TYPE_XP)
669 source = &ccn->xp[node_xp];
670 else
671 source = &ccn->node[node_xp];
672 ccn->dt.pmu_counters[hw->idx].source = source;
673
674 /* Allocate an event source or a watchpoint */
675 if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
676 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
677 CCN_NUM_XP_WATCHPOINTS);
678 else
679 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
680 CCN_NUM_PMU_EVENTS);
681 if (bit < 0) {
682 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
683 node_xp);
684 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
685 return -EAGAIN;
686 }
687 hw->config_base = bit;
688
689 ccn->dt.pmu_counters[hw->idx].event = event;
690
691 return 0;
692 }
693
694 static void arm_ccn_pmu_event_release(struct perf_event *event)
695 {
696 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
697 struct hw_perf_event *hw = &event->hw;
698
699 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
700 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
701 } else {
702 struct arm_ccn_component *source =
703 ccn->dt.pmu_counters[hw->idx].source;
704
705 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
706 CCN_CONFIG_EVENT(event->attr.config) ==
707 CCN_EVENT_WATCHPOINT)
708 clear_bit(hw->config_base, source->xp.dt_cmp_mask);
709 else
710 clear_bit(hw->config_base, source->pmu_events_mask);
711 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
712 }
713
714 ccn->dt.pmu_counters[hw->idx].source = NULL;
715 ccn->dt.pmu_counters[hw->idx].event = NULL;
716 }
717
718 static int arm_ccn_pmu_event_init(struct perf_event *event)
719 {
720 struct arm_ccn *ccn;
721 struct hw_perf_event *hw = &event->hw;
722 u32 node_xp, type, event_id;
723 int valid;
724 int i;
725 struct perf_event *sibling;
726
727 if (event->attr.type != event->pmu->type)
728 return -ENOENT;
729
730 ccn = pmu_to_arm_ccn(event->pmu);
731
732 if (hw->sample_period) {
733 dev_warn(ccn->dev, "Sampling not supported!\n");
734 return -EOPNOTSUPP;
735 }
736
737 if (has_branch_stack(event) || event->attr.exclude_user ||
738 event->attr.exclude_kernel || event->attr.exclude_hv ||
739 event->attr.exclude_idle) {
740 dev_warn(ccn->dev, "Can't exclude execution levels!\n");
741 return -EOPNOTSUPP;
742 }
743
744 if (event->cpu < 0) {
745 dev_warn(ccn->dev, "Can't provide per-task data!\n");
746 return -EOPNOTSUPP;
747 }
748 /*
749 * Many perf core operations (eg. events rotation) operate on a
750 * single CPU context. This is obvious for CPU PMUs, where one
751 * expects the same sets of events being observed on all CPUs,
752 * but can lead to issues for off-core PMUs, like CCN, where each
753 * event could be theoretically assigned to a different CPU. To
754 * mitigate this, we enforce CPU assignment to one, selected
755 * processor (the one described in the "cpumask" attribute).
756 */
757 event->cpu = cpumask_first(&ccn->dt.cpu);
758
759 node_xp = CCN_CONFIG_NODE(event->attr.config);
760 type = CCN_CONFIG_TYPE(event->attr.config);
761 event_id = CCN_CONFIG_EVENT(event->attr.config);
762
763 /* Validate node/xp vs topology */
764 switch (type) {
765 case CCN_TYPE_MN:
766 if (node_xp != ccn->mn_id) {
767 dev_warn(ccn->dev, "Invalid MN ID %d!\n", node_xp);
768 return -EINVAL;
769 }
770 break;
771 case CCN_TYPE_XP:
772 if (node_xp >= ccn->num_xps) {
773 dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp);
774 return -EINVAL;
775 }
776 break;
777 case CCN_TYPE_CYCLES:
778 break;
779 default:
780 if (node_xp >= ccn->num_nodes) {
781 dev_warn(ccn->dev, "Invalid node ID %d!\n", node_xp);
782 return -EINVAL;
783 }
784 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
785 dev_warn(ccn->dev, "Invalid type 0x%x for node %d!\n",
786 type, node_xp);
787 return -EINVAL;
788 }
789 break;
790 }
791
792 /* Validate event ID vs available for the type */
793 for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
794 i++) {
795 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
796 u32 port = CCN_CONFIG_PORT(event->attr.config);
797 u32 vc = CCN_CONFIG_VC(event->attr.config);
798
799 if (!arm_ccn_pmu_type_eq(type, e->type))
800 continue;
801 if (event_id != e->event)
802 continue;
803 if (e->num_ports && port >= e->num_ports) {
804 dev_warn(ccn->dev, "Invalid port %d for node/XP %d!\n",
805 port, node_xp);
806 return -EINVAL;
807 }
808 if (e->num_vcs && vc >= e->num_vcs) {
809 dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n",
810 vc, node_xp);
811 return -EINVAL;
812 }
813 valid = 1;
814 }
815 if (!valid) {
816 dev_warn(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
817 event_id, node_xp);
818 return -EINVAL;
819 }
820
821 /* Watchpoint-based event for a node is actually set on XP */
822 if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
823 u32 port;
824
825 type = CCN_TYPE_XP;
826 port = arm_ccn_node_to_xp_port(node_xp);
827 node_xp = arm_ccn_node_to_xp(node_xp);
828
829 arm_ccn_pmu_config_set(&event->attr.config,
830 node_xp, type, port);
831 }
832
833 /*
834 * We must NOT create groups containing mixed PMUs, although software
835 * events are acceptable (for example to create a CCN group
836 * periodically read when a hrtimer aka cpu-clock leader triggers).
837 */
838 if (event->group_leader->pmu != event->pmu &&
839 !is_software_event(event->group_leader))
840 return -EINVAL;
841
842 list_for_each_entry(sibling, &event->group_leader->sibling_list,
843 group_entry)
844 if (sibling->pmu != event->pmu &&
845 !is_software_event(sibling))
846 return -EINVAL;
847
848 return 0;
849 }
850
851 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
852 {
853 u64 res;
854
855 if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
856 #ifdef readq
857 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
858 #else
859 /* 40 bit counter, can do snapshot and read in two parts */
860 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
861 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
862 ;
863 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
864 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
865 res <<= 32;
866 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
867 #endif
868 } else {
869 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
870 }
871
872 return res;
873 }
874
875 static void arm_ccn_pmu_event_update(struct perf_event *event)
876 {
877 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
878 struct hw_perf_event *hw = &event->hw;
879 u64 prev_count, new_count, mask;
880
881 do {
882 prev_count = local64_read(&hw->prev_count);
883 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
884 } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
885
886 mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
887
888 local64_add((new_count - prev_count) & mask, &event->count);
889 }
890
891 static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
892 {
893 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
894 struct hw_perf_event *hw = &event->hw;
895 struct arm_ccn_component *xp;
896 u32 val, dt_cfg;
897
898 /* Nothing to do for cycle counter */
899 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
900 return;
901
902 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
903 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
904 else
905 xp = &ccn->xp[arm_ccn_node_to_xp(
906 CCN_CONFIG_NODE(event->attr.config))];
907
908 if (enable)
909 dt_cfg = hw->event_base;
910 else
911 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
912
913 spin_lock(&ccn->dt.config_lock);
914
915 val = readl(xp->base + CCN_XP_DT_CONFIG);
916 val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
917 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
918 val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
919 writel(val, xp->base + CCN_XP_DT_CONFIG);
920
921 spin_unlock(&ccn->dt.config_lock);
922 }
923
924 static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
925 {
926 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
927 struct hw_perf_event *hw = &event->hw;
928
929 local64_set(&event->hw.prev_count,
930 arm_ccn_pmu_read_counter(ccn, hw->idx));
931 hw->state = 0;
932
933 /*
934 * Pin the timer, so that the overflows are handled by the chosen
935 * event->cpu (this is the same one as presented in "cpumask"
936 * attribute).
937 */
938 if (!ccn->irq)
939 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
940 HRTIMER_MODE_REL_PINNED);
941
942 /* Set the DT bus input, engaging the counter */
943 arm_ccn_pmu_xp_dt_config(event, 1);
944 }
945
946 static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
947 {
948 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
949 struct hw_perf_event *hw = &event->hw;
950 u64 timeout;
951
952 /* Disable counting, setting the DT bus to pass-through mode */
953 arm_ccn_pmu_xp_dt_config(event, 0);
954
955 if (!ccn->irq)
956 hrtimer_cancel(&ccn->dt.hrtimer);
957
958 /* Let the DT bus drain */
959 timeout = arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) +
960 ccn->num_xps;
961 while (arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) <
962 timeout)
963 cpu_relax();
964
965 if (flags & PERF_EF_UPDATE)
966 arm_ccn_pmu_event_update(event);
967
968 hw->state |= PERF_HES_STOPPED;
969 }
970
971 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
972 {
973 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
974 struct hw_perf_event *hw = &event->hw;
975 struct arm_ccn_component *source =
976 ccn->dt.pmu_counters[hw->idx].source;
977 unsigned long wp = hw->config_base;
978 u32 val;
979 u64 cmp_l = event->attr.config1;
980 u64 cmp_h = event->attr.config2;
981 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
982 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
983
984 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
985
986 /* Direction (RX/TX), device (port) & virtual channel */
987 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
988 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
989 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
990 val |= CCN_CONFIG_DIR(event->attr.config) <<
991 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
992 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
993 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
994 val |= CCN_CONFIG_PORT(event->attr.config) <<
995 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
996 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
997 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
998 val |= CCN_CONFIG_VC(event->attr.config) <<
999 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
1000 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
1001
1002 /* Comparison values */
1003 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
1004 writel((cmp_l >> 32) & 0x7fffffff,
1005 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
1006 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
1007 writel((cmp_h >> 32) & 0x0fffffff,
1008 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
1009
1010 /* Mask */
1011 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
1012 writel((mask_l >> 32) & 0x7fffffff,
1013 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
1014 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
1015 writel((mask_h >> 32) & 0x0fffffff,
1016 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
1017 }
1018
1019 static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
1020 {
1021 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1022 struct hw_perf_event *hw = &event->hw;
1023 struct arm_ccn_component *source =
1024 ccn->dt.pmu_counters[hw->idx].source;
1025 u32 val, id;
1026
1027 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
1028
1029 id = (CCN_CONFIG_VC(event->attr.config) << 4) |
1030 (CCN_CONFIG_PORT(event->attr.config) << 3) |
1031 (CCN_CONFIG_EVENT(event->attr.config) << 0);
1032
1033 val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
1034 val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
1035 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1036 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1037 writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1038 }
1039
1040 static void arm_ccn_pmu_node_event_config(struct perf_event *event)
1041 {
1042 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1043 struct hw_perf_event *hw = &event->hw;
1044 struct arm_ccn_component *source =
1045 ccn->dt.pmu_counters[hw->idx].source;
1046 u32 type = CCN_CONFIG_TYPE(event->attr.config);
1047 u32 val, port;
1048
1049 port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
1050 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
1051 hw->config_base);
1052
1053 /* These *_event_sel regs should be identical, but let's make sure... */
1054 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
1055 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
1056 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
1057 CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
1058 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
1059 CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
1060 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
1061 CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
1062 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
1063 CCN_RNI_PMU_EVENT_SEL__ID__MASK);
1064 if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
1065 !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
1066 return;
1067
1068 /* Set the event id for the pre-allocated counter */
1069 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1070 val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
1071 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1072 val |= CCN_CONFIG_EVENT(event->attr.config) <<
1073 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1074 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1075 }
1076
1077 static void arm_ccn_pmu_event_config(struct perf_event *event)
1078 {
1079 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1080 struct hw_perf_event *hw = &event->hw;
1081 u32 xp, offset, val;
1082
1083 /* Cycle counter requires no setup */
1084 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
1085 return;
1086
1087 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
1088 xp = CCN_CONFIG_XP(event->attr.config);
1089 else
1090 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
1091
1092 spin_lock(&ccn->dt.config_lock);
1093
1094 /* Set the DT bus "distance" register */
1095 offset = (hw->idx / 4) * 4;
1096 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1097 val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
1098 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
1099 val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
1100 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1101
1102 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
1103 if (CCN_CONFIG_EVENT(event->attr.config) ==
1104 CCN_EVENT_WATCHPOINT)
1105 arm_ccn_pmu_xp_watchpoint_config(event);
1106 else
1107 arm_ccn_pmu_xp_event_config(event);
1108 } else {
1109 arm_ccn_pmu_node_event_config(event);
1110 }
1111
1112 spin_unlock(&ccn->dt.config_lock);
1113 }
1114
1115 static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1116 {
1117 int err;
1118 struct hw_perf_event *hw = &event->hw;
1119
1120 err = arm_ccn_pmu_event_alloc(event);
1121 if (err)
1122 return err;
1123
1124 arm_ccn_pmu_event_config(event);
1125
1126 hw->state = PERF_HES_STOPPED;
1127
1128 if (flags & PERF_EF_START)
1129 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
1130
1131 return 0;
1132 }
1133
1134 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1135 {
1136 arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1137
1138 arm_ccn_pmu_event_release(event);
1139 }
1140
1141 static void arm_ccn_pmu_event_read(struct perf_event *event)
1142 {
1143 arm_ccn_pmu_event_update(event);
1144 }
1145
1146 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
1147 {
1148 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1149 int idx;
1150
1151 if (!pmovsr)
1152 return IRQ_NONE;
1153
1154 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1155
1156 BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
1157
1158 for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
1159 struct perf_event *event = dt->pmu_counters[idx].event;
1160 int overflowed = pmovsr & BIT(idx);
1161
1162 WARN_ON_ONCE(overflowed && !event &&
1163 idx != CCN_IDX_PMU_CYCLE_COUNTER);
1164
1165 if (!event || !overflowed)
1166 continue;
1167
1168 arm_ccn_pmu_event_update(event);
1169 }
1170
1171 return IRQ_HANDLED;
1172 }
1173
1174 static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
1175 {
1176 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
1177 hrtimer);
1178 unsigned long flags;
1179
1180 local_irq_save(flags);
1181 arm_ccn_pmu_overflow_handler(dt);
1182 local_irq_restore(flags);
1183
1184 hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
1185 return HRTIMER_RESTART;
1186 }
1187
1188
1189 static int arm_ccn_pmu_cpu_notifier(struct notifier_block *nb,
1190 unsigned long action, void *hcpu)
1191 {
1192 struct arm_ccn_dt *dt = container_of(nb, struct arm_ccn_dt, cpu_nb);
1193 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);
1194 unsigned int cpu = (long)hcpu; /* for (long) see kernel/cpu.c */
1195 unsigned int target;
1196
1197 switch (action & ~CPU_TASKS_FROZEN) {
1198 case CPU_DOWN_PREPARE:
1199 if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu))
1200 break;
1201 target = cpumask_any_but(cpu_online_mask, cpu);
1202 if (target >= nr_cpu_ids)
1203 break;
1204 perf_pmu_migrate_context(&dt->pmu, cpu, target);
1205 cpumask_set_cpu(target, &dt->cpu);
1206 if (ccn->irq)
1207 WARN_ON(irq_set_affinity(ccn->irq, &dt->cpu) != 0);
1208 default:
1209 break;
1210 }
1211
1212 return NOTIFY_OK;
1213 }
1214
1215
1216 static DEFINE_IDA(arm_ccn_pmu_ida);
1217
1218 static int arm_ccn_pmu_init(struct arm_ccn *ccn)
1219 {
1220 int i;
1221 char *name;
1222 int err;
1223
1224 /* Initialize DT subsystem */
1225 ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1226 spin_lock_init(&ccn->dt.config_lock);
1227 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1228 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1229 writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
1230 ccn->dt.base + CCN_DT_PMCR);
1231 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1232 for (i = 0; i < ccn->num_xps; i++) {
1233 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1234 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1235 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1236 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1237 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1238 CCN_XP_DT_CONTROL__DT_ENABLE,
1239 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1240 }
1241 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
1242 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
1243 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
1244 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
1245 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
1246 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
1247 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
1248 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
1249
1250 /* Get a convenient /sys/event_source/devices/ name */
1251 ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);
1252 if (ccn->dt.id == 0) {
1253 name = "ccn";
1254 } else {
1255 int len = snprintf(NULL, 0, "ccn_%d", ccn->dt.id);
1256
1257 name = devm_kzalloc(ccn->dev, len + 1, GFP_KERNEL);
1258 snprintf(name, len + 1, "ccn_%d", ccn->dt.id);
1259 }
1260
1261 /* Perf driver registration */
1262 ccn->dt.pmu = (struct pmu) {
1263 .module = THIS_MODULE,
1264 .attr_groups = arm_ccn_pmu_attr_groups,
1265 .task_ctx_nr = perf_invalid_context,
1266 .event_init = arm_ccn_pmu_event_init,
1267 .add = arm_ccn_pmu_event_add,
1268 .del = arm_ccn_pmu_event_del,
1269 .start = arm_ccn_pmu_event_start,
1270 .stop = arm_ccn_pmu_event_stop,
1271 .read = arm_ccn_pmu_event_read,
1272 };
1273
1274 /* No overflow interrupt? Have to use a timer instead. */
1275 if (!ccn->irq) {
1276 dev_info(ccn->dev, "No access to interrupts, using timer.\n");
1277 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,
1278 HRTIMER_MODE_REL);
1279 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;
1280 }
1281
1282 /* Pick one CPU which we will use to collect data from CCN... */
1283 cpumask_set_cpu(smp_processor_id(), &ccn->dt.cpu);
1284
1285 /*
1286 * ... and change the selection when it goes offline. Priority is
1287 * picked to have a chance to migrate events before perf is notified.
1288 */
1289 ccn->dt.cpu_nb.notifier_call = arm_ccn_pmu_cpu_notifier;
1290 ccn->dt.cpu_nb.priority = CPU_PRI_PERF + 1,
1291 err = register_cpu_notifier(&ccn->dt.cpu_nb);
1292 if (err)
1293 goto error_cpu_notifier;
1294
1295 /* Also make sure that the overflow interrupt is handled by this CPU */
1296 if (ccn->irq) {
1297 err = irq_set_affinity(ccn->irq, &ccn->dt.cpu);
1298 if (err) {
1299 dev_err(ccn->dev, "Failed to set interrupt affinity!\n");
1300 goto error_set_affinity;
1301 }
1302 }
1303
1304 err = perf_pmu_register(&ccn->dt.pmu, name, -1);
1305 if (err)
1306 goto error_pmu_register;
1307
1308 return 0;
1309
1310 error_pmu_register:
1311 error_set_affinity:
1312 unregister_cpu_notifier(&ccn->dt.cpu_nb);
1313 error_cpu_notifier:
1314 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1315 for (i = 0; i < ccn->num_xps; i++)
1316 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1317 writel(0, ccn->dt.base + CCN_DT_PMCR);
1318 return err;
1319 }
1320
1321 static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
1322 {
1323 int i;
1324
1325 irq_set_affinity(ccn->irq, cpu_possible_mask);
1326 unregister_cpu_notifier(&ccn->dt.cpu_nb);
1327 for (i = 0; i < ccn->num_xps; i++)
1328 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1329 writel(0, ccn->dt.base + CCN_DT_PMCR);
1330 perf_pmu_unregister(&ccn->dt.pmu);
1331 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1332 }
1333
1334
1335 static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
1336 int (*callback)(struct arm_ccn *ccn, int region,
1337 void __iomem *base, u32 type, u32 id))
1338 {
1339 int region;
1340
1341 for (region = 0; region < CCN_NUM_REGIONS; region++) {
1342 u32 val, type, id;
1343 void __iomem *base;
1344 int err;
1345
1346 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1347 4 * (region / 32));
1348 if (!(val & (1 << (region % 32))))
1349 continue;
1350
1351 base = ccn->base + region * CCN_REGION_SIZE;
1352 val = readl(base + CCN_ALL_OLY_ID);
1353 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
1354 CCN_ALL_OLY_ID__OLY_ID__MASK;
1355 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
1356 CCN_ALL_OLY_ID__NODE_ID__MASK;
1357
1358 err = callback(ccn, region, base, type, id);
1359 if (err)
1360 return err;
1361 }
1362
1363 return 0;
1364 }
1365
1366 static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
1367 void __iomem *base, u32 type, u32 id)
1368 {
1369
1370 if (type == CCN_TYPE_XP && id >= ccn->num_xps)
1371 ccn->num_xps = id + 1;
1372 else if (id >= ccn->num_nodes)
1373 ccn->num_nodes = id + 1;
1374
1375 return 0;
1376 }
1377
1378 static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
1379 void __iomem *base, u32 type, u32 id)
1380 {
1381 struct arm_ccn_component *component;
1382
1383 dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
1384
1385 switch (type) {
1386 case CCN_TYPE_MN:
1387 ccn->mn_id = id;
1388 return 0;
1389 case CCN_TYPE_DT:
1390 return 0;
1391 case CCN_TYPE_XP:
1392 component = &ccn->xp[id];
1393 break;
1394 case CCN_TYPE_SBSX:
1395 ccn->sbsx_present = 1;
1396 component = &ccn->node[id];
1397 break;
1398 case CCN_TYPE_SBAS:
1399 ccn->sbas_present = 1;
1400 /* Fall-through */
1401 default:
1402 component = &ccn->node[id];
1403 break;
1404 }
1405
1406 component->base = base;
1407 component->type = type;
1408
1409 return 0;
1410 }
1411
1412
1413 static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
1414 const u32 *err_sig_val)
1415 {
1416 /* This should be really handled by firmware... */
1417 dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1418 err_sig_val[5], err_sig_val[4], err_sig_val[3],
1419 err_sig_val[2], err_sig_val[1], err_sig_val[0]);
1420 dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
1421 writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
1422 ccn->base + CCN_MN_ERRINT_STATUS);
1423
1424 return IRQ_HANDLED;
1425 }
1426
1427
1428 static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
1429 {
1430 irqreturn_t res = IRQ_NONE;
1431 struct arm_ccn *ccn = dev_id;
1432 u32 err_sig_val[6];
1433 u32 err_or;
1434 int i;
1435
1436 /* PMU overflow is a special case */
1437 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1438 if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
1439 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
1440 res = arm_ccn_pmu_overflow_handler(&ccn->dt);
1441 }
1442
1443 /* Have to read all err_sig_vals to clear them */
1444 for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
1445 err_sig_val[i] = readl(ccn->base +
1446 CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
1447 err_or |= err_sig_val[i];
1448 }
1449 if (err_or)
1450 res |= arm_ccn_error_handler(ccn, err_sig_val);
1451
1452 if (res != IRQ_NONE)
1453 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
1454 ccn->base + CCN_MN_ERRINT_STATUS);
1455
1456 return res;
1457 }
1458
1459
1460 static int arm_ccn_probe(struct platform_device *pdev)
1461 {
1462 struct arm_ccn *ccn;
1463 struct resource *res;
1464 unsigned int irq;
1465 int err;
1466
1467 ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
1468 if (!ccn)
1469 return -ENOMEM;
1470 ccn->dev = &pdev->dev;
1471 platform_set_drvdata(pdev, ccn);
1472
1473 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1474 if (!res)
1475 return -EINVAL;
1476
1477 if (!devm_request_mem_region(ccn->dev, res->start,
1478 resource_size(res), pdev->name))
1479 return -EBUSY;
1480
1481 ccn->base = devm_ioremap(ccn->dev, res->start,
1482 resource_size(res));
1483 if (!ccn->base)
1484 return -EFAULT;
1485
1486 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1487 if (!res)
1488 return -EINVAL;
1489 irq = res->start;
1490
1491 /* Check if we can use the interrupt */
1492 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
1493 ccn->base + CCN_MN_ERRINT_STATUS);
1494 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1495 CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
1496 /* Can set 'disable' bits, so can acknowledge interrupts */
1497 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1498 ccn->base + CCN_MN_ERRINT_STATUS);
1499 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, 0,
1500 dev_name(ccn->dev), ccn);
1501 if (err)
1502 return err;
1503
1504 ccn->irq = irq;
1505 }
1506
1507
1508 /* Build topology */
1509
1510 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
1511 if (err)
1512 return err;
1513
1514 ccn->node = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_nodes,
1515 GFP_KERNEL);
1516 ccn->xp = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_xps,
1517 GFP_KERNEL);
1518 if (!ccn->node || !ccn->xp)
1519 return -ENOMEM;
1520
1521 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
1522 if (err)
1523 return err;
1524
1525 return arm_ccn_pmu_init(ccn);
1526 }
1527
1528 static int arm_ccn_remove(struct platform_device *pdev)
1529 {
1530 struct arm_ccn *ccn = platform_get_drvdata(pdev);
1531
1532 arm_ccn_pmu_cleanup(ccn);
1533
1534 return 0;
1535 }
1536
1537 static const struct of_device_id arm_ccn_match[] = {
1538 { .compatible = "arm,ccn-504", },
1539 {},
1540 };
1541
1542 static struct platform_driver arm_ccn_driver = {
1543 .driver = {
1544 .name = "arm-ccn",
1545 .of_match_table = arm_ccn_match,
1546 },
1547 .probe = arm_ccn_probe,
1548 .remove = arm_ccn_remove,
1549 };
1550
1551 static int __init arm_ccn_init(void)
1552 {
1553 int i;
1554
1555 for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
1556 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
1557
1558 return platform_driver_register(&arm_ccn_driver);
1559 }
1560
1561 static void __exit arm_ccn_exit(void)
1562 {
1563 platform_driver_unregister(&arm_ccn_driver);
1564 }
1565
1566 module_init(arm_ccn_init);
1567 module_exit(arm_ccn_exit);
1568
1569 MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
1570 MODULE_LICENSE("GPL");
Linux with added FPC-III support