drivers/irqchip/irq-versatile-fpga.c

   1 /*
   2  *  Support for Versatile FPGA-based IRQ controllers
   3  */
   4 #include <linux/bitops.h>
   5 #include <linux/irq.h>
   6 #include <linux/io.h>
   7 #include <linux/irqchip.h>
   8 #include <linux/irqchip/chained_irq.h>
   9 #include <linux/irqchip/versatile-fpga.h>
  10 #include <linux/irqdomain.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_irq.h>
  15
  16 #include <asm/exception.h>
  17 #include <asm/mach/irq.h>
  18
  19 #define IRQ_STATUS              0x00
  20 #define IRQ_RAW_STATUS          0x04
  21 #define IRQ_ENABLE_SET          0x08
  22 #define IRQ_ENABLE_CLEAR        0x0c
  23 #define INT_SOFT_SET            0x10
  24 #define INT_SOFT_CLEAR          0x14
  25 #define FIQ_STATUS              0x20
  26 #define FIQ_RAW_STATUS          0x24
  27 #define FIQ_ENABLE              0x28
  28 #define FIQ_ENABLE_SET          0x28
  29 #define FIQ_ENABLE_CLEAR        0x2C
  30
  31 #define PIC_ENABLES             0x20    /* set interrupt pass through bits */
  32
  33 /**
  34  * struct fpga_irq_data - irq data container for the FPGA IRQ controller
  35  * @base: memory offset in virtual memory
  36  * @chip: chip container for this instance
  37  * @domain: IRQ domain for this instance
  38  * @valid: mask for valid IRQs on this controller
  39  * @used_irqs: number of active IRQs on this controller
  40  */
  41 struct fpga_irq_data {
  42         void __iomem *base;
  43         struct irq_chip chip;
  44         u32 valid;
  45         struct irq_domain *domain;
  46         u8 used_irqs;
  47 };
  48
  49 /* we cannot allocate memory when the controllers are initially registered */
  50 static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
  51 static int fpga_irq_id;
  52
  53 static void fpga_irq_mask(struct irq_data *d)
  54 {
  55         struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
  56         u32 mask = 1 << d->hwirq;
  57
  58         writel(mask, f->base + IRQ_ENABLE_CLEAR);
  59 }
  60
  61 static void fpga_irq_unmask(struct irq_data *d)
  62 {
  63         struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
  64         u32 mask = 1 << d->hwirq;
  65
  66         writel(mask, f->base + IRQ_ENABLE_SET);
  67 }
  68
  69 static void fpga_irq_handle(struct irq_desc *desc)
  70 {
  71         struct irq_chip *chip = irq_desc_get_chip(desc);
  72         struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
  73         u32 status;
  74
  75         chained_irq_enter(chip, desc);
  76
  77         status = readl(f->base + IRQ_STATUS);
  78         if (status == 0) {
  79                 do_bad_IRQ(desc);
  80                 goto out;
  81         }
  82
  83         do {
  84                 unsigned int irq = ffs(status) - 1;
  85
  86                 status &= ~(1 << irq);
  87                 generic_handle_irq(irq_find_mapping(f->domain, irq));
  88         } while (status);
  89
  90 out:
  91         chained_irq_exit(chip, desc);
  92 }
  93
  94 /*
  95  * Handle each interrupt in a single FPGA IRQ controller.  Returns non-zero
  96  * if we've handled at least one interrupt.  This does a single read of the
  97  * status register and handles all interrupts in order from LSB first.
  98  */
  99 static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
 100 {
 101         int handled = 0;
 102         int irq;
 103         u32 status;
 104
 105         while ((status  = readl(f->base + IRQ_STATUS))) {
 106                 irq = ffs(status) - 1;
 107                 handle_domain_irq(f->domain, irq, regs);
 108                 handled = 1;
 109         }
 110
 111         return handled;
 112 }
 113
 114 /*
 115  * Keep iterating over all registered FPGA IRQ controllers until there are
 116  * no pending interrupts.
 117  */
 118 asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
 119 {
 120         int i, handled;
 121
 122         do {
 123                 for (i = 0, handled = 0; i < fpga_irq_id; ++i)
 124                         handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
 125         } while (handled);
 126 }
 127
 128 static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
 129                 irq_hw_number_t hwirq)
 130 {
 131         struct fpga_irq_data *f = d->host_data;
 132
 133         /* Skip invalid IRQs, only register handlers for the real ones */
 134         if (!(f->valid & BIT(hwirq)))
 135                 return -EPERM;
 136         irq_set_chip_data(irq, f);
 137         irq_set_chip_and_handler(irq, &f->chip,
 138                                 handle_level_irq);
 139         irq_set_probe(irq);
 140         return 0;
 141 }
 142
 143 static const struct irq_domain_ops fpga_irqdomain_ops = {
 144         .map = fpga_irqdomain_map,
 145         .xlate = irq_domain_xlate_onetwocell,
 146 };
 147
 148 void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
 149                           int parent_irq, u32 valid, struct device_node *node)
 150 {
 151         struct fpga_irq_data *f;
 152         int i;
 153
 154         if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
 155                 pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__);
 156                 return;
 157         }
 158         f = &fpga_irq_devices[fpga_irq_id];
 159         f->base = base;
 160         f->chip.name = name;
 161         f->chip.irq_ack = fpga_irq_mask;
 162         f->chip.irq_mask = fpga_irq_mask;
 163         f->chip.irq_unmask = fpga_irq_unmask;
 164         f->valid = valid;
 165
 166         if (parent_irq != -1) {
 167                 irq_set_chained_handler_and_data(parent_irq, fpga_irq_handle,
 168                                                  f);
 169         }
 170
 171         /* This will also allocate irq descriptors */
 172         f->domain = irq_domain_add_simple(node, fls(valid), irq_start,
 173                                           &fpga_irqdomain_ops, f);
 174
 175         /* This will allocate all valid descriptors in the linear case */
 176         for (i = 0; i < fls(valid); i++)
 177                 if (valid & BIT(i)) {
 178                         if (!irq_start)
 179                                 irq_create_mapping(f->domain, i);
 180                         f->used_irqs++;
 181                 }
 182
 183         pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
 184                 fpga_irq_id, name, base, f->used_irqs);
 185         if (parent_irq != -1)
 186                 pr_cont(", parent IRQ: %d\n", parent_irq);
 187         else
 188                 pr_cont("\n");
 189
 190         fpga_irq_id++;
 191 }
 192
 193 #ifdef CONFIG_OF
 194 int __init fpga_irq_of_init(struct device_node *node,
 195                             struct device_node *parent)
 196 {
 197         void __iomem *base;
 198         u32 clear_mask;
 199         u32 valid_mask;
 200         int parent_irq;
 201
 202         if (WARN_ON(!node))
 203                 return -ENODEV;
 204
 205         base = of_iomap(node, 0);
 206         WARN(!base, "unable to map fpga irq registers\n");
 207
 208         if (of_property_read_u32(node, "clear-mask", &clear_mask))
 209                 clear_mask = 0;
 210
 211         if (of_property_read_u32(node, "valid-mask", &valid_mask))
 212                 valid_mask = 0;
 213
 214         writel(clear_mask, base + IRQ_ENABLE_CLEAR);
 215         writel(clear_mask, base + FIQ_ENABLE_CLEAR);
 216
 217         /* Some chips are cascaded from a parent IRQ */
 218         parent_irq = irq_of_parse_and_map(node, 0);
 219         if (!parent_irq) {
 220                 set_handle_irq(fpga_handle_irq);
 221                 parent_irq = -1;
 222         }
 223
 224 #ifdef CONFIG_ARCH_VERSATILE
 225         fpga_irq_init(base, node->name, IRQ_SIC_START, parent_irq, valid_mask,
 226                                   node);
 227 #else
 228         fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
 229 #endif
 230
 231         /*
 232          * On Versatile AB/PB, some secondary interrupts have a direct
 233          * pass-thru to the primary controller for IRQs 20 and 22-31 which need
 234          * to be enabled. See section 3.10 of the Versatile AB user guide.
 235          */
 236         if (of_device_is_compatible(node, "arm,versatile-sic"))
 237                 writel(0xffd00000, base + PIC_ENABLES);
 238
 239         return 0;
 240 }
 241 IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init);
 242 IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init);
 243 #endif