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HID: hiddev: Fix slab-out-of-bounds write in hiddev_ioctl_usage()
[linux/fpc-iii.git] / drivers / scsi / arcmsr / arcmsr_hba.c
blob7aa01c1960ea99f01b946c5fa2d714c99ea39247
1 /*
2 *******************************************************************************
3 ** O.S : Linux
4 ** FILE NAME : arcmsr_hba.c
5 ** BY : Nick Cheng, C.L. Huang
6 ** Description: SCSI RAID Device Driver for Areca RAID Controller
7 *******************************************************************************
8 ** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved
9 **
10 ** Web site: www.areca.com.tw
11 ** E-mail: support@areca.com.tw
12 **
13 ** This program is free software; you can redistribute it and/or modify
14 ** it under the terms of the GNU General Public License version 2 as
15 ** published by the Free Software Foundation.
16 ** This program is distributed in the hope that it will be useful,
17 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ** GNU General Public License for more details.
20 *******************************************************************************
21 ** Redistribution and use in source and binary forms, with or without
22 ** modification, are permitted provided that the following conditions
23 ** are met:
24 ** 1. Redistributions of source code must retain the above copyright
25 ** notice, this list of conditions and the following disclaimer.
26 ** 2. Redistributions in binary form must reproduce the above copyright
27 ** notice, this list of conditions and the following disclaimer in the
28 ** documentation and/or other materials provided with the distribution.
29 ** 3. The name of the author may not be used to endorse or promote products
30 ** derived from this software without specific prior written permission.
31 **
32 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
33 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
34 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
35 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
36 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
37 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
39 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
41 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *******************************************************************************
43 ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
44 ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
45 *******************************************************************************
46 */
47 #include <linux/module.h>
48 #include <linux/reboot.h>
49 #include <linux/spinlock.h>
50 #include <linux/pci_ids.h>
51 #include <linux/interrupt.h>
52 #include <linux/moduleparam.h>
53 #include <linux/errno.h>
54 #include <linux/types.h>
55 #include <linux/delay.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/timer.h>
58 #include <linux/slab.h>
59 #include <linux/pci.h>
60 #include <linux/aer.h>
61 #include <linux/circ_buf.h>
62 #include <asm/dma.h>
63 #include <asm/io.h>
64 #include <asm/uaccess.h>
65 #include <scsi/scsi_host.h>
66 #include <scsi/scsi.h>
67 #include <scsi/scsi_cmnd.h>
68 #include <scsi/scsi_tcq.h>
69 #include <scsi/scsi_device.h>
70 #include <scsi/scsi_transport.h>
71 #include <scsi/scsicam.h>
72 #include "arcmsr.h"
73 MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>");
74 MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver");
75 MODULE_LICENSE("Dual BSD/GPL");
76 MODULE_VERSION(ARCMSR_DRIVER_VERSION);
77
78 #define ARCMSR_SLEEPTIME 10
79 #define ARCMSR_RETRYCOUNT 12
80
81 static wait_queue_head_t wait_q;
82 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
83 struct scsi_cmnd *cmd);
84 static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
85 static int arcmsr_abort(struct scsi_cmnd *);
86 static int arcmsr_bus_reset(struct scsi_cmnd *);
87 static int arcmsr_bios_param(struct scsi_device *sdev,
88 struct block_device *bdev, sector_t capacity, int *info);
89 static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
90 static int arcmsr_probe(struct pci_dev *pdev,
91 const struct pci_device_id *id);
92 static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state);
93 static int arcmsr_resume(struct pci_dev *pdev);
94 static void arcmsr_remove(struct pci_dev *pdev);
95 static void arcmsr_shutdown(struct pci_dev *pdev);
96 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
97 static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
98 static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
99 static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
100 u32 intmask_org);
101 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
102 static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb);
103 static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb);
104 static void arcmsr_request_device_map(unsigned long pacb);
105 static void arcmsr_hbaA_request_device_map(struct AdapterControlBlock *acb);
106 static void arcmsr_hbaB_request_device_map(struct AdapterControlBlock *acb);
107 static void arcmsr_hbaC_request_device_map(struct AdapterControlBlock *acb);
108 static void arcmsr_message_isr_bh_fn(struct work_struct *work);
109 static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
110 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
111 static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB);
112 static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb);
113 static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
114 static const char *arcmsr_info(struct Scsi_Host *);
115 static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
116 static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *);
117 static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth)
118 {
119 if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
120 queue_depth = ARCMSR_MAX_CMD_PERLUN;
121 return scsi_change_queue_depth(sdev, queue_depth);
122 }
123
124 static struct scsi_host_template arcmsr_scsi_host_template = {
125 .module = THIS_MODULE,
126 .name = "Areca SAS/SATA RAID driver",
127 .info = arcmsr_info,
128 .queuecommand = arcmsr_queue_command,
129 .eh_abort_handler = arcmsr_abort,
130 .eh_bus_reset_handler = arcmsr_bus_reset,
131 .bios_param = arcmsr_bios_param,
132 .change_queue_depth = arcmsr_adjust_disk_queue_depth,
133 .can_queue = ARCMSR_MAX_OUTSTANDING_CMD,
134 .this_id = ARCMSR_SCSI_INITIATOR_ID,
135 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
136 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
137 .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
138 .use_clustering = ENABLE_CLUSTERING,
139 .shost_attrs = arcmsr_host_attrs,
140 .no_write_same = 1,
141 };
142
143 static struct pci_device_id arcmsr_device_id_table[] = {
144 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110),
145 .driver_data = ACB_ADAPTER_TYPE_A},
146 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120),
147 .driver_data = ACB_ADAPTER_TYPE_A},
148 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130),
149 .driver_data = ACB_ADAPTER_TYPE_A},
150 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160),
151 .driver_data = ACB_ADAPTER_TYPE_A},
152 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170),
153 .driver_data = ACB_ADAPTER_TYPE_A},
154 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200),
155 .driver_data = ACB_ADAPTER_TYPE_B},
156 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201),
157 .driver_data = ACB_ADAPTER_TYPE_B},
158 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202),
159 .driver_data = ACB_ADAPTER_TYPE_B},
160 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210),
161 .driver_data = ACB_ADAPTER_TYPE_A},
162 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214),
163 .driver_data = ACB_ADAPTER_TYPE_D},
164 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220),
165 .driver_data = ACB_ADAPTER_TYPE_A},
166 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230),
167 .driver_data = ACB_ADAPTER_TYPE_A},
168 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260),
169 .driver_data = ACB_ADAPTER_TYPE_A},
170 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270),
171 .driver_data = ACB_ADAPTER_TYPE_A},
172 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280),
173 .driver_data = ACB_ADAPTER_TYPE_A},
174 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380),
175 .driver_data = ACB_ADAPTER_TYPE_A},
176 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381),
177 .driver_data = ACB_ADAPTER_TYPE_A},
178 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680),
179 .driver_data = ACB_ADAPTER_TYPE_A},
180 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681),
181 .driver_data = ACB_ADAPTER_TYPE_A},
182 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880),
183 .driver_data = ACB_ADAPTER_TYPE_C},
184 {0, 0}, /* Terminating entry */
185 };
186 MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
187
188 static struct pci_driver arcmsr_pci_driver = {
189 .name = "arcmsr",
190 .id_table = arcmsr_device_id_table,
191 .probe = arcmsr_probe,
192 .remove = arcmsr_remove,
193 .suspend = arcmsr_suspend,
194 .resume = arcmsr_resume,
195 .shutdown = arcmsr_shutdown,
196 };
197 /*
198 ****************************************************************************
199 ****************************************************************************
200 */
201
202 static void arcmsr_free_mu(struct AdapterControlBlock *acb)
203 {
204 switch (acb->adapter_type) {
205 case ACB_ADAPTER_TYPE_B:
206 case ACB_ADAPTER_TYPE_D: {
207 dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize,
208 acb->dma_coherent2, acb->dma_coherent_handle2);
209 break;
210 }
211 }
212 }
213
214 static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
215 {
216 struct pci_dev *pdev = acb->pdev;
217 switch (acb->adapter_type){
218 case ACB_ADAPTER_TYPE_A:{
219 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
220 if (!acb->pmuA) {
221 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
222 return false;
223 }
224 break;
225 }
226 case ACB_ADAPTER_TYPE_B:{
227 void __iomem *mem_base0, *mem_base1;
228 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
229 if (!mem_base0) {
230 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
231 return false;
232 }
233 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
234 if (!mem_base1) {
235 iounmap(mem_base0);
236 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
237 return false;
238 }
239 acb->mem_base0 = mem_base0;
240 acb->mem_base1 = mem_base1;
241 break;
242 }
243 case ACB_ADAPTER_TYPE_C:{
244 acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
245 if (!acb->pmuC) {
246 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
247 return false;
248 }
249 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
250 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
251 return true;
252 }
253 break;
254 }
255 case ACB_ADAPTER_TYPE_D: {
256 void __iomem *mem_base0;
257 unsigned long addr, range, flags;
258
259 addr = (unsigned long)pci_resource_start(pdev, 0);
260 range = pci_resource_len(pdev, 0);
261 flags = pci_resource_flags(pdev, 0);
262 mem_base0 = ioremap(addr, range);
263 if (!mem_base0) {
264 pr_notice("arcmsr%d: memory mapping region fail\n",
265 acb->host->host_no);
266 return false;
267 }
268 acb->mem_base0 = mem_base0;
269 break;
270 }
271 }
272 return true;
273 }
274
275 static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
276 {
277 switch (acb->adapter_type) {
278 case ACB_ADAPTER_TYPE_A:{
279 iounmap(acb->pmuA);
280 }
281 break;
282 case ACB_ADAPTER_TYPE_B:{
283 iounmap(acb->mem_base0);
284 iounmap(acb->mem_base1);
285 }
286
287 break;
288 case ACB_ADAPTER_TYPE_C:{
289 iounmap(acb->pmuC);
290 }
291 break;
292 case ACB_ADAPTER_TYPE_D:
293 iounmap(acb->mem_base0);
294 break;
295 }
296 }
297
298 static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
299 {
300 irqreturn_t handle_state;
301 struct AdapterControlBlock *acb = dev_id;
302
303 handle_state = arcmsr_interrupt(acb);
304 return handle_state;
305 }
306
307 static int arcmsr_bios_param(struct scsi_device *sdev,
308 struct block_device *bdev, sector_t capacity, int *geom)
309 {
310 int ret, heads, sectors, cylinders, total_capacity;
311 unsigned char *buffer;/* return copy of block device's partition table */
312
313 buffer = scsi_bios_ptable(bdev);
314 if (buffer) {
315 ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
316 kfree(buffer);
317 if (ret != -1)
318 return ret;
319 }
320 total_capacity = capacity;
321 heads = 64;
322 sectors = 32;
323 cylinders = total_capacity / (heads * sectors);
324 if (cylinders > 1024) {
325 heads = 255;
326 sectors = 63;
327 cylinders = total_capacity / (heads * sectors);
328 }
329 geom[0] = heads;
330 geom[1] = sectors;
331 geom[2] = cylinders;
332 return 0;
333 }
334
335 static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)
336 {
337 struct MessageUnit_A __iomem *reg = acb->pmuA;
338 int i;
339
340 for (i = 0; i < 2000; i++) {
341 if (readl(&reg->outbound_intstatus) &
342 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
343 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
344 &reg->outbound_intstatus);
345 return true;
346 }
347 msleep(10);
348 } /* max 20 seconds */
349
350 return false;
351 }
352
353 static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)
354 {
355 struct MessageUnit_B *reg = acb->pmuB;
356 int i;
357
358 for (i = 0; i < 2000; i++) {
359 if (readl(reg->iop2drv_doorbell)
360 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
361 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
362 reg->iop2drv_doorbell);
363 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
364 reg->drv2iop_doorbell);
365 return true;
366 }
367 msleep(10);
368 } /* max 20 seconds */
369
370 return false;
371 }
372
373 static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)
374 {
375 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
376 int i;
377
378 for (i = 0; i < 2000; i++) {
379 if (readl(&phbcmu->outbound_doorbell)
380 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
381 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
382 &phbcmu->outbound_doorbell_clear); /*clear interrupt*/
383 return true;
384 }
385 msleep(10);
386 } /* max 20 seconds */
387
388 return false;
389 }
390
391 static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB)
392 {
393 struct MessageUnit_D *reg = pACB->pmuD;
394 int i;
395
396 for (i = 0; i < 2000; i++) {
397 if (readl(reg->outbound_doorbell)
398 & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
399 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
400 reg->outbound_doorbell);
401 return true;
402 }
403 msleep(10);
404 } /* max 20 seconds */
405 return false;
406 }
407
408 static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb)
409 {
410 struct MessageUnit_A __iomem *reg = acb->pmuA;
411 int retry_count = 30;
412 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
413 do {
414 if (arcmsr_hbaA_wait_msgint_ready(acb))
415 break;
416 else {
417 retry_count--;
418 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
419 timeout, retry count down = %d \n", acb->host->host_no, retry_count);
420 }
421 } while (retry_count != 0);
422 }
423
424 static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb)
425 {
426 struct MessageUnit_B *reg = acb->pmuB;
427 int retry_count = 30;
428 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
429 do {
430 if (arcmsr_hbaB_wait_msgint_ready(acb))
431 break;
432 else {
433 retry_count--;
434 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
435 timeout,retry count down = %d \n", acb->host->host_no, retry_count);
436 }
437 } while (retry_count != 0);
438 }
439
440 static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB)
441 {
442 struct MessageUnit_C __iomem *reg = pACB->pmuC;
443 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
444 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
445 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
446 do {
447 if (arcmsr_hbaC_wait_msgint_ready(pACB)) {
448 break;
449 } else {
450 retry_count--;
451 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
452 timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
453 }
454 } while (retry_count != 0);
455 return;
456 }
457
458 static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB)
459 {
460 int retry_count = 15;
461 struct MessageUnit_D *reg = pACB->pmuD;
462
463 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
464 do {
465 if (arcmsr_hbaD_wait_msgint_ready(pACB))
466 break;
467
468 retry_count--;
469 pr_notice("arcmsr%d: wait 'flush adapter "
470 "cache' timeout, retry count down = %d\n",
471 pACB->host->host_no, retry_count);
472 } while (retry_count != 0);
473 }
474
475 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
476 {
477 switch (acb->adapter_type) {
478
479 case ACB_ADAPTER_TYPE_A: {
480 arcmsr_hbaA_flush_cache(acb);
481 }
482 break;
483
484 case ACB_ADAPTER_TYPE_B: {
485 arcmsr_hbaB_flush_cache(acb);
486 }
487 break;
488 case ACB_ADAPTER_TYPE_C: {
489 arcmsr_hbaC_flush_cache(acb);
490 }
491 break;
492 case ACB_ADAPTER_TYPE_D:
493 arcmsr_hbaD_flush_cache(acb);
494 break;
495 }
496 }
497
498 static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
499 {
500 struct pci_dev *pdev = acb->pdev;
501 void *dma_coherent;
502 dma_addr_t dma_coherent_handle;
503 struct CommandControlBlock *ccb_tmp;
504 int i = 0, j = 0;
505 dma_addr_t cdb_phyaddr;
506 unsigned long roundup_ccbsize;
507 unsigned long max_xfer_len;
508 unsigned long max_sg_entrys;
509 uint32_t firm_config_version;
510
511 for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
512 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
513 acb->devstate[i][j] = ARECA_RAID_GONE;
514
515 max_xfer_len = ARCMSR_MAX_XFER_LEN;
516 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
517 firm_config_version = acb->firm_cfg_version;
518 if((firm_config_version & 0xFF) >= 3){
519 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
520 max_sg_entrys = (max_xfer_len/4096);
521 }
522 acb->host->max_sectors = max_xfer_len/512;
523 acb->host->sg_tablesize = max_sg_entrys;
524 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
525 acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM;
526 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
527 if(!dma_coherent){
528 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
529 return -ENOMEM;
530 }
531 acb->dma_coherent = dma_coherent;
532 acb->dma_coherent_handle = dma_coherent_handle;
533 memset(dma_coherent, 0, acb->uncache_size);
534 ccb_tmp = dma_coherent;
535 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
536 for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
537 cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
538 switch (acb->adapter_type) {
539 case ACB_ADAPTER_TYPE_A:
540 case ACB_ADAPTER_TYPE_B:
541 ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5;
542 break;
543 case ACB_ADAPTER_TYPE_C:
544 case ACB_ADAPTER_TYPE_D:
545 ccb_tmp->cdb_phyaddr = cdb_phyaddr;
546 break;
547 }
548 acb->pccb_pool[i] = ccb_tmp;
549 ccb_tmp->acb = acb;
550 INIT_LIST_HEAD(&ccb_tmp->list);
551 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
552 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
553 dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
554 }
555 return 0;
556 }
557
558 static void arcmsr_message_isr_bh_fn(struct work_struct *work)
559 {
560 struct AdapterControlBlock *acb = container_of(work,
561 struct AdapterControlBlock, arcmsr_do_message_isr_bh);
562 char *acb_dev_map = (char *)acb->device_map;
563 uint32_t __iomem *signature = NULL;
564 char __iomem *devicemap = NULL;
565 int target, lun;
566 struct scsi_device *psdev;
567 char diff, temp;
568
569 switch (acb->adapter_type) {
570 case ACB_ADAPTER_TYPE_A: {
571 struct MessageUnit_A __iomem *reg = acb->pmuA;
572
573 signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
574 devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
575 break;
576 }
577 case ACB_ADAPTER_TYPE_B: {
578 struct MessageUnit_B *reg = acb->pmuB;
579
580 signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
581 devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
582 break;
583 }
584 case ACB_ADAPTER_TYPE_C: {
585 struct MessageUnit_C __iomem *reg = acb->pmuC;
586
587 signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
588 devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
589 break;
590 }
591 case ACB_ADAPTER_TYPE_D: {
592 struct MessageUnit_D *reg = acb->pmuD;
593
594 signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
595 devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
596 break;
597 }
598 }
599 atomic_inc(&acb->rq_map_token);
600 if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG)
601 return;
602 for (target = 0; target < ARCMSR_MAX_TARGETID - 1;
603 target++) {
604 temp = readb(devicemap);
605 diff = (*acb_dev_map) ^ temp;
606 if (diff != 0) {
607 *acb_dev_map = temp;
608 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN;
609 lun++) {
610 if ((diff & 0x01) == 1 &&
611 (temp & 0x01) == 1) {
612 scsi_add_device(acb->host,
613 0, target, lun);
614 } else if ((diff & 0x01) == 1
615 && (temp & 0x01) == 0) {
616 psdev = scsi_device_lookup(acb->host,
617 0, target, lun);
618 if (psdev != NULL) {
619 scsi_remove_device(psdev);
620 scsi_device_put(psdev);
621 }
622 }
623 temp >>= 1;
624 diff >>= 1;
625 }
626 }
627 devicemap++;
628 acb_dev_map++;
629 }
630 }
631
632 static int
633 arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb)
634 {
635 int i, j, r;
636 struct msix_entry entries[ARCMST_NUM_MSIX_VECTORS];
637
638 for (i = 0; i < ARCMST_NUM_MSIX_VECTORS; i++)
639 entries[i].entry = i;
640 r = pci_enable_msix_range(pdev, entries, 1, ARCMST_NUM_MSIX_VECTORS);
641 if (r < 0)
642 goto msi_int;
643 acb->msix_vector_count = r;
644 for (i = 0; i < r; i++) {
645 if (request_irq(entries[i].vector,
646 arcmsr_do_interrupt, 0, "arcmsr", acb)) {
647 pr_warn("arcmsr%d: request_irq =%d failed!\n",
648 acb->host->host_no, entries[i].vector);
649 for (j = 0 ; j < i ; j++)
650 free_irq(entries[j].vector, acb);
651 pci_disable_msix(pdev);
652 goto msi_int;
653 }
654 acb->entries[i] = entries[i];
655 }
656 acb->acb_flags |= ACB_F_MSIX_ENABLED;
657 pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no);
658 return SUCCESS;
659 msi_int:
660 if (pci_enable_msi_exact(pdev, 1) < 0)
661 goto legacy_int;
662 if (request_irq(pdev->irq, arcmsr_do_interrupt,
663 IRQF_SHARED, "arcmsr", acb)) {
664 pr_warn("arcmsr%d: request_irq =%d failed!\n",
665 acb->host->host_no, pdev->irq);
666 pci_disable_msi(pdev);
667 goto legacy_int;
668 }
669 acb->acb_flags |= ACB_F_MSI_ENABLED;
670 pr_info("arcmsr%d: msi enabled\n", acb->host->host_no);
671 return SUCCESS;
672 legacy_int:
673 if (request_irq(pdev->irq, arcmsr_do_interrupt,
674 IRQF_SHARED, "arcmsr", acb)) {
675 pr_warn("arcmsr%d: request_irq = %d failed!\n",
676 acb->host->host_no, pdev->irq);
677 return FAILED;
678 }
679 return SUCCESS;
680 }
681
682 static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
683 {
684 struct Scsi_Host *host;
685 struct AdapterControlBlock *acb;
686 uint8_t bus,dev_fun;
687 int error;
688 error = pci_enable_device(pdev);
689 if(error){
690 return -ENODEV;
691 }
692 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
693 if(!host){
694 goto pci_disable_dev;
695 }
696 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
697 if(error){
698 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
699 if(error){
700 printk(KERN_WARNING
701 "scsi%d: No suitable DMA mask available\n",
702 host->host_no);
703 goto scsi_host_release;
704 }
705 }
706 init_waitqueue_head(&wait_q);
707 bus = pdev->bus->number;
708 dev_fun = pdev->devfn;
709 acb = (struct AdapterControlBlock *) host->hostdata;
710 memset(acb,0,sizeof(struct AdapterControlBlock));
711 acb->pdev = pdev;
712 acb->host = host;
713 host->max_lun = ARCMSR_MAX_TARGETLUN;
714 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
715 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
716 host->can_queue = ARCMSR_MAX_OUTSTANDING_CMD;
717 host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
718 host->this_id = ARCMSR_SCSI_INITIATOR_ID;
719 host->unique_id = (bus << 8) | dev_fun;
720 pci_set_drvdata(pdev, host);
721 pci_set_master(pdev);
722 error = pci_request_regions(pdev, "arcmsr");
723 if(error){
724 goto scsi_host_release;
725 }
726 spin_lock_init(&acb->eh_lock);
727 spin_lock_init(&acb->ccblist_lock);
728 spin_lock_init(&acb->postq_lock);
729 spin_lock_init(&acb->doneq_lock);
730 spin_lock_init(&acb->rqbuffer_lock);
731 spin_lock_init(&acb->wqbuffer_lock);
732 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
733 ACB_F_MESSAGE_RQBUFFER_CLEARED |
734 ACB_F_MESSAGE_WQBUFFER_READED);
735 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
736 INIT_LIST_HEAD(&acb->ccb_free_list);
737 acb->adapter_type = id->driver_data;
738 error = arcmsr_remap_pciregion(acb);
739 if(!error){
740 goto pci_release_regs;
741 }
742 error = arcmsr_get_firmware_spec(acb);
743 if(!error){
744 goto unmap_pci_region;
745 }
746 error = arcmsr_alloc_ccb_pool(acb);
747 if(error){
748 goto free_hbb_mu;
749 }
750 error = scsi_add_host(host, &pdev->dev);
751 if(error){
752 goto free_ccb_pool;
753 }
754 if (arcmsr_request_irq(pdev, acb) == FAILED)
755 goto scsi_host_remove;
756 arcmsr_iop_init(acb);
757 INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
758 atomic_set(&acb->rq_map_token, 16);
759 atomic_set(&acb->ante_token_value, 16);
760 acb->fw_flag = FW_NORMAL;
761 init_timer(&acb->eternal_timer);
762 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
763 acb->eternal_timer.data = (unsigned long) acb;
764 acb->eternal_timer.function = &arcmsr_request_device_map;
765 add_timer(&acb->eternal_timer);
766 if(arcmsr_alloc_sysfs_attr(acb))
767 goto out_free_sysfs;
768 scsi_scan_host(host);
769 return 0;
770 out_free_sysfs:
771 del_timer_sync(&acb->eternal_timer);
772 flush_work(&acb->arcmsr_do_message_isr_bh);
773 arcmsr_stop_adapter_bgrb(acb);
774 arcmsr_flush_adapter_cache(acb);
775 arcmsr_free_irq(pdev, acb);
776 scsi_host_remove:
777 scsi_remove_host(host);
778 free_ccb_pool:
779 arcmsr_free_ccb_pool(acb);
780 free_hbb_mu:
781 arcmsr_free_mu(acb);
782 unmap_pci_region:
783 arcmsr_unmap_pciregion(acb);
784 pci_release_regs:
785 pci_release_regions(pdev);
786 scsi_host_release:
787 scsi_host_put(host);
788 pci_disable_dev:
789 pci_disable_device(pdev);
790 return -ENODEV;
791 }
792
793 static void arcmsr_free_irq(struct pci_dev *pdev,
794 struct AdapterControlBlock *acb)
795 {
796 int i;
797
798 if (acb->acb_flags & ACB_F_MSI_ENABLED) {
799 free_irq(pdev->irq, acb);
800 pci_disable_msi(pdev);
801 } else if (acb->acb_flags & ACB_F_MSIX_ENABLED) {
802 for (i = 0; i < acb->msix_vector_count; i++)
803 free_irq(acb->entries[i].vector, acb);
804 pci_disable_msix(pdev);
805 } else
806 free_irq(pdev->irq, acb);
807 }
808
809 static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state)
810 {
811 uint32_t intmask_org;
812 struct Scsi_Host *host = pci_get_drvdata(pdev);
813 struct AdapterControlBlock *acb =
814 (struct AdapterControlBlock *)host->hostdata;
815
816 intmask_org = arcmsr_disable_outbound_ints(acb);
817 arcmsr_free_irq(pdev, acb);
818 del_timer_sync(&acb->eternal_timer);
819 flush_work(&acb->arcmsr_do_message_isr_bh);
820 arcmsr_stop_adapter_bgrb(acb);
821 arcmsr_flush_adapter_cache(acb);
822 pci_set_drvdata(pdev, host);
823 pci_save_state(pdev);
824 pci_disable_device(pdev);
825 pci_set_power_state(pdev, pci_choose_state(pdev, state));
826 return 0;
827 }
828
829 static int arcmsr_resume(struct pci_dev *pdev)
830 {
831 int error;
832 struct Scsi_Host *host = pci_get_drvdata(pdev);
833 struct AdapterControlBlock *acb =
834 (struct AdapterControlBlock *)host->hostdata;
835
836 pci_set_power_state(pdev, PCI_D0);
837 pci_enable_wake(pdev, PCI_D0, 0);
838 pci_restore_state(pdev);
839 if (pci_enable_device(pdev)) {
840 pr_warn("%s: pci_enable_device error\n", __func__);
841 return -ENODEV;
842 }
843 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
844 if (error) {
845 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
846 if (error) {
847 pr_warn("scsi%d: No suitable DMA mask available\n",
848 host->host_no);
849 goto controller_unregister;
850 }
851 }
852 pci_set_master(pdev);
853 if (arcmsr_request_irq(pdev, acb) == FAILED)
854 goto controller_stop;
855 arcmsr_iop_init(acb);
856 INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
857 atomic_set(&acb->rq_map_token, 16);
858 atomic_set(&acb->ante_token_value, 16);
859 acb->fw_flag = FW_NORMAL;
860 init_timer(&acb->eternal_timer);
861 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
862 acb->eternal_timer.data = (unsigned long) acb;
863 acb->eternal_timer.function = &arcmsr_request_device_map;
864 add_timer(&acb->eternal_timer);
865 return 0;
866 controller_stop:
867 arcmsr_stop_adapter_bgrb(acb);
868 arcmsr_flush_adapter_cache(acb);
869 controller_unregister:
870 scsi_remove_host(host);
871 arcmsr_free_ccb_pool(acb);
872 arcmsr_unmap_pciregion(acb);
873 pci_release_regions(pdev);
874 scsi_host_put(host);
875 pci_disable_device(pdev);
876 return -ENODEV;
877 }
878
879 static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)
880 {
881 struct MessageUnit_A __iomem *reg = acb->pmuA;
882 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
883 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
884 printk(KERN_NOTICE
885 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
886 , acb->host->host_no);
887 return false;
888 }
889 return true;
890 }
891
892 static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)
893 {
894 struct MessageUnit_B *reg = acb->pmuB;
895
896 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
897 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
898 printk(KERN_NOTICE
899 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
900 , acb->host->host_no);
901 return false;
902 }
903 return true;
904 }
905 static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)
906 {
907 struct MessageUnit_C __iomem *reg = pACB->pmuC;
908 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
909 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
910 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
911 printk(KERN_NOTICE
912 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
913 , pACB->host->host_no);
914 return false;
915 }
916 return true;
917 }
918
919 static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)
920 {
921 struct MessageUnit_D *reg = pACB->pmuD;
922
923 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
924 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
925 pr_notice("arcmsr%d: wait 'abort all outstanding "
926 "command' timeout\n", pACB->host->host_no);
927 return false;
928 }
929 return true;
930 }
931
932 static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
933 {
934 uint8_t rtnval = 0;
935 switch (acb->adapter_type) {
936 case ACB_ADAPTER_TYPE_A: {
937 rtnval = arcmsr_hbaA_abort_allcmd(acb);
938 }
939 break;
940
941 case ACB_ADAPTER_TYPE_B: {
942 rtnval = arcmsr_hbaB_abort_allcmd(acb);
943 }
944 break;
945
946 case ACB_ADAPTER_TYPE_C: {
947 rtnval = arcmsr_hbaC_abort_allcmd(acb);
948 }
949 break;
950
951 case ACB_ADAPTER_TYPE_D:
952 rtnval = arcmsr_hbaD_abort_allcmd(acb);
953 break;
954 }
955 return rtnval;
956 }
957
958 static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
959 {
960 struct scsi_cmnd *pcmd = ccb->pcmd;
961
962 scsi_dma_unmap(pcmd);
963 }
964
965 static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
966 {
967 struct AdapterControlBlock *acb = ccb->acb;
968 struct scsi_cmnd *pcmd = ccb->pcmd;
969 unsigned long flags;
970 atomic_dec(&acb->ccboutstandingcount);
971 arcmsr_pci_unmap_dma(ccb);
972 ccb->startdone = ARCMSR_CCB_DONE;
973 spin_lock_irqsave(&acb->ccblist_lock, flags);
974 list_add_tail(&ccb->list, &acb->ccb_free_list);
975 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
976 pcmd->scsi_done(pcmd);
977 }
978
979 static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
980 {
981
982 struct scsi_cmnd *pcmd = ccb->pcmd;
983 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
984 pcmd->result = DID_OK << 16;
985 if (sensebuffer) {
986 int sense_data_length =
987 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
988 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
989 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
990 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
991 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
992 sensebuffer->Valid = 1;
993 }
994 }
995
996 static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
997 {
998 u32 orig_mask = 0;
999 switch (acb->adapter_type) {
1000 case ACB_ADAPTER_TYPE_A : {
1001 struct MessageUnit_A __iomem *reg = acb->pmuA;
1002 orig_mask = readl(&reg->outbound_intmask);
1003 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
1004 &reg->outbound_intmask);
1005 }
1006 break;
1007 case ACB_ADAPTER_TYPE_B : {
1008 struct MessageUnit_B *reg = acb->pmuB;
1009 orig_mask = readl(reg->iop2drv_doorbell_mask);
1010 writel(0, reg->iop2drv_doorbell_mask);
1011 }
1012 break;
1013 case ACB_ADAPTER_TYPE_C:{
1014 struct MessageUnit_C __iomem *reg = acb->pmuC;
1015 /* disable all outbound interrupt */
1016 orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
1017 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
1018 }
1019 break;
1020 case ACB_ADAPTER_TYPE_D: {
1021 struct MessageUnit_D *reg = acb->pmuD;
1022 /* disable all outbound interrupt */
1023 writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
1024 }
1025 break;
1026 }
1027 return orig_mask;
1028 }
1029
1030 static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
1031 struct CommandControlBlock *ccb, bool error)
1032 {
1033 uint8_t id, lun;
1034 id = ccb->pcmd->device->id;
1035 lun = ccb->pcmd->device->lun;
1036 if (!error) {
1037 if (acb->devstate[id][lun] == ARECA_RAID_GONE)
1038 acb->devstate[id][lun] = ARECA_RAID_GOOD;
1039 ccb->pcmd->result = DID_OK << 16;
1040 arcmsr_ccb_complete(ccb);
1041 }else{
1042 switch (ccb->arcmsr_cdb.DeviceStatus) {
1043 case ARCMSR_DEV_SELECT_TIMEOUT: {
1044 acb->devstate[id][lun] = ARECA_RAID_GONE;
1045 ccb->pcmd->result = DID_NO_CONNECT << 16;
1046 arcmsr_ccb_complete(ccb);
1047 }
1048 break;
1049
1050 case ARCMSR_DEV_ABORTED:
1051
1052 case ARCMSR_DEV_INIT_FAIL: {
1053 acb->devstate[id][lun] = ARECA_RAID_GONE;
1054 ccb->pcmd->result = DID_BAD_TARGET << 16;
1055 arcmsr_ccb_complete(ccb);
1056 }
1057 break;
1058
1059 case ARCMSR_DEV_CHECK_CONDITION: {
1060 acb->devstate[id][lun] = ARECA_RAID_GOOD;
1061 arcmsr_report_sense_info(ccb);
1062 arcmsr_ccb_complete(ccb);
1063 }
1064 break;
1065
1066 default:
1067 printk(KERN_NOTICE
1068 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
1069 but got unknown DeviceStatus = 0x%x \n"
1070 , acb->host->host_no
1071 , id
1072 , lun
1073 , ccb->arcmsr_cdb.DeviceStatus);
1074 acb->devstate[id][lun] = ARECA_RAID_GONE;
1075 ccb->pcmd->result = DID_NO_CONNECT << 16;
1076 arcmsr_ccb_complete(ccb);
1077 break;
1078 }
1079 }
1080 }
1081
1082 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
1083 {
1084 int id, lun;
1085 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
1086 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
1087 struct scsi_cmnd *abortcmd = pCCB->pcmd;
1088 if (abortcmd) {
1089 id = abortcmd->device->id;
1090 lun = abortcmd->device->lun;
1091 abortcmd->result |= DID_ABORT << 16;
1092 arcmsr_ccb_complete(pCCB);
1093 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
1094 acb->host->host_no, pCCB);
1095 }
1096 return;
1097 }
1098 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
1099 done acb = '0x%p'"
1100 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
1101 " ccboutstandingcount = %d \n"
1102 , acb->host->host_no
1103 , acb
1104 , pCCB
1105 , pCCB->acb
1106 , pCCB->startdone
1107 , atomic_read(&acb->ccboutstandingcount));
1108 return;
1109 }
1110 arcmsr_report_ccb_state(acb, pCCB, error);
1111 }
1112
1113 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
1114 {
1115 int i = 0;
1116 uint32_t flag_ccb, ccb_cdb_phy;
1117 struct ARCMSR_CDB *pARCMSR_CDB;
1118 bool error;
1119 struct CommandControlBlock *pCCB;
1120 switch (acb->adapter_type) {
1121
1122 case ACB_ADAPTER_TYPE_A: {
1123 struct MessageUnit_A __iomem *reg = acb->pmuA;
1124 uint32_t outbound_intstatus;
1125 outbound_intstatus = readl(&reg->outbound_intstatus) &
1126 acb->outbound_int_enable;
1127 /*clear and abort all outbound posted Q*/
1128 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
1129 while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
1130 && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
1131 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
1132 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1133 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1134 arcmsr_drain_donequeue(acb, pCCB, error);
1135 }
1136 }
1137 break;
1138
1139 case ACB_ADAPTER_TYPE_B: {
1140 struct MessageUnit_B *reg = acb->pmuB;
1141 /*clear all outbound posted Q*/
1142 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
1143 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
1144 flag_ccb = reg->done_qbuffer[i];
1145 if (flag_ccb != 0) {
1146 reg->done_qbuffer[i] = 0;
1147 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
1148 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1149 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1150 arcmsr_drain_donequeue(acb, pCCB, error);
1151 }
1152 reg->post_qbuffer[i] = 0;
1153 }
1154 reg->doneq_index = 0;
1155 reg->postq_index = 0;
1156 }
1157 break;
1158 case ACB_ADAPTER_TYPE_C: {
1159 struct MessageUnit_C __iomem *reg = acb->pmuC;
1160 while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
1161 /*need to do*/
1162 flag_ccb = readl(&reg->outbound_queueport_low);
1163 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
1164 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/
1165 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1166 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1167 arcmsr_drain_donequeue(acb, pCCB, error);
1168 }
1169 }
1170 break;
1171 case ACB_ADAPTER_TYPE_D: {
1172 struct MessageUnit_D *pmu = acb->pmuD;
1173 uint32_t outbound_write_pointer;
1174 uint32_t doneq_index, index_stripped, addressLow, residual, toggle;
1175 unsigned long flags;
1176
1177 residual = atomic_read(&acb->ccboutstandingcount);
1178 for (i = 0; i < residual; i++) {
1179 spin_lock_irqsave(&acb->doneq_lock, flags);
1180 outbound_write_pointer =
1181 pmu->done_qbuffer[0].addressLow + 1;
1182 doneq_index = pmu->doneq_index;
1183 if ((doneq_index & 0xFFF) !=
1184 (outbound_write_pointer & 0xFFF)) {
1185 toggle = doneq_index & 0x4000;
1186 index_stripped = (doneq_index & 0xFFF) + 1;
1187 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
1188 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
1189 ((toggle ^ 0x4000) + 1);
1190 doneq_index = pmu->doneq_index;
1191 spin_unlock_irqrestore(&acb->doneq_lock, flags);
1192 addressLow = pmu->done_qbuffer[doneq_index &
1193 0xFFF].addressLow;
1194 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
1195 pARCMSR_CDB = (struct ARCMSR_CDB *)
1196 (acb->vir2phy_offset + ccb_cdb_phy);
1197 pCCB = container_of(pARCMSR_CDB,
1198 struct CommandControlBlock, arcmsr_cdb);
1199 error = (addressLow &
1200 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ?
1201 true : false;
1202 arcmsr_drain_donequeue(acb, pCCB, error);
1203 writel(doneq_index,
1204 pmu->outboundlist_read_pointer);
1205 } else {
1206 spin_unlock_irqrestore(&acb->doneq_lock, flags);
1207 mdelay(10);
1208 }
1209 }
1210 pmu->postq_index = 0;
1211 pmu->doneq_index = 0x40FF;
1212 }
1213 break;
1214 }
1215 }
1216
1217 static void arcmsr_remove(struct pci_dev *pdev)
1218 {
1219 struct Scsi_Host *host = pci_get_drvdata(pdev);
1220 struct AdapterControlBlock *acb =
1221 (struct AdapterControlBlock *) host->hostdata;
1222 int poll_count = 0;
1223 arcmsr_free_sysfs_attr(acb);
1224 scsi_remove_host(host);
1225 flush_work(&acb->arcmsr_do_message_isr_bh);
1226 del_timer_sync(&acb->eternal_timer);
1227 arcmsr_disable_outbound_ints(acb);
1228 arcmsr_stop_adapter_bgrb(acb);
1229 arcmsr_flush_adapter_cache(acb);
1230 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
1231 acb->acb_flags &= ~ACB_F_IOP_INITED;
1232
1233 for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++){
1234 if (!atomic_read(&acb->ccboutstandingcount))
1235 break;
1236 arcmsr_interrupt(acb);/* FIXME: need spinlock */
1237 msleep(25);
1238 }
1239
1240 if (atomic_read(&acb->ccboutstandingcount)) {
1241 int i;
1242
1243 arcmsr_abort_allcmd(acb);
1244 arcmsr_done4abort_postqueue(acb);
1245 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
1246 struct CommandControlBlock *ccb = acb->pccb_pool[i];
1247 if (ccb->startdone == ARCMSR_CCB_START) {
1248 ccb->startdone = ARCMSR_CCB_ABORTED;
1249 ccb->pcmd->result = DID_ABORT << 16;
1250 arcmsr_ccb_complete(ccb);
1251 }
1252 }
1253 }
1254 arcmsr_free_irq(pdev, acb);
1255 arcmsr_free_ccb_pool(acb);
1256 arcmsr_free_mu(acb);
1257 arcmsr_unmap_pciregion(acb);
1258 pci_release_regions(pdev);
1259 scsi_host_put(host);
1260 pci_disable_device(pdev);
1261 }
1262
1263 static void arcmsr_shutdown(struct pci_dev *pdev)
1264 {
1265 struct Scsi_Host *host = pci_get_drvdata(pdev);
1266 struct AdapterControlBlock *acb =
1267 (struct AdapterControlBlock *)host->hostdata;
1268 del_timer_sync(&acb->eternal_timer);
1269 arcmsr_disable_outbound_ints(acb);
1270 arcmsr_free_irq(pdev, acb);
1271 flush_work(&acb->arcmsr_do_message_isr_bh);
1272 arcmsr_stop_adapter_bgrb(acb);
1273 arcmsr_flush_adapter_cache(acb);
1274 }
1275
1276 static int arcmsr_module_init(void)
1277 {
1278 int error = 0;
1279 error = pci_register_driver(&arcmsr_pci_driver);
1280 return error;
1281 }
1282
1283 static void arcmsr_module_exit(void)
1284 {
1285 pci_unregister_driver(&arcmsr_pci_driver);
1286 }
1287 module_init(arcmsr_module_init);
1288 module_exit(arcmsr_module_exit);
1289
1290 static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
1291 u32 intmask_org)
1292 {
1293 u32 mask;
1294 switch (acb->adapter_type) {
1295
1296 case ACB_ADAPTER_TYPE_A: {
1297 struct MessageUnit_A __iomem *reg = acb->pmuA;
1298 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
1299 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
1300 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
1301 writel(mask, &reg->outbound_intmask);
1302 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
1303 }
1304 break;
1305
1306 case ACB_ADAPTER_TYPE_B: {
1307 struct MessageUnit_B *reg = acb->pmuB;
1308 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
1309 ARCMSR_IOP2DRV_DATA_READ_OK |
1310 ARCMSR_IOP2DRV_CDB_DONE |
1311 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
1312 writel(mask, reg->iop2drv_doorbell_mask);
1313 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
1314 }
1315 break;
1316 case ACB_ADAPTER_TYPE_C: {
1317 struct MessageUnit_C __iomem *reg = acb->pmuC;
1318 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
1319 writel(intmask_org & mask, &reg->host_int_mask);
1320 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
1321 }
1322 break;
1323 case ACB_ADAPTER_TYPE_D: {
1324 struct MessageUnit_D *reg = acb->pmuD;
1325
1326 mask = ARCMSR_ARC1214_ALL_INT_ENABLE;
1327 writel(intmask_org | mask, reg->pcief0_int_enable);
1328 break;
1329 }
1330 }
1331 }
1332
1333 static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
1334 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
1335 {
1336 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1337 int8_t *psge = (int8_t *)&arcmsr_cdb->u;
1338 __le32 address_lo, address_hi;
1339 int arccdbsize = 0x30;
1340 __le32 length = 0;
1341 int i;
1342 struct scatterlist *sg;
1343 int nseg;
1344 ccb->pcmd = pcmd;
1345 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1346 arcmsr_cdb->TargetID = pcmd->device->id;
1347 arcmsr_cdb->LUN = pcmd->device->lun;
1348 arcmsr_cdb->Function = 1;
1349 arcmsr_cdb->msgContext = 0;
1350 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
1351
1352 nseg = scsi_dma_map(pcmd);
1353 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
1354 return FAILED;
1355 scsi_for_each_sg(pcmd, sg, nseg, i) {
1356 /* Get the physical address of the current data pointer */
1357 length = cpu_to_le32(sg_dma_len(sg));
1358 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
1359 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
1360 if (address_hi == 0) {
1361 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1362
1363 pdma_sg->address = address_lo;
1364 pdma_sg->length = length;
1365 psge += sizeof (struct SG32ENTRY);
1366 arccdbsize += sizeof (struct SG32ENTRY);
1367 } else {
1368 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1369
1370 pdma_sg->addresshigh = address_hi;
1371 pdma_sg->address = address_lo;
1372 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
1373 psge += sizeof (struct SG64ENTRY);
1374 arccdbsize += sizeof (struct SG64ENTRY);
1375 }
1376 }
1377 arcmsr_cdb->sgcount = (uint8_t)nseg;
1378 arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
1379 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
1380 if ( arccdbsize > 256)
1381 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1382 if (pcmd->sc_data_direction == DMA_TO_DEVICE)
1383 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1384 ccb->arc_cdb_size = arccdbsize;
1385 return SUCCESS;
1386 }
1387
1388 static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
1389 {
1390 uint32_t cdb_phyaddr = ccb->cdb_phyaddr;
1391 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1392 atomic_inc(&acb->ccboutstandingcount);
1393 ccb->startdone = ARCMSR_CCB_START;
1394 switch (acb->adapter_type) {
1395 case ACB_ADAPTER_TYPE_A: {
1396 struct MessageUnit_A __iomem *reg = acb->pmuA;
1397
1398 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
1399 writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
1400 &reg->inbound_queueport);
1401 else
1402 writel(cdb_phyaddr, &reg->inbound_queueport);
1403 break;
1404 }
1405
1406 case ACB_ADAPTER_TYPE_B: {
1407 struct MessageUnit_B *reg = acb->pmuB;
1408 uint32_t ending_index, index = reg->postq_index;
1409
1410 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
1411 reg->post_qbuffer[ending_index] = 0;
1412 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1413 reg->post_qbuffer[index] =
1414 cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE;
1415 } else {
1416 reg->post_qbuffer[index] = cdb_phyaddr;
1417 }
1418 index++;
1419 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
1420 reg->postq_index = index;
1421 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
1422 }
1423 break;
1424 case ACB_ADAPTER_TYPE_C: {
1425 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
1426 uint32_t ccb_post_stamp, arc_cdb_size;
1427
1428 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
1429 ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1);
1430 if (acb->cdb_phyaddr_hi32) {
1431 writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
1432 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1433 } else {
1434 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1435 }
1436 }
1437 break;
1438 case ACB_ADAPTER_TYPE_D: {
1439 struct MessageUnit_D *pmu = acb->pmuD;
1440 u16 index_stripped;
1441 u16 postq_index, toggle;
1442 unsigned long flags;
1443 struct InBound_SRB *pinbound_srb;
1444
1445 spin_lock_irqsave(&acb->postq_lock, flags);
1446 postq_index = pmu->postq_index;
1447 pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]);
1448 pinbound_srb->addressHigh = dma_addr_hi32(cdb_phyaddr);
1449 pinbound_srb->addressLow = dma_addr_lo32(cdb_phyaddr);
1450 pinbound_srb->length = ccb->arc_cdb_size >> 2;
1451 arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr);
1452 toggle = postq_index & 0x4000;
1453 index_stripped = postq_index + 1;
1454 index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1);
1455 pmu->postq_index = index_stripped ? (index_stripped | toggle) :
1456 (toggle ^ 0x4000);
1457 writel(postq_index, pmu->inboundlist_write_pointer);
1458 spin_unlock_irqrestore(&acb->postq_lock, flags);
1459 break;
1460 }
1461 }
1462 }
1463
1464 static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb)
1465 {
1466 struct MessageUnit_A __iomem *reg = acb->pmuA;
1467 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1468 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
1469 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1470 printk(KERN_NOTICE
1471 "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
1472 , acb->host->host_no);
1473 }
1474 }
1475
1476 static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb)
1477 {
1478 struct MessageUnit_B *reg = acb->pmuB;
1479 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1480 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
1481
1482 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1483 printk(KERN_NOTICE
1484 "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
1485 , acb->host->host_no);
1486 }
1487 }
1488
1489 static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB)
1490 {
1491 struct MessageUnit_C __iomem *reg = pACB->pmuC;
1492 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1493 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
1494 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
1495 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
1496 printk(KERN_NOTICE
1497 "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
1498 , pACB->host->host_no);
1499 }
1500 return;
1501 }
1502
1503 static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB)
1504 {
1505 struct MessageUnit_D *reg = pACB->pmuD;
1506
1507 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1508 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
1509 if (!arcmsr_hbaD_wait_msgint_ready(pACB))
1510 pr_notice("arcmsr%d: wait 'stop adapter background rebulid' "
1511 "timeout\n", pACB->host->host_no);
1512 }
1513
1514 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1515 {
1516 switch (acb->adapter_type) {
1517 case ACB_ADAPTER_TYPE_A: {
1518 arcmsr_hbaA_stop_bgrb(acb);
1519 }
1520 break;
1521
1522 case ACB_ADAPTER_TYPE_B: {
1523 arcmsr_hbaB_stop_bgrb(acb);
1524 }
1525 break;
1526 case ACB_ADAPTER_TYPE_C: {
1527 arcmsr_hbaC_stop_bgrb(acb);
1528 }
1529 break;
1530 case ACB_ADAPTER_TYPE_D:
1531 arcmsr_hbaD_stop_bgrb(acb);
1532 break;
1533 }
1534 }
1535
1536 static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
1537 {
1538 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
1539 }
1540
1541 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1542 {
1543 switch (acb->adapter_type) {
1544 case ACB_ADAPTER_TYPE_A: {
1545 struct MessageUnit_A __iomem *reg = acb->pmuA;
1546 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
1547 }
1548 break;
1549
1550 case ACB_ADAPTER_TYPE_B: {
1551 struct MessageUnit_B *reg = acb->pmuB;
1552 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1553 }
1554 break;
1555 case ACB_ADAPTER_TYPE_C: {
1556 struct MessageUnit_C __iomem *reg = acb->pmuC;
1557
1558 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
1559 }
1560 break;
1561 case ACB_ADAPTER_TYPE_D: {
1562 struct MessageUnit_D *reg = acb->pmuD;
1563 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
1564 reg->inbound_doorbell);
1565 }
1566 break;
1567 }
1568 }
1569
1570 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1571 {
1572 switch (acb->adapter_type) {
1573 case ACB_ADAPTER_TYPE_A: {
1574 struct MessageUnit_A __iomem *reg = acb->pmuA;
1575 /*
1576 ** push inbound doorbell tell iop, driver data write ok
1577 ** and wait reply on next hwinterrupt for next Qbuffer post
1578 */
1579 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
1580 }
1581 break;
1582
1583 case ACB_ADAPTER_TYPE_B: {
1584 struct MessageUnit_B *reg = acb->pmuB;
1585 /*
1586 ** push inbound doorbell tell iop, driver data write ok
1587 ** and wait reply on next hwinterrupt for next Qbuffer post
1588 */
1589 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
1590 }
1591 break;
1592 case ACB_ADAPTER_TYPE_C: {
1593 struct MessageUnit_C __iomem *reg = acb->pmuC;
1594 /*
1595 ** push inbound doorbell tell iop, driver data write ok
1596 ** and wait reply on next hwinterrupt for next Qbuffer post
1597 */
1598 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
1599 }
1600 break;
1601 case ACB_ADAPTER_TYPE_D: {
1602 struct MessageUnit_D *reg = acb->pmuD;
1603 writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
1604 reg->inbound_doorbell);
1605 }
1606 break;
1607 }
1608 }
1609
1610 struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
1611 {
1612 struct QBUFFER __iomem *qbuffer = NULL;
1613 switch (acb->adapter_type) {
1614
1615 case ACB_ADAPTER_TYPE_A: {
1616 struct MessageUnit_A __iomem *reg = acb->pmuA;
1617 qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
1618 }
1619 break;
1620
1621 case ACB_ADAPTER_TYPE_B: {
1622 struct MessageUnit_B *reg = acb->pmuB;
1623 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1624 }
1625 break;
1626 case ACB_ADAPTER_TYPE_C: {
1627 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
1628 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
1629 }
1630 break;
1631 case ACB_ADAPTER_TYPE_D: {
1632 struct MessageUnit_D *reg = acb->pmuD;
1633 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1634 }
1635 break;
1636 }
1637 return qbuffer;
1638 }
1639
1640 static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
1641 {
1642 struct QBUFFER __iomem *pqbuffer = NULL;
1643 switch (acb->adapter_type) {
1644
1645 case ACB_ADAPTER_TYPE_A: {
1646 struct MessageUnit_A __iomem *reg = acb->pmuA;
1647 pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
1648 }
1649 break;
1650
1651 case ACB_ADAPTER_TYPE_B: {
1652 struct MessageUnit_B *reg = acb->pmuB;
1653 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
1654 }
1655 break;
1656 case ACB_ADAPTER_TYPE_C: {
1657 struct MessageUnit_C __iomem *reg = acb->pmuC;
1658 pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
1659 }
1660 break;
1661 case ACB_ADAPTER_TYPE_D: {
1662 struct MessageUnit_D *reg = acb->pmuD;
1663 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
1664 }
1665 break;
1666 }
1667 return pqbuffer;
1668 }
1669
1670 static uint32_t
1671 arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb,
1672 struct QBUFFER __iomem *prbuffer)
1673 {
1674 uint8_t *pQbuffer;
1675 uint8_t *buf1 = NULL;
1676 uint32_t __iomem *iop_data;
1677 uint32_t iop_len, data_len, *buf2 = NULL;
1678
1679 iop_data = (uint32_t __iomem *)prbuffer->data;
1680 iop_len = readl(&prbuffer->data_len);
1681 if (iop_len > 0) {
1682 buf1 = kmalloc(128, GFP_ATOMIC);
1683 buf2 = (uint32_t *)buf1;
1684 if (buf1 == NULL)
1685 return 0;
1686 data_len = iop_len;
1687 while (data_len >= 4) {
1688 *buf2++ = readl(iop_data);
1689 iop_data++;
1690 data_len -= 4;
1691 }
1692 if (data_len)
1693 *buf2 = readl(iop_data);
1694 buf2 = (uint32_t *)buf1;
1695 }
1696 while (iop_len > 0) {
1697 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
1698 *pQbuffer = *buf1;
1699 acb->rqbuf_putIndex++;
1700 /* if last, index number set it to 0 */
1701 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
1702 buf1++;
1703 iop_len--;
1704 }
1705 kfree(buf2);
1706 /* let IOP know data has been read */
1707 arcmsr_iop_message_read(acb);
1708 return 1;
1709 }
1710
1711 uint32_t
1712 arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1713 struct QBUFFER __iomem *prbuffer) {
1714
1715 uint8_t *pQbuffer;
1716 uint8_t __iomem *iop_data;
1717 uint32_t iop_len;
1718
1719 if (acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D))
1720 return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer);
1721 iop_data = (uint8_t __iomem *)prbuffer->data;
1722 iop_len = readl(&prbuffer->data_len);
1723 while (iop_len > 0) {
1724 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
1725 *pQbuffer = readb(iop_data);
1726 acb->rqbuf_putIndex++;
1727 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
1728 iop_data++;
1729 iop_len--;
1730 }
1731 arcmsr_iop_message_read(acb);
1732 return 1;
1733 }
1734
1735 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1736 {
1737 unsigned long flags;
1738 struct QBUFFER __iomem *prbuffer;
1739 int32_t buf_empty_len;
1740
1741 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
1742 prbuffer = arcmsr_get_iop_rqbuffer(acb);
1743 buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) &
1744 (ARCMSR_MAX_QBUFFER - 1);
1745 if (buf_empty_len >= readl(&prbuffer->data_len)) {
1746 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1747 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1748 } else
1749 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1750 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
1751 }
1752
1753 static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb)
1754 {
1755 uint8_t *pQbuffer;
1756 struct QBUFFER __iomem *pwbuffer;
1757 uint8_t *buf1 = NULL;
1758 uint32_t __iomem *iop_data;
1759 uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data;
1760
1761 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
1762 buf1 = kmalloc(128, GFP_ATOMIC);
1763 buf2 = (uint32_t *)buf1;
1764 if (buf1 == NULL)
1765 return;
1766
1767 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1768 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1769 iop_data = (uint32_t __iomem *)pwbuffer->data;
1770 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
1771 && (allxfer_len < 124)) {
1772 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
1773 *buf1 = *pQbuffer;
1774 acb->wqbuf_getIndex++;
1775 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
1776 buf1++;
1777 allxfer_len++;
1778 }
1779 data_len = allxfer_len;
1780 buf1 = (uint8_t *)buf2;
1781 while (data_len >= 4) {
1782 data = *buf2++;
1783 writel(data, iop_data);
1784 iop_data++;
1785 data_len -= 4;
1786 }
1787 if (data_len) {
1788 data = *buf2;
1789 writel(data, iop_data);
1790 }
1791 writel(allxfer_len, &pwbuffer->data_len);
1792 kfree(buf1);
1793 arcmsr_iop_message_wrote(acb);
1794 }
1795 }
1796
1797 void
1798 arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb)
1799 {
1800 uint8_t *pQbuffer;
1801 struct QBUFFER __iomem *pwbuffer;
1802 uint8_t __iomem *iop_data;
1803 int32_t allxfer_len = 0;
1804
1805 if (acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
1806 arcmsr_write_ioctldata2iop_in_DWORD(acb);
1807 return;
1808 }
1809 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
1810 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1811 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1812 iop_data = (uint8_t __iomem *)pwbuffer->data;
1813 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
1814 && (allxfer_len < 124)) {
1815 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
1816 writeb(*pQbuffer, iop_data);
1817 acb->wqbuf_getIndex++;
1818 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
1819 iop_data++;
1820 allxfer_len++;
1821 }
1822 writel(allxfer_len, &pwbuffer->data_len);
1823 arcmsr_iop_message_wrote(acb);
1824 }
1825 }
1826
1827 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1828 {
1829 unsigned long flags;
1830
1831 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
1832 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
1833 if (acb->wqbuf_getIndex != acb->wqbuf_putIndex)
1834 arcmsr_write_ioctldata2iop(acb);
1835 if (acb->wqbuf_getIndex == acb->wqbuf_putIndex)
1836 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1837 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
1838 }
1839
1840 static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb)
1841 {
1842 uint32_t outbound_doorbell;
1843 struct MessageUnit_A __iomem *reg = acb->pmuA;
1844 outbound_doorbell = readl(&reg->outbound_doorbell);
1845 do {
1846 writel(outbound_doorbell, &reg->outbound_doorbell);
1847 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK)
1848 arcmsr_iop2drv_data_wrote_handle(acb);
1849 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)
1850 arcmsr_iop2drv_data_read_handle(acb);
1851 outbound_doorbell = readl(&reg->outbound_doorbell);
1852 } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
1853 | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK));
1854 }
1855 static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB)
1856 {
1857 uint32_t outbound_doorbell;
1858 struct MessageUnit_C __iomem *reg = pACB->pmuC;
1859 /*
1860 *******************************************************************
1861 ** Maybe here we need to check wrqbuffer_lock is lock or not
1862 ** DOORBELL: din! don!
1863 ** check if there are any mail need to pack from firmware
1864 *******************************************************************
1865 */
1866 outbound_doorbell = readl(&reg->outbound_doorbell);
1867 do {
1868 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
1869 readl(&reg->outbound_doorbell_clear);
1870 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK)
1871 arcmsr_iop2drv_data_wrote_handle(pACB);
1872 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK)
1873 arcmsr_iop2drv_data_read_handle(pACB);
1874 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)
1875 arcmsr_hbaC_message_isr(pACB);
1876 outbound_doorbell = readl(&reg->outbound_doorbell);
1877 } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
1878 | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
1879 | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE));
1880 }
1881
1882 static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB)
1883 {
1884 uint32_t outbound_doorbell;
1885 struct MessageUnit_D *pmu = pACB->pmuD;
1886
1887 outbound_doorbell = readl(pmu->outbound_doorbell);
1888 do {
1889 writel(outbound_doorbell, pmu->outbound_doorbell);
1890 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)
1891 arcmsr_hbaD_message_isr(pACB);
1892 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK)
1893 arcmsr_iop2drv_data_wrote_handle(pACB);
1894 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK)
1895 arcmsr_iop2drv_data_read_handle(pACB);
1896 outbound_doorbell = readl(pmu->outbound_doorbell);
1897 } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
1898 | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
1899 | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE));
1900 }
1901
1902 static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb)
1903 {
1904 uint32_t flag_ccb;
1905 struct MessageUnit_A __iomem *reg = acb->pmuA;
1906 struct ARCMSR_CDB *pARCMSR_CDB;
1907 struct CommandControlBlock *pCCB;
1908 bool error;
1909 while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
1910 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
1911 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1912 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1913 arcmsr_drain_donequeue(acb, pCCB, error);
1914 }
1915 }
1916 static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb)
1917 {
1918 uint32_t index;
1919 uint32_t flag_ccb;
1920 struct MessageUnit_B *reg = acb->pmuB;
1921 struct ARCMSR_CDB *pARCMSR_CDB;
1922 struct CommandControlBlock *pCCB;
1923 bool error;
1924 index = reg->doneq_index;
1925 while ((flag_ccb = reg->done_qbuffer[index]) != 0) {
1926 reg->done_qbuffer[index] = 0;
1927 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
1928 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1929 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1930 arcmsr_drain_donequeue(acb, pCCB, error);
1931 index++;
1932 index %= ARCMSR_MAX_HBB_POSTQUEUE;
1933 reg->doneq_index = index;
1934 }
1935 }
1936
1937 static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb)
1938 {
1939 struct MessageUnit_C __iomem *phbcmu;
1940 struct ARCMSR_CDB *arcmsr_cdb;
1941 struct CommandControlBlock *ccb;
1942 uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
1943 int error;
1944
1945 phbcmu = acb->pmuC;
1946 /* areca cdb command done */
1947 /* Use correct offset and size for syncing */
1948
1949 while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) !=
1950 0xFFFFFFFF) {
1951 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
1952 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
1953 + ccb_cdb_phy);
1954 ccb = container_of(arcmsr_cdb, struct CommandControlBlock,
1955 arcmsr_cdb);
1956 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
1957 ? true : false;
1958 /* check if command done with no error */
1959 arcmsr_drain_donequeue(acb, ccb, error);
1960 throttling++;
1961 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1962 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
1963 &phbcmu->inbound_doorbell);
1964 throttling = 0;
1965 }
1966 }
1967 }
1968
1969 static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb)
1970 {
1971 u32 outbound_write_pointer, doneq_index, index_stripped, toggle;
1972 uint32_t addressLow, ccb_cdb_phy;
1973 int error;
1974 struct MessageUnit_D *pmu;
1975 struct ARCMSR_CDB *arcmsr_cdb;
1976 struct CommandControlBlock *ccb;
1977 unsigned long flags;
1978
1979 spin_lock_irqsave(&acb->doneq_lock, flags);
1980 pmu = acb->pmuD;
1981 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
1982 doneq_index = pmu->doneq_index;
1983 if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) {
1984 do {
1985 toggle = doneq_index & 0x4000;
1986 index_stripped = (doneq_index & 0xFFF) + 1;
1987 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
1988 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
1989 ((toggle ^ 0x4000) + 1);
1990 doneq_index = pmu->doneq_index;
1991 addressLow = pmu->done_qbuffer[doneq_index &
1992 0xFFF].addressLow;
1993 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
1994 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
1995 + ccb_cdb_phy);
1996 ccb = container_of(arcmsr_cdb,
1997 struct CommandControlBlock, arcmsr_cdb);
1998 error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
1999 ? true : false;
2000 arcmsr_drain_donequeue(acb, ccb, error);
2001 writel(doneq_index, pmu->outboundlist_read_pointer);
2002 } while ((doneq_index & 0xFFF) !=
2003 (outbound_write_pointer & 0xFFF));
2004 }
2005 writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
2006 pmu->outboundlist_interrupt_cause);
2007 readl(pmu->outboundlist_interrupt_cause);
2008 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2009 }
2010
2011 /*
2012 **********************************************************************************
2013 ** Handle a message interrupt
2014 **
2015 ** The only message interrupt we expect is in response to a query for the current adapter config.
2016 ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
2017 **********************************************************************************
2018 */
2019 static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb)
2020 {
2021 struct MessageUnit_A __iomem *reg = acb->pmuA;
2022 /*clear interrupt and message state*/
2023 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
2024 schedule_work(&acb->arcmsr_do_message_isr_bh);
2025 }
2026 static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb)
2027 {
2028 struct MessageUnit_B *reg = acb->pmuB;
2029
2030 /*clear interrupt and message state*/
2031 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
2032 schedule_work(&acb->arcmsr_do_message_isr_bh);
2033 }
2034 /*
2035 **********************************************************************************
2036 ** Handle a message interrupt
2037 **
2038 ** The only message interrupt we expect is in response to a query for the
2039 ** current adapter config.
2040 ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
2041 **********************************************************************************
2042 */
2043 static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb)
2044 {
2045 struct MessageUnit_C __iomem *reg = acb->pmuC;
2046 /*clear interrupt and message state*/
2047 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
2048 schedule_work(&acb->arcmsr_do_message_isr_bh);
2049 }
2050
2051 static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb)
2052 {
2053 struct MessageUnit_D *reg = acb->pmuD;
2054
2055 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
2056 readl(reg->outbound_doorbell);
2057 schedule_work(&acb->arcmsr_do_message_isr_bh);
2058 }
2059
2060 static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb)
2061 {
2062 uint32_t outbound_intstatus;
2063 struct MessageUnit_A __iomem *reg = acb->pmuA;
2064 outbound_intstatus = readl(&reg->outbound_intstatus) &
2065 acb->outbound_int_enable;
2066 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT))
2067 return IRQ_NONE;
2068 do {
2069 writel(outbound_intstatus, &reg->outbound_intstatus);
2070 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT)
2071 arcmsr_hbaA_doorbell_isr(acb);
2072 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT)
2073 arcmsr_hbaA_postqueue_isr(acb);
2074 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT)
2075 arcmsr_hbaA_message_isr(acb);
2076 outbound_intstatus = readl(&reg->outbound_intstatus) &
2077 acb->outbound_int_enable;
2078 } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT
2079 | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
2080 | ARCMSR_MU_OUTBOUND_MESSAGE0_INT));
2081 return IRQ_HANDLED;
2082 }
2083
2084 static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb)
2085 {
2086 uint32_t outbound_doorbell;
2087 struct MessageUnit_B *reg = acb->pmuB;
2088 outbound_doorbell = readl(reg->iop2drv_doorbell) &
2089 acb->outbound_int_enable;
2090 if (!outbound_doorbell)
2091 return IRQ_NONE;
2092 do {
2093 writel(~outbound_doorbell, reg->iop2drv_doorbell);
2094 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
2095 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK)
2096 arcmsr_iop2drv_data_wrote_handle(acb);
2097 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK)
2098 arcmsr_iop2drv_data_read_handle(acb);
2099 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE)
2100 arcmsr_hbaB_postqueue_isr(acb);
2101 if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)
2102 arcmsr_hbaB_message_isr(acb);
2103 outbound_doorbell = readl(reg->iop2drv_doorbell) &
2104 acb->outbound_int_enable;
2105 } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK
2106 | ARCMSR_IOP2DRV_DATA_READ_OK
2107 | ARCMSR_IOP2DRV_CDB_DONE
2108 | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE));
2109 return IRQ_HANDLED;
2110 }
2111
2112 static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB)
2113 {
2114 uint32_t host_interrupt_status;
2115 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
2116 /*
2117 *********************************************
2118 ** check outbound intstatus
2119 *********************************************
2120 */
2121 host_interrupt_status = readl(&phbcmu->host_int_status) &
2122 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2123 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2124 if (!host_interrupt_status)
2125 return IRQ_NONE;
2126 do {
2127 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)
2128 arcmsr_hbaC_doorbell_isr(pACB);
2129 /* MU post queue interrupts*/
2130 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)
2131 arcmsr_hbaC_postqueue_isr(pACB);
2132 host_interrupt_status = readl(&phbcmu->host_int_status);
2133 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2134 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2135 return IRQ_HANDLED;
2136 }
2137
2138 static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB)
2139 {
2140 u32 host_interrupt_status;
2141 struct MessageUnit_D *pmu = pACB->pmuD;
2142
2143 host_interrupt_status = readl(pmu->host_int_status) &
2144 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2145 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR);
2146 if (!host_interrupt_status)
2147 return IRQ_NONE;
2148 do {
2149 /* MU post queue interrupts*/
2150 if (host_interrupt_status &
2151 ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR)
2152 arcmsr_hbaD_postqueue_isr(pACB);
2153 if (host_interrupt_status &
2154 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)
2155 arcmsr_hbaD_doorbell_isr(pACB);
2156 host_interrupt_status = readl(pmu->host_int_status);
2157 } while (host_interrupt_status &
2158 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2159 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR));
2160 return IRQ_HANDLED;
2161 }
2162
2163 static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
2164 {
2165 switch (acb->adapter_type) {
2166 case ACB_ADAPTER_TYPE_A:
2167 return arcmsr_hbaA_handle_isr(acb);
2168 break;
2169 case ACB_ADAPTER_TYPE_B:
2170 return arcmsr_hbaB_handle_isr(acb);
2171 break;
2172 case ACB_ADAPTER_TYPE_C:
2173 return arcmsr_hbaC_handle_isr(acb);
2174 case ACB_ADAPTER_TYPE_D:
2175 return arcmsr_hbaD_handle_isr(acb);
2176 default:
2177 return IRQ_NONE;
2178 }
2179 }
2180
2181 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2182 {
2183 if (acb) {
2184 /* stop adapter background rebuild */
2185 if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
2186 uint32_t intmask_org;
2187 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
2188 intmask_org = arcmsr_disable_outbound_ints(acb);
2189 arcmsr_stop_adapter_bgrb(acb);
2190 arcmsr_flush_adapter_cache(acb);
2191 arcmsr_enable_outbound_ints(acb, intmask_org);
2192 }
2193 }
2194 }
2195
2196
2197 void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb)
2198 {
2199 uint32_t i;
2200
2201 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2202 for (i = 0; i < 15; i++) {
2203 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2204 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2205 acb->rqbuf_getIndex = 0;
2206 acb->rqbuf_putIndex = 0;
2207 arcmsr_iop_message_read(acb);
2208 mdelay(30);
2209 } else if (acb->rqbuf_getIndex !=
2210 acb->rqbuf_putIndex) {
2211 acb->rqbuf_getIndex = 0;
2212 acb->rqbuf_putIndex = 0;
2213 mdelay(30);
2214 } else
2215 break;
2216 }
2217 }
2218 }
2219
2220 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
2221 struct scsi_cmnd *cmd)
2222 {
2223 char *buffer;
2224 unsigned short use_sg;
2225 int retvalue = 0, transfer_len = 0;
2226 unsigned long flags;
2227 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2228 uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 |
2229 (uint32_t)cmd->cmnd[6] << 16 |
2230 (uint32_t)cmd->cmnd[7] << 8 |
2231 (uint32_t)cmd->cmnd[8];
2232 struct scatterlist *sg;
2233
2234 use_sg = scsi_sg_count(cmd);
2235 sg = scsi_sglist(cmd);
2236 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
2237 if (use_sg > 1) {
2238 retvalue = ARCMSR_MESSAGE_FAIL;
2239 goto message_out;
2240 }
2241 transfer_len += sg->length;
2242 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2243 retvalue = ARCMSR_MESSAGE_FAIL;
2244 pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__);
2245 goto message_out;
2246 }
2247 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer;
2248 switch (controlcode) {
2249 case ARCMSR_MESSAGE_READ_RQBUFFER: {
2250 unsigned char *ver_addr;
2251 uint8_t *ptmpQbuffer;
2252 uint32_t allxfer_len = 0;
2253 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
2254 if (!ver_addr) {
2255 retvalue = ARCMSR_MESSAGE_FAIL;
2256 pr_info("%s: memory not enough!\n", __func__);
2257 goto message_out;
2258 }
2259 ptmpQbuffer = ver_addr;
2260 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2261 if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) {
2262 unsigned int tail = acb->rqbuf_getIndex;
2263 unsigned int head = acb->rqbuf_putIndex;
2264 unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER);
2265
2266 allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER);
2267 if (allxfer_len > ARCMSR_API_DATA_BUFLEN)
2268 allxfer_len = ARCMSR_API_DATA_BUFLEN;
2269
2270 if (allxfer_len <= cnt_to_end)
2271 memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len);
2272 else {
2273 memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end);
2274 memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end);
2275 }
2276 acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER;
2277 }
2278 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr,
2279 allxfer_len);
2280 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2281 struct QBUFFER __iomem *prbuffer;
2282 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2283 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2284 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2285 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2286 }
2287 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2288 kfree(ver_addr);
2289 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2290 if (acb->fw_flag == FW_DEADLOCK)
2291 pcmdmessagefld->cmdmessage.ReturnCode =
2292 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2293 else
2294 pcmdmessagefld->cmdmessage.ReturnCode =
2295 ARCMSR_MESSAGE_RETURNCODE_OK;
2296 break;
2297 }
2298 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2299 unsigned char *ver_addr;
2300 uint32_t user_len;
2301 int32_t cnt2end;
2302 uint8_t *pQbuffer, *ptmpuserbuffer;
2303
2304 user_len = pcmdmessagefld->cmdmessage.Length;
2305 if (user_len > ARCMSR_API_DATA_BUFLEN) {
2306 retvalue = ARCMSR_MESSAGE_FAIL;
2307 goto message_out;
2308 }
2309
2310 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
2311 if (!ver_addr) {
2312 retvalue = ARCMSR_MESSAGE_FAIL;
2313 goto message_out;
2314 }
2315 ptmpuserbuffer = ver_addr;
2316
2317 memcpy(ptmpuserbuffer,
2318 pcmdmessagefld->messagedatabuffer, user_len);
2319 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2320 if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) {
2321 struct SENSE_DATA *sensebuffer =
2322 (struct SENSE_DATA *)cmd->sense_buffer;
2323 arcmsr_write_ioctldata2iop(acb);
2324 /* has error report sensedata */
2325 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
2326 sensebuffer->SenseKey = ILLEGAL_REQUEST;
2327 sensebuffer->AdditionalSenseLength = 0x0A;
2328 sensebuffer->AdditionalSenseCode = 0x20;
2329 sensebuffer->Valid = 1;
2330 retvalue = ARCMSR_MESSAGE_FAIL;
2331 } else {
2332 pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex];
2333 cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex;
2334 if (user_len > cnt2end) {
2335 memcpy(pQbuffer, ptmpuserbuffer, cnt2end);
2336 ptmpuserbuffer += cnt2end;
2337 user_len -= cnt2end;
2338 acb->wqbuf_putIndex = 0;
2339 pQbuffer = acb->wqbuffer;
2340 }
2341 memcpy(pQbuffer, ptmpuserbuffer, user_len);
2342 acb->wqbuf_putIndex += user_len;
2343 acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
2344 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2345 acb->acb_flags &=
2346 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2347 arcmsr_write_ioctldata2iop(acb);
2348 }
2349 }
2350 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2351 kfree(ver_addr);
2352 if (acb->fw_flag == FW_DEADLOCK)
2353 pcmdmessagefld->cmdmessage.ReturnCode =
2354 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2355 else
2356 pcmdmessagefld->cmdmessage.ReturnCode =
2357 ARCMSR_MESSAGE_RETURNCODE_OK;
2358 break;
2359 }
2360 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2361 uint8_t *pQbuffer = acb->rqbuffer;
2362
2363 arcmsr_clear_iop2drv_rqueue_buffer(acb);
2364 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2365 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2366 acb->rqbuf_getIndex = 0;
2367 acb->rqbuf_putIndex = 0;
2368 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2369 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2370 if (acb->fw_flag == FW_DEADLOCK)
2371 pcmdmessagefld->cmdmessage.ReturnCode =
2372 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2373 else
2374 pcmdmessagefld->cmdmessage.ReturnCode =
2375 ARCMSR_MESSAGE_RETURNCODE_OK;
2376 break;
2377 }
2378 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2379 uint8_t *pQbuffer = acb->wqbuffer;
2380 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2381 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2382 ACB_F_MESSAGE_WQBUFFER_READED);
2383 acb->wqbuf_getIndex = 0;
2384 acb->wqbuf_putIndex = 0;
2385 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2386 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2387 if (acb->fw_flag == FW_DEADLOCK)
2388 pcmdmessagefld->cmdmessage.ReturnCode =
2389 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2390 else
2391 pcmdmessagefld->cmdmessage.ReturnCode =
2392 ARCMSR_MESSAGE_RETURNCODE_OK;
2393 break;
2394 }
2395 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2396 uint8_t *pQbuffer;
2397 arcmsr_clear_iop2drv_rqueue_buffer(acb);
2398 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2399 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2400 acb->rqbuf_getIndex = 0;
2401 acb->rqbuf_putIndex = 0;
2402 pQbuffer = acb->rqbuffer;
2403 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2404 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2405 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2406 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2407 ACB_F_MESSAGE_WQBUFFER_READED);
2408 acb->wqbuf_getIndex = 0;
2409 acb->wqbuf_putIndex = 0;
2410 pQbuffer = acb->wqbuffer;
2411 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2412 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2413 if (acb->fw_flag == FW_DEADLOCK)
2414 pcmdmessagefld->cmdmessage.ReturnCode =
2415 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2416 else
2417 pcmdmessagefld->cmdmessage.ReturnCode =
2418 ARCMSR_MESSAGE_RETURNCODE_OK;
2419 break;
2420 }
2421 case ARCMSR_MESSAGE_RETURN_CODE_3F: {
2422 if (acb->fw_flag == FW_DEADLOCK)
2423 pcmdmessagefld->cmdmessage.ReturnCode =
2424 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2425 else
2426 pcmdmessagefld->cmdmessage.ReturnCode =
2427 ARCMSR_MESSAGE_RETURNCODE_3F;
2428 break;
2429 }
2430 case ARCMSR_MESSAGE_SAY_HELLO: {
2431 int8_t *hello_string = "Hello! I am ARCMSR";
2432 if (acb->fw_flag == FW_DEADLOCK)
2433 pcmdmessagefld->cmdmessage.ReturnCode =
2434 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2435 else
2436 pcmdmessagefld->cmdmessage.ReturnCode =
2437 ARCMSR_MESSAGE_RETURNCODE_OK;
2438 memcpy(pcmdmessagefld->messagedatabuffer,
2439 hello_string, (int16_t)strlen(hello_string));
2440 break;
2441 }
2442 case ARCMSR_MESSAGE_SAY_GOODBYE: {
2443 if (acb->fw_flag == FW_DEADLOCK)
2444 pcmdmessagefld->cmdmessage.ReturnCode =
2445 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2446 else
2447 pcmdmessagefld->cmdmessage.ReturnCode =
2448 ARCMSR_MESSAGE_RETURNCODE_OK;
2449 arcmsr_iop_parking(acb);
2450 break;
2451 }
2452 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2453 if (acb->fw_flag == FW_DEADLOCK)
2454 pcmdmessagefld->cmdmessage.ReturnCode =
2455 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2456 else
2457 pcmdmessagefld->cmdmessage.ReturnCode =
2458 ARCMSR_MESSAGE_RETURNCODE_OK;
2459 arcmsr_flush_adapter_cache(acb);
2460 break;
2461 }
2462 default:
2463 retvalue = ARCMSR_MESSAGE_FAIL;
2464 pr_info("%s: unknown controlcode!\n", __func__);
2465 }
2466 message_out:
2467 if (use_sg) {
2468 struct scatterlist *sg = scsi_sglist(cmd);
2469 kunmap_atomic(buffer - sg->offset);
2470 }
2471 return retvalue;
2472 }
2473
2474 static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
2475 {
2476 struct list_head *head = &acb->ccb_free_list;
2477 struct CommandControlBlock *ccb = NULL;
2478 unsigned long flags;
2479 spin_lock_irqsave(&acb->ccblist_lock, flags);
2480 if (!list_empty(head)) {
2481 ccb = list_entry(head->next, struct CommandControlBlock, list);
2482 list_del_init(&ccb->list);
2483 }else{
2484 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
2485 return NULL;
2486 }
2487 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
2488 return ccb;
2489 }
2490
2491 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2492 struct scsi_cmnd *cmd)
2493 {
2494 switch (cmd->cmnd[0]) {
2495 case INQUIRY: {
2496 unsigned char inqdata[36];
2497 char *buffer;
2498 struct scatterlist *sg;
2499
2500 if (cmd->device->lun) {
2501 cmd->result = (DID_TIME_OUT << 16);
2502 cmd->scsi_done(cmd);
2503 return;
2504 }
2505 inqdata[0] = TYPE_PROCESSOR;
2506 /* Periph Qualifier & Periph Dev Type */
2507 inqdata[1] = 0;
2508 /* rem media bit & Dev Type Modifier */
2509 inqdata[2] = 0;
2510 /* ISO, ECMA, & ANSI versions */
2511 inqdata[4] = 31;
2512 /* length of additional data */
2513 strncpy(&inqdata[8], "Areca ", 8);
2514 /* Vendor Identification */
2515 strncpy(&inqdata[16], "RAID controller ", 16);
2516 /* Product Identification */
2517 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
2518
2519 sg = scsi_sglist(cmd);
2520 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
2521
2522 memcpy(buffer, inqdata, sizeof(inqdata));
2523 sg = scsi_sglist(cmd);
2524 kunmap_atomic(buffer - sg->offset);
2525
2526 cmd->scsi_done(cmd);
2527 }
2528 break;
2529 case WRITE_BUFFER:
2530 case READ_BUFFER: {
2531 if (arcmsr_iop_message_xfer(acb, cmd))
2532 cmd->result = (DID_ERROR << 16);
2533 cmd->scsi_done(cmd);
2534 }
2535 break;
2536 default:
2537 cmd->scsi_done(cmd);
2538 }
2539 }
2540
2541 static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
2542 void (* done)(struct scsi_cmnd *))
2543 {
2544 struct Scsi_Host *host = cmd->device->host;
2545 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
2546 struct CommandControlBlock *ccb;
2547 int target = cmd->device->id;
2548 cmd->scsi_done = done;
2549 cmd->host_scribble = NULL;
2550 cmd->result = 0;
2551 if (target == 16) {
2552 /* virtual device for iop message transfer */
2553 arcmsr_handle_virtual_command(acb, cmd);
2554 return 0;
2555 }
2556 ccb = arcmsr_get_freeccb(acb);
2557 if (!ccb)
2558 return SCSI_MLQUEUE_HOST_BUSY;
2559 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
2560 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
2561 cmd->scsi_done(cmd);
2562 return 0;
2563 }
2564 arcmsr_post_ccb(acb, ccb);
2565 return 0;
2566 }
2567
2568 static DEF_SCSI_QCMD(arcmsr_queue_command)
2569
2570 static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb)
2571 {
2572 struct MessageUnit_A __iomem *reg = acb->pmuA;
2573 char *acb_firm_model = acb->firm_model;
2574 char *acb_firm_version = acb->firm_version;
2575 char *acb_device_map = acb->device_map;
2576 char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
2577 char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
2578 char __iomem *iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]);
2579 int count;
2580 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2581 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
2582 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2583 miscellaneous data' timeout \n", acb->host->host_no);
2584 return false;
2585 }
2586 count = 8;
2587 while (count){
2588 *acb_firm_model = readb(iop_firm_model);
2589 acb_firm_model++;
2590 iop_firm_model++;
2591 count--;
2592 }
2593
2594 count = 16;
2595 while (count){
2596 *acb_firm_version = readb(iop_firm_version);
2597 acb_firm_version++;
2598 iop_firm_version++;
2599 count--;
2600 }
2601
2602 count=16;
2603 while(count){
2604 *acb_device_map = readb(iop_device_map);
2605 acb_device_map++;
2606 iop_device_map++;
2607 count--;
2608 }
2609 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
2610 acb->host->host_no,
2611 acb->firm_model,
2612 acb->firm_version);
2613 acb->signature = readl(&reg->message_rwbuffer[0]);
2614 acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
2615 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
2616 acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
2617 acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
2618 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2619 return true;
2620 }
2621 static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb)
2622 {
2623 struct MessageUnit_B *reg = acb->pmuB;
2624 struct pci_dev *pdev = acb->pdev;
2625 void *dma_coherent;
2626 dma_addr_t dma_coherent_handle;
2627 char *acb_firm_model = acb->firm_model;
2628 char *acb_firm_version = acb->firm_version;
2629 char *acb_device_map = acb->device_map;
2630 char __iomem *iop_firm_model;
2631 /*firm_model,15,60-67*/
2632 char __iomem *iop_firm_version;
2633 /*firm_version,17,68-83*/
2634 char __iomem *iop_device_map;
2635 /*firm_version,21,84-99*/
2636 int count;
2637
2638 acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_B), 32);
2639 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->roundup_ccbsize,
2640 &dma_coherent_handle, GFP_KERNEL);
2641 if (!dma_coherent){
2642 printk(KERN_NOTICE
2643 "arcmsr%d: dma_alloc_coherent got error for hbb mu\n",
2644 acb->host->host_no);
2645 return false;
2646 }
2647 acb->dma_coherent_handle2 = dma_coherent_handle;
2648 acb->dma_coherent2 = dma_coherent;
2649 reg = (struct MessageUnit_B *)dma_coherent;
2650 acb->pmuB = reg;
2651 reg->drv2iop_doorbell= (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL);
2652 reg->drv2iop_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL_MASK);
2653 reg->iop2drv_doorbell = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL);
2654 reg->iop2drv_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL_MASK);
2655 reg->message_wbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_WBUFFER);
2656 reg->message_rbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RBUFFER);
2657 reg->message_rwbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RWBUFFER);
2658 iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]); /*firm_model,15,60-67*/
2659 iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]); /*firm_version,17,68-83*/
2660 iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]); /*firm_version,21,84-99*/
2661
2662 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
2663 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
2664 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2665 miscellaneous data' timeout \n", acb->host->host_no);
2666 goto err_free_dma;
2667 }
2668 count = 8;
2669 while (count){
2670 *acb_firm_model = readb(iop_firm_model);
2671 acb_firm_model++;
2672 iop_firm_model++;
2673 count--;
2674 }
2675 count = 16;
2676 while (count){
2677 *acb_firm_version = readb(iop_firm_version);
2678 acb_firm_version++;
2679 iop_firm_version++;
2680 count--;
2681 }
2682
2683 count = 16;
2684 while(count){
2685 *acb_device_map = readb(iop_device_map);
2686 acb_device_map++;
2687 iop_device_map++;
2688 count--;
2689 }
2690
2691 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
2692 acb->host->host_no,
2693 acb->firm_model,
2694 acb->firm_version);
2695
2696 acb->signature = readl(&reg->message_rwbuffer[0]);
2697 /*firm_signature,1,00-03*/
2698 acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
2699 /*firm_request_len,1,04-07*/
2700 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
2701 /*firm_numbers_queue,2,08-11*/
2702 acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
2703 /*firm_sdram_size,3,12-15*/
2704 acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
2705 /*firm_ide_channels,4,16-19*/
2706 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2707 /*firm_ide_channels,4,16-19*/
2708 return true;
2709 err_free_dma:
2710 dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize,
2711 acb->dma_coherent2, acb->dma_coherent_handle2);
2712 return false;
2713 }
2714
2715 static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB)
2716 {
2717 uint32_t intmask_org, Index, firmware_state = 0;
2718 struct MessageUnit_C __iomem *reg = pACB->pmuC;
2719 char *acb_firm_model = pACB->firm_model;
2720 char *acb_firm_version = pACB->firm_version;
2721 char __iomem *iop_firm_model = (char __iomem *)(&reg->msgcode_rwbuffer[15]); /*firm_model,15,60-67*/
2722 char __iomem *iop_firm_version = (char __iomem *)(&reg->msgcode_rwbuffer[17]); /*firm_version,17,68-83*/
2723 int count;
2724 /* disable all outbound interrupt */
2725 intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
2726 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
2727 /* wait firmware ready */
2728 do {
2729 firmware_state = readl(&reg->outbound_msgaddr1);
2730 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
2731 /* post "get config" instruction */
2732 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2733 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2734 /* wait message ready */
2735 for (Index = 0; Index < 2000; Index++) {
2736 if (readl(&reg->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
2737 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);/*clear interrupt*/
2738 break;
2739 }
2740 udelay(10);
2741 } /*max 1 seconds*/
2742 if (Index >= 2000) {
2743 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2744 miscellaneous data' timeout \n", pACB->host->host_no);
2745 return false;
2746 }
2747 count = 8;
2748 while (count) {
2749 *acb_firm_model = readb(iop_firm_model);
2750 acb_firm_model++;
2751 iop_firm_model++;
2752 count--;
2753 }
2754 count = 16;
2755 while (count) {
2756 *acb_firm_version = readb(iop_firm_version);
2757 acb_firm_version++;
2758 iop_firm_version++;
2759 count--;
2760 }
2761 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
2762 pACB->host->host_no,
2763 pACB->firm_model,
2764 pACB->firm_version);
2765 pACB->firm_request_len = readl(&reg->msgcode_rwbuffer[1]); /*firm_request_len,1,04-07*/
2766 pACB->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]); /*firm_numbers_queue,2,08-11*/
2767 pACB->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]); /*firm_sdram_size,3,12-15*/
2768 pACB->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]); /*firm_ide_channels,4,16-19*/
2769 pACB->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2770 /*all interrupt service will be enable at arcmsr_iop_init*/
2771 return true;
2772 }
2773
2774 static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb)
2775 {
2776 char *acb_firm_model = acb->firm_model;
2777 char *acb_firm_version = acb->firm_version;
2778 char *acb_device_map = acb->device_map;
2779 char __iomem *iop_firm_model;
2780 char __iomem *iop_firm_version;
2781 char __iomem *iop_device_map;
2782 u32 count;
2783 struct MessageUnit_D *reg;
2784 void *dma_coherent2;
2785 dma_addr_t dma_coherent_handle2;
2786 struct pci_dev *pdev = acb->pdev;
2787
2788 acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_D), 32);
2789 dma_coherent2 = dma_alloc_coherent(&pdev->dev, acb->roundup_ccbsize,
2790 &dma_coherent_handle2, GFP_KERNEL);
2791 if (!dma_coherent2) {
2792 pr_notice("DMA allocation failed...\n");
2793 return false;
2794 }
2795 memset(dma_coherent2, 0, acb->roundup_ccbsize);
2796 acb->dma_coherent_handle2 = dma_coherent_handle2;
2797 acb->dma_coherent2 = dma_coherent2;
2798 reg = (struct MessageUnit_D *)dma_coherent2;
2799 acb->pmuD = reg;
2800 reg->chip_id = acb->mem_base0 + ARCMSR_ARC1214_CHIP_ID;
2801 reg->cpu_mem_config = acb->mem_base0 +
2802 ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION;
2803 reg->i2o_host_interrupt_mask = acb->mem_base0 +
2804 ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK;
2805 reg->sample_at_reset = acb->mem_base0 + ARCMSR_ARC1214_SAMPLE_RESET;
2806 reg->reset_request = acb->mem_base0 + ARCMSR_ARC1214_RESET_REQUEST;
2807 reg->host_int_status = acb->mem_base0 +
2808 ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS;
2809 reg->pcief0_int_enable = acb->mem_base0 +
2810 ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE;
2811 reg->inbound_msgaddr0 = acb->mem_base0 +
2812 ARCMSR_ARC1214_INBOUND_MESSAGE0;
2813 reg->inbound_msgaddr1 = acb->mem_base0 +
2814 ARCMSR_ARC1214_INBOUND_MESSAGE1;
2815 reg->outbound_msgaddr0 = acb->mem_base0 +
2816 ARCMSR_ARC1214_OUTBOUND_MESSAGE0;
2817 reg->outbound_msgaddr1 = acb->mem_base0 +
2818 ARCMSR_ARC1214_OUTBOUND_MESSAGE1;
2819 reg->inbound_doorbell = acb->mem_base0 +
2820 ARCMSR_ARC1214_INBOUND_DOORBELL;
2821 reg->outbound_doorbell = acb->mem_base0 +
2822 ARCMSR_ARC1214_OUTBOUND_DOORBELL;
2823 reg->outbound_doorbell_enable = acb->mem_base0 +
2824 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE;
2825 reg->inboundlist_base_low = acb->mem_base0 +
2826 ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW;
2827 reg->inboundlist_base_high = acb->mem_base0 +
2828 ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH;
2829 reg->inboundlist_write_pointer = acb->mem_base0 +
2830 ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER;
2831 reg->outboundlist_base_low = acb->mem_base0 +
2832 ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW;
2833 reg->outboundlist_base_high = acb->mem_base0 +
2834 ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH;
2835 reg->outboundlist_copy_pointer = acb->mem_base0 +
2836 ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER;
2837 reg->outboundlist_read_pointer = acb->mem_base0 +
2838 ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER;
2839 reg->outboundlist_interrupt_cause = acb->mem_base0 +
2840 ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE;
2841 reg->outboundlist_interrupt_enable = acb->mem_base0 +
2842 ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE;
2843 reg->message_wbuffer = acb->mem_base0 + ARCMSR_ARC1214_MESSAGE_WBUFFER;
2844 reg->message_rbuffer = acb->mem_base0 + ARCMSR_ARC1214_MESSAGE_RBUFFER;
2845 reg->msgcode_rwbuffer = acb->mem_base0 +
2846 ARCMSR_ARC1214_MESSAGE_RWBUFFER;
2847 iop_firm_model = (char __iomem *)(&reg->msgcode_rwbuffer[15]);
2848 iop_firm_version = (char __iomem *)(&reg->msgcode_rwbuffer[17]);
2849 iop_device_map = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
2850 if (readl(acb->pmuD->outbound_doorbell) &
2851 ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
2852 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
2853 acb->pmuD->outbound_doorbell);/*clear interrupt*/
2854 }
2855 /* post "get config" instruction */
2856 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
2857 /* wait message ready */
2858 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
2859 pr_notice("arcmsr%d: wait get adapter firmware "
2860 "miscellaneous data timeout\n", acb->host->host_no);
2861 dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize,
2862 acb->dma_coherent2, acb->dma_coherent_handle2);
2863 return false;
2864 }
2865 count = 8;
2866 while (count) {
2867 *acb_firm_model = readb(iop_firm_model);
2868 acb_firm_model++;
2869 iop_firm_model++;
2870 count--;
2871 }
2872 count = 16;
2873 while (count) {
2874 *acb_firm_version = readb(iop_firm_version);
2875 acb_firm_version++;
2876 iop_firm_version++;
2877 count--;
2878 }
2879 count = 16;
2880 while (count) {
2881 *acb_device_map = readb(iop_device_map);
2882 acb_device_map++;
2883 iop_device_map++;
2884 count--;
2885 }
2886 acb->signature = readl(&reg->msgcode_rwbuffer[0]);
2887 /*firm_signature,1,00-03*/
2888 acb->firm_request_len = readl(&reg->msgcode_rwbuffer[1]);
2889 /*firm_request_len,1,04-07*/
2890 acb->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]);
2891 /*firm_numbers_queue,2,08-11*/
2892 acb->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]);
2893 /*firm_sdram_size,3,12-15*/
2894 acb->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]);
2895 /*firm_hd_channels,4,16-19*/
2896 acb->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]);
2897 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
2898 acb->host->host_no,
2899 acb->firm_model,
2900 acb->firm_version);
2901 return true;
2902 }
2903
2904 static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
2905 {
2906 bool rtn = false;
2907
2908 switch (acb->adapter_type) {
2909 case ACB_ADAPTER_TYPE_A:
2910 rtn = arcmsr_hbaA_get_config(acb);
2911 break;
2912 case ACB_ADAPTER_TYPE_B:
2913 rtn = arcmsr_hbaB_get_config(acb);
2914 break;
2915 case ACB_ADAPTER_TYPE_C:
2916 rtn = arcmsr_hbaC_get_config(acb);
2917 break;
2918 case ACB_ADAPTER_TYPE_D:
2919 rtn = arcmsr_hbaD_get_config(acb);
2920 break;
2921 default:
2922 break;
2923 }
2924 if (acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
2925 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD;
2926 else
2927 acb->maxOutstanding = acb->firm_numbers_queue - 1;
2928 acb->host->can_queue = acb->maxOutstanding;
2929 return rtn;
2930 }
2931
2932 static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb,
2933 struct CommandControlBlock *poll_ccb)
2934 {
2935 struct MessageUnit_A __iomem *reg = acb->pmuA;
2936 struct CommandControlBlock *ccb;
2937 struct ARCMSR_CDB *arcmsr_cdb;
2938 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
2939 int rtn;
2940 bool error;
2941 polling_hba_ccb_retry:
2942 poll_count++;
2943 outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
2944 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
2945 while (1) {
2946 if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
2947 if (poll_ccb_done){
2948 rtn = SUCCESS;
2949 break;
2950 }else {
2951 msleep(25);
2952 if (poll_count > 100){
2953 rtn = FAILED;
2954 break;
2955 }
2956 goto polling_hba_ccb_retry;
2957 }
2958 }
2959 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
2960 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
2961 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
2962 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
2963 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
2964 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
2965 " poll command abort successfully \n"
2966 , acb->host->host_no
2967 , ccb->pcmd->device->id
2968 , (u32)ccb->pcmd->device->lun
2969 , ccb);
2970 ccb->pcmd->result = DID_ABORT << 16;
2971 arcmsr_ccb_complete(ccb);
2972 continue;
2973 }
2974 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2975 " command done ccb = '0x%p'"
2976 "ccboutstandingcount = %d \n"
2977 , acb->host->host_no
2978 , ccb
2979 , atomic_read(&acb->ccboutstandingcount));
2980 continue;
2981 }
2982 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2983 arcmsr_report_ccb_state(acb, ccb, error);
2984 }
2985 return rtn;
2986 }
2987
2988 static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb,
2989 struct CommandControlBlock *poll_ccb)
2990 {
2991 struct MessageUnit_B *reg = acb->pmuB;
2992 struct ARCMSR_CDB *arcmsr_cdb;
2993 struct CommandControlBlock *ccb;
2994 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
2995 int index, rtn;
2996 bool error;
2997 polling_hbb_ccb_retry:
2998
2999 poll_count++;
3000 /* clear doorbell interrupt */
3001 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
3002 while(1){
3003 index = reg->doneq_index;
3004 flag_ccb = reg->done_qbuffer[index];
3005 if (flag_ccb == 0) {
3006 if (poll_ccb_done){
3007 rtn = SUCCESS;
3008 break;
3009 }else {
3010 msleep(25);
3011 if (poll_count > 100){
3012 rtn = FAILED;
3013 break;
3014 }
3015 goto polling_hbb_ccb_retry;
3016 }
3017 }
3018 reg->done_qbuffer[index] = 0;
3019 index++;
3020 /*if last index number set it to 0 */
3021 index %= ARCMSR_MAX_HBB_POSTQUEUE;
3022 reg->doneq_index = index;
3023 /* check if command done with no error*/
3024 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
3025 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
3026 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
3027 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
3028 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
3029 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3030 " poll command abort successfully \n"
3031 ,acb->host->host_no
3032 ,ccb->pcmd->device->id
3033 ,(u32)ccb->pcmd->device->lun
3034 ,ccb);
3035 ccb->pcmd->result = DID_ABORT << 16;
3036 arcmsr_ccb_complete(ccb);
3037 continue;
3038 }
3039 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3040 " command done ccb = '0x%p'"
3041 "ccboutstandingcount = %d \n"
3042 , acb->host->host_no
3043 , ccb
3044 , atomic_read(&acb->ccboutstandingcount));
3045 continue;
3046 }
3047 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
3048 arcmsr_report_ccb_state(acb, ccb, error);
3049 }
3050 return rtn;
3051 }
3052
3053 static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb,
3054 struct CommandControlBlock *poll_ccb)
3055 {
3056 struct MessageUnit_C __iomem *reg = acb->pmuC;
3057 uint32_t flag_ccb, ccb_cdb_phy;
3058 struct ARCMSR_CDB *arcmsr_cdb;
3059 bool error;
3060 struct CommandControlBlock *pCCB;
3061 uint32_t poll_ccb_done = 0, poll_count = 0;
3062 int rtn;
3063 polling_hbc_ccb_retry:
3064 poll_count++;
3065 while (1) {
3066 if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
3067 if (poll_ccb_done) {
3068 rtn = SUCCESS;
3069 break;
3070 } else {
3071 msleep(25);
3072 if (poll_count > 100) {
3073 rtn = FAILED;
3074 break;
3075 }
3076 goto polling_hbc_ccb_retry;
3077 }
3078 }
3079 flag_ccb = readl(&reg->outbound_queueport_low);
3080 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
3081 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/
3082 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
3083 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3084 /* check ifcommand done with no error*/
3085 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
3086 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3087 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3088 " poll command abort successfully \n"
3089 , acb->host->host_no
3090 , pCCB->pcmd->device->id
3091 , (u32)pCCB->pcmd->device->lun
3092 , pCCB);
3093 pCCB->pcmd->result = DID_ABORT << 16;
3094 arcmsr_ccb_complete(pCCB);
3095 continue;
3096 }
3097 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3098 " command done ccb = '0x%p'"
3099 "ccboutstandingcount = %d \n"
3100 , acb->host->host_no
3101 , pCCB
3102 , atomic_read(&acb->ccboutstandingcount));
3103 continue;
3104 }
3105 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
3106 arcmsr_report_ccb_state(acb, pCCB, error);
3107 }
3108 return rtn;
3109 }
3110
3111 static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb,
3112 struct CommandControlBlock *poll_ccb)
3113 {
3114 bool error;
3115 uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb, ccb_cdb_phy;
3116 int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle;
3117 unsigned long flags;
3118 struct ARCMSR_CDB *arcmsr_cdb;
3119 struct CommandControlBlock *pCCB;
3120 struct MessageUnit_D *pmu = acb->pmuD;
3121
3122 polling_hbaD_ccb_retry:
3123 poll_count++;
3124 while (1) {
3125 spin_lock_irqsave(&acb->doneq_lock, flags);
3126 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
3127 doneq_index = pmu->doneq_index;
3128 if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) {
3129 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3130 if (poll_ccb_done) {
3131 rtn = SUCCESS;
3132 break;
3133 } else {
3134 msleep(25);
3135 if (poll_count > 40) {
3136 rtn = FAILED;
3137 break;
3138 }
3139 goto polling_hbaD_ccb_retry;
3140 }
3141 }
3142 toggle = doneq_index & 0x4000;
3143 index_stripped = (doneq_index & 0xFFF) + 1;
3144 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
3145 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
3146 ((toggle ^ 0x4000) + 1);
3147 doneq_index = pmu->doneq_index;
3148 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3149 flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow;
3150 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
3151 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset +
3152 ccb_cdb_phy);
3153 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock,
3154 arcmsr_cdb);
3155 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3156 if ((pCCB->acb != acb) ||
3157 (pCCB->startdone != ARCMSR_CCB_START)) {
3158 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3159 pr_notice("arcmsr%d: scsi id = %d "
3160 "lun = %d ccb = '0x%p' poll command "
3161 "abort successfully\n"
3162 , acb->host->host_no
3163 , pCCB->pcmd->device->id
3164 , (u32)pCCB->pcmd->device->lun
3165 , pCCB);
3166 pCCB->pcmd->result = DID_ABORT << 16;
3167 arcmsr_ccb_complete(pCCB);
3168 continue;
3169 }
3170 pr_notice("arcmsr%d: polling an illegal "
3171 "ccb command done ccb = '0x%p' "
3172 "ccboutstandingcount = %d\n"
3173 , acb->host->host_no
3174 , pCCB
3175 , atomic_read(&acb->ccboutstandingcount));
3176 continue;
3177 }
3178 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
3179 ? true : false;
3180 arcmsr_report_ccb_state(acb, pCCB, error);
3181 }
3182 return rtn;
3183 }
3184
3185 static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
3186 struct CommandControlBlock *poll_ccb)
3187 {
3188 int rtn = 0;
3189 switch (acb->adapter_type) {
3190
3191 case ACB_ADAPTER_TYPE_A: {
3192 rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb);
3193 }
3194 break;
3195
3196 case ACB_ADAPTER_TYPE_B: {
3197 rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb);
3198 }
3199 break;
3200 case ACB_ADAPTER_TYPE_C: {
3201 rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb);
3202 }
3203 break;
3204 case ACB_ADAPTER_TYPE_D:
3205 rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb);
3206 break;
3207 }
3208 return rtn;
3209 }
3210
3211 static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
3212 {
3213 uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
3214 dma_addr_t dma_coherent_handle;
3215
3216 /*
3217 ********************************************************************
3218 ** here we need to tell iop 331 our freeccb.HighPart
3219 ** if freeccb.HighPart is not zero
3220 ********************************************************************
3221 */
3222 switch (acb->adapter_type) {
3223 case ACB_ADAPTER_TYPE_B:
3224 case ACB_ADAPTER_TYPE_D:
3225 dma_coherent_handle = acb->dma_coherent_handle2;
3226 break;
3227 default:
3228 dma_coherent_handle = acb->dma_coherent_handle;
3229 break;
3230 }
3231 cdb_phyaddr = lower_32_bits(dma_coherent_handle);
3232 cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);
3233 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
3234 /*
3235 ***********************************************************************
3236 ** if adapter type B, set window of "post command Q"
3237 ***********************************************************************
3238 */
3239 switch (acb->adapter_type) {
3240
3241 case ACB_ADAPTER_TYPE_A: {
3242 if (cdb_phyaddr_hi32 != 0) {
3243 struct MessageUnit_A __iomem *reg = acb->pmuA;
3244 writel(ARCMSR_SIGNATURE_SET_CONFIG, \
3245 &reg->message_rwbuffer[0]);
3246 writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
3247 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
3248 &reg->inbound_msgaddr0);
3249 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
3250 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
3251 part physical address timeout\n",
3252 acb->host->host_no);
3253 return 1;
3254 }
3255 }
3256 }
3257 break;
3258
3259 case ACB_ADAPTER_TYPE_B: {
3260 uint32_t __iomem *rwbuffer;
3261
3262 struct MessageUnit_B *reg = acb->pmuB;
3263 reg->postq_index = 0;
3264 reg->doneq_index = 0;
3265 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
3266 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3267 printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \
3268 acb->host->host_no);
3269 return 1;
3270 }
3271 rwbuffer = reg->message_rwbuffer;
3272 /* driver "set config" signature */
3273 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
3274 /* normal should be zero */
3275 writel(cdb_phyaddr_hi32, rwbuffer++);
3276 /* postQ size (256 + 8)*4 */
3277 writel(cdb_phyaddr, rwbuffer++);
3278 /* doneQ size (256 + 8)*4 */
3279 writel(cdb_phyaddr + 1056, rwbuffer++);
3280 /* ccb maxQ size must be --> [(256 + 8)*4]*/
3281 writel(1056, rwbuffer);
3282
3283 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
3284 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3285 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
3286 timeout \n",acb->host->host_no);
3287 return 1;
3288 }
3289 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
3290 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3291 pr_err("arcmsr%d: can't set driver mode.\n",
3292 acb->host->host_no);
3293 return 1;
3294 }
3295 }
3296 break;
3297 case ACB_ADAPTER_TYPE_C: {
3298 if (cdb_phyaddr_hi32 != 0) {
3299 struct MessageUnit_C __iomem *reg = acb->pmuC;
3300
3301 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
3302 acb->adapter_index, cdb_phyaddr_hi32);
3303 writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
3304 writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
3305 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
3306 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
3307 if (!arcmsr_hbaC_wait_msgint_ready(acb)) {
3308 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
3309 timeout \n", acb->host->host_no);
3310 return 1;
3311 }
3312 }
3313 }
3314 break;
3315 case ACB_ADAPTER_TYPE_D: {
3316 uint32_t __iomem *rwbuffer;
3317 struct MessageUnit_D *reg = acb->pmuD;
3318 reg->postq_index = 0;
3319 reg->doneq_index = 0;
3320 rwbuffer = reg->msgcode_rwbuffer;
3321 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
3322 writel(cdb_phyaddr_hi32, rwbuffer++);
3323 writel(cdb_phyaddr, rwbuffer++);
3324 writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
3325 sizeof(struct InBound_SRB)), rwbuffer++);
3326 writel(0x100, rwbuffer);
3327 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
3328 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
3329 pr_notice("arcmsr%d: 'set command Q window' timeout\n",
3330 acb->host->host_no);
3331 return 1;
3332 }
3333 }
3334 break;
3335 }
3336 return 0;
3337 }
3338
3339 static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
3340 {
3341 uint32_t firmware_state = 0;
3342 switch (acb->adapter_type) {
3343
3344 case ACB_ADAPTER_TYPE_A: {
3345 struct MessageUnit_A __iomem *reg = acb->pmuA;
3346 do {
3347 firmware_state = readl(&reg->outbound_msgaddr1);
3348 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
3349 }
3350 break;
3351
3352 case ACB_ADAPTER_TYPE_B: {
3353 struct MessageUnit_B *reg = acb->pmuB;
3354 do {
3355 firmware_state = readl(reg->iop2drv_doorbell);
3356 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
3357 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
3358 }
3359 break;
3360 case ACB_ADAPTER_TYPE_C: {
3361 struct MessageUnit_C __iomem *reg = acb->pmuC;
3362 do {
3363 firmware_state = readl(&reg->outbound_msgaddr1);
3364 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
3365 }
3366 break;
3367 case ACB_ADAPTER_TYPE_D: {
3368 struct MessageUnit_D *reg = acb->pmuD;
3369 do {
3370 firmware_state = readl(reg->outbound_msgaddr1);
3371 } while ((firmware_state &
3372 ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0);
3373 }
3374 break;
3375 }
3376 }
3377
3378 static void arcmsr_hbaA_request_device_map(struct AdapterControlBlock *acb)
3379 {
3380 struct MessageUnit_A __iomem *reg = acb->pmuA;
3381 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
3382 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3383 return;
3384 } else {
3385 acb->fw_flag = FW_NORMAL;
3386 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)){
3387 atomic_set(&acb->rq_map_token, 16);
3388 }
3389 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
3390 if (atomic_dec_and_test(&acb->rq_map_token)) {
3391 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3392 return;
3393 }
3394 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3395 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3396 }
3397 return;
3398 }
3399
3400 static void arcmsr_hbaB_request_device_map(struct AdapterControlBlock *acb)
3401 {
3402 struct MessageUnit_B *reg = acb->pmuB;
3403 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
3404 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3405 return;
3406 } else {
3407 acb->fw_flag = FW_NORMAL;
3408 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
3409 atomic_set(&acb->rq_map_token, 16);
3410 }
3411 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
3412 if (atomic_dec_and_test(&acb->rq_map_token)) {
3413 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3414 return;
3415 }
3416 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
3417 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3418 }
3419 return;
3420 }
3421
3422 static void arcmsr_hbaC_request_device_map(struct AdapterControlBlock *acb)
3423 {
3424 struct MessageUnit_C __iomem *reg = acb->pmuC;
3425 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0) || ((acb->acb_flags & ACB_F_ABORT) != 0)) {
3426 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3427 return;
3428 } else {
3429 acb->fw_flag = FW_NORMAL;
3430 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
3431 atomic_set(&acb->rq_map_token, 16);
3432 }
3433 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
3434 if (atomic_dec_and_test(&acb->rq_map_token)) {
3435 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3436 return;
3437 }
3438 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3439 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
3440 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3441 }
3442 return;
3443 }
3444
3445 static void arcmsr_hbaD_request_device_map(struct AdapterControlBlock *acb)
3446 {
3447 struct MessageUnit_D *reg = acb->pmuD;
3448
3449 if (unlikely(atomic_read(&acb->rq_map_token) == 0) ||
3450 ((acb->acb_flags & ACB_F_BUS_RESET) != 0) ||
3451 ((acb->acb_flags & ACB_F_ABORT) != 0)) {
3452 mod_timer(&acb->eternal_timer,
3453 jiffies + msecs_to_jiffies(6 * HZ));
3454 } else {
3455 acb->fw_flag = FW_NORMAL;
3456 if (atomic_read(&acb->ante_token_value) ==
3457 atomic_read(&acb->rq_map_token)) {
3458 atomic_set(&acb->rq_map_token, 16);
3459 }
3460 atomic_set(&acb->ante_token_value,
3461 atomic_read(&acb->rq_map_token));
3462 if (atomic_dec_and_test(&acb->rq_map_token)) {
3463 mod_timer(&acb->eternal_timer, jiffies +
3464 msecs_to_jiffies(6 * HZ));
3465 return;
3466 }
3467 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG,
3468 reg->inbound_msgaddr0);
3469 mod_timer(&acb->eternal_timer, jiffies +
3470 msecs_to_jiffies(6 * HZ));
3471 }
3472 }
3473
3474 static void arcmsr_request_device_map(unsigned long pacb)
3475 {
3476 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)pacb;
3477 switch (acb->adapter_type) {
3478 case ACB_ADAPTER_TYPE_A: {
3479 arcmsr_hbaA_request_device_map(acb);
3480 }
3481 break;
3482 case ACB_ADAPTER_TYPE_B: {
3483 arcmsr_hbaB_request_device_map(acb);
3484 }
3485 break;
3486 case ACB_ADAPTER_TYPE_C: {
3487 arcmsr_hbaC_request_device_map(acb);
3488 }
3489 break;
3490 case ACB_ADAPTER_TYPE_D:
3491 arcmsr_hbaD_request_device_map(acb);
3492 break;
3493 }
3494 }
3495
3496 static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb)
3497 {
3498 struct MessageUnit_A __iomem *reg = acb->pmuA;
3499 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3500 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
3501 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
3502 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
3503 rebulid' timeout \n", acb->host->host_no);
3504 }
3505 }
3506
3507 static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb)
3508 {
3509 struct MessageUnit_B *reg = acb->pmuB;
3510 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3511 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
3512 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3513 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
3514 rebulid' timeout \n",acb->host->host_no);
3515 }
3516 }
3517
3518 static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB)
3519 {
3520 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
3521 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
3522 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
3523 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
3524 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
3525 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
3526 rebulid' timeout \n", pACB->host->host_no);
3527 }
3528 return;
3529 }
3530
3531 static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB)
3532 {
3533 struct MessageUnit_D *pmu = pACB->pmuD;
3534
3535 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
3536 writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
3537 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
3538 pr_notice("arcmsr%d: wait 'start adapter "
3539 "background rebulid' timeout\n", pACB->host->host_no);
3540 }
3541 }
3542
3543 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3544 {
3545 switch (acb->adapter_type) {
3546 case ACB_ADAPTER_TYPE_A:
3547 arcmsr_hbaA_start_bgrb(acb);
3548 break;
3549 case ACB_ADAPTER_TYPE_B:
3550 arcmsr_hbaB_start_bgrb(acb);
3551 break;
3552 case ACB_ADAPTER_TYPE_C:
3553 arcmsr_hbaC_start_bgrb(acb);
3554 break;
3555 case ACB_ADAPTER_TYPE_D:
3556 arcmsr_hbaD_start_bgrb(acb);
3557 break;
3558 }
3559 }
3560
3561 static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
3562 {
3563 switch (acb->adapter_type) {
3564 case ACB_ADAPTER_TYPE_A: {
3565 struct MessageUnit_A __iomem *reg = acb->pmuA;
3566 uint32_t outbound_doorbell;
3567 /* empty doorbell Qbuffer if door bell ringed */
3568 outbound_doorbell = readl(&reg->outbound_doorbell);
3569 /*clear doorbell interrupt */
3570 writel(outbound_doorbell, &reg->outbound_doorbell);
3571 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
3572 }
3573 break;
3574
3575 case ACB_ADAPTER_TYPE_B: {
3576 struct MessageUnit_B *reg = acb->pmuB;
3577 /*clear interrupt and message state*/
3578 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
3579 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
3580 /* let IOP know data has been read */
3581 }
3582 break;
3583 case ACB_ADAPTER_TYPE_C: {
3584 struct MessageUnit_C __iomem *reg = acb->pmuC;
3585 uint32_t outbound_doorbell, i;
3586 /* empty doorbell Qbuffer if door bell ringed */
3587 outbound_doorbell = readl(&reg->outbound_doorbell);
3588 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
3589 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
3590 for (i = 0; i < 200; i++) {
3591 msleep(20);
3592 outbound_doorbell = readl(&reg->outbound_doorbell);
3593 if (outbound_doorbell &
3594 ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
3595 writel(outbound_doorbell,
3596 &reg->outbound_doorbell_clear);
3597 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
3598 &reg->inbound_doorbell);
3599 } else
3600 break;
3601 }
3602 }
3603 break;
3604 case ACB_ADAPTER_TYPE_D: {
3605 struct MessageUnit_D *reg = acb->pmuD;
3606 uint32_t outbound_doorbell, i;
3607 /* empty doorbell Qbuffer if door bell ringed */
3608 outbound_doorbell = readl(reg->outbound_doorbell);
3609 writel(outbound_doorbell, reg->outbound_doorbell);
3610 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
3611 reg->inbound_doorbell);
3612 for (i = 0; i < 200; i++) {
3613 msleep(20);
3614 outbound_doorbell = readl(reg->outbound_doorbell);
3615 if (outbound_doorbell &
3616 ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) {
3617 writel(outbound_doorbell,
3618 reg->outbound_doorbell);
3619 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
3620 reg->inbound_doorbell);
3621 } else
3622 break;
3623 }
3624 }
3625 break;
3626 }
3627 }
3628
3629 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
3630 {
3631 switch (acb->adapter_type) {
3632 case ACB_ADAPTER_TYPE_A:
3633 return;
3634 case ACB_ADAPTER_TYPE_B:
3635 {
3636 struct MessageUnit_B *reg = acb->pmuB;
3637 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
3638 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3639 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
3640 return;
3641 }
3642 }
3643 break;
3644 case ACB_ADAPTER_TYPE_C:
3645 return;
3646 }
3647 return;
3648 }
3649
3650 static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
3651 {
3652 uint8_t value[64];
3653 int i, count = 0;
3654 struct MessageUnit_A __iomem *pmuA = acb->pmuA;
3655 struct MessageUnit_C __iomem *pmuC = acb->pmuC;
3656 struct MessageUnit_D *pmuD = acb->pmuD;
3657
3658 /* backup pci config data */
3659 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
3660 for (i = 0; i < 64; i++) {
3661 pci_read_config_byte(acb->pdev, i, &value[i]);
3662 }
3663 /* hardware reset signal */
3664 if ((acb->dev_id == 0x1680)) {
3665 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
3666 } else if ((acb->dev_id == 0x1880)) {
3667 do {
3668 count++;
3669 writel(0xF, &pmuC->write_sequence);
3670 writel(0x4, &pmuC->write_sequence);
3671 writel(0xB, &pmuC->write_sequence);
3672 writel(0x2, &pmuC->write_sequence);
3673 writel(0x7, &pmuC->write_sequence);
3674 writel(0xD, &pmuC->write_sequence);
3675 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
3676 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
3677 } else if ((acb->dev_id == 0x1214)) {
3678 writel(0x20, pmuD->reset_request);
3679 } else {
3680 pci_write_config_byte(acb->pdev, 0x84, 0x20);
3681 }
3682 msleep(2000);
3683 /* write back pci config data */
3684 for (i = 0; i < 64; i++) {
3685 pci_write_config_byte(acb->pdev, i, value[i]);
3686 }
3687 msleep(1000);
3688 return;
3689 }
3690 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
3691 {
3692 uint32_t intmask_org;
3693 /* disable all outbound interrupt */
3694 intmask_org = arcmsr_disable_outbound_ints(acb);
3695 arcmsr_wait_firmware_ready(acb);
3696 arcmsr_iop_confirm(acb);
3697 /*start background rebuild*/
3698 arcmsr_start_adapter_bgrb(acb);
3699 /* empty doorbell Qbuffer if door bell ringed */
3700 arcmsr_clear_doorbell_queue_buffer(acb);
3701 arcmsr_enable_eoi_mode(acb);
3702 /* enable outbound Post Queue,outbound doorbell Interrupt */
3703 arcmsr_enable_outbound_ints(acb, intmask_org);
3704 acb->acb_flags |= ACB_F_IOP_INITED;
3705 }
3706
3707 static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
3708 {
3709 struct CommandControlBlock *ccb;
3710 uint32_t intmask_org;
3711 uint8_t rtnval = 0x00;
3712 int i = 0;
3713 unsigned long flags;
3714
3715 if (atomic_read(&acb->ccboutstandingcount) != 0) {
3716 /* disable all outbound interrupt */
3717 intmask_org = arcmsr_disable_outbound_ints(acb);
3718 /* talk to iop 331 outstanding command aborted */
3719 rtnval = arcmsr_abort_allcmd(acb);
3720 /* clear all outbound posted Q */
3721 arcmsr_done4abort_postqueue(acb);
3722 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
3723 ccb = acb->pccb_pool[i];
3724 if (ccb->startdone == ARCMSR_CCB_START) {
3725 scsi_dma_unmap(ccb->pcmd);
3726 ccb->startdone = ARCMSR_CCB_DONE;
3727 ccb->ccb_flags = 0;
3728 spin_lock_irqsave(&acb->ccblist_lock, flags);
3729 list_add_tail(&ccb->list, &acb->ccb_free_list);
3730 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
3731 }
3732 }
3733 atomic_set(&acb->ccboutstandingcount, 0);
3734 /* enable all outbound interrupt */
3735 arcmsr_enable_outbound_ints(acb, intmask_org);
3736 return rtnval;
3737 }
3738 return rtnval;
3739 }
3740
3741 static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
3742 {
3743 struct AdapterControlBlock *acb;
3744 uint32_t intmask_org, outbound_doorbell;
3745 int retry_count = 0;
3746 int rtn = FAILED;
3747 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
3748 printk(KERN_ERR "arcmsr: executing bus reset eh.....num_resets = %d, num_aborts = %d \n", acb->num_resets, acb->num_aborts);
3749 acb->num_resets++;
3750
3751 switch(acb->adapter_type){
3752 case ACB_ADAPTER_TYPE_A:{
3753 if (acb->acb_flags & ACB_F_BUS_RESET){
3754 long timeout;
3755 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
3756 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
3757 if (timeout) {
3758 return SUCCESS;
3759 }
3760 }
3761 acb->acb_flags |= ACB_F_BUS_RESET;
3762 if (!arcmsr_iop_reset(acb)) {
3763 struct MessageUnit_A __iomem *reg;
3764 reg = acb->pmuA;
3765 arcmsr_hardware_reset(acb);
3766 acb->acb_flags &= ~ACB_F_IOP_INITED;
3767 sleep_again:
3768 ssleep(ARCMSR_SLEEPTIME);
3769 if ((readl(&reg->outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) {
3770 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
3771 if (retry_count > ARCMSR_RETRYCOUNT) {
3772 acb->fw_flag = FW_DEADLOCK;
3773 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
3774 return FAILED;
3775 }
3776 retry_count++;
3777 goto sleep_again;
3778 }
3779 acb->acb_flags |= ACB_F_IOP_INITED;
3780 /* disable all outbound interrupt */
3781 intmask_org = arcmsr_disable_outbound_ints(acb);
3782 arcmsr_get_firmware_spec(acb);
3783 arcmsr_start_adapter_bgrb(acb);
3784 /* clear Qbuffer if door bell ringed */
3785 outbound_doorbell = readl(&reg->outbound_doorbell);
3786 writel(outbound_doorbell, &reg->outbound_doorbell); /*clear interrupt */
3787 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
3788 /* enable outbound Post Queue,outbound doorbell Interrupt */
3789 arcmsr_enable_outbound_ints(acb, intmask_org);
3790 atomic_set(&acb->rq_map_token, 16);
3791 atomic_set(&acb->ante_token_value, 16);
3792 acb->fw_flag = FW_NORMAL;
3793 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3794 acb->acb_flags &= ~ACB_F_BUS_RESET;
3795 rtn = SUCCESS;
3796 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
3797 } else {
3798 acb->acb_flags &= ~ACB_F_BUS_RESET;
3799 atomic_set(&acb->rq_map_token, 16);
3800 atomic_set(&acb->ante_token_value, 16);
3801 acb->fw_flag = FW_NORMAL;
3802 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
3803 rtn = SUCCESS;
3804 }
3805 break;
3806 }
3807 case ACB_ADAPTER_TYPE_B:{
3808 acb->acb_flags |= ACB_F_BUS_RESET;
3809 if (!arcmsr_iop_reset(acb)) {
3810 acb->acb_flags &= ~ACB_F_BUS_RESET;
3811 rtn = FAILED;
3812 } else {
3813 acb->acb_flags &= ~ACB_F_BUS_RESET;
3814 atomic_set(&acb->rq_map_token, 16);
3815 atomic_set(&acb->ante_token_value, 16);
3816 acb->fw_flag = FW_NORMAL;
3817 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3818 rtn = SUCCESS;
3819 }
3820 break;
3821 }
3822 case ACB_ADAPTER_TYPE_C:{
3823 if (acb->acb_flags & ACB_F_BUS_RESET) {
3824 long timeout;
3825 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
3826 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
3827 if (timeout) {
3828 return SUCCESS;
3829 }
3830 }
3831 acb->acb_flags |= ACB_F_BUS_RESET;
3832 if (!arcmsr_iop_reset(acb)) {
3833 struct MessageUnit_C __iomem *reg;
3834 reg = acb->pmuC;
3835 arcmsr_hardware_reset(acb);
3836 acb->acb_flags &= ~ACB_F_IOP_INITED;
3837 sleep:
3838 ssleep(ARCMSR_SLEEPTIME);
3839 if ((readl(&reg->host_diagnostic) & 0x04) != 0) {
3840 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
3841 if (retry_count > ARCMSR_RETRYCOUNT) {
3842 acb->fw_flag = FW_DEADLOCK;
3843 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
3844 return FAILED;
3845 }
3846 retry_count++;
3847 goto sleep;
3848 }
3849 acb->acb_flags |= ACB_F_IOP_INITED;
3850 /* disable all outbound interrupt */
3851 intmask_org = arcmsr_disable_outbound_ints(acb);
3852 arcmsr_get_firmware_spec(acb);
3853 arcmsr_start_adapter_bgrb(acb);
3854 /* clear Qbuffer if door bell ringed */
3855 arcmsr_clear_doorbell_queue_buffer(acb);
3856 /* enable outbound Post Queue,outbound doorbell Interrupt */
3857 arcmsr_enable_outbound_ints(acb, intmask_org);
3858 atomic_set(&acb->rq_map_token, 16);
3859 atomic_set(&acb->ante_token_value, 16);
3860 acb->fw_flag = FW_NORMAL;
3861 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3862 acb->acb_flags &= ~ACB_F_BUS_RESET;
3863 rtn = SUCCESS;
3864 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
3865 } else {
3866 acb->acb_flags &= ~ACB_F_BUS_RESET;
3867 atomic_set(&acb->rq_map_token, 16);
3868 atomic_set(&acb->ante_token_value, 16);
3869 acb->fw_flag = FW_NORMAL;
3870 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
3871 rtn = SUCCESS;
3872 }
3873 break;
3874 }
3875 case ACB_ADAPTER_TYPE_D: {
3876 if (acb->acb_flags & ACB_F_BUS_RESET) {
3877 long timeout;
3878 pr_notice("arcmsr: there is an bus reset"
3879 " eh proceeding.......\n");
3880 timeout = wait_event_timeout(wait_q, (acb->acb_flags
3881 & ACB_F_BUS_RESET) == 0, 220 * HZ);
3882 if (timeout)
3883 return SUCCESS;
3884 }
3885 acb->acb_flags |= ACB_F_BUS_RESET;
3886 if (!arcmsr_iop_reset(acb)) {
3887 struct MessageUnit_D *reg;
3888 reg = acb->pmuD;
3889 arcmsr_hardware_reset(acb);
3890 acb->acb_flags &= ~ACB_F_IOP_INITED;
3891 nap:
3892 ssleep(ARCMSR_SLEEPTIME);
3893 if ((readl(reg->sample_at_reset) & 0x80) != 0) {
3894 pr_err("arcmsr%d: waiting for "
3895 "hw bus reset return, retry=%d\n",
3896 acb->host->host_no, retry_count);
3897 if (retry_count > ARCMSR_RETRYCOUNT) {
3898 acb->fw_flag = FW_DEADLOCK;
3899 pr_err("arcmsr%d: waiting for hw bus"
3900 " reset return, "
3901 "RETRY TERMINATED!!\n",
3902 acb->host->host_no);
3903 return FAILED;
3904 }
3905 retry_count++;
3906 goto nap;
3907 }
3908 acb->acb_flags |= ACB_F_IOP_INITED;
3909 /* disable all outbound interrupt */
3910 intmask_org = arcmsr_disable_outbound_ints(acb);
3911 arcmsr_get_firmware_spec(acb);
3912 arcmsr_start_adapter_bgrb(acb);
3913 arcmsr_clear_doorbell_queue_buffer(acb);
3914 arcmsr_enable_outbound_ints(acb, intmask_org);
3915 atomic_set(&acb->rq_map_token, 16);
3916 atomic_set(&acb->ante_token_value, 16);
3917 acb->fw_flag = FW_NORMAL;
3918 mod_timer(&acb->eternal_timer,
3919 jiffies + msecs_to_jiffies(6 * HZ));
3920 acb->acb_flags &= ~ACB_F_BUS_RESET;
3921 rtn = SUCCESS;
3922 pr_err("arcmsr: scsi bus reset "
3923 "eh returns with success\n");
3924 } else {
3925 acb->acb_flags &= ~ACB_F_BUS_RESET;
3926 atomic_set(&acb->rq_map_token, 16);
3927 atomic_set(&acb->ante_token_value, 16);
3928 acb->fw_flag = FW_NORMAL;
3929 mod_timer(&acb->eternal_timer,
3930 jiffies + msecs_to_jiffies(6 * HZ));
3931 rtn = SUCCESS;
3932 }
3933 break;
3934 }
3935 }
3936 return rtn;
3937 }
3938
3939 static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
3940 struct CommandControlBlock *ccb)
3941 {
3942 int rtn;
3943 rtn = arcmsr_polling_ccbdone(acb, ccb);
3944 return rtn;
3945 }
3946
3947 static int arcmsr_abort(struct scsi_cmnd *cmd)
3948 {
3949 struct AdapterControlBlock *acb =
3950 (struct AdapterControlBlock *)cmd->device->host->hostdata;
3951 int i = 0;
3952 int rtn = FAILED;
3953 uint32_t intmask_org;
3954
3955 printk(KERN_NOTICE
3956 "arcmsr%d: abort device command of scsi id = %d lun = %d\n",
3957 acb->host->host_no, cmd->device->id, (u32)cmd->device->lun);
3958 acb->acb_flags |= ACB_F_ABORT;
3959 acb->num_aborts++;
3960 /*
3961 ************************************************
3962 ** the all interrupt service routine is locked
3963 ** we need to handle it as soon as possible and exit
3964 ************************************************
3965 */
3966 if (!atomic_read(&acb->ccboutstandingcount)) {
3967 acb->acb_flags &= ~ACB_F_ABORT;
3968 return rtn;
3969 }
3970
3971 intmask_org = arcmsr_disable_outbound_ints(acb);
3972 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
3973 struct CommandControlBlock *ccb = acb->pccb_pool[i];
3974 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
3975 ccb->startdone = ARCMSR_CCB_ABORTED;
3976 rtn = arcmsr_abort_one_cmd(acb, ccb);
3977 break;
3978 }
3979 }
3980 acb->acb_flags &= ~ACB_F_ABORT;
3981 arcmsr_enable_outbound_ints(acb, intmask_org);
3982 return rtn;
3983 }
3984
3985 static const char *arcmsr_info(struct Scsi_Host *host)
3986 {
3987 struct AdapterControlBlock *acb =
3988 (struct AdapterControlBlock *) host->hostdata;
3989 static char buf[256];
3990 char *type;
3991 int raid6 = 1;
3992 switch (acb->pdev->device) {
3993 case PCI_DEVICE_ID_ARECA_1110:
3994 case PCI_DEVICE_ID_ARECA_1200:
3995 case PCI_DEVICE_ID_ARECA_1202:
3996 case PCI_DEVICE_ID_ARECA_1210:
3997 raid6 = 0;
3998 /*FALLTHRU*/
3999 case PCI_DEVICE_ID_ARECA_1120:
4000 case PCI_DEVICE_ID_ARECA_1130:
4001 case PCI_DEVICE_ID_ARECA_1160:
4002 case PCI_DEVICE_ID_ARECA_1170:
4003 case PCI_DEVICE_ID_ARECA_1201:
4004 case PCI_DEVICE_ID_ARECA_1220:
4005 case PCI_DEVICE_ID_ARECA_1230:
4006 case PCI_DEVICE_ID_ARECA_1260:
4007 case PCI_DEVICE_ID_ARECA_1270:
4008 case PCI_DEVICE_ID_ARECA_1280:
4009 type = "SATA";
4010 break;
4011 case PCI_DEVICE_ID_ARECA_1214:
4012 case PCI_DEVICE_ID_ARECA_1380:
4013 case PCI_DEVICE_ID_ARECA_1381:
4014 case PCI_DEVICE_ID_ARECA_1680:
4015 case PCI_DEVICE_ID_ARECA_1681:
4016 case PCI_DEVICE_ID_ARECA_1880:
4017 type = "SAS/SATA";
4018 break;
4019 default:
4020 type = "unknown";
4021 raid6 = 0;
4022 break;
4023 }
4024 sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n",
4025 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
4026 return buf;
4027 }
Linux with added FPC-III support