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HID: hiddev: Fix slab-out-of-bounds write in hiddev_ioctl_usage()
[linux/fpc-iii.git] / drivers / scsi / lpfc / lpfc_hw.h
bloba8ad97300177e37b7b259a7742ac277202a11936
1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2015 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21 #define FDMI_DID 0xfffffaU
22 #define NameServer_DID 0xfffffcU
23 #define SCR_DID 0xfffffdU
24 #define Fabric_DID 0xfffffeU
25 #define Bcast_DID 0xffffffU
26 #define Mask_DID 0xffffffU
27 #define CT_DID_MASK 0xffff00U
28 #define Fabric_DID_MASK 0xfff000U
29 #define WELL_KNOWN_DID_MASK 0xfffff0U
30
31 #define PT2PT_LocalID 1
32 #define PT2PT_RemoteID 2
33
34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42 #define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47 #define LPFC_FCP_NEXT_RING 3
48 #define LPFC_FCP_OAS_RING 3
49
50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
58 #define SLI2_IOCB_CMD_R3_ENTRIES 0
59 #define SLI2_IOCB_RSP_R3_ENTRIES 0
60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
63 #define SLI2_IOCB_CMD_SIZE 32
64 #define SLI2_IOCB_RSP_SIZE 32
65 #define SLI3_IOCB_CMD_SIZE 128
66 #define SLI3_IOCB_RSP_SIZE 64
67
68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
70
71 /* vendor ID used in SCSI netlink calls */
72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
74 #define FW_REV_STR_SIZE 32
75 /* Common Transport structures and definitions */
76
77 union CtRevisionId {
78 /* Structure is in Big Endian format */
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84 };
85
86 union CtCommandResponse {
87 /* Structure is in Big Endian format */
88 struct {
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
91 } bits;
92 uint32_t word;
93 };
94
95 #define FC4_FEATURE_INIT 0x2
96 #define FC4_FEATURE_TARGET 0x1
97
98 struct lpfc_sli_ct_request {
99 /* Structure is in Big Endian format */
100 union CtRevisionId RevisionId;
101 uint8_t FsType;
102 uint8_t FsSubType;
103 uint8_t Options;
104 uint8_t Rsrvd1;
105 union CtCommandResponse CommandResponse;
106 uint8_t Rsrvd2;
107 uint8_t ReasonCode;
108 uint8_t Explanation;
109 uint8_t VendorUnique;
110 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
111
112 union {
113 uint32_t PortID;
114 struct gid {
115 uint8_t PortType; /* for GID_PT requests */
116 uint8_t DomainScope;
117 uint8_t AreaScope;
118 uint8_t Fc4Type; /* for GID_FT requests */
119 } gid;
120 struct rft {
121 uint32_t PortId; /* For RFT_ID requests */
122
123 #ifdef __BIG_ENDIAN_BITFIELD
124 uint32_t rsvd0:16;
125 uint32_t rsvd1:7;
126 uint32_t fcpReg:1; /* Type 8 */
127 uint32_t rsvd2:2;
128 uint32_t ipReg:1; /* Type 5 */
129 uint32_t rsvd3:5;
130 #else /* __LITTLE_ENDIAN_BITFIELD */
131 uint32_t rsvd0:16;
132 uint32_t fcpReg:1; /* Type 8 */
133 uint32_t rsvd1:7;
134 uint32_t rsvd3:5;
135 uint32_t ipReg:1; /* Type 5 */
136 uint32_t rsvd2:2;
137 #endif
138
139 uint32_t rsvd[7];
140 } rft;
141 struct rnn {
142 uint32_t PortId; /* For RNN_ID requests */
143 uint8_t wwnn[8];
144 } rnn;
145 struct rsnn { /* For RSNN_ID requests */
146 uint8_t wwnn[8];
147 uint8_t len;
148 uint8_t symbname[255];
149 } rsnn;
150 struct da_id { /* For DA_ID requests */
151 uint32_t port_id;
152 } da_id;
153 struct rspn { /* For RSPN_ID requests */
154 uint32_t PortId;
155 uint8_t len;
156 uint8_t symbname[255];
157 } rspn;
158 struct gff {
159 uint32_t PortId;
160 } gff;
161 struct gff_acc {
162 uint8_t fbits[128];
163 } gff_acc;
164 #define FCP_TYPE_FEATURE_OFFSET 7
165 struct rff {
166 uint32_t PortId;
167 uint8_t reserved[2];
168 uint8_t fbits;
169 uint8_t type_code; /* type=8 for FCP */
170 } rff;
171 } un;
172 };
173
174 #define LPFC_MAX_CT_SIZE (60 * 4096)
175
176 #define SLI_CT_REVISION 1
177 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
178 sizeof(struct gid))
179 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
180 sizeof(struct gff))
181 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
182 sizeof(struct rft))
183 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
184 sizeof(struct rff))
185 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
186 sizeof(struct rnn))
187 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
188 sizeof(struct rsnn))
189 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
190 sizeof(struct da_id))
191 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
192 sizeof(struct rspn))
193
194 /*
195 * FsType Definitions
196 */
197
198 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
199 #define SLI_CT_TIME_SERVICE 0xFB
200 #define SLI_CT_DIRECTORY_SERVICE 0xFC
201 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
202
203 /*
204 * Directory Service Subtypes
205 */
206
207 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
208
209 /*
210 * Response Codes
211 */
212
213 #define SLI_CT_RESPONSE_FS_RJT 0x8001
214 #define SLI_CT_RESPONSE_FS_ACC 0x8002
215
216 /*
217 * Reason Codes
218 */
219
220 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
221 #define SLI_CT_INVALID_COMMAND 0x01
222 #define SLI_CT_INVALID_VERSION 0x02
223 #define SLI_CT_LOGICAL_ERROR 0x03
224 #define SLI_CT_INVALID_IU_SIZE 0x04
225 #define SLI_CT_LOGICAL_BUSY 0x05
226 #define SLI_CT_PROTOCOL_ERROR 0x07
227 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
228 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
229 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
230 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
231 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
232 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
233 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
234 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
235 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
236 #define SLI_CT_VENDOR_UNIQUE 0xff
237
238 /*
239 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
240 */
241
242 #define SLI_CT_NO_PORT_ID 0x01
243 #define SLI_CT_NO_PORT_NAME 0x02
244 #define SLI_CT_NO_NODE_NAME 0x03
245 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
246 #define SLI_CT_NO_IP_ADDRESS 0x05
247 #define SLI_CT_NO_IPA 0x06
248 #define SLI_CT_NO_FC4_TYPES 0x07
249 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
250 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
251 #define SLI_CT_NO_PORT_TYPE 0x0A
252 #define SLI_CT_ACCESS_DENIED 0x10
253 #define SLI_CT_INVALID_PORT_ID 0x11
254 #define SLI_CT_DATABASE_EMPTY 0x12
255
256 /*
257 * Name Server Command Codes
258 */
259
260 #define SLI_CTNS_GA_NXT 0x0100
261 #define SLI_CTNS_GPN_ID 0x0112
262 #define SLI_CTNS_GNN_ID 0x0113
263 #define SLI_CTNS_GCS_ID 0x0114
264 #define SLI_CTNS_GFT_ID 0x0117
265 #define SLI_CTNS_GSPN_ID 0x0118
266 #define SLI_CTNS_GPT_ID 0x011A
267 #define SLI_CTNS_GFF_ID 0x011F
268 #define SLI_CTNS_GID_PN 0x0121
269 #define SLI_CTNS_GID_NN 0x0131
270 #define SLI_CTNS_GIP_NN 0x0135
271 #define SLI_CTNS_GIPA_NN 0x0136
272 #define SLI_CTNS_GSNN_NN 0x0139
273 #define SLI_CTNS_GNN_IP 0x0153
274 #define SLI_CTNS_GIPA_IP 0x0156
275 #define SLI_CTNS_GID_FT 0x0171
276 #define SLI_CTNS_GID_PT 0x01A1
277 #define SLI_CTNS_RPN_ID 0x0212
278 #define SLI_CTNS_RNN_ID 0x0213
279 #define SLI_CTNS_RCS_ID 0x0214
280 #define SLI_CTNS_RFT_ID 0x0217
281 #define SLI_CTNS_RSPN_ID 0x0218
282 #define SLI_CTNS_RPT_ID 0x021A
283 #define SLI_CTNS_RFF_ID 0x021F
284 #define SLI_CTNS_RIP_NN 0x0235
285 #define SLI_CTNS_RIPA_NN 0x0236
286 #define SLI_CTNS_RSNN_NN 0x0239
287 #define SLI_CTNS_DA_ID 0x0300
288
289 /*
290 * Port Types
291 */
292
293 #define SLI_CTPT_N_PORT 0x01
294 #define SLI_CTPT_NL_PORT 0x02
295 #define SLI_CTPT_FNL_PORT 0x03
296 #define SLI_CTPT_IP 0x04
297 #define SLI_CTPT_FCP 0x08
298 #define SLI_CTPT_NX_PORT 0x7F
299 #define SLI_CTPT_F_PORT 0x81
300 #define SLI_CTPT_FL_PORT 0x82
301 #define SLI_CTPT_E_PORT 0x84
302
303 #define SLI_CT_LAST_ENTRY 0x80000000
304
305 /* Fibre Channel Service Parameter definitions */
306
307 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
308 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
309 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
310 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
311
312 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
313 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
314 #define FC_PH3 0x20 /* FC-PH-3 version */
315
316 #define FF_FRAME_SIZE 2048
317
318 struct lpfc_name {
319 union {
320 struct {
321 #ifdef __BIG_ENDIAN_BITFIELD
322 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
323 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
324 8:11 of IEEE ext */
325 #else /* __LITTLE_ENDIAN_BITFIELD */
326 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
327 8:11 of IEEE ext */
328 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
329 #endif
330
331 #define NAME_IEEE 0x1 /* IEEE name - nameType */
332 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
333 #define NAME_FC_TYPE 0x3 /* FC native name type */
334 #define NAME_IP_TYPE 0x4 /* IP address */
335 #define NAME_CCITT_TYPE 0xC
336 #define NAME_CCITT_GR_TYPE 0xE
337 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
338 extended Lsb */
339 uint8_t IEEE[6]; /* FC IEEE address */
340 } s;
341 uint8_t wwn[8];
342 } u;
343 };
344
345 struct csp {
346 uint8_t fcphHigh; /* FC Word 0, byte 0 */
347 uint8_t fcphLow;
348 uint8_t bbCreditMsb;
349 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
350
351 /*
352 * Word 1 Bit 31 in common service parameter is overloaded.
353 * Word 1 Bit 31 in FLOGI request is multiple NPort request
354 * Word 1 Bit 31 in FLOGI response is clean address bit
355 */
356 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
357 /*
358 * Word 1 Bit 30 in common service parameter is overloaded.
359 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
360 * Word 1 Bit 30 in PLOGI request is random offset
361 */
362 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
363 /*
364 * Word 1 Bit 29 in common service parameter is overloaded.
365 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
366 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
367 */
368 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
369 #ifdef __BIG_ENDIAN_BITFIELD
370 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
371 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
372 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
373 uint16_t fPort:1; /* FC Word 1, bit 28 */
374 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
375 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
376 uint16_t multicast:1; /* FC Word 1, bit 25 */
377 uint16_t broadcast:1; /* FC Word 1, bit 24 */
378
379 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
380 uint16_t simplex:1; /* FC Word 1, bit 22 */
381 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
382 uint16_t dhd:1; /* FC Word 1, bit 18 */
383 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
384 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
385 #else /* __LITTLE_ENDIAN_BITFIELD */
386 uint16_t broadcast:1; /* FC Word 1, bit 24 */
387 uint16_t multicast:1; /* FC Word 1, bit 25 */
388 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
389 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
390 uint16_t fPort:1; /* FC Word 1, bit 28 */
391 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
392 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
393 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
394
395 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
396 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
397 uint16_t dhd:1; /* FC Word 1, bit 18 */
398 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
399 uint16_t simplex:1; /* FC Word 1, bit 22 */
400 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
401 #endif
402
403 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
404 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
405 union {
406 struct {
407 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
408
409 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
410 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
411
412 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
413 } nPort;
414 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
415 } w2;
416
417 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
418 };
419
420 struct class_parms {
421 #ifdef __BIG_ENDIAN_BITFIELD
422 uint8_t classValid:1; /* FC Word 0, bit 31 */
423 uint8_t intermix:1; /* FC Word 0, bit 30 */
424 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
425 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
426 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
427 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
428 #else /* __LITTLE_ENDIAN_BITFIELD */
429 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
430 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
431 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
432 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
433 uint8_t intermix:1; /* FC Word 0, bit 30 */
434 uint8_t classValid:1; /* FC Word 0, bit 31 */
435
436 #endif
437
438 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
439
440 #ifdef __BIG_ENDIAN_BITFIELD
441 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
442 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
443 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
444 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
445 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
446 #else /* __LITTLE_ENDIAN_BITFIELD */
447 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
448 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
449 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
450 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
451 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
452 #endif
453
454 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
455
456 #ifdef __BIG_ENDIAN_BITFIELD
457 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
458 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
459 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
460 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
461 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
462 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
463 #else /* __LITTLE_ENDIAN_BITFIELD */
464 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
465 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
466 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
467 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
468 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
469 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
470 #endif
471
472 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
473 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
474 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
475
476 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
477 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
478 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
479 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
480
481 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
482 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
483 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
484 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
485 };
486
487 struct serv_parm { /* Structure is in Big Endian format */
488 struct csp cmn;
489 struct lpfc_name portName;
490 struct lpfc_name nodeName;
491 struct class_parms cls1;
492 struct class_parms cls2;
493 struct class_parms cls3;
494 struct class_parms cls4;
495 uint8_t vendorVersion[16];
496 };
497
498 /*
499 * Virtual Fabric Tagging Header
500 */
501 struct fc_vft_header {
502 uint32_t word0;
503 #define fc_vft_hdr_r_ctl_SHIFT 24
504 #define fc_vft_hdr_r_ctl_MASK 0xFF
505 #define fc_vft_hdr_r_ctl_WORD word0
506 #define fc_vft_hdr_ver_SHIFT 22
507 #define fc_vft_hdr_ver_MASK 0x3
508 #define fc_vft_hdr_ver_WORD word0
509 #define fc_vft_hdr_type_SHIFT 18
510 #define fc_vft_hdr_type_MASK 0xF
511 #define fc_vft_hdr_type_WORD word0
512 #define fc_vft_hdr_e_SHIFT 16
513 #define fc_vft_hdr_e_MASK 0x1
514 #define fc_vft_hdr_e_WORD word0
515 #define fc_vft_hdr_priority_SHIFT 13
516 #define fc_vft_hdr_priority_MASK 0x7
517 #define fc_vft_hdr_priority_WORD word0
518 #define fc_vft_hdr_vf_id_SHIFT 1
519 #define fc_vft_hdr_vf_id_MASK 0xFFF
520 #define fc_vft_hdr_vf_id_WORD word0
521 uint32_t word1;
522 #define fc_vft_hdr_hopct_SHIFT 24
523 #define fc_vft_hdr_hopct_MASK 0xFF
524 #define fc_vft_hdr_hopct_WORD word1
525 };
526
527 /*
528 * Extended Link Service LS_COMMAND codes (Payload Word 0)
529 */
530 #ifdef __BIG_ENDIAN_BITFIELD
531 #define ELS_CMD_MASK 0xffff0000
532 #define ELS_RSP_MASK 0xff000000
533 #define ELS_CMD_LS_RJT 0x01000000
534 #define ELS_CMD_ACC 0x02000000
535 #define ELS_CMD_PLOGI 0x03000000
536 #define ELS_CMD_FLOGI 0x04000000
537 #define ELS_CMD_LOGO 0x05000000
538 #define ELS_CMD_ABTX 0x06000000
539 #define ELS_CMD_RCS 0x07000000
540 #define ELS_CMD_RES 0x08000000
541 #define ELS_CMD_RSS 0x09000000
542 #define ELS_CMD_RSI 0x0A000000
543 #define ELS_CMD_ESTS 0x0B000000
544 #define ELS_CMD_ESTC 0x0C000000
545 #define ELS_CMD_ADVC 0x0D000000
546 #define ELS_CMD_RTV 0x0E000000
547 #define ELS_CMD_RLS 0x0F000000
548 #define ELS_CMD_ECHO 0x10000000
549 #define ELS_CMD_TEST 0x11000000
550 #define ELS_CMD_RRQ 0x12000000
551 #define ELS_CMD_REC 0x13000000
552 #define ELS_CMD_RDP 0x18000000
553 #define ELS_CMD_PRLI 0x20100014
554 #define ELS_CMD_PRLO 0x21100014
555 #define ELS_CMD_PRLO_ACC 0x02100014
556 #define ELS_CMD_PDISC 0x50000000
557 #define ELS_CMD_FDISC 0x51000000
558 #define ELS_CMD_ADISC 0x52000000
559 #define ELS_CMD_FARP 0x54000000
560 #define ELS_CMD_FARPR 0x55000000
561 #define ELS_CMD_RPS 0x56000000
562 #define ELS_CMD_RPL 0x57000000
563 #define ELS_CMD_FAN 0x60000000
564 #define ELS_CMD_RSCN 0x61040000
565 #define ELS_CMD_SCR 0x62000000
566 #define ELS_CMD_RNID 0x78000000
567 #define ELS_CMD_LIRR 0x7A000000
568 #define ELS_CMD_LCB 0x81000000
569 #else /* __LITTLE_ENDIAN_BITFIELD */
570 #define ELS_CMD_MASK 0xffff
571 #define ELS_RSP_MASK 0xff
572 #define ELS_CMD_LS_RJT 0x01
573 #define ELS_CMD_ACC 0x02
574 #define ELS_CMD_PLOGI 0x03
575 #define ELS_CMD_FLOGI 0x04
576 #define ELS_CMD_LOGO 0x05
577 #define ELS_CMD_ABTX 0x06
578 #define ELS_CMD_RCS 0x07
579 #define ELS_CMD_RES 0x08
580 #define ELS_CMD_RSS 0x09
581 #define ELS_CMD_RSI 0x0A
582 #define ELS_CMD_ESTS 0x0B
583 #define ELS_CMD_ESTC 0x0C
584 #define ELS_CMD_ADVC 0x0D
585 #define ELS_CMD_RTV 0x0E
586 #define ELS_CMD_RLS 0x0F
587 #define ELS_CMD_ECHO 0x10
588 #define ELS_CMD_TEST 0x11
589 #define ELS_CMD_RRQ 0x12
590 #define ELS_CMD_REC 0x13
591 #define ELS_CMD_RDP 0x18
592 #define ELS_CMD_PRLI 0x14001020
593 #define ELS_CMD_PRLO 0x14001021
594 #define ELS_CMD_PRLO_ACC 0x14001002
595 #define ELS_CMD_PDISC 0x50
596 #define ELS_CMD_FDISC 0x51
597 #define ELS_CMD_ADISC 0x52
598 #define ELS_CMD_FARP 0x54
599 #define ELS_CMD_FARPR 0x55
600 #define ELS_CMD_RPS 0x56
601 #define ELS_CMD_RPL 0x57
602 #define ELS_CMD_FAN 0x60
603 #define ELS_CMD_RSCN 0x0461
604 #define ELS_CMD_SCR 0x62
605 #define ELS_CMD_RNID 0x78
606 #define ELS_CMD_LIRR 0x7A
607 #define ELS_CMD_LCB 0x81
608 #endif
609
610 /*
611 * LS_RJT Payload Definition
612 */
613
614 struct ls_rjt { /* Structure is in Big Endian format */
615 union {
616 uint32_t lsRjtError;
617 struct {
618 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
619
620 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
621 /* LS_RJT reason codes */
622 #define LSRJT_INVALID_CMD 0x01
623 #define LSRJT_LOGICAL_ERR 0x03
624 #define LSRJT_LOGICAL_BSY 0x05
625 #define LSRJT_PROTOCOL_ERR 0x07
626 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
627 #define LSRJT_CMD_UNSUPPORTED 0x0B
628 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
629
630 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
631 /* LS_RJT reason explanation */
632 #define LSEXP_NOTHING_MORE 0x00
633 #define LSEXP_SPARM_OPTIONS 0x01
634 #define LSEXP_SPARM_ICTL 0x03
635 #define LSEXP_SPARM_RCTL 0x05
636 #define LSEXP_SPARM_RCV_SIZE 0x07
637 #define LSEXP_SPARM_CONCUR_SEQ 0x09
638 #define LSEXP_SPARM_CREDIT 0x0B
639 #define LSEXP_INVALID_PNAME 0x0D
640 #define LSEXP_INVALID_NNAME 0x0E
641 #define LSEXP_INVALID_CSP 0x0F
642 #define LSEXP_INVALID_ASSOC_HDR 0x11
643 #define LSEXP_ASSOC_HDR_REQ 0x13
644 #define LSEXP_INVALID_O_SID 0x15
645 #define LSEXP_INVALID_OX_RX 0x17
646 #define LSEXP_CMD_IN_PROGRESS 0x19
647 #define LSEXP_PORT_LOGIN_REQ 0x1E
648 #define LSEXP_INVALID_NPORT_ID 0x1F
649 #define LSEXP_INVALID_SEQ_ID 0x21
650 #define LSEXP_INVALID_XCHG 0x23
651 #define LSEXP_INACTIVE_XCHG 0x25
652 #define LSEXP_RQ_REQUIRED 0x27
653 #define LSEXP_OUT_OF_RESOURCE 0x29
654 #define LSEXP_CANT_GIVE_DATA 0x2A
655 #define LSEXP_REQ_UNSUPPORTED 0x2C
656 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
657 } b;
658 } un;
659 };
660
661 /*
662 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
663 */
664
665 typedef struct _LOGO { /* Structure is in Big Endian format */
666 union {
667 uint32_t nPortId32; /* Access nPortId as a word */
668 struct {
669 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
670 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
671 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
672 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
673 } b;
674 } un;
675 struct lpfc_name portName; /* N_port name field */
676 } LOGO;
677
678 /*
679 * FCP Login (PRLI Request / ACC) Payload Definition
680 */
681
682 #define PRLX_PAGE_LEN 0x10
683 #define TPRLO_PAGE_LEN 0x14
684
685 typedef struct _PRLI { /* Structure is in Big Endian format */
686 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
687
688 #define PRLI_FCP_TYPE 0x08
689 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
690
691 #ifdef __BIG_ENDIAN_BITFIELD
692 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
693 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
694 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
695
696 /* ACC = imagePairEstablished */
697 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
698 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
699 #else /* __LITTLE_ENDIAN_BITFIELD */
700 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
701 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
702 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
703 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
704 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
705 /* ACC = imagePairEstablished */
706 #endif
707
708 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
709 #define PRLI_NO_RESOURCES 0x2
710 #define PRLI_INIT_INCOMPLETE 0x3
711 #define PRLI_NO_SUCH_PA 0x4
712 #define PRLI_PREDEF_CONFIG 0x5
713 #define PRLI_PARTIAL_SUCCESS 0x6
714 #define PRLI_INVALID_PAGE_CNT 0x7
715 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
716
717 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
718
719 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
720
721 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
722 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
723
724 #ifdef __BIG_ENDIAN_BITFIELD
725 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
726 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
727 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
728 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
729 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
730 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
731 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
732 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
733 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
734 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
735 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
736 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
737 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
738 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
739 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
740 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
741 #else /* __LITTLE_ENDIAN_BITFIELD */
742 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
743 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
744 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
745 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
746 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
747 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
748 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
749 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
750 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
751 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
752 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
753 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
754 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
755 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
756 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
757 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
758 #endif
759 } PRLI;
760
761 /*
762 * FCP Logout (PRLO Request / ACC) Payload Definition
763 */
764
765 typedef struct _PRLO { /* Structure is in Big Endian format */
766 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
767
768 #define PRLO_FCP_TYPE 0x08
769 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
770
771 #ifdef __BIG_ENDIAN_BITFIELD
772 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
773 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
774 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
775 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
776 #else /* __LITTLE_ENDIAN_BITFIELD */
777 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
778 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
779 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
780 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
781 #endif
782
783 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
784 #define PRLO_NO_SUCH_IMAGE 0x4
785 #define PRLO_INVALID_PAGE_CNT 0x7
786
787 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
788
789 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
790
791 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
792
793 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
794 } PRLO;
795
796 typedef struct _ADISC { /* Structure is in Big Endian format */
797 uint32_t hardAL_PA;
798 struct lpfc_name portName;
799 struct lpfc_name nodeName;
800 uint32_t DID;
801 } ADISC;
802
803 typedef struct _FARP { /* Structure is in Big Endian format */
804 uint32_t Mflags:8;
805 uint32_t Odid:24;
806 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
807 action */
808 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
809 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
810 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
811 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
812 supported */
813 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
814 supported */
815 uint32_t Rflags:8;
816 uint32_t Rdid:24;
817 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
818 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
819 struct lpfc_name OportName;
820 struct lpfc_name OnodeName;
821 struct lpfc_name RportName;
822 struct lpfc_name RnodeName;
823 uint8_t Oipaddr[16];
824 uint8_t Ripaddr[16];
825 } FARP;
826
827 typedef struct _FAN { /* Structure is in Big Endian format */
828 uint32_t Fdid;
829 struct lpfc_name FportName;
830 struct lpfc_name FnodeName;
831 } FAN;
832
833 typedef struct _SCR { /* Structure is in Big Endian format */
834 uint8_t resvd1;
835 uint8_t resvd2;
836 uint8_t resvd3;
837 uint8_t Function;
838 #define SCR_FUNC_FABRIC 0x01
839 #define SCR_FUNC_NPORT 0x02
840 #define SCR_FUNC_FULL 0x03
841 #define SCR_CLEAR 0xff
842 } SCR;
843
844 typedef struct _RNID_TOP_DISC {
845 struct lpfc_name portName;
846 uint8_t resvd[8];
847 uint32_t unitType;
848 #define RNID_HBA 0x7
849 #define RNID_HOST 0xa
850 #define RNID_DRIVER 0xd
851 uint32_t physPort;
852 uint32_t attachedNodes;
853 uint16_t ipVersion;
854 #define RNID_IPV4 0x1
855 #define RNID_IPV6 0x2
856 uint16_t UDPport;
857 uint8_t ipAddr[16];
858 uint16_t resvd1;
859 uint16_t flags;
860 #define RNID_TD_SUPPORT 0x1
861 #define RNID_LP_VALID 0x2
862 } RNID_TOP_DISC;
863
864 typedef struct _RNID { /* Structure is in Big Endian format */
865 uint8_t Format;
866 #define RNID_TOPOLOGY_DISC 0xdf
867 uint8_t CommonLen;
868 uint8_t resvd1;
869 uint8_t SpecificLen;
870 struct lpfc_name portName;
871 struct lpfc_name nodeName;
872 union {
873 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
874 } un;
875 } RNID;
876
877 typedef struct _RPS { /* Structure is in Big Endian format */
878 union {
879 uint32_t portNum;
880 struct lpfc_name portName;
881 } un;
882 } RPS;
883
884 typedef struct _RPS_RSP { /* Structure is in Big Endian format */
885 uint16_t rsvd1;
886 uint16_t portStatus;
887 uint32_t linkFailureCnt;
888 uint32_t lossSyncCnt;
889 uint32_t lossSignalCnt;
890 uint32_t primSeqErrCnt;
891 uint32_t invalidXmitWord;
892 uint32_t crcCnt;
893 } RPS_RSP;
894
895 struct RLS { /* Structure is in Big Endian format */
896 uint32_t rls;
897 #define rls_rsvd_SHIFT 24
898 #define rls_rsvd_MASK 0x000000ff
899 #define rls_rsvd_WORD rls
900 #define rls_did_SHIFT 0
901 #define rls_did_MASK 0x00ffffff
902 #define rls_did_WORD rls
903 };
904
905 struct RLS_RSP { /* Structure is in Big Endian format */
906 uint32_t linkFailureCnt;
907 uint32_t lossSyncCnt;
908 uint32_t lossSignalCnt;
909 uint32_t primSeqErrCnt;
910 uint32_t invalidXmitWord;
911 uint32_t crcCnt;
912 };
913
914 struct RRQ { /* Structure is in Big Endian format */
915 uint32_t rrq;
916 #define rrq_rsvd_SHIFT 24
917 #define rrq_rsvd_MASK 0x000000ff
918 #define rrq_rsvd_WORD rrq
919 #define rrq_did_SHIFT 0
920 #define rrq_did_MASK 0x00ffffff
921 #define rrq_did_WORD rrq
922 uint32_t rrq_exchg;
923 #define rrq_oxid_SHIFT 16
924 #define rrq_oxid_MASK 0xffff
925 #define rrq_oxid_WORD rrq_exchg
926 #define rrq_rxid_SHIFT 0
927 #define rrq_rxid_MASK 0xffff
928 #define rrq_rxid_WORD rrq_exchg
929 };
930
931 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
932 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
933
934 struct RTV_RSP { /* Structure is in Big Endian format */
935 uint32_t ratov;
936 uint32_t edtov;
937 uint32_t qtov;
938 #define qtov_rsvd0_SHIFT 28
939 #define qtov_rsvd0_MASK 0x0000000f
940 #define qtov_rsvd0_WORD qtov /* reserved */
941 #define qtov_edtovres_SHIFT 27
942 #define qtov_edtovres_MASK 0x00000001
943 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
944 #define qtov__rsvd1_SHIFT 19
945 #define qtov_rsvd1_MASK 0x0000003f
946 #define qtov_rsvd1_WORD qtov /* reserved */
947 #define qtov_rttov_SHIFT 18
948 #define qtov_rttov_MASK 0x00000001
949 #define qtov_rttov_WORD qtov /* R_T_TOV value */
950 #define qtov_rsvd2_SHIFT 0
951 #define qtov_rsvd2_MASK 0x0003ffff
952 #define qtov_rsvd2_WORD qtov /* reserved */
953 };
954
955
956 typedef struct _RPL { /* Structure is in Big Endian format */
957 uint32_t maxsize;
958 uint32_t index;
959 } RPL;
960
961 typedef struct _PORT_NUM_BLK {
962 uint32_t portNum;
963 uint32_t portID;
964 struct lpfc_name portName;
965 } PORT_NUM_BLK;
966
967 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
968 uint32_t listLen;
969 uint32_t index;
970 PORT_NUM_BLK port_num_blk;
971 } RPL_RSP;
972
973 /* This is used for RSCN command */
974 typedef struct _D_ID { /* Structure is in Big Endian format */
975 union {
976 uint32_t word;
977 struct {
978 #ifdef __BIG_ENDIAN_BITFIELD
979 uint8_t resv;
980 uint8_t domain;
981 uint8_t area;
982 uint8_t id;
983 #else /* __LITTLE_ENDIAN_BITFIELD */
984 uint8_t id;
985 uint8_t area;
986 uint8_t domain;
987 uint8_t resv;
988 #endif
989 } b;
990 } un;
991 } D_ID;
992
993 #define RSCN_ADDRESS_FORMAT_PORT 0x0
994 #define RSCN_ADDRESS_FORMAT_AREA 0x1
995 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
996 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
997 #define RSCN_ADDRESS_FORMAT_MASK 0x3
998
999 /*
1000 * Structure to define all ELS Payload types
1001 */
1002
1003 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
1004 uint8_t elsCode; /* FC Word 0, bit 24:31 */
1005 uint8_t elsByte1;
1006 uint8_t elsByte2;
1007 uint8_t elsByte3;
1008 union {
1009 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
1010 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
1011 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
1012 PRLI prli; /* Payload for PRLI/ACC */
1013 PRLO prlo; /* Payload for PRLO/ACC */
1014 ADISC adisc; /* Payload for ADISC/ACC */
1015 FARP farp; /* Payload for FARP/ACC */
1016 FAN fan; /* Payload for FAN */
1017 SCR scr; /* Payload for SCR/ACC */
1018 RNID rnid; /* Payload for RNID */
1019 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1020 } un;
1021 } ELS_PKT;
1022
1023 /*
1024 * Link Cable Beacon (LCB) ELS Frame
1025 */
1026
1027 struct fc_lcb_request_frame {
1028 uint32_t lcb_command; /* ELS command opcode (0x81) */
1029 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1030 #define LPFC_LCB_ON 0x1
1031 #define LPFC_LCB_OFF 0x2
1032 uint8_t reserved[3];
1033
1034 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1035 #define LPFC_LCB_GREEN 0x1
1036 #define LPFC_LCB_AMBER 0x2
1037 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1038 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1039 };
1040
1041 /*
1042 * Link Cable Beacon (LCB) ELS Response Frame
1043 */
1044 struct fc_lcb_res_frame {
1045 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
1046 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1047 uint8_t reserved[3];
1048 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1049 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1050 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1051 };
1052
1053 /*
1054 * Read Diagnostic Parameters (RDP) ELS frame.
1055 */
1056 #define SFF_PG0_IDENT_SFP 0x3
1057
1058 #define SFP_FLAG_PT_OPTICAL 0x0
1059 #define SFP_FLAG_PT_SWLASER 0x01
1060 #define SFP_FLAG_PT_LWLASER_LC1310 0x02
1061 #define SFP_FLAG_PT_LWLASER_LL1550 0x03
1062 #define SFP_FLAG_PT_MASK 0x0F
1063 #define SFP_FLAG_PT_SHIFT 0
1064
1065 #define SFP_FLAG_IS_OPTICAL_PORT 0x01
1066 #define SFP_FLAG_IS_OPTICAL_MASK 0x010
1067 #define SFP_FLAG_IS_OPTICAL_SHIFT 4
1068
1069 #define SFP_FLAG_IS_DESC_VALID 0x01
1070 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1071 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1072
1073 #define SFP_FLAG_CT_UNKNOWN 0x0
1074 #define SFP_FLAG_CT_SFP_PLUS 0x01
1075 #define SFP_FLAG_CT_MASK 0x3C
1076 #define SFP_FLAG_CT_SHIFT 6
1077
1078 struct fc_rdp_port_name_info {
1079 uint8_t wwnn[8];
1080 uint8_t wwpn[8];
1081 };
1082
1083
1084 /*
1085 * Link Error Status Block Structure (FC-FS-3) for RDP
1086 * This similar to RPS ELS
1087 */
1088 struct fc_link_status {
1089 uint32_t link_failure_cnt;
1090 uint32_t loss_of_synch_cnt;
1091 uint32_t loss_of_signal_cnt;
1092 uint32_t primitive_seq_proto_err;
1093 uint32_t invalid_trans_word;
1094 uint32_t invalid_crc_cnt;
1095
1096 };
1097
1098 #define RDP_PORT_NAMES_DESC_TAG 0x00010003
1099 struct fc_rdp_port_name_desc {
1100 uint32_t tag; /* 0001 0003h */
1101 uint32_t length; /* set to size of payload struct */
1102 struct fc_rdp_port_name_info port_names;
1103 };
1104
1105
1106 struct fc_rdp_link_error_status_payload_info {
1107 struct fc_link_status link_status; /* 24 bytes */
1108 uint32_t port_type; /* bits 31-30 only */
1109 };
1110
1111 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1112 struct fc_rdp_link_error_status_desc {
1113 uint32_t tag; /* 0001 0002h */
1114 uint32_t length; /* set to size of payload struct */
1115 struct fc_rdp_link_error_status_payload_info info;
1116 };
1117
1118 #define VN_PT_PHY_UNKNOWN 0x00
1119 #define VN_PT_PHY_PF_PORT 0x01
1120 #define VN_PT_PHY_ETH_MAC 0x10
1121 #define VN_PT_PHY_SHIFT 30
1122
1123 #define RDP_PS_1GB 0x8000
1124 #define RDP_PS_2GB 0x4000
1125 #define RDP_PS_4GB 0x2000
1126 #define RDP_PS_10GB 0x1000
1127 #define RDP_PS_8GB 0x0800
1128 #define RDP_PS_16GB 0x0400
1129 #define RDP_PS_32GB 0x0200
1130
1131 #define RDP_CAP_UNKNOWN 0x0001
1132 #define RDP_PS_UNKNOWN 0x0002
1133 #define RDP_PS_NOT_ESTABLISHED 0x0001
1134
1135 struct fc_rdp_port_speed {
1136 uint16_t capabilities;
1137 uint16_t speed;
1138 };
1139
1140 struct fc_rdp_port_speed_info {
1141 struct fc_rdp_port_speed port_speed;
1142 };
1143
1144 #define RDP_PORT_SPEED_DESC_TAG 0x00010001
1145 struct fc_rdp_port_speed_desc {
1146 uint32_t tag; /* 00010001h */
1147 uint32_t length; /* set to size of payload struct */
1148 struct fc_rdp_port_speed_info info;
1149 };
1150
1151 #define RDP_NPORT_ID_SIZE 4
1152 #define RDP_N_PORT_DESC_TAG 0x00000003
1153 struct fc_rdp_nport_desc {
1154 uint32_t tag; /* 0000 0003h, big endian */
1155 uint32_t length; /* size of RDP_N_PORT_ID struct */
1156 uint32_t nport_id : 12;
1157 uint32_t reserved : 8;
1158 };
1159
1160
1161 struct fc_rdp_link_service_info {
1162 uint32_t els_req; /* Request payload word 0 value.*/
1163 };
1164
1165 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1166 struct fc_rdp_link_service_desc {
1167 uint32_t tag; /* Descriptor tag 1 */
1168 uint32_t length; /* set to size of payload struct. */
1169 struct fc_rdp_link_service_info payload;
1170 /* must be ELS req Word 0(0x18) */
1171 };
1172
1173 struct fc_rdp_sfp_info {
1174 uint16_t temperature;
1175 uint16_t vcc;
1176 uint16_t tx_bias;
1177 uint16_t tx_power;
1178 uint16_t rx_power;
1179 uint16_t flags;
1180 };
1181
1182 #define RDP_SFP_DESC_TAG 0x00010000
1183 struct fc_rdp_sfp_desc {
1184 uint32_t tag;
1185 uint32_t length; /* set to size of sfp_info struct */
1186 struct fc_rdp_sfp_info sfp_info;
1187 };
1188
1189 struct fc_rdp_req_frame {
1190 uint32_t rdp_command; /* ELS command opcode (0x18)*/
1191 uint32_t rdp_des_length; /* RDP Payload Word 1 */
1192 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1193 };
1194
1195
1196 struct fc_rdp_res_frame {
1197 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
1198 uint32_t length; /* FC Word 1 */
1199 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
1200 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
1201 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10-12 */
1202 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13-21 */
1203 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22-27 */
1204 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28-33 */
1205 };
1206
1207
1208 #define RDP_DESC_PAYLOAD_SIZE (sizeof(struct fc_rdp_link_service_desc) \
1209 + sizeof(struct fc_rdp_sfp_desc) \
1210 + sizeof(struct fc_rdp_port_speed_desc) \
1211 + sizeof(struct fc_rdp_link_error_status_desc) \
1212 + (sizeof(struct fc_rdp_port_name_desc) * 2))
1213
1214
1215 /******** FDMI ********/
1216
1217 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1218 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
1219
1220 /*
1221 * Registered Port List Format
1222 */
1223 struct lpfc_fdmi_reg_port_list {
1224 uint32_t EntryCnt;
1225 uint32_t pe; /* Variable-length array */
1226 };
1227
1228
1229 /* Definitions for HBA / Port attribute entries */
1230
1231 struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1232 /* Structure is in Big Endian format */
1233 uint32_t AttrType:16;
1234 uint32_t AttrLen:16;
1235 uint32_t AttrValue; /* Marks start of Value (ATTRIBUTE_ENTRY) */
1236 };
1237
1238
1239 /* Attribute Entry */
1240 struct lpfc_fdmi_attr_entry {
1241 union {
1242 uint32_t VendorSpecific;
1243 uint32_t SupportClass;
1244 uint32_t SupportSpeed;
1245 uint32_t PortSpeed;
1246 uint32_t MaxFrameSize;
1247 uint32_t MaxCTPayloadLen;
1248 uint32_t PortState;
1249 uint32_t PortId;
1250 struct lpfc_name NodeName;
1251 struct lpfc_name PortName;
1252 struct lpfc_name FabricName;
1253 uint8_t FC4Types[32];
1254 uint8_t Manufacturer[64];
1255 uint8_t SerialNumber[64];
1256 uint8_t Model[256];
1257 uint8_t ModelDescription[256];
1258 uint8_t HardwareVersion[256];
1259 uint8_t DriverVersion[256];
1260 uint8_t OptionROMVersion[256];
1261 uint8_t FirmwareVersion[256];
1262 uint8_t OsHostName[256];
1263 uint8_t NodeSymName[256];
1264 uint8_t OsDeviceName[256];
1265 uint8_t OsNameVersion[256];
1266 uint8_t HostName[256];
1267 } un;
1268 };
1269
1270 #define LPFC_FDMI_MAX_AE_SIZE sizeof(struct lpfc_fdmi_attr_entry)
1271
1272 /*
1273 * HBA Attribute Block
1274 */
1275 struct lpfc_fdmi_attr_block {
1276 uint32_t EntryCnt; /* Number of HBA attribute entries */
1277 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */
1278 };
1279
1280 /*
1281 * Port Entry
1282 */
1283 struct lpfc_fdmi_port_entry {
1284 struct lpfc_name PortName;
1285 };
1286
1287 /*
1288 * HBA Identifier
1289 */
1290 struct lpfc_fdmi_hba_ident {
1291 struct lpfc_name PortName;
1292 };
1293
1294 /*
1295 * Register HBA(RHBA)
1296 */
1297 struct lpfc_fdmi_reg_hba {
1298 struct lpfc_fdmi_hba_ident hi;
1299 struct lpfc_fdmi_reg_port_list rpl; /* variable-length array */
1300 /* struct lpfc_fdmi_attr_block ab; */
1301 };
1302
1303 /*
1304 * Register HBA Attributes (RHAT)
1305 */
1306 struct lpfc_fdmi_reg_hbaattr {
1307 struct lpfc_name HBA_PortName;
1308 struct lpfc_fdmi_attr_block ab;
1309 };
1310
1311 /*
1312 * Register Port Attributes (RPA)
1313 */
1314 struct lpfc_fdmi_reg_portattr {
1315 struct lpfc_name PortName;
1316 struct lpfc_fdmi_attr_block ab;
1317 };
1318
1319 /*
1320 * HBA MAnagement Operations Command Codes
1321 */
1322 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1323 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1324 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1325 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1326 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
1327 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
1328 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1329 #define SLI_MGMT_RPRT 0x210 /* Register Port */
1330 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1331 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1332 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
1333 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
1334 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
1335
1336 /*
1337 * HBA Attribute Types
1338 */
1339 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */
1340 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
1341 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
1342 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
1343 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
1344 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
1345 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
1346 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1347 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
1348 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
1349 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1350 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
1351
1352 /*
1353 * Port Attrubute Types
1354 */
1355 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
1356 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
1357 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
1358 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
1359 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
1360 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
1361 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */
1362 #define RPRT_PORTNAME 0x8 /* 8 byte WWNN */
1363 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
1364 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
1365 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
1366 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWNN */
1367 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
1368 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
1369 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
1370 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
1371
1372 /*
1373 * Begin HBA configuration parameters.
1374 * The PCI configuration register BAR assignments are:
1375 * BAR0, offset 0x10 - SLIM base memory address
1376 * BAR1, offset 0x14 - SLIM base memory high address
1377 * BAR2, offset 0x18 - REGISTER base memory address
1378 * BAR3, offset 0x1c - REGISTER base memory high address
1379 * BAR4, offset 0x20 - BIU I/O registers
1380 * BAR5, offset 0x24 - REGISTER base io high address
1381 */
1382
1383 /* Number of rings currently used and available. */
1384 #define MAX_SLI3_CONFIGURED_RINGS 3
1385 #define MAX_SLI3_RINGS 4
1386
1387 /* IOCB / Mailbox is owned by FireFly */
1388 #define OWN_CHIP 1
1389
1390 /* IOCB / Mailbox is owned by Host */
1391 #define OWN_HOST 0
1392
1393 /* Number of 4-byte words in an IOCB. */
1394 #define IOCB_WORD_SZ 8
1395
1396 /* network headers for Dfctl field */
1397 #define FC_NET_HDR 0x20
1398
1399 /* Start FireFly Register definitions */
1400 #define PCI_VENDOR_ID_EMULEX 0x10df
1401 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1402 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1403 #define PCI_DEVICE_ID_BALIUS 0xe131
1404 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1405 #define PCI_DEVICE_ID_LANCER_FC 0xe200
1406 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1407 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1408 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1409 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1410 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1411 #define PCI_DEVICE_ID_SAT_MID 0xf015
1412 #define PCI_DEVICE_ID_RFLY 0xf095
1413 #define PCI_DEVICE_ID_PFLY 0xf098
1414 #define PCI_DEVICE_ID_LP101 0xf0a1
1415 #define PCI_DEVICE_ID_TFLY 0xf0a5
1416 #define PCI_DEVICE_ID_BSMB 0xf0d1
1417 #define PCI_DEVICE_ID_BMID 0xf0d5
1418 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1419 #define PCI_DEVICE_ID_ZMID 0xf0e5
1420 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1421 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1422 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1423 #define PCI_DEVICE_ID_SAT 0xf100
1424 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1425 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1426 #define PCI_DEVICE_ID_FALCON 0xf180
1427 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1428 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1429 #define PCI_DEVICE_ID_CENTAUR 0xf900
1430 #define PCI_DEVICE_ID_PEGASUS 0xf980
1431 #define PCI_DEVICE_ID_THOR 0xfa00
1432 #define PCI_DEVICE_ID_VIPER 0xfb00
1433 #define PCI_DEVICE_ID_LP10000S 0xfc00
1434 #define PCI_DEVICE_ID_LP11000S 0xfc10
1435 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1436 #define PCI_DEVICE_ID_SAT_S 0xfc40
1437 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1438 #define PCI_DEVICE_ID_HELIOS 0xfd00
1439 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1440 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1441 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1442 #define PCI_DEVICE_ID_HORNET 0xfe05
1443 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1444 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1445 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1446 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1447 #define PCI_DEVICE_ID_TOMCAT 0x0714
1448 #define PCI_DEVICE_ID_SKYHAWK 0x0724
1449 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1450
1451 #define JEDEC_ID_ADDRESS 0x0080001c
1452 #define FIREFLY_JEDEC_ID 0x1ACC
1453 #define SUPERFLY_JEDEC_ID 0x0020
1454 #define DRAGONFLY_JEDEC_ID 0x0021
1455 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1456 #define CENTAUR_2G_JEDEC_ID 0x0026
1457 #define CENTAUR_1G_JEDEC_ID 0x0028
1458 #define PEGASUS_ORION_JEDEC_ID 0x0036
1459 #define PEGASUS_JEDEC_ID 0x0038
1460 #define THOR_JEDEC_ID 0x0012
1461 #define HELIOS_JEDEC_ID 0x0364
1462 #define ZEPHYR_JEDEC_ID 0x0577
1463 #define VIPER_JEDEC_ID 0x4838
1464 #define SATURN_JEDEC_ID 0x1004
1465 #define HORNET_JDEC_ID 0x2057706D
1466
1467 #define JEDEC_ID_MASK 0x0FFFF000
1468 #define JEDEC_ID_SHIFT 12
1469 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1470
1471 typedef struct { /* FireFly BIU registers */
1472 uint32_t hostAtt; /* See definitions for Host Attention
1473 register */
1474 uint32_t chipAtt; /* See definitions for Chip Attention
1475 register */
1476 uint32_t hostStatus; /* See definitions for Host Status register */
1477 uint32_t hostControl; /* See definitions for Host Control register */
1478 uint32_t buiConfig; /* See definitions for BIU configuration
1479 register */
1480 } FF_REGS;
1481
1482 /* IO Register size in bytes */
1483 #define FF_REG_AREA_SIZE 256
1484
1485 /* Host Attention Register */
1486
1487 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1488
1489 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1490 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1491 #define HA_R0ATT 0x00000008 /* Bit 3 */
1492 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1493 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1494 #define HA_R1ATT 0x00000080 /* Bit 7 */
1495 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1496 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1497 #define HA_R2ATT 0x00000800 /* Bit 11 */
1498 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1499 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1500 #define HA_R3ATT 0x00008000 /* Bit 15 */
1501 #define HA_LATT 0x20000000 /* Bit 29 */
1502 #define HA_MBATT 0x40000000 /* Bit 30 */
1503 #define HA_ERATT 0x80000000 /* Bit 31 */
1504
1505 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1506 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1507 #define HA_RXATT 0x00000008 /* Bit 3 */
1508 #define HA_RXMASK 0x0000000f
1509
1510 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1511 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1512 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1513 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1514
1515 #define HA_R0_POS 3
1516 #define HA_R1_POS 7
1517 #define HA_R2_POS 11
1518 #define HA_R3_POS 15
1519 #define HA_LE_POS 29
1520 #define HA_MB_POS 30
1521 #define HA_ER_POS 31
1522 /* Chip Attention Register */
1523
1524 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1525
1526 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1527 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1528 #define CA_R0ATT 0x00000008 /* Bit 3 */
1529 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1530 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1531 #define CA_R1ATT 0x00000080 /* Bit 7 */
1532 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1533 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1534 #define CA_R2ATT 0x00000800 /* Bit 11 */
1535 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1536 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1537 #define CA_R3ATT 0x00008000 /* Bit 15 */
1538 #define CA_MBATT 0x40000000 /* Bit 30 */
1539
1540 /* Host Status Register */
1541
1542 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1543
1544 #define HS_MBRDY 0x00400000 /* Bit 22 */
1545 #define HS_FFRDY 0x00800000 /* Bit 23 */
1546 #define HS_FFER8 0x01000000 /* Bit 24 */
1547 #define HS_FFER7 0x02000000 /* Bit 25 */
1548 #define HS_FFER6 0x04000000 /* Bit 26 */
1549 #define HS_FFER5 0x08000000 /* Bit 27 */
1550 #define HS_FFER4 0x10000000 /* Bit 28 */
1551 #define HS_FFER3 0x20000000 /* Bit 29 */
1552 #define HS_FFER2 0x40000000 /* Bit 30 */
1553 #define HS_FFER1 0x80000000 /* Bit 31 */
1554 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1555 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1556 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1557 /* Host Control Register */
1558
1559 #define HC_REG_OFFSET 12 /* Byte offset from register base address */
1560
1561 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1562 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1563 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1564 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1565 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1566 #define HC_INITHBI 0x02000000 /* Bit 25 */
1567 #define HC_INITMB 0x04000000 /* Bit 26 */
1568 #define HC_INITFF 0x08000000 /* Bit 27 */
1569 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1570 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1571
1572 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1573 #define MSIX_DFLT_ID 0
1574 #define MSIX_RNG0_ID 0
1575 #define MSIX_RNG1_ID 1
1576 #define MSIX_RNG2_ID 2
1577 #define MSIX_RNG3_ID 3
1578
1579 #define MSIX_LINK_ID 4
1580 #define MSIX_MBOX_ID 5
1581
1582 #define MSIX_SPARE0_ID 6
1583 #define MSIX_SPARE1_ID 7
1584
1585 /* Mailbox Commands */
1586 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1587 #define MBX_LOAD_SM 0x01
1588 #define MBX_READ_NV 0x02
1589 #define MBX_WRITE_NV 0x03
1590 #define MBX_RUN_BIU_DIAG 0x04
1591 #define MBX_INIT_LINK 0x05
1592 #define MBX_DOWN_LINK 0x06
1593 #define MBX_CONFIG_LINK 0x07
1594 #define MBX_CONFIG_RING 0x09
1595 #define MBX_RESET_RING 0x0A
1596 #define MBX_READ_CONFIG 0x0B
1597 #define MBX_READ_RCONFIG 0x0C
1598 #define MBX_READ_SPARM 0x0D
1599 #define MBX_READ_STATUS 0x0E
1600 #define MBX_READ_RPI 0x0F
1601 #define MBX_READ_XRI 0x10
1602 #define MBX_READ_REV 0x11
1603 #define MBX_READ_LNK_STAT 0x12
1604 #define MBX_REG_LOGIN 0x13
1605 #define MBX_UNREG_LOGIN 0x14
1606 #define MBX_CLEAR_LA 0x16
1607 #define MBX_DUMP_MEMORY 0x17
1608 #define MBX_DUMP_CONTEXT 0x18
1609 #define MBX_RUN_DIAGS 0x19
1610 #define MBX_RESTART 0x1A
1611 #define MBX_UPDATE_CFG 0x1B
1612 #define MBX_DOWN_LOAD 0x1C
1613 #define MBX_DEL_LD_ENTRY 0x1D
1614 #define MBX_RUN_PROGRAM 0x1E
1615 #define MBX_SET_MASK 0x20
1616 #define MBX_SET_VARIABLE 0x21
1617 #define MBX_UNREG_D_ID 0x23
1618 #define MBX_KILL_BOARD 0x24
1619 #define MBX_CONFIG_FARP 0x25
1620 #define MBX_BEACON 0x2A
1621 #define MBX_CONFIG_MSI 0x30
1622 #define MBX_HEARTBEAT 0x31
1623 #define MBX_WRITE_VPARMS 0x32
1624 #define MBX_ASYNCEVT_ENABLE 0x33
1625 #define MBX_READ_EVENT_LOG_STATUS 0x37
1626 #define MBX_READ_EVENT_LOG 0x38
1627 #define MBX_WRITE_EVENT_LOG 0x39
1628
1629 #define MBX_PORT_CAPABILITIES 0x3B
1630 #define MBX_PORT_IOV_CONTROL 0x3C
1631
1632 #define MBX_CONFIG_HBQ 0x7C
1633 #define MBX_LOAD_AREA 0x81
1634 #define MBX_RUN_BIU_DIAG64 0x84
1635 #define MBX_CONFIG_PORT 0x88
1636 #define MBX_READ_SPARM64 0x8D
1637 #define MBX_READ_RPI64 0x8F
1638 #define MBX_REG_LOGIN64 0x93
1639 #define MBX_READ_TOPOLOGY 0x95
1640 #define MBX_REG_VPI 0x96
1641 #define MBX_UNREG_VPI 0x97
1642
1643 #define MBX_WRITE_WWN 0x98
1644 #define MBX_SET_DEBUG 0x99
1645 #define MBX_LOAD_EXP_ROM 0x9C
1646 #define MBX_SLI4_CONFIG 0x9B
1647 #define MBX_SLI4_REQ_FTRS 0x9D
1648 #define MBX_MAX_CMDS 0x9E
1649 #define MBX_RESUME_RPI 0x9E
1650 #define MBX_SLI2_CMD_MASK 0x80
1651 #define MBX_REG_VFI 0x9F
1652 #define MBX_REG_FCFI 0xA0
1653 #define MBX_UNREG_VFI 0xA1
1654 #define MBX_UNREG_FCFI 0xA2
1655 #define MBX_INIT_VFI 0xA3
1656 #define MBX_INIT_VPI 0xA4
1657 #define MBX_ACCESS_VDATA 0xA5
1658
1659 #define MBX_AUTH_PORT 0xF8
1660 #define MBX_SECURITY_MGMT 0xF9
1661
1662 /* IOCB Commands */
1663
1664 #define CMD_RCV_SEQUENCE_CX 0x01
1665 #define CMD_XMIT_SEQUENCE_CR 0x02
1666 #define CMD_XMIT_SEQUENCE_CX 0x03
1667 #define CMD_XMIT_BCAST_CN 0x04
1668 #define CMD_XMIT_BCAST_CX 0x05
1669 #define CMD_QUE_RING_BUF_CN 0x06
1670 #define CMD_QUE_XRI_BUF_CX 0x07
1671 #define CMD_IOCB_CONTINUE_CN 0x08
1672 #define CMD_RET_XRI_BUF_CX 0x09
1673 #define CMD_ELS_REQUEST_CR 0x0A
1674 #define CMD_ELS_REQUEST_CX 0x0B
1675 #define CMD_RCV_ELS_REQ_CX 0x0D
1676 #define CMD_ABORT_XRI_CN 0x0E
1677 #define CMD_ABORT_XRI_CX 0x0F
1678 #define CMD_CLOSE_XRI_CN 0x10
1679 #define CMD_CLOSE_XRI_CX 0x11
1680 #define CMD_CREATE_XRI_CR 0x12
1681 #define CMD_CREATE_XRI_CX 0x13
1682 #define CMD_GET_RPI_CN 0x14
1683 #define CMD_XMIT_ELS_RSP_CX 0x15
1684 #define CMD_GET_RPI_CR 0x16
1685 #define CMD_XRI_ABORTED_CX 0x17
1686 #define CMD_FCP_IWRITE_CR 0x18
1687 #define CMD_FCP_IWRITE_CX 0x19
1688 #define CMD_FCP_IREAD_CR 0x1A
1689 #define CMD_FCP_IREAD_CX 0x1B
1690 #define CMD_FCP_ICMND_CR 0x1C
1691 #define CMD_FCP_ICMND_CX 0x1D
1692 #define CMD_FCP_TSEND_CX 0x1F
1693 #define CMD_FCP_TRECEIVE_CX 0x21
1694 #define CMD_FCP_TRSP_CX 0x23
1695 #define CMD_FCP_AUTO_TRSP_CX 0x29
1696
1697 #define CMD_ADAPTER_MSG 0x20
1698 #define CMD_ADAPTER_DUMP 0x22
1699
1700 /* SLI_2 IOCB Command Set */
1701
1702 #define CMD_ASYNC_STATUS 0x7C
1703 #define CMD_RCV_SEQUENCE64_CX 0x81
1704 #define CMD_XMIT_SEQUENCE64_CR 0x82
1705 #define CMD_XMIT_SEQUENCE64_CX 0x83
1706 #define CMD_XMIT_BCAST64_CN 0x84
1707 #define CMD_XMIT_BCAST64_CX 0x85
1708 #define CMD_QUE_RING_BUF64_CN 0x86
1709 #define CMD_QUE_XRI_BUF64_CX 0x87
1710 #define CMD_IOCB_CONTINUE64_CN 0x88
1711 #define CMD_RET_XRI_BUF64_CX 0x89
1712 #define CMD_ELS_REQUEST64_CR 0x8A
1713 #define CMD_ELS_REQUEST64_CX 0x8B
1714 #define CMD_ABORT_MXRI64_CN 0x8C
1715 #define CMD_RCV_ELS_REQ64_CX 0x8D
1716 #define CMD_XMIT_ELS_RSP64_CX 0x95
1717 #define CMD_XMIT_BLS_RSP64_CX 0x97
1718 #define CMD_FCP_IWRITE64_CR 0x98
1719 #define CMD_FCP_IWRITE64_CX 0x99
1720 #define CMD_FCP_IREAD64_CR 0x9A
1721 #define CMD_FCP_IREAD64_CX 0x9B
1722 #define CMD_FCP_ICMND64_CR 0x9C
1723 #define CMD_FCP_ICMND64_CX 0x9D
1724 #define CMD_FCP_TSEND64_CX 0x9F
1725 #define CMD_FCP_TRECEIVE64_CX 0xA1
1726 #define CMD_FCP_TRSP64_CX 0xA3
1727
1728 #define CMD_QUE_XRI64_CX 0xB3
1729 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1730 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1731 #define CMD_IOCB_RET_XRI64_CX 0xB9
1732 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1733
1734 #define CMD_GEN_REQUEST64_CR 0xC2
1735 #define CMD_GEN_REQUEST64_CX 0xC3
1736
1737 /* Unhandled SLI-3 Commands */
1738 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1739 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1740 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1741 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1742 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1743 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1744 #define CMD_IOCB_RET_HBQE64_CN 0xCA
1745 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1746 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1747 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1748 #define CMD_IOCB_LOGENTRY_CN 0x94
1749 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1750
1751 /* Data Security SLI Commands */
1752 #define DSSCMD_IWRITE64_CR 0xF8
1753 #define DSSCMD_IWRITE64_CX 0xF9
1754 #define DSSCMD_IREAD64_CR 0xFA
1755 #define DSSCMD_IREAD64_CX 0xFB
1756
1757 #define CMD_MAX_IOCB_CMD 0xFB
1758 #define CMD_IOCB_MASK 0xff
1759
1760 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1761 iocb */
1762 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1763 /*
1764 * Define Status
1765 */
1766 #define MBX_SUCCESS 0
1767 #define MBXERR_NUM_RINGS 1
1768 #define MBXERR_NUM_IOCBS 2
1769 #define MBXERR_IOCBS_EXCEEDED 3
1770 #define MBXERR_BAD_RING_NUMBER 4
1771 #define MBXERR_MASK_ENTRIES_RANGE 5
1772 #define MBXERR_MASKS_EXCEEDED 6
1773 #define MBXERR_BAD_PROFILE 7
1774 #define MBXERR_BAD_DEF_CLASS 8
1775 #define MBXERR_BAD_MAX_RESPONDER 9
1776 #define MBXERR_BAD_MAX_ORIGINATOR 10
1777 #define MBXERR_RPI_REGISTERED 11
1778 #define MBXERR_RPI_FULL 12
1779 #define MBXERR_NO_RESOURCES 13
1780 #define MBXERR_BAD_RCV_LENGTH 14
1781 #define MBXERR_DMA_ERROR 15
1782 #define MBXERR_ERROR 16
1783 #define MBXERR_LINK_DOWN 0x33
1784 #define MBXERR_SEC_NO_PERMISSION 0xF02
1785 #define MBX_NOT_FINISHED 255
1786
1787 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1788 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1789
1790 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1791
1792 /*
1793 * return code Fail
1794 */
1795 #define FAILURE 1
1796
1797 /*
1798 * Begin Structure Definitions for Mailbox Commands
1799 */
1800
1801 typedef struct {
1802 #ifdef __BIG_ENDIAN_BITFIELD
1803 uint8_t tval;
1804 uint8_t tmask;
1805 uint8_t rval;
1806 uint8_t rmask;
1807 #else /* __LITTLE_ENDIAN_BITFIELD */
1808 uint8_t rmask;
1809 uint8_t rval;
1810 uint8_t tmask;
1811 uint8_t tval;
1812 #endif
1813 } RR_REG;
1814
1815 struct ulp_bde {
1816 uint32_t bdeAddress;
1817 #ifdef __BIG_ENDIAN_BITFIELD
1818 uint32_t bdeReserved:4;
1819 uint32_t bdeAddrHigh:4;
1820 uint32_t bdeSize:24;
1821 #else /* __LITTLE_ENDIAN_BITFIELD */
1822 uint32_t bdeSize:24;
1823 uint32_t bdeAddrHigh:4;
1824 uint32_t bdeReserved:4;
1825 #endif
1826 };
1827
1828 typedef struct ULP_BDL { /* SLI-2 */
1829 #ifdef __BIG_ENDIAN_BITFIELD
1830 uint32_t bdeFlags:8; /* BDL Flags */
1831 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1832 #else /* __LITTLE_ENDIAN_BITFIELD */
1833 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1834 uint32_t bdeFlags:8; /* BDL Flags */
1835 #endif
1836
1837 uint32_t addrLow; /* Address 0:31 */
1838 uint32_t addrHigh; /* Address 32:63 */
1839 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1840 } ULP_BDL;
1841
1842 /*
1843 * BlockGuard Definitions
1844 */
1845
1846 enum lpfc_protgrp_type {
1847 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
1848 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
1849 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
1850 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
1851 };
1852
1853 /* PDE Descriptors */
1854 #define LPFC_PDE5_DESCRIPTOR 0x85
1855 #define LPFC_PDE6_DESCRIPTOR 0x86
1856 #define LPFC_PDE7_DESCRIPTOR 0x87
1857
1858 /* BlockGuard Opcodes */
1859 #define BG_OP_IN_NODIF_OUT_CRC 0x0
1860 #define BG_OP_IN_CRC_OUT_NODIF 0x1
1861 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
1862 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
1863 #define BG_OP_IN_CRC_OUT_CRC 0x4
1864 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
1865 #define BG_OP_IN_CRC_OUT_CSUM 0x6
1866 #define BG_OP_IN_CSUM_OUT_CRC 0x7
1867 #define BG_OP_RAW_MODE 0x8
1868
1869 struct lpfc_pde5 {
1870 uint32_t word0;
1871 #define pde5_type_SHIFT 24
1872 #define pde5_type_MASK 0x000000ff
1873 #define pde5_type_WORD word0
1874 #define pde5_rsvd0_SHIFT 0
1875 #define pde5_rsvd0_MASK 0x00ffffff
1876 #define pde5_rsvd0_WORD word0
1877 uint32_t reftag; /* Reference Tag Value */
1878 uint32_t reftagtr; /* Reference Tag Translation Value */
1879 };
1880
1881 struct lpfc_pde6 {
1882 uint32_t word0;
1883 #define pde6_type_SHIFT 24
1884 #define pde6_type_MASK 0x000000ff
1885 #define pde6_type_WORD word0
1886 #define pde6_rsvd0_SHIFT 0
1887 #define pde6_rsvd0_MASK 0x00ffffff
1888 #define pde6_rsvd0_WORD word0
1889 uint32_t word1;
1890 #define pde6_rsvd1_SHIFT 26
1891 #define pde6_rsvd1_MASK 0x0000003f
1892 #define pde6_rsvd1_WORD word1
1893 #define pde6_na_SHIFT 25
1894 #define pde6_na_MASK 0x00000001
1895 #define pde6_na_WORD word1
1896 #define pde6_rsvd2_SHIFT 16
1897 #define pde6_rsvd2_MASK 0x000001FF
1898 #define pde6_rsvd2_WORD word1
1899 #define pde6_apptagtr_SHIFT 0
1900 #define pde6_apptagtr_MASK 0x0000ffff
1901 #define pde6_apptagtr_WORD word1
1902 uint32_t word2;
1903 #define pde6_optx_SHIFT 28
1904 #define pde6_optx_MASK 0x0000000f
1905 #define pde6_optx_WORD word2
1906 #define pde6_oprx_SHIFT 24
1907 #define pde6_oprx_MASK 0x0000000f
1908 #define pde6_oprx_WORD word2
1909 #define pde6_nr_SHIFT 23
1910 #define pde6_nr_MASK 0x00000001
1911 #define pde6_nr_WORD word2
1912 #define pde6_ce_SHIFT 22
1913 #define pde6_ce_MASK 0x00000001
1914 #define pde6_ce_WORD word2
1915 #define pde6_re_SHIFT 21
1916 #define pde6_re_MASK 0x00000001
1917 #define pde6_re_WORD word2
1918 #define pde6_ae_SHIFT 20
1919 #define pde6_ae_MASK 0x00000001
1920 #define pde6_ae_WORD word2
1921 #define pde6_ai_SHIFT 19
1922 #define pde6_ai_MASK 0x00000001
1923 #define pde6_ai_WORD word2
1924 #define pde6_bs_SHIFT 16
1925 #define pde6_bs_MASK 0x00000007
1926 #define pde6_bs_WORD word2
1927 #define pde6_apptagval_SHIFT 0
1928 #define pde6_apptagval_MASK 0x0000ffff
1929 #define pde6_apptagval_WORD word2
1930 };
1931
1932 struct lpfc_pde7 {
1933 uint32_t word0;
1934 #define pde7_type_SHIFT 24
1935 #define pde7_type_MASK 0x000000ff
1936 #define pde7_type_WORD word0
1937 #define pde7_rsvd0_SHIFT 0
1938 #define pde7_rsvd0_MASK 0x00ffffff
1939 #define pde7_rsvd0_WORD word0
1940 uint32_t addrHigh;
1941 uint32_t addrLow;
1942 };
1943
1944 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1945
1946 typedef struct {
1947 #ifdef __BIG_ENDIAN_BITFIELD
1948 uint32_t rsvd2:25;
1949 uint32_t acknowledgment:1;
1950 uint32_t version:1;
1951 uint32_t erase_or_prog:1;
1952 uint32_t update_flash:1;
1953 uint32_t update_ram:1;
1954 uint32_t method:1;
1955 uint32_t load_cmplt:1;
1956 #else /* __LITTLE_ENDIAN_BITFIELD */
1957 uint32_t load_cmplt:1;
1958 uint32_t method:1;
1959 uint32_t update_ram:1;
1960 uint32_t update_flash:1;
1961 uint32_t erase_or_prog:1;
1962 uint32_t version:1;
1963 uint32_t acknowledgment:1;
1964 uint32_t rsvd2:25;
1965 #endif
1966
1967 uint32_t dl_to_adr_low;
1968 uint32_t dl_to_adr_high;
1969 uint32_t dl_len;
1970 union {
1971 uint32_t dl_from_mbx_offset;
1972 struct ulp_bde dl_from_bde;
1973 struct ulp_bde64 dl_from_bde64;
1974 } un;
1975
1976 } LOAD_SM_VAR;
1977
1978 /* Structure for MB Command READ_NVPARM (02) */
1979
1980 typedef struct {
1981 uint32_t rsvd1[3]; /* Read as all one's */
1982 uint32_t rsvd2; /* Read as all zero's */
1983 uint32_t portname[2]; /* N_PORT name */
1984 uint32_t nodename[2]; /* NODE name */
1985
1986 #ifdef __BIG_ENDIAN_BITFIELD
1987 uint32_t pref_DID:24;
1988 uint32_t hardAL_PA:8;
1989 #else /* __LITTLE_ENDIAN_BITFIELD */
1990 uint32_t hardAL_PA:8;
1991 uint32_t pref_DID:24;
1992 #endif
1993
1994 uint32_t rsvd3[21]; /* Read as all one's */
1995 } READ_NV_VAR;
1996
1997 /* Structure for MB Command WRITE_NVPARMS (03) */
1998
1999 typedef struct {
2000 uint32_t rsvd1[3]; /* Must be all one's */
2001 uint32_t rsvd2; /* Must be all zero's */
2002 uint32_t portname[2]; /* N_PORT name */
2003 uint32_t nodename[2]; /* NODE name */
2004
2005 #ifdef __BIG_ENDIAN_BITFIELD
2006 uint32_t pref_DID:24;
2007 uint32_t hardAL_PA:8;
2008 #else /* __LITTLE_ENDIAN_BITFIELD */
2009 uint32_t hardAL_PA:8;
2010 uint32_t pref_DID:24;
2011 #endif
2012
2013 uint32_t rsvd3[21]; /* Must be all one's */
2014 } WRITE_NV_VAR;
2015
2016 /* Structure for MB Command RUN_BIU_DIAG (04) */
2017 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2018
2019 typedef struct {
2020 uint32_t rsvd1;
2021 union {
2022 struct {
2023 struct ulp_bde xmit_bde;
2024 struct ulp_bde rcv_bde;
2025 } s1;
2026 struct {
2027 struct ulp_bde64 xmit_bde64;
2028 struct ulp_bde64 rcv_bde64;
2029 } s2;
2030 } un;
2031 } BIU_DIAG_VAR;
2032
2033 /* Structure for MB command READ_EVENT_LOG (0x38) */
2034 struct READ_EVENT_LOG_VAR {
2035 uint32_t word1;
2036 #define lpfc_event_log_SHIFT 29
2037 #define lpfc_event_log_MASK 0x00000001
2038 #define lpfc_event_log_WORD word1
2039 #define USE_MAILBOX_RESPONSE 1
2040 uint32_t offset;
2041 struct ulp_bde64 rcv_bde64;
2042 };
2043
2044 /* Structure for MB Command INIT_LINK (05) */
2045
2046 typedef struct {
2047 #ifdef __BIG_ENDIAN_BITFIELD
2048 uint32_t rsvd1:24;
2049 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2050 #else /* __LITTLE_ENDIAN_BITFIELD */
2051 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2052 uint32_t rsvd1:24;
2053 #endif
2054
2055 #ifdef __BIG_ENDIAN_BITFIELD
2056 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2057 uint8_t rsvd2;
2058 uint16_t link_flags;
2059 #else /* __LITTLE_ENDIAN_BITFIELD */
2060 uint16_t link_flags;
2061 uint8_t rsvd2;
2062 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2063 #endif
2064
2065 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
2066 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
2067 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
2068 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
2069 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
2070 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
2071 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
2072
2073 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
2074 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
2075 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
2076
2077 uint32_t link_speed;
2078 #define LINK_SPEED_AUTO 0x0 /* Auto selection */
2079 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
2080 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
2081 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
2082 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
2083 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
2084 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
2085 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
2086
2087 } INIT_LINK_VAR;
2088
2089 /* Structure for MB Command DOWN_LINK (06) */
2090
2091 typedef struct {
2092 uint32_t rsvd1;
2093 } DOWN_LINK_VAR;
2094
2095 /* Structure for MB Command CONFIG_LINK (07) */
2096
2097 typedef struct {
2098 #ifdef __BIG_ENDIAN_BITFIELD
2099 uint32_t cr:1;
2100 uint32_t ci:1;
2101 uint32_t cr_delay:6;
2102 uint32_t cr_count:8;
2103 uint32_t rsvd1:8;
2104 uint32_t MaxBBC:8;
2105 #else /* __LITTLE_ENDIAN_BITFIELD */
2106 uint32_t MaxBBC:8;
2107 uint32_t rsvd1:8;
2108 uint32_t cr_count:8;
2109 uint32_t cr_delay:6;
2110 uint32_t ci:1;
2111 uint32_t cr:1;
2112 #endif
2113
2114 uint32_t myId;
2115 uint32_t rsvd2;
2116 uint32_t edtov;
2117 uint32_t arbtov;
2118 uint32_t ratov;
2119 uint32_t rttov;
2120 uint32_t altov;
2121 uint32_t crtov;
2122 uint32_t citov;
2123 #ifdef __BIG_ENDIAN_BITFIELD
2124 uint32_t rrq_enable:1;
2125 uint32_t rrq_immed:1;
2126 uint32_t rsvd4:29;
2127 uint32_t ack0_enable:1;
2128 #else /* __LITTLE_ENDIAN_BITFIELD */
2129 uint32_t ack0_enable:1;
2130 uint32_t rsvd4:29;
2131 uint32_t rrq_immed:1;
2132 uint32_t rrq_enable:1;
2133 #endif
2134 } CONFIG_LINK;
2135
2136 /* Structure for MB Command PART_SLIM (08)
2137 * will be removed since SLI1 is no longer supported!
2138 */
2139 typedef struct {
2140 #ifdef __BIG_ENDIAN_BITFIELD
2141 uint16_t offCiocb;
2142 uint16_t numCiocb;
2143 uint16_t offRiocb;
2144 uint16_t numRiocb;
2145 #else /* __LITTLE_ENDIAN_BITFIELD */
2146 uint16_t numCiocb;
2147 uint16_t offCiocb;
2148 uint16_t numRiocb;
2149 uint16_t offRiocb;
2150 #endif
2151 } RING_DEF;
2152
2153 typedef struct {
2154 #ifdef __BIG_ENDIAN_BITFIELD
2155 uint32_t unused1:24;
2156 uint32_t numRing:8;
2157 #else /* __LITTLE_ENDIAN_BITFIELD */
2158 uint32_t numRing:8;
2159 uint32_t unused1:24;
2160 #endif
2161
2162 RING_DEF ringdef[4];
2163 uint32_t hbainit;
2164 } PART_SLIM_VAR;
2165
2166 /* Structure for MB Command CONFIG_RING (09) */
2167
2168 typedef struct {
2169 #ifdef __BIG_ENDIAN_BITFIELD
2170 uint32_t unused2:6;
2171 uint32_t recvSeq:1;
2172 uint32_t recvNotify:1;
2173 uint32_t numMask:8;
2174 uint32_t profile:8;
2175 uint32_t unused1:4;
2176 uint32_t ring:4;
2177 #else /* __LITTLE_ENDIAN_BITFIELD */
2178 uint32_t ring:4;
2179 uint32_t unused1:4;
2180 uint32_t profile:8;
2181 uint32_t numMask:8;
2182 uint32_t recvNotify:1;
2183 uint32_t recvSeq:1;
2184 uint32_t unused2:6;
2185 #endif
2186
2187 #ifdef __BIG_ENDIAN_BITFIELD
2188 uint16_t maxRespXchg;
2189 uint16_t maxOrigXchg;
2190 #else /* __LITTLE_ENDIAN_BITFIELD */
2191 uint16_t maxOrigXchg;
2192 uint16_t maxRespXchg;
2193 #endif
2194
2195 RR_REG rrRegs[6];
2196 } CONFIG_RING_VAR;
2197
2198 /* Structure for MB Command RESET_RING (10) */
2199
2200 typedef struct {
2201 uint32_t ring_no;
2202 } RESET_RING_VAR;
2203
2204 /* Structure for MB Command READ_CONFIG (11) */
2205
2206 typedef struct {
2207 #ifdef __BIG_ENDIAN_BITFIELD
2208 uint32_t cr:1;
2209 uint32_t ci:1;
2210 uint32_t cr_delay:6;
2211 uint32_t cr_count:8;
2212 uint32_t InitBBC:8;
2213 uint32_t MaxBBC:8;
2214 #else /* __LITTLE_ENDIAN_BITFIELD */
2215 uint32_t MaxBBC:8;
2216 uint32_t InitBBC:8;
2217 uint32_t cr_count:8;
2218 uint32_t cr_delay:6;
2219 uint32_t ci:1;
2220 uint32_t cr:1;
2221 #endif
2222
2223 #ifdef __BIG_ENDIAN_BITFIELD
2224 uint32_t topology:8;
2225 uint32_t myDid:24;
2226 #else /* __LITTLE_ENDIAN_BITFIELD */
2227 uint32_t myDid:24;
2228 uint32_t topology:8;
2229 #endif
2230
2231 /* Defines for topology (defined previously) */
2232 #ifdef __BIG_ENDIAN_BITFIELD
2233 uint32_t AR:1;
2234 uint32_t IR:1;
2235 uint32_t rsvd1:29;
2236 uint32_t ack0:1;
2237 #else /* __LITTLE_ENDIAN_BITFIELD */
2238 uint32_t ack0:1;
2239 uint32_t rsvd1:29;
2240 uint32_t IR:1;
2241 uint32_t AR:1;
2242 #endif
2243
2244 uint32_t edtov;
2245 uint32_t arbtov;
2246 uint32_t ratov;
2247 uint32_t rttov;
2248 uint32_t altov;
2249 uint32_t lmt;
2250 #define LMT_RESERVED 0x000 /* Not used */
2251 #define LMT_1Gb 0x004
2252 #define LMT_2Gb 0x008
2253 #define LMT_4Gb 0x040
2254 #define LMT_8Gb 0x080
2255 #define LMT_10Gb 0x100
2256 #define LMT_16Gb 0x200
2257 #define LMT_32Gb 0x400
2258 uint32_t rsvd2;
2259 uint32_t rsvd3;
2260 uint32_t max_xri;
2261 uint32_t max_iocb;
2262 uint32_t max_rpi;
2263 uint32_t avail_xri;
2264 uint32_t avail_iocb;
2265 uint32_t avail_rpi;
2266 uint32_t max_vpi;
2267 uint32_t rsvd4;
2268 uint32_t rsvd5;
2269 uint32_t avail_vpi;
2270 } READ_CONFIG_VAR;
2271
2272 /* Structure for MB Command READ_RCONFIG (12) */
2273
2274 typedef struct {
2275 #ifdef __BIG_ENDIAN_BITFIELD
2276 uint32_t rsvd2:7;
2277 uint32_t recvNotify:1;
2278 uint32_t numMask:8;
2279 uint32_t profile:8;
2280 uint32_t rsvd1:4;
2281 uint32_t ring:4;
2282 #else /* __LITTLE_ENDIAN_BITFIELD */
2283 uint32_t ring:4;
2284 uint32_t rsvd1:4;
2285 uint32_t profile:8;
2286 uint32_t numMask:8;
2287 uint32_t recvNotify:1;
2288 uint32_t rsvd2:7;
2289 #endif
2290
2291 #ifdef __BIG_ENDIAN_BITFIELD
2292 uint16_t maxResp;
2293 uint16_t maxOrig;
2294 #else /* __LITTLE_ENDIAN_BITFIELD */
2295 uint16_t maxOrig;
2296 uint16_t maxResp;
2297 #endif
2298
2299 RR_REG rrRegs[6];
2300
2301 #ifdef __BIG_ENDIAN_BITFIELD
2302 uint16_t cmdRingOffset;
2303 uint16_t cmdEntryCnt;
2304 uint16_t rspRingOffset;
2305 uint16_t rspEntryCnt;
2306 uint16_t nextCmdOffset;
2307 uint16_t rsvd3;
2308 uint16_t nextRspOffset;
2309 uint16_t rsvd4;
2310 #else /* __LITTLE_ENDIAN_BITFIELD */
2311 uint16_t cmdEntryCnt;
2312 uint16_t cmdRingOffset;
2313 uint16_t rspEntryCnt;
2314 uint16_t rspRingOffset;
2315 uint16_t rsvd3;
2316 uint16_t nextCmdOffset;
2317 uint16_t rsvd4;
2318 uint16_t nextRspOffset;
2319 #endif
2320 } READ_RCONF_VAR;
2321
2322 /* Structure for MB Command READ_SPARM (13) */
2323 /* Structure for MB Command READ_SPARM64 (0x8D) */
2324
2325 typedef struct {
2326 uint32_t rsvd1;
2327 uint32_t rsvd2;
2328 union {
2329 struct ulp_bde sp; /* This BDE points to struct serv_parm
2330 structure */
2331 struct ulp_bde64 sp64;
2332 } un;
2333 #ifdef __BIG_ENDIAN_BITFIELD
2334 uint16_t rsvd3;
2335 uint16_t vpi;
2336 #else /* __LITTLE_ENDIAN_BITFIELD */
2337 uint16_t vpi;
2338 uint16_t rsvd3;
2339 #endif
2340 } READ_SPARM_VAR;
2341
2342 /* Structure for MB Command READ_STATUS (14) */
2343
2344 typedef struct {
2345 #ifdef __BIG_ENDIAN_BITFIELD
2346 uint32_t rsvd1:31;
2347 uint32_t clrCounters:1;
2348 uint16_t activeXriCnt;
2349 uint16_t activeRpiCnt;
2350 #else /* __LITTLE_ENDIAN_BITFIELD */
2351 uint32_t clrCounters:1;
2352 uint32_t rsvd1:31;
2353 uint16_t activeRpiCnt;
2354 uint16_t activeXriCnt;
2355 #endif
2356
2357 uint32_t xmitByteCnt;
2358 uint32_t rcvByteCnt;
2359 uint32_t xmitFrameCnt;
2360 uint32_t rcvFrameCnt;
2361 uint32_t xmitSeqCnt;
2362 uint32_t rcvSeqCnt;
2363 uint32_t totalOrigExchanges;
2364 uint32_t totalRespExchanges;
2365 uint32_t rcvPbsyCnt;
2366 uint32_t rcvFbsyCnt;
2367 } READ_STATUS_VAR;
2368
2369 /* Structure for MB Command READ_RPI (15) */
2370 /* Structure for MB Command READ_RPI64 (0x8F) */
2371
2372 typedef struct {
2373 #ifdef __BIG_ENDIAN_BITFIELD
2374 uint16_t nextRpi;
2375 uint16_t reqRpi;
2376 uint32_t rsvd2:8;
2377 uint32_t DID:24;
2378 #else /* __LITTLE_ENDIAN_BITFIELD */
2379 uint16_t reqRpi;
2380 uint16_t nextRpi;
2381 uint32_t DID:24;
2382 uint32_t rsvd2:8;
2383 #endif
2384
2385 union {
2386 struct ulp_bde sp;
2387 struct ulp_bde64 sp64;
2388 } un;
2389
2390 } READ_RPI_VAR;
2391
2392 /* Structure for MB Command READ_XRI (16) */
2393
2394 typedef struct {
2395 #ifdef __BIG_ENDIAN_BITFIELD
2396 uint16_t nextXri;
2397 uint16_t reqXri;
2398 uint16_t rsvd1;
2399 uint16_t rpi;
2400 uint32_t rsvd2:8;
2401 uint32_t DID:24;
2402 uint32_t rsvd3:8;
2403 uint32_t SID:24;
2404 uint32_t rsvd4;
2405 uint8_t seqId;
2406 uint8_t rsvd5;
2407 uint16_t seqCount;
2408 uint16_t oxId;
2409 uint16_t rxId;
2410 uint32_t rsvd6:30;
2411 uint32_t si:1;
2412 uint32_t exchOrig:1;
2413 #else /* __LITTLE_ENDIAN_BITFIELD */
2414 uint16_t reqXri;
2415 uint16_t nextXri;
2416 uint16_t rpi;
2417 uint16_t rsvd1;
2418 uint32_t DID:24;
2419 uint32_t rsvd2:8;
2420 uint32_t SID:24;
2421 uint32_t rsvd3:8;
2422 uint32_t rsvd4;
2423 uint16_t seqCount;
2424 uint8_t rsvd5;
2425 uint8_t seqId;
2426 uint16_t rxId;
2427 uint16_t oxId;
2428 uint32_t exchOrig:1;
2429 uint32_t si:1;
2430 uint32_t rsvd6:30;
2431 #endif
2432 } READ_XRI_VAR;
2433
2434 /* Structure for MB Command READ_REV (17) */
2435
2436 typedef struct {
2437 #ifdef __BIG_ENDIAN_BITFIELD
2438 uint32_t cv:1;
2439 uint32_t rr:1;
2440 uint32_t rsvd2:2;
2441 uint32_t v3req:1;
2442 uint32_t v3rsp:1;
2443 uint32_t rsvd1:25;
2444 uint32_t rv:1;
2445 #else /* __LITTLE_ENDIAN_BITFIELD */
2446 uint32_t rv:1;
2447 uint32_t rsvd1:25;
2448 uint32_t v3rsp:1;
2449 uint32_t v3req:1;
2450 uint32_t rsvd2:2;
2451 uint32_t rr:1;
2452 uint32_t cv:1;
2453 #endif
2454
2455 uint32_t biuRev;
2456 uint32_t smRev;
2457 union {
2458 uint32_t smFwRev;
2459 struct {
2460 #ifdef __BIG_ENDIAN_BITFIELD
2461 uint8_t ProgType;
2462 uint8_t ProgId;
2463 uint16_t ProgVer:4;
2464 uint16_t ProgRev:4;
2465 uint16_t ProgFixLvl:2;
2466 uint16_t ProgDistType:2;
2467 uint16_t DistCnt:4;
2468 #else /* __LITTLE_ENDIAN_BITFIELD */
2469 uint16_t DistCnt:4;
2470 uint16_t ProgDistType:2;
2471 uint16_t ProgFixLvl:2;
2472 uint16_t ProgRev:4;
2473 uint16_t ProgVer:4;
2474 uint8_t ProgId;
2475 uint8_t ProgType;
2476 #endif
2477
2478 } b;
2479 } un;
2480 uint32_t endecRev;
2481 #ifdef __BIG_ENDIAN_BITFIELD
2482 uint8_t feaLevelHigh;
2483 uint8_t feaLevelLow;
2484 uint8_t fcphHigh;
2485 uint8_t fcphLow;
2486 #else /* __LITTLE_ENDIAN_BITFIELD */
2487 uint8_t fcphLow;
2488 uint8_t fcphHigh;
2489 uint8_t feaLevelLow;
2490 uint8_t feaLevelHigh;
2491 #endif
2492
2493 uint32_t postKernRev;
2494 uint32_t opFwRev;
2495 uint8_t opFwName[16];
2496 uint32_t sli1FwRev;
2497 uint8_t sli1FwName[16];
2498 uint32_t sli2FwRev;
2499 uint8_t sli2FwName[16];
2500 uint32_t sli3Feat;
2501 uint32_t RandomData[6];
2502 } READ_REV_VAR;
2503
2504 /* Structure for MB Command READ_LINK_STAT (18) */
2505
2506 typedef struct {
2507 uint32_t rsvd1;
2508 uint32_t linkFailureCnt;
2509 uint32_t lossSyncCnt;
2510
2511 uint32_t lossSignalCnt;
2512 uint32_t primSeqErrCnt;
2513 uint32_t invalidXmitWord;
2514 uint32_t crcCnt;
2515 uint32_t primSeqTimeout;
2516 uint32_t elasticOverrun;
2517 uint32_t arbTimeout;
2518 } READ_LNK_VAR;
2519
2520 /* Structure for MB Command REG_LOGIN (19) */
2521 /* Structure for MB Command REG_LOGIN64 (0x93) */
2522
2523 typedef struct {
2524 #ifdef __BIG_ENDIAN_BITFIELD
2525 uint16_t rsvd1;
2526 uint16_t rpi;
2527 uint32_t rsvd2:8;
2528 uint32_t did:24;
2529 #else /* __LITTLE_ENDIAN_BITFIELD */
2530 uint16_t rpi;
2531 uint16_t rsvd1;
2532 uint32_t did:24;
2533 uint32_t rsvd2:8;
2534 #endif
2535
2536 union {
2537 struct ulp_bde sp;
2538 struct ulp_bde64 sp64;
2539 } un;
2540
2541 #ifdef __BIG_ENDIAN_BITFIELD
2542 uint16_t rsvd6;
2543 uint16_t vpi;
2544 #else /* __LITTLE_ENDIAN_BITFIELD */
2545 uint16_t vpi;
2546 uint16_t rsvd6;
2547 #endif
2548
2549 } REG_LOGIN_VAR;
2550
2551 /* Word 30 contents for REG_LOGIN */
2552 typedef union {
2553 struct {
2554 #ifdef __BIG_ENDIAN_BITFIELD
2555 uint16_t rsvd1:12;
2556 uint16_t wd30_class:4;
2557 uint16_t xri;
2558 #else /* __LITTLE_ENDIAN_BITFIELD */
2559 uint16_t xri;
2560 uint16_t wd30_class:4;
2561 uint16_t rsvd1:12;
2562 #endif
2563 } f;
2564 uint32_t word;
2565 } REG_WD30;
2566
2567 /* Structure for MB Command UNREG_LOGIN (20) */
2568
2569 typedef struct {
2570 #ifdef __BIG_ENDIAN_BITFIELD
2571 uint16_t rsvd1;
2572 uint16_t rpi;
2573 uint32_t rsvd2;
2574 uint32_t rsvd3;
2575 uint32_t rsvd4;
2576 uint32_t rsvd5;
2577 uint16_t rsvd6;
2578 uint16_t vpi;
2579 #else /* __LITTLE_ENDIAN_BITFIELD */
2580 uint16_t rpi;
2581 uint16_t rsvd1;
2582 uint32_t rsvd2;
2583 uint32_t rsvd3;
2584 uint32_t rsvd4;
2585 uint32_t rsvd5;
2586 uint16_t vpi;
2587 uint16_t rsvd6;
2588 #endif
2589 } UNREG_LOGIN_VAR;
2590
2591 /* Structure for MB Command REG_VPI (0x96) */
2592 typedef struct {
2593 #ifdef __BIG_ENDIAN_BITFIELD
2594 uint32_t rsvd1;
2595 uint32_t rsvd2:7;
2596 uint32_t upd:1;
2597 uint32_t sid:24;
2598 uint32_t wwn[2];
2599 uint32_t rsvd5;
2600 uint16_t vfi;
2601 uint16_t vpi;
2602 #else /* __LITTLE_ENDIAN */
2603 uint32_t rsvd1;
2604 uint32_t sid:24;
2605 uint32_t upd:1;
2606 uint32_t rsvd2:7;
2607 uint32_t wwn[2];
2608 uint32_t rsvd5;
2609 uint16_t vpi;
2610 uint16_t vfi;
2611 #endif
2612 } REG_VPI_VAR;
2613
2614 /* Structure for MB Command UNREG_VPI (0x97) */
2615 typedef struct {
2616 uint32_t rsvd1;
2617 #ifdef __BIG_ENDIAN_BITFIELD
2618 uint16_t rsvd2;
2619 uint16_t sli4_vpi;
2620 #else /* __LITTLE_ENDIAN */
2621 uint16_t sli4_vpi;
2622 uint16_t rsvd2;
2623 #endif
2624 uint32_t rsvd3;
2625 uint32_t rsvd4;
2626 uint32_t rsvd5;
2627 #ifdef __BIG_ENDIAN_BITFIELD
2628 uint16_t rsvd6;
2629 uint16_t vpi;
2630 #else /* __LITTLE_ENDIAN */
2631 uint16_t vpi;
2632 uint16_t rsvd6;
2633 #endif
2634 } UNREG_VPI_VAR;
2635
2636 /* Structure for MB Command UNREG_D_ID (0x23) */
2637
2638 typedef struct {
2639 uint32_t did;
2640 uint32_t rsvd2;
2641 uint32_t rsvd3;
2642 uint32_t rsvd4;
2643 uint32_t rsvd5;
2644 #ifdef __BIG_ENDIAN_BITFIELD
2645 uint16_t rsvd6;
2646 uint16_t vpi;
2647 #else
2648 uint16_t vpi;
2649 uint16_t rsvd6;
2650 #endif
2651 } UNREG_D_ID_VAR;
2652
2653 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2654 struct lpfc_mbx_read_top {
2655 uint32_t eventTag; /* Event tag */
2656 uint32_t word2;
2657 #define lpfc_mbx_read_top_fa_SHIFT 12
2658 #define lpfc_mbx_read_top_fa_MASK 0x00000001
2659 #define lpfc_mbx_read_top_fa_WORD word2
2660 #define lpfc_mbx_read_top_mm_SHIFT 11
2661 #define lpfc_mbx_read_top_mm_MASK 0x00000001
2662 #define lpfc_mbx_read_top_mm_WORD word2
2663 #define lpfc_mbx_read_top_pb_SHIFT 9
2664 #define lpfc_mbx_read_top_pb_MASK 0X00000001
2665 #define lpfc_mbx_read_top_pb_WORD word2
2666 #define lpfc_mbx_read_top_il_SHIFT 8
2667 #define lpfc_mbx_read_top_il_MASK 0x00000001
2668 #define lpfc_mbx_read_top_il_WORD word2
2669 #define lpfc_mbx_read_top_att_type_SHIFT 0
2670 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2671 #define lpfc_mbx_read_top_att_type_WORD word2
2672 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2673 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2674 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2675 uint32_t word3;
2676 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2677 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2678 #define lpfc_mbx_read_top_alpa_granted_WORD word3
2679 #define lpfc_mbx_read_top_lip_alps_SHIFT 16
2680 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2681 #define lpfc_mbx_read_top_lip_alps_WORD word3
2682 #define lpfc_mbx_read_top_lip_type_SHIFT 8
2683 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2684 #define lpfc_mbx_read_top_lip_type_WORD word3
2685 #define lpfc_mbx_read_top_topology_SHIFT 0
2686 #define lpfc_mbx_read_top_topology_MASK 0x000000FF
2687 #define lpfc_mbx_read_top_topology_WORD word3
2688 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2689 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2690 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2691 /* store the LILP AL_PA position map into */
2692 struct ulp_bde64 lilpBde64;
2693 #define LPFC_ALPA_MAP_SIZE 128
2694 uint32_t word7;
2695 #define lpfc_mbx_read_top_ld_lu_SHIFT 31
2696 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2697 #define lpfc_mbx_read_top_ld_lu_WORD word7
2698 #define lpfc_mbx_read_top_ld_tf_SHIFT 30
2699 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2700 #define lpfc_mbx_read_top_ld_tf_WORD word7
2701 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2702 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2703 #define lpfc_mbx_read_top_ld_link_spd_WORD word7
2704 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2705 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2706 #define lpfc_mbx_read_top_ld_nl_port_WORD word7
2707 #define lpfc_mbx_read_top_ld_tx_SHIFT 2
2708 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2709 #define lpfc_mbx_read_top_ld_tx_WORD word7
2710 #define lpfc_mbx_read_top_ld_rx_SHIFT 0
2711 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2712 #define lpfc_mbx_read_top_ld_rx_WORD word7
2713 uint32_t word8;
2714 #define lpfc_mbx_read_top_lu_SHIFT 31
2715 #define lpfc_mbx_read_top_lu_MASK 0x00000001
2716 #define lpfc_mbx_read_top_lu_WORD word8
2717 #define lpfc_mbx_read_top_tf_SHIFT 30
2718 #define lpfc_mbx_read_top_tf_MASK 0x00000001
2719 #define lpfc_mbx_read_top_tf_WORD word8
2720 #define lpfc_mbx_read_top_link_spd_SHIFT 8
2721 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2722 #define lpfc_mbx_read_top_link_spd_WORD word8
2723 #define lpfc_mbx_read_top_nl_port_SHIFT 4
2724 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2725 #define lpfc_mbx_read_top_nl_port_WORD word8
2726 #define lpfc_mbx_read_top_tx_SHIFT 2
2727 #define lpfc_mbx_read_top_tx_MASK 0x00000003
2728 #define lpfc_mbx_read_top_tx_WORD word8
2729 #define lpfc_mbx_read_top_rx_SHIFT 0
2730 #define lpfc_mbx_read_top_rx_MASK 0x00000003
2731 #define lpfc_mbx_read_top_rx_WORD word8
2732 #define LPFC_LINK_SPEED_UNKNOWN 0x0
2733 #define LPFC_LINK_SPEED_1GHZ 0x04
2734 #define LPFC_LINK_SPEED_2GHZ 0x08
2735 #define LPFC_LINK_SPEED_4GHZ 0x10
2736 #define LPFC_LINK_SPEED_8GHZ 0x20
2737 #define LPFC_LINK_SPEED_10GHZ 0x40
2738 #define LPFC_LINK_SPEED_16GHZ 0x80
2739 #define LPFC_LINK_SPEED_32GHZ 0x90
2740 };
2741
2742 /* Structure for MB Command CLEAR_LA (22) */
2743
2744 typedef struct {
2745 uint32_t eventTag; /* Event tag */
2746 uint32_t rsvd1;
2747 } CLEAR_LA_VAR;
2748
2749 /* Structure for MB Command DUMP */
2750
2751 typedef struct {
2752 #ifdef __BIG_ENDIAN_BITFIELD
2753 uint32_t rsvd:25;
2754 uint32_t ra:1;
2755 uint32_t co:1;
2756 uint32_t cv:1;
2757 uint32_t type:4;
2758 uint32_t entry_index:16;
2759 uint32_t region_id:16;
2760 #else /* __LITTLE_ENDIAN_BITFIELD */
2761 uint32_t type:4;
2762 uint32_t cv:1;
2763 uint32_t co:1;
2764 uint32_t ra:1;
2765 uint32_t rsvd:25;
2766 uint32_t region_id:16;
2767 uint32_t entry_index:16;
2768 #endif
2769
2770 uint32_t sli4_length;
2771 uint32_t word_cnt;
2772 uint32_t resp_offset;
2773 } DUMP_VAR;
2774
2775 #define DMP_MEM_REG 0x1
2776 #define DMP_NV_PARAMS 0x2
2777 #define DMP_LMSD 0x3 /* Link Module Serial Data */
2778 #define DMP_WELL_KNOWN 0x4
2779
2780 #define DMP_REGION_VPD 0xe
2781 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2782 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2783 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2784
2785 #define DMP_REGION_VPORT 0x16 /* VPort info region */
2786 #define DMP_VPORT_REGION_SIZE 0x200
2787 #define DMP_MBOX_OFFSET_WORD 0x5
2788
2789 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
2790 #define DMP_RGN23_SIZE 0x400
2791
2792 #define WAKE_UP_PARMS_REGION_ID 4
2793 #define WAKE_UP_PARMS_WORD_SIZE 15
2794
2795 struct vport_rec {
2796 uint8_t wwpn[8];
2797 uint8_t wwnn[8];
2798 };
2799
2800 #define VPORT_INFO_SIG 0x32324752
2801 #define VPORT_INFO_REV_MASK 0xff
2802 #define VPORT_INFO_REV 0x1
2803 #define MAX_STATIC_VPORT_COUNT 16
2804 struct static_vport_info {
2805 uint32_t signature;
2806 uint32_t rev;
2807 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
2808 uint32_t resvd[66];
2809 };
2810
2811 /* Option rom version structure */
2812 struct prog_id {
2813 #ifdef __BIG_ENDIAN_BITFIELD
2814 uint8_t type;
2815 uint8_t id;
2816 uint32_t ver:4; /* Major Version */
2817 uint32_t rev:4; /* Revision */
2818 uint32_t lev:2; /* Level */
2819 uint32_t dist:2; /* Dist Type */
2820 uint32_t num:4; /* number after dist type */
2821 #else /* __LITTLE_ENDIAN_BITFIELD */
2822 uint32_t num:4; /* number after dist type */
2823 uint32_t dist:2; /* Dist Type */
2824 uint32_t lev:2; /* Level */
2825 uint32_t rev:4; /* Revision */
2826 uint32_t ver:4; /* Major Version */
2827 uint8_t id;
2828 uint8_t type;
2829 #endif
2830 };
2831
2832 /* Structure for MB Command UPDATE_CFG (0x1B) */
2833
2834 struct update_cfg_var {
2835 #ifdef __BIG_ENDIAN_BITFIELD
2836 uint32_t rsvd2:16;
2837 uint32_t type:8;
2838 uint32_t rsvd:1;
2839 uint32_t ra:1;
2840 uint32_t co:1;
2841 uint32_t cv:1;
2842 uint32_t req:4;
2843 uint32_t entry_length:16;
2844 uint32_t region_id:16;
2845 #else /* __LITTLE_ENDIAN_BITFIELD */
2846 uint32_t req:4;
2847 uint32_t cv:1;
2848 uint32_t co:1;
2849 uint32_t ra:1;
2850 uint32_t rsvd:1;
2851 uint32_t type:8;
2852 uint32_t rsvd2:16;
2853 uint32_t region_id:16;
2854 uint32_t entry_length:16;
2855 #endif
2856
2857 uint32_t resp_info;
2858 uint32_t byte_cnt;
2859 uint32_t data_offset;
2860 };
2861
2862 struct hbq_mask {
2863 #ifdef __BIG_ENDIAN_BITFIELD
2864 uint8_t tmatch;
2865 uint8_t tmask;
2866 uint8_t rctlmatch;
2867 uint8_t rctlmask;
2868 #else /* __LITTLE_ENDIAN */
2869 uint8_t rctlmask;
2870 uint8_t rctlmatch;
2871 uint8_t tmask;
2872 uint8_t tmatch;
2873 #endif
2874 };
2875
2876
2877 /* Structure for MB Command CONFIG_HBQ (7c) */
2878
2879 struct config_hbq_var {
2880 #ifdef __BIG_ENDIAN_BITFIELD
2881 uint32_t rsvd1 :7;
2882 uint32_t recvNotify :1; /* Receive Notification */
2883 uint32_t numMask :8; /* # Mask Entries */
2884 uint32_t profile :8; /* Selection Profile */
2885 uint32_t rsvd2 :8;
2886 #else /* __LITTLE_ENDIAN */
2887 uint32_t rsvd2 :8;
2888 uint32_t profile :8; /* Selection Profile */
2889 uint32_t numMask :8; /* # Mask Entries */
2890 uint32_t recvNotify :1; /* Receive Notification */
2891 uint32_t rsvd1 :7;
2892 #endif
2893
2894 #ifdef __BIG_ENDIAN_BITFIELD
2895 uint32_t hbqId :16;
2896 uint32_t rsvd3 :12;
2897 uint32_t ringMask :4;
2898 #else /* __LITTLE_ENDIAN */
2899 uint32_t ringMask :4;
2900 uint32_t rsvd3 :12;
2901 uint32_t hbqId :16;
2902 #endif
2903
2904 #ifdef __BIG_ENDIAN_BITFIELD
2905 uint32_t entry_count :16;
2906 uint32_t rsvd4 :8;
2907 uint32_t headerLen :8;
2908 #else /* __LITTLE_ENDIAN */
2909 uint32_t headerLen :8;
2910 uint32_t rsvd4 :8;
2911 uint32_t entry_count :16;
2912 #endif
2913
2914 uint32_t hbqaddrLow;
2915 uint32_t hbqaddrHigh;
2916
2917 #ifdef __BIG_ENDIAN_BITFIELD
2918 uint32_t rsvd5 :31;
2919 uint32_t logEntry :1;
2920 #else /* __LITTLE_ENDIAN */
2921 uint32_t logEntry :1;
2922 uint32_t rsvd5 :31;
2923 #endif
2924
2925 uint32_t rsvd6; /* w7 */
2926 uint32_t rsvd7; /* w8 */
2927 uint32_t rsvd8; /* w9 */
2928
2929 struct hbq_mask hbqMasks[6];
2930
2931
2932 union {
2933 uint32_t allprofiles[12];
2934
2935 struct {
2936 #ifdef __BIG_ENDIAN_BITFIELD
2937 uint32_t seqlenoff :16;
2938 uint32_t maxlen :16;
2939 #else /* __LITTLE_ENDIAN */
2940 uint32_t maxlen :16;
2941 uint32_t seqlenoff :16;
2942 #endif
2943 #ifdef __BIG_ENDIAN_BITFIELD
2944 uint32_t rsvd1 :28;
2945 uint32_t seqlenbcnt :4;
2946 #else /* __LITTLE_ENDIAN */
2947 uint32_t seqlenbcnt :4;
2948 uint32_t rsvd1 :28;
2949 #endif
2950 uint32_t rsvd[10];
2951 } profile2;
2952
2953 struct {
2954 #ifdef __BIG_ENDIAN_BITFIELD
2955 uint32_t seqlenoff :16;
2956 uint32_t maxlen :16;
2957 #else /* __LITTLE_ENDIAN */
2958 uint32_t maxlen :16;
2959 uint32_t seqlenoff :16;
2960 #endif
2961 #ifdef __BIG_ENDIAN_BITFIELD
2962 uint32_t cmdcodeoff :28;
2963 uint32_t rsvd1 :12;
2964 uint32_t seqlenbcnt :4;
2965 #else /* __LITTLE_ENDIAN */
2966 uint32_t seqlenbcnt :4;
2967 uint32_t rsvd1 :12;
2968 uint32_t cmdcodeoff :28;
2969 #endif
2970 uint32_t cmdmatch[8];
2971
2972 uint32_t rsvd[2];
2973 } profile3;
2974
2975 struct {
2976 #ifdef __BIG_ENDIAN_BITFIELD
2977 uint32_t seqlenoff :16;
2978 uint32_t maxlen :16;
2979 #else /* __LITTLE_ENDIAN */
2980 uint32_t maxlen :16;
2981 uint32_t seqlenoff :16;
2982 #endif
2983 #ifdef __BIG_ENDIAN_BITFIELD
2984 uint32_t cmdcodeoff :28;
2985 uint32_t rsvd1 :12;
2986 uint32_t seqlenbcnt :4;
2987 #else /* __LITTLE_ENDIAN */
2988 uint32_t seqlenbcnt :4;
2989 uint32_t rsvd1 :12;
2990 uint32_t cmdcodeoff :28;
2991 #endif
2992 uint32_t cmdmatch[8];
2993
2994 uint32_t rsvd[2];
2995 } profile5;
2996
2997 } profiles;
2998
2999 };
3000
3001
3002
3003 /* Structure for MB Command CONFIG_PORT (0x88) */
3004 typedef struct {
3005 #ifdef __BIG_ENDIAN_BITFIELD
3006 uint32_t cBE : 1;
3007 uint32_t cET : 1;
3008 uint32_t cHpcb : 1;
3009 uint32_t cMA : 1;
3010 uint32_t sli_mode : 4;
3011 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3012 * config block */
3013 #else /* __LITTLE_ENDIAN */
3014 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3015 * config block */
3016 uint32_t sli_mode : 4;
3017 uint32_t cMA : 1;
3018 uint32_t cHpcb : 1;
3019 uint32_t cET : 1;
3020 uint32_t cBE : 1;
3021 #endif
3022
3023 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
3024 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
3025 uint32_t hbainit[5];
3026 #ifdef __BIG_ENDIAN_BITFIELD
3027 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3028 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3029 #else /* __LITTLE_ENDIAN */
3030 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3031 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3032 #endif
3033
3034 #ifdef __BIG_ENDIAN_BITFIELD
3035 uint32_t rsvd1 : 19; /* Reserved */
3036 uint32_t cdss : 1; /* Configure Data Security SLI */
3037 uint32_t casabt : 1; /* Configure async abts status notice */
3038 uint32_t rsvd2 : 2; /* Reserved */
3039 uint32_t cbg : 1; /* Configure BlockGuard */
3040 uint32_t cmv : 1; /* Configure Max VPIs */
3041 uint32_t ccrp : 1; /* Config Command Ring Polling */
3042 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3043 uint32_t chbs : 1; /* Cofigure Host Backing store */
3044 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3045 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3046 uint32_t cmx : 1; /* Configure Max XRIs */
3047 uint32_t cmr : 1; /* Configure Max RPIs */
3048 #else /* __LITTLE_ENDIAN */
3049 uint32_t cmr : 1; /* Configure Max RPIs */
3050 uint32_t cmx : 1; /* Configure Max XRIs */
3051 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3052 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3053 uint32_t chbs : 1; /* Cofigure Host Backing store */
3054 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3055 uint32_t ccrp : 1; /* Config Command Ring Polling */
3056 uint32_t cmv : 1; /* Configure Max VPIs */
3057 uint32_t cbg : 1; /* Configure BlockGuard */
3058 uint32_t rsvd2 : 2; /* Reserved */
3059 uint32_t casabt : 1; /* Configure async abts status notice */
3060 uint32_t cdss : 1; /* Configure Data Security SLI */
3061 uint32_t rsvd1 : 19; /* Reserved */
3062 #endif
3063 #ifdef __BIG_ENDIAN_BITFIELD
3064 uint32_t rsvd3 : 19; /* Reserved */
3065 uint32_t gdss : 1; /* Configure Data Security SLI */
3066 uint32_t gasabt : 1; /* Grant async abts status notice */
3067 uint32_t rsvd4 : 2; /* Reserved */
3068 uint32_t gbg : 1; /* Grant BlockGuard */
3069 uint32_t gmv : 1; /* Grant Max VPIs */
3070 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3071 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3072 uint32_t ghbs : 1; /* Grant Host Backing Store */
3073 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3074 uint32_t gerbm : 1; /* Grant ERBM Request */
3075 uint32_t gmx : 1; /* Grant Max XRIs */
3076 uint32_t gmr : 1; /* Grant Max RPIs */
3077 #else /* __LITTLE_ENDIAN */
3078 uint32_t gmr : 1; /* Grant Max RPIs */
3079 uint32_t gmx : 1; /* Grant Max XRIs */
3080 uint32_t gerbm : 1; /* Grant ERBM Request */
3081 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3082 uint32_t ghbs : 1; /* Grant Host Backing Store */
3083 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3084 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3085 uint32_t gmv : 1; /* Grant Max VPIs */
3086 uint32_t gbg : 1; /* Grant BlockGuard */
3087 uint32_t rsvd4 : 2; /* Reserved */
3088 uint32_t gasabt : 1; /* Grant async abts status notice */
3089 uint32_t gdss : 1; /* Configure Data Security SLI */
3090 uint32_t rsvd3 : 19; /* Reserved */
3091 #endif
3092
3093 #ifdef __BIG_ENDIAN_BITFIELD
3094 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3095 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3096 #else /* __LITTLE_ENDIAN */
3097 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3098 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3099 #endif
3100
3101 #ifdef __BIG_ENDIAN_BITFIELD
3102 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3103 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3104 #else /* __LITTLE_ENDIAN */
3105 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3106 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3107 #endif
3108
3109 uint32_t rsvd6; /* Reserved */
3110
3111 #ifdef __BIG_ENDIAN_BITFIELD
3112 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3113 uint32_t fips_level : 4; /* FIPS Level */
3114 uint32_t sec_err : 9; /* security crypto error */
3115 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3116 #else /* __LITTLE_ENDIAN */
3117 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3118 uint32_t sec_err : 9; /* security crypto error */
3119 uint32_t fips_level : 4; /* FIPS Level */
3120 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3121 #endif
3122
3123 } CONFIG_PORT_VAR;
3124
3125 /* Structure for MB Command CONFIG_MSI (0x30) */
3126 struct config_msi_var {
3127 #ifdef __BIG_ENDIAN_BITFIELD
3128 uint32_t dfltMsgNum:8; /* Default message number */
3129 uint32_t rsvd1:11; /* Reserved */
3130 uint32_t NID:5; /* Number of secondary attention IDs */
3131 uint32_t rsvd2:5; /* Reserved */
3132 uint32_t dfltPresent:1; /* Default message number present */
3133 uint32_t addFlag:1; /* Add association flag */
3134 uint32_t reportFlag:1; /* Report association flag */
3135 #else /* __LITTLE_ENDIAN_BITFIELD */
3136 uint32_t reportFlag:1; /* Report association flag */
3137 uint32_t addFlag:1; /* Add association flag */
3138 uint32_t dfltPresent:1; /* Default message number present */
3139 uint32_t rsvd2:5; /* Reserved */
3140 uint32_t NID:5; /* Number of secondary attention IDs */
3141 uint32_t rsvd1:11; /* Reserved */
3142 uint32_t dfltMsgNum:8; /* Default message number */
3143 #endif
3144 uint32_t attentionConditions[2];
3145 uint8_t attentionId[16];
3146 uint8_t messageNumberByHA[64];
3147 uint8_t messageNumberByID[16];
3148 uint32_t autoClearHA[2];
3149 #ifdef __BIG_ENDIAN_BITFIELD
3150 uint32_t rsvd3:16;
3151 uint32_t autoClearID:16;
3152 #else /* __LITTLE_ENDIAN_BITFIELD */
3153 uint32_t autoClearID:16;
3154 uint32_t rsvd3:16;
3155 #endif
3156 uint32_t rsvd4;
3157 };
3158
3159 /* SLI-2 Port Control Block */
3160
3161 /* SLIM POINTER */
3162 #define SLIMOFF 0x30 /* WORD */
3163
3164 typedef struct _SLI2_RDSC {
3165 uint32_t cmdEntries;
3166 uint32_t cmdAddrLow;
3167 uint32_t cmdAddrHigh;
3168
3169 uint32_t rspEntries;
3170 uint32_t rspAddrLow;
3171 uint32_t rspAddrHigh;
3172 } SLI2_RDSC;
3173
3174 typedef struct _PCB {
3175 #ifdef __BIG_ENDIAN_BITFIELD
3176 uint32_t type:8;
3177 #define TYPE_NATIVE_SLI2 0x01
3178 uint32_t feature:8;
3179 #define FEATURE_INITIAL_SLI2 0x01
3180 uint32_t rsvd:12;
3181 uint32_t maxRing:4;
3182 #else /* __LITTLE_ENDIAN_BITFIELD */
3183 uint32_t maxRing:4;
3184 uint32_t rsvd:12;
3185 uint32_t feature:8;
3186 #define FEATURE_INITIAL_SLI2 0x01
3187 uint32_t type:8;
3188 #define TYPE_NATIVE_SLI2 0x01
3189 #endif
3190
3191 uint32_t mailBoxSize;
3192 uint32_t mbAddrLow;
3193 uint32_t mbAddrHigh;
3194
3195 uint32_t hgpAddrLow;
3196 uint32_t hgpAddrHigh;
3197
3198 uint32_t pgpAddrLow;
3199 uint32_t pgpAddrHigh;
3200 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3201 } PCB_t;
3202
3203 /* NEW_FEATURE */
3204 typedef struct {
3205 #ifdef __BIG_ENDIAN_BITFIELD
3206 uint32_t rsvd0:27;
3207 uint32_t discardFarp:1;
3208 uint32_t IPEnable:1;
3209 uint32_t nodeName:1;
3210 uint32_t portName:1;
3211 uint32_t filterEnable:1;
3212 #else /* __LITTLE_ENDIAN_BITFIELD */
3213 uint32_t filterEnable:1;
3214 uint32_t portName:1;
3215 uint32_t nodeName:1;
3216 uint32_t IPEnable:1;
3217 uint32_t discardFarp:1;
3218 uint32_t rsvd:27;
3219 #endif
3220
3221 uint8_t portname[8]; /* Used to be struct lpfc_name */
3222 uint8_t nodename[8];
3223 uint32_t rsvd1;
3224 uint32_t rsvd2;
3225 uint32_t rsvd3;
3226 uint32_t IPAddress;
3227 } CONFIG_FARP_VAR;
3228
3229 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3230
3231 typedef struct {
3232 #ifdef __BIG_ENDIAN_BITFIELD
3233 uint32_t rsvd:30;
3234 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3235 #else /* __LITTLE_ENDIAN */
3236 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3237 uint32_t rsvd:30;
3238 #endif
3239 } ASYNCEVT_ENABLE_VAR;
3240
3241 /* Union of all Mailbox Command types */
3242 #define MAILBOX_CMD_WSIZE 32
3243 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3244 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3245 #define MAILBOX_EXT_WSIZE 512
3246 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3247 #define MAILBOX_HBA_EXT_OFFSET 0x100
3248 /* max mbox xmit size is a page size for sysfs IO operations */
3249 #define MAILBOX_SYSFS_MAX 4096
3250
3251 typedef union {
3252 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3253 * feature/max ring number
3254 */
3255 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3256 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3257 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3258 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3259 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3260 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3261 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3262 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3263 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3264 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3265 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3266 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3267 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3268 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3269 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3270 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3271 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3272 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3273 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3274 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3275 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3276 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3277 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3278 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3279 * NEW_FEATURE
3280 */
3281 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3282 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3283 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3284 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3285 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3286 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3287 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3288 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3289 * (READ_EVENT_LOG)
3290 */
3291 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3292 } MAILVARIANTS;
3293
3294 /*
3295 * SLI-2 specific structures
3296 */
3297
3298 struct lpfc_hgp {
3299 __le32 cmdPutInx;
3300 __le32 rspGetInx;
3301 };
3302
3303 struct lpfc_pgp {
3304 __le32 cmdGetInx;
3305 __le32 rspPutInx;
3306 };
3307
3308 struct sli2_desc {
3309 uint32_t unused1[16];
3310 struct lpfc_hgp host[MAX_SLI3_RINGS];
3311 struct lpfc_pgp port[MAX_SLI3_RINGS];
3312 };
3313
3314 struct sli3_desc {
3315 struct lpfc_hgp host[MAX_SLI3_RINGS];
3316 uint32_t reserved[8];
3317 uint32_t hbq_put[16];
3318 };
3319
3320 struct sli3_pgp {
3321 struct lpfc_pgp port[MAX_SLI3_RINGS];
3322 uint32_t hbq_get[16];
3323 };
3324
3325 union sli_var {
3326 struct sli2_desc s2;
3327 struct sli3_desc s3;
3328 struct sli3_pgp s3_pgp;
3329 };
3330
3331 typedef struct {
3332 #ifdef __BIG_ENDIAN_BITFIELD
3333 uint16_t mbxStatus;
3334 uint8_t mbxCommand;
3335 uint8_t mbxReserved:6;
3336 uint8_t mbxHc:1;
3337 uint8_t mbxOwner:1; /* Low order bit first word */
3338 #else /* __LITTLE_ENDIAN_BITFIELD */
3339 uint8_t mbxOwner:1; /* Low order bit first word */
3340 uint8_t mbxHc:1;
3341 uint8_t mbxReserved:6;
3342 uint8_t mbxCommand;
3343 uint16_t mbxStatus;
3344 #endif
3345
3346 MAILVARIANTS un;
3347 union sli_var us;
3348 } MAILBOX_t;
3349
3350 /*
3351 * Begin Structure Definitions for IOCB Commands
3352 */
3353
3354 typedef struct {
3355 #ifdef __BIG_ENDIAN_BITFIELD
3356 uint8_t statAction;
3357 uint8_t statRsn;
3358 uint8_t statBaExp;
3359 uint8_t statLocalError;
3360 #else /* __LITTLE_ENDIAN_BITFIELD */
3361 uint8_t statLocalError;
3362 uint8_t statBaExp;
3363 uint8_t statRsn;
3364 uint8_t statAction;
3365 #endif
3366 /* statRsn P/F_RJT reason codes */
3367 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3368 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3369 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3370 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3371 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3372 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3373 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3374 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3375 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3376 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3377 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3378 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3379 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3380 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3381 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3382 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3383 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3384 #define RJT_PROT_ERR 0x12 /* Protocol error */
3385 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3386 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3387 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3388 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3389 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3390 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3391 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3392 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3393
3394 #define IOERR_SUCCESS 0x00 /* statLocalError */
3395 #define IOERR_MISSING_CONTINUE 0x01
3396 #define IOERR_SEQUENCE_TIMEOUT 0x02
3397 #define IOERR_INTERNAL_ERROR 0x03
3398 #define IOERR_INVALID_RPI 0x04
3399 #define IOERR_NO_XRI 0x05
3400 #define IOERR_ILLEGAL_COMMAND 0x06
3401 #define IOERR_XCHG_DROPPED 0x07
3402 #define IOERR_ILLEGAL_FIELD 0x08
3403 #define IOERR_BAD_CONTINUE 0x09
3404 #define IOERR_TOO_MANY_BUFFERS 0x0A
3405 #define IOERR_RCV_BUFFER_WAITING 0x0B
3406 #define IOERR_NO_CONNECTION 0x0C
3407 #define IOERR_TX_DMA_FAILED 0x0D
3408 #define IOERR_RX_DMA_FAILED 0x0E
3409 #define IOERR_ILLEGAL_FRAME 0x0F
3410 #define IOERR_EXTRA_DATA 0x10
3411 #define IOERR_NO_RESOURCES 0x11
3412 #define IOERR_RESERVED 0x12
3413 #define IOERR_ILLEGAL_LENGTH 0x13
3414 #define IOERR_UNSUPPORTED_FEATURE 0x14
3415 #define IOERR_ABORT_IN_PROGRESS 0x15
3416 #define IOERR_ABORT_REQUESTED 0x16
3417 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3418 #define IOERR_LOOP_OPEN_FAILURE 0x18
3419 #define IOERR_RING_RESET 0x19
3420 #define IOERR_LINK_DOWN 0x1A
3421 #define IOERR_CORRUPTED_DATA 0x1B
3422 #define IOERR_CORRUPTED_RPI 0x1C
3423 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3424 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3425 #define IOERR_DUP_FRAME 0x1F
3426 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3427 #define IOERR_BAD_HOST_ADDRESS 0x21
3428 #define IOERR_RCV_HDRBUF_WAITING 0x22
3429 #define IOERR_MISSING_HDR_BUFFER 0x23
3430 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3431 #define IOERR_ABORTMULT_REQUESTED 0x25
3432 #define IOERR_BUFFER_SHORTAGE 0x28
3433 #define IOERR_DEFAULT 0x29
3434 #define IOERR_CNT 0x2A
3435 #define IOERR_SLER_FAILURE 0x46
3436 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3437 #define IOERR_SLER_REC_RJT_ERR 0x48
3438 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3439 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3440 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3441 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3442 #define IOERR_SLER_ABTS_ERR 0x4E
3443 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3444 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3445 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3446 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3447 #define IOERR_DRVR_MASK 0x100
3448 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3449 #define IOERR_SLI_BRESET 0x102
3450 #define IOERR_SLI_ABORTED 0x103
3451 #define IOERR_PARAM_MASK 0x1ff
3452 } PARM_ERR;
3453
3454 typedef union {
3455 struct {
3456 #ifdef __BIG_ENDIAN_BITFIELD
3457 uint8_t Rctl; /* R_CTL field */
3458 uint8_t Type; /* TYPE field */
3459 uint8_t Dfctl; /* DF_CTL field */
3460 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3461 #else /* __LITTLE_ENDIAN_BITFIELD */
3462 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3463 uint8_t Dfctl; /* DF_CTL field */
3464 uint8_t Type; /* TYPE field */
3465 uint8_t Rctl; /* R_CTL field */
3466 #endif
3467
3468 #define BC 0x02 /* Broadcast Received - Fctl */
3469 #define SI 0x04 /* Sequence Initiative */
3470 #define LA 0x08 /* Ignore Link Attention state */
3471 #define LS 0x80 /* Last Sequence */
3472 } hcsw;
3473 uint32_t reserved;
3474 } WORD5;
3475
3476 /* IOCB Command template for a generic response */
3477 typedef struct {
3478 uint32_t reserved[4];
3479 PARM_ERR perr;
3480 } GENERIC_RSP;
3481
3482 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3483 typedef struct {
3484 struct ulp_bde xrsqbde[2];
3485 uint32_t xrsqRo; /* Starting Relative Offset */
3486 WORD5 w5; /* Header control/status word */
3487 } XR_SEQ_FIELDS;
3488
3489 /* IOCB Command template for ELS_REQUEST */
3490 typedef struct {
3491 struct ulp_bde elsReq;
3492 struct ulp_bde elsRsp;
3493
3494 #ifdef __BIG_ENDIAN_BITFIELD
3495 uint32_t word4Rsvd:7;
3496 uint32_t fl:1;
3497 uint32_t myID:24;
3498 uint32_t word5Rsvd:8;
3499 uint32_t remoteID:24;
3500 #else /* __LITTLE_ENDIAN_BITFIELD */
3501 uint32_t myID:24;
3502 uint32_t fl:1;
3503 uint32_t word4Rsvd:7;
3504 uint32_t remoteID:24;
3505 uint32_t word5Rsvd:8;
3506 #endif
3507 } ELS_REQUEST;
3508
3509 /* IOCB Command template for RCV_ELS_REQ */
3510 typedef struct {
3511 struct ulp_bde elsReq[2];
3512 uint32_t parmRo;
3513
3514 #ifdef __BIG_ENDIAN_BITFIELD
3515 uint32_t word5Rsvd:8;
3516 uint32_t remoteID:24;
3517 #else /* __LITTLE_ENDIAN_BITFIELD */
3518 uint32_t remoteID:24;
3519 uint32_t word5Rsvd:8;
3520 #endif
3521 } RCV_ELS_REQ;
3522
3523 /* IOCB Command template for ABORT / CLOSE_XRI */
3524 typedef struct {
3525 uint32_t rsvd[3];
3526 uint32_t abortType;
3527 #define ABORT_TYPE_ABTX 0x00000000
3528 #define ABORT_TYPE_ABTS 0x00000001
3529 uint32_t parm;
3530 #ifdef __BIG_ENDIAN_BITFIELD
3531 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3532 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3533 #else /* __LITTLE_ENDIAN_BITFIELD */
3534 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3535 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3536 #endif
3537 } AC_XRI;
3538
3539 /* IOCB Command template for ABORT_MXRI64 */
3540 typedef struct {
3541 uint32_t rsvd[3];
3542 uint32_t abortType;
3543 uint32_t parm;
3544 uint32_t iotag32;
3545 } A_MXRI64;
3546
3547 /* IOCB Command template for GET_RPI */
3548 typedef struct {
3549 uint32_t rsvd[4];
3550 uint32_t parmRo;
3551 #ifdef __BIG_ENDIAN_BITFIELD
3552 uint32_t word5Rsvd:8;
3553 uint32_t remoteID:24;
3554 #else /* __LITTLE_ENDIAN_BITFIELD */
3555 uint32_t remoteID:24;
3556 uint32_t word5Rsvd:8;
3557 #endif
3558 } GET_RPI;
3559
3560 /* IOCB Command template for all FCP Initiator commands */
3561 typedef struct {
3562 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3563 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3564 uint32_t fcpi_parm;
3565 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3566 } FCPI_FIELDS;
3567
3568 /* IOCB Command template for all FCP Target commands */
3569 typedef struct {
3570 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3571 uint32_t fcpt_Offset;
3572 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3573 } FCPT_FIELDS;
3574
3575 /* SLI-2 IOCB structure definitions */
3576
3577 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3578 typedef struct {
3579 ULP_BDL bdl;
3580 uint32_t xrsqRo; /* Starting Relative Offset */
3581 WORD5 w5; /* Header control/status word */
3582 } XMT_SEQ_FIELDS64;
3583
3584 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3585 #define xmit_els_remoteID xrsqRo
3586
3587 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3588 typedef struct {
3589 struct ulp_bde64 rcvBde;
3590 uint32_t rsvd1;
3591 uint32_t xrsqRo; /* Starting Relative Offset */
3592 WORD5 w5; /* Header control/status word */
3593 } RCV_SEQ_FIELDS64;
3594
3595 /* IOCB Command template for ELS_REQUEST64 */
3596 typedef struct {
3597 ULP_BDL bdl;
3598 #ifdef __BIG_ENDIAN_BITFIELD
3599 uint32_t word4Rsvd:7;
3600 uint32_t fl:1;
3601 uint32_t myID:24;
3602 uint32_t word5Rsvd:8;
3603 uint32_t remoteID:24;
3604 #else /* __LITTLE_ENDIAN_BITFIELD */
3605 uint32_t myID:24;
3606 uint32_t fl:1;
3607 uint32_t word4Rsvd:7;
3608 uint32_t remoteID:24;
3609 uint32_t word5Rsvd:8;
3610 #endif
3611 } ELS_REQUEST64;
3612
3613 /* IOCB Command template for GEN_REQUEST64 */
3614 typedef struct {
3615 ULP_BDL bdl;
3616 uint32_t xrsqRo; /* Starting Relative Offset */
3617 WORD5 w5; /* Header control/status word */
3618 } GEN_REQUEST64;
3619
3620 /* IOCB Command template for RCV_ELS_REQ64 */
3621 typedef struct {
3622 struct ulp_bde64 elsReq;
3623 uint32_t rcvd1;
3624 uint32_t parmRo;
3625
3626 #ifdef __BIG_ENDIAN_BITFIELD
3627 uint32_t word5Rsvd:8;
3628 uint32_t remoteID:24;
3629 #else /* __LITTLE_ENDIAN_BITFIELD */
3630 uint32_t remoteID:24;
3631 uint32_t word5Rsvd:8;
3632 #endif
3633 } RCV_ELS_REQ64;
3634
3635 /* IOCB Command template for RCV_SEQ64 */
3636 struct rcv_seq64 {
3637 struct ulp_bde64 elsReq;
3638 uint32_t hbq_1;
3639 uint32_t parmRo;
3640 #ifdef __BIG_ENDIAN_BITFIELD
3641 uint32_t rctl:8;
3642 uint32_t type:8;
3643 uint32_t dfctl:8;
3644 uint32_t ls:1;
3645 uint32_t fs:1;
3646 uint32_t rsvd2:3;
3647 uint32_t si:1;
3648 uint32_t bc:1;
3649 uint32_t rsvd3:1;
3650 #else /* __LITTLE_ENDIAN_BITFIELD */
3651 uint32_t rsvd3:1;
3652 uint32_t bc:1;
3653 uint32_t si:1;
3654 uint32_t rsvd2:3;
3655 uint32_t fs:1;
3656 uint32_t ls:1;
3657 uint32_t dfctl:8;
3658 uint32_t type:8;
3659 uint32_t rctl:8;
3660 #endif
3661 };
3662
3663 /* IOCB Command template for all 64 bit FCP Initiator commands */
3664 typedef struct {
3665 ULP_BDL bdl;
3666 uint32_t fcpi_parm;
3667 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3668 } FCPI_FIELDS64;
3669
3670 /* IOCB Command template for all 64 bit FCP Target commands */
3671 typedef struct {
3672 ULP_BDL bdl;
3673 uint32_t fcpt_Offset;
3674 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3675 } FCPT_FIELDS64;
3676
3677 /* IOCB Command template for Async Status iocb commands */
3678 typedef struct {
3679 uint32_t rsvd[4];
3680 uint32_t param;
3681 #ifdef __BIG_ENDIAN_BITFIELD
3682 uint16_t evt_code; /* High order bits word 5 */
3683 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3684 #else /* __LITTLE_ENDIAN_BITFIELD */
3685 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3686 uint16_t evt_code; /* Low order bits word 5 */
3687 #endif
3688 } ASYNCSTAT_FIELDS;
3689 #define ASYNC_TEMP_WARN 0x100
3690 #define ASYNC_TEMP_SAFE 0x101
3691 #define ASYNC_STATUS_CN 0x102
3692
3693 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3694 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3695
3696 struct rcv_sli3 {
3697 #ifdef __BIG_ENDIAN_BITFIELD
3698 uint16_t ox_id;
3699 uint16_t seq_cnt;
3700
3701 uint16_t vpi;
3702 uint16_t word9Rsvd;
3703 #else /* __LITTLE_ENDIAN */
3704 uint16_t seq_cnt;
3705 uint16_t ox_id;
3706
3707 uint16_t word9Rsvd;
3708 uint16_t vpi;
3709 #endif
3710 uint32_t word10Rsvd;
3711 uint32_t acc_len; /* accumulated length */
3712 struct ulp_bde64 bde2;
3713 };
3714
3715 /* Structure used for a single HBQ entry */
3716 struct lpfc_hbq_entry {
3717 struct ulp_bde64 bde;
3718 uint32_t buffer_tag;
3719 };
3720
3721 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3722 typedef struct {
3723 struct lpfc_hbq_entry buff;
3724 uint32_t rsvd;
3725 uint32_t rsvd1;
3726 } QUE_XRI64_CX_FIELDS;
3727
3728 struct que_xri64cx_ext_fields {
3729 uint32_t iotag64_low;
3730 uint32_t iotag64_high;
3731 uint32_t ebde_count;
3732 uint32_t rsvd;
3733 struct lpfc_hbq_entry buff[5];
3734 };
3735
3736 struct sli3_bg_fields {
3737 uint32_t filler[6]; /* word 8-13 in IOCB */
3738 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3739 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3740 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
3741 #define BGS_BIDIR_BG_PROF_SHIFT 24
3742 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3743 #define BGS_BIDIR_ERR_COND_SHIFT 16
3744 #define BGS_BG_PROFILE_MASK 0x0000ff00
3745 #define BGS_BG_PROFILE_SHIFT 8
3746 #define BGS_INVALID_PROF_MASK 0x00000020
3747 #define BGS_INVALID_PROF_SHIFT 5
3748 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3749 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3750 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3751 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3752 #define BGS_REFTAG_ERR_MASK 0x00000004
3753 #define BGS_REFTAG_ERR_SHIFT 2
3754 #define BGS_APPTAG_ERR_MASK 0x00000002
3755 #define BGS_APPTAG_ERR_SHIFT 1
3756 #define BGS_GUARD_ERR_MASK 0x00000001
3757 #define BGS_GUARD_ERR_SHIFT 0
3758 uint32_t bgstat; /* word 15 - BlockGuard Status */
3759 };
3760
3761 static inline uint32_t
3762 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3763 {
3764 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3765 BGS_BIDIR_BG_PROF_SHIFT;
3766 }
3767
3768 static inline uint32_t
3769 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3770 {
3771 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3772 BGS_BIDIR_ERR_COND_SHIFT;
3773 }
3774
3775 static inline uint32_t
3776 lpfc_bgs_get_bg_prof(uint32_t bgstat)
3777 {
3778 return (bgstat & BGS_BG_PROFILE_MASK) >>
3779 BGS_BG_PROFILE_SHIFT;
3780 }
3781
3782 static inline uint32_t
3783 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3784 {
3785 return (bgstat & BGS_INVALID_PROF_MASK) >>
3786 BGS_INVALID_PROF_SHIFT;
3787 }
3788
3789 static inline uint32_t
3790 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3791 {
3792 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
3793 BGS_UNINIT_DIF_BLOCK_SHIFT;
3794 }
3795
3796 static inline uint32_t
3797 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3798 {
3799 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
3800 BGS_HI_WATER_MARK_PRESENT_SHIFT;
3801 }
3802
3803 static inline uint32_t
3804 lpfc_bgs_get_reftag_err(uint32_t bgstat)
3805 {
3806 return (bgstat & BGS_REFTAG_ERR_MASK) >>
3807 BGS_REFTAG_ERR_SHIFT;
3808 }
3809
3810 static inline uint32_t
3811 lpfc_bgs_get_apptag_err(uint32_t bgstat)
3812 {
3813 return (bgstat & BGS_APPTAG_ERR_MASK) >>
3814 BGS_APPTAG_ERR_SHIFT;
3815 }
3816
3817 static inline uint32_t
3818 lpfc_bgs_get_guard_err(uint32_t bgstat)
3819 {
3820 return (bgstat & BGS_GUARD_ERR_MASK) >>
3821 BGS_GUARD_ERR_SHIFT;
3822 }
3823
3824 #define LPFC_EXT_DATA_BDE_COUNT 3
3825 struct fcp_irw_ext {
3826 uint32_t io_tag64_low;
3827 uint32_t io_tag64_high;
3828 #ifdef __BIG_ENDIAN_BITFIELD
3829 uint8_t reserved1;
3830 uint8_t reserved2;
3831 uint8_t reserved3;
3832 uint8_t ebde_count;
3833 #else /* __LITTLE_ENDIAN */
3834 uint8_t ebde_count;
3835 uint8_t reserved3;
3836 uint8_t reserved2;
3837 uint8_t reserved1;
3838 #endif
3839 uint32_t reserved4;
3840 struct ulp_bde64 rbde; /* response bde */
3841 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3842 uint8_t icd[32]; /* immediate command data (32 bytes) */
3843 };
3844
3845 typedef struct _IOCB { /* IOCB structure */
3846 union {
3847 GENERIC_RSP grsp; /* Generic response */
3848 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3849 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3850 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3851 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3852 A_MXRI64 amxri; /* abort multiple xri command overlay */
3853 GET_RPI getrpi; /* GET_RPI template */
3854 FCPI_FIELDS fcpi; /* FCP Initiator template */
3855 FCPT_FIELDS fcpt; /* FCP target template */
3856
3857 /* SLI-2 structures */
3858
3859 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3860 * bde_64s */
3861 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3862 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3863 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3864 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3865 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3866 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
3867 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
3868 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
3869 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
3870 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
3871 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3872 } un;
3873 union {
3874 struct {
3875 #ifdef __BIG_ENDIAN_BITFIELD
3876 uint16_t ulpContext; /* High order bits word 6 */
3877 uint16_t ulpIoTag; /* Low order bits word 6 */
3878 #else /* __LITTLE_ENDIAN_BITFIELD */
3879 uint16_t ulpIoTag; /* Low order bits word 6 */
3880 uint16_t ulpContext; /* High order bits word 6 */
3881 #endif
3882 } t1;
3883 struct {
3884 #ifdef __BIG_ENDIAN_BITFIELD
3885 uint16_t ulpContext; /* High order bits word 6 */
3886 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3887 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3888 #else /* __LITTLE_ENDIAN_BITFIELD */
3889 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3890 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3891 uint16_t ulpContext; /* High order bits word 6 */
3892 #endif
3893 } t2;
3894 } un1;
3895 #define ulpContext un1.t1.ulpContext
3896 #define ulpIoTag un1.t1.ulpIoTag
3897 #define ulpIoTag0 un1.t2.ulpIoTag0
3898
3899 #ifdef __BIG_ENDIAN_BITFIELD
3900 uint32_t ulpTimeout:8;
3901 uint32_t ulpXS:1;
3902 uint32_t ulpFCP2Rcvy:1;
3903 uint32_t ulpPU:2;
3904 uint32_t ulpIr:1;
3905 uint32_t ulpClass:3;
3906 uint32_t ulpCommand:8;
3907 uint32_t ulpStatus:4;
3908 uint32_t ulpBdeCount:2;
3909 uint32_t ulpLe:1;
3910 uint32_t ulpOwner:1; /* Low order bit word 7 */
3911 #else /* __LITTLE_ENDIAN_BITFIELD */
3912 uint32_t ulpOwner:1; /* Low order bit word 7 */
3913 uint32_t ulpLe:1;
3914 uint32_t ulpBdeCount:2;
3915 uint32_t ulpStatus:4;
3916 uint32_t ulpCommand:8;
3917 uint32_t ulpClass:3;
3918 uint32_t ulpIr:1;
3919 uint32_t ulpPU:2;
3920 uint32_t ulpFCP2Rcvy:1;
3921 uint32_t ulpXS:1;
3922 uint32_t ulpTimeout:8;
3923 #endif
3924
3925 union {
3926 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3927
3928 /* words 8-31 used for que_xri_cx iocb */
3929 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
3930 struct fcp_irw_ext fcp_ext;
3931 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3932
3933 /* words 8-15 for BlockGuard */
3934 struct sli3_bg_fields sli3_bg;
3935 } unsli3;
3936
3937 #define ulpCt_h ulpXS
3938 #define ulpCt_l ulpFCP2Rcvy
3939
3940 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3941 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
3942 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
3943 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3944 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
3945 #define PARM_NPIV_DID 3
3946 #define CLASS1 0 /* Class 1 */
3947 #define CLASS2 1 /* Class 2 */
3948 #define CLASS3 2 /* Class 3 */
3949 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3950
3951 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3952 #define IOSTAT_FCP_RSP_ERROR 0x1
3953 #define IOSTAT_REMOTE_STOP 0x2
3954 #define IOSTAT_LOCAL_REJECT 0x3
3955 #define IOSTAT_NPORT_RJT 0x4
3956 #define IOSTAT_FABRIC_RJT 0x5
3957 #define IOSTAT_NPORT_BSY 0x6
3958 #define IOSTAT_FABRIC_BSY 0x7
3959 #define IOSTAT_INTERMED_RSP 0x8
3960 #define IOSTAT_LS_RJT 0x9
3961 #define IOSTAT_BA_RJT 0xA
3962 #define IOSTAT_RSVD1 0xB
3963 #define IOSTAT_RSVD2 0xC
3964 #define IOSTAT_RSVD3 0xD
3965 #define IOSTAT_RSVD4 0xE
3966 #define IOSTAT_NEED_BUFFER 0xF
3967 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3968 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3969 #define IOSTAT_CNT 0x11
3970
3971 } IOCB_t;
3972
3973
3974 #define SLI1_SLIM_SIZE (4 * 1024)
3975
3976 /* Up to 498 IOCBs will fit into 16k
3977 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3978 */
3979 #define SLI2_SLIM_SIZE (64 * 1024)
3980
3981 /* Maximum IOCBs that will fit in SLI2 slim */
3982 #define MAX_SLI2_IOCB 498
3983 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3984 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
3985 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
3986
3987 /* HBQ entries are 4 words each = 4k */
3988 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3989 lpfc_sli_hbq_count())
3990
3991 struct lpfc_sli2_slim {
3992 MAILBOX_t mbx;
3993 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
3994 PCB_t pcb;
3995 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3996 };
3997
3998 /*
3999 * This function checks PCI device to allow special handling for LC HBAs.
4000 *
4001 * Parameters:
4002 * device : struct pci_dev 's device field
4003 *
4004 * return 1 => TRUE
4005 * 0 => FALSE
4006 */
4007 static inline int
4008 lpfc_is_LC_HBA(unsigned short device)
4009 {
4010 if ((device == PCI_DEVICE_ID_TFLY) ||
4011 (device == PCI_DEVICE_ID_PFLY) ||
4012 (device == PCI_DEVICE_ID_LP101) ||
4013 (device == PCI_DEVICE_ID_BMID) ||
4014 (device == PCI_DEVICE_ID_BSMB) ||
4015 (device == PCI_DEVICE_ID_ZMID) ||
4016 (device == PCI_DEVICE_ID_ZSMB) ||
4017 (device == PCI_DEVICE_ID_SAT_MID) ||
4018 (device == PCI_DEVICE_ID_SAT_SMB) ||
4019 (device == PCI_DEVICE_ID_RFLY))
4020 return 1;
4021 else
4022 return 0;
4023 }
4024
4025 /*
4026 * Determine if an IOCB failed because of a link event or firmware reset.
4027 */
4028
4029 static inline int
4030 lpfc_error_lost_link(IOCB_t *iocbp)
4031 {
4032 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4033 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4034 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4035 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4036 }
4037
4038 #define MENLO_TRANSPORT_TYPE 0xfe
4039 #define MENLO_CONTEXT 0
4040 #define MENLO_PU 3
4041 #define MENLO_TIMEOUT 30
4042 #define SETVAR_MLOMNT 0x103107
4043 #define SETVAR_MLORST 0x103007
4044
4045 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
Linux with added FPC-III support