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HID: hiddev: Fix slab-out-of-bounds write in hiddev_ioctl_usage()
[linux/fpc-iii.git] / sound / pci / rme9652 / hdsp.c
blobdd6c9e6a1d53c4abb5558690b6603f37c7a918b5
1 /*
2 * ALSA driver for RME Hammerfall DSP audio interface(s)
3 *
4 * Copyright (c) 2002 Paul Davis
5 * Marcus Andersson
6 * Thomas Charbonnel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/firmware.h>
29 #include <linux/module.h>
30 #include <linux/math64.h>
31 #include <linux/vmalloc.h>
32 #include <linux/io.h>
33 #include <linux/nospec.h>
34
35 #include <sound/core.h>
36 #include <sound/control.h>
37 #include <sound/pcm.h>
38 #include <sound/info.h>
39 #include <sound/asoundef.h>
40 #include <sound/rawmidi.h>
41 #include <sound/hwdep.h>
42 #include <sound/initval.h>
43 #include <sound/hdsp.h>
44
45 #include <asm/byteorder.h>
46 #include <asm/current.h>
47
48 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
49 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
50 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
51
52 module_param_array(index, int, NULL, 0444);
53 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
54 module_param_array(id, charp, NULL, 0444);
55 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
56 module_param_array(enable, bool, NULL, 0444);
57 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
58 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
59 MODULE_DESCRIPTION("RME Hammerfall DSP");
60 MODULE_LICENSE("GPL");
61 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
62 "{RME HDSP-9652},"
63 "{RME HDSP-9632}}");
64 MODULE_FIRMWARE("rpm_firmware.bin");
65 MODULE_FIRMWARE("multiface_firmware.bin");
66 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
67 MODULE_FIRMWARE("digiface_firmware.bin");
68 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
69
70 #define HDSP_MAX_CHANNELS 26
71 #define HDSP_MAX_DS_CHANNELS 14
72 #define HDSP_MAX_QS_CHANNELS 8
73 #define DIGIFACE_SS_CHANNELS 26
74 #define DIGIFACE_DS_CHANNELS 14
75 #define MULTIFACE_SS_CHANNELS 18
76 #define MULTIFACE_DS_CHANNELS 14
77 #define H9652_SS_CHANNELS 26
78 #define H9652_DS_CHANNELS 14
79 /* This does not include possible Analog Extension Boards
80 AEBs are detected at card initialization
81 */
82 #define H9632_SS_CHANNELS 12
83 #define H9632_DS_CHANNELS 8
84 #define H9632_QS_CHANNELS 4
85 #define RPM_CHANNELS 6
86
87 /* Write registers. These are defined as byte-offsets from the iobase value.
88 */
89 #define HDSP_resetPointer 0
90 #define HDSP_freqReg 0
91 #define HDSP_outputBufferAddress 32
92 #define HDSP_inputBufferAddress 36
93 #define HDSP_controlRegister 64
94 #define HDSP_interruptConfirmation 96
95 #define HDSP_outputEnable 128
96 #define HDSP_control2Reg 256
97 #define HDSP_midiDataOut0 352
98 #define HDSP_midiDataOut1 356
99 #define HDSP_fifoData 368
100 #define HDSP_inputEnable 384
101
102 /* Read registers. These are defined as byte-offsets from the iobase value
103 */
104
105 #define HDSP_statusRegister 0
106 #define HDSP_timecode 128
107 #define HDSP_status2Register 192
108 #define HDSP_midiDataIn0 360
109 #define HDSP_midiDataIn1 364
110 #define HDSP_midiStatusOut0 384
111 #define HDSP_midiStatusOut1 388
112 #define HDSP_midiStatusIn0 392
113 #define HDSP_midiStatusIn1 396
114 #define HDSP_fifoStatus 400
115
116 /* the meters are regular i/o-mapped registers, but offset
117 considerably from the rest. the peak registers are reset
118 when read; the least-significant 4 bits are full-scale counters;
119 the actual peak value is in the most-significant 24 bits.
120 */
121
122 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
123 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
124 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
125 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
126 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
127
128
129 /* This is for H9652 cards
130 Peak values are read downward from the base
131 Rms values are read upward
132 There are rms values for the outputs too
133 26*3 values are read in ss mode
134 14*3 in ds mode, with no gap between values
135 */
136 #define HDSP_9652_peakBase 7164
137 #define HDSP_9652_rmsBase 4096
138
139 /* c.f. the hdsp_9632_meters_t struct */
140 #define HDSP_9632_metersBase 4096
141
142 #define HDSP_IO_EXTENT 7168
143
144 /* control2 register bits */
145
146 #define HDSP_TMS 0x01
147 #define HDSP_TCK 0x02
148 #define HDSP_TDI 0x04
149 #define HDSP_JTAG 0x08
150 #define HDSP_PWDN 0x10
151 #define HDSP_PROGRAM 0x020
152 #define HDSP_CONFIG_MODE_0 0x040
153 #define HDSP_CONFIG_MODE_1 0x080
154 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
155 #define HDSP_BIGENDIAN_MODE 0x200
156 #define HDSP_RD_MULTIPLE 0x400
157 #define HDSP_9652_ENABLE_MIXER 0x800
158 #define HDSP_S200 0x800
159 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
160 #define HDSP_CYCLIC_MODE 0x1000
161 #define HDSP_TDO 0x10000000
162
163 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
164 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
165
166 /* Control Register bits */
167
168 #define HDSP_Start (1<<0) /* start engine */
169 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
170 #define HDSP_Latency1 (1<<2) /* [ see above ] */
171 #define HDSP_Latency2 (1<<3) /* [ see above ] */
172 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
173 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
174 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
175 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
176 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
177 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
178 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
179 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
180 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
181 #define HDSP_SyncRef2 (1<<13)
182 #define HDSP_SPDIFInputSelect0 (1<<14)
183 #define HDSP_SPDIFInputSelect1 (1<<15)
184 #define HDSP_SyncRef0 (1<<16)
185 #define HDSP_SyncRef1 (1<<17)
186 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
187 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
188 #define HDSP_Midi0InterruptEnable (1<<22)
189 #define HDSP_Midi1InterruptEnable (1<<23)
190 #define HDSP_LineOut (1<<24)
191 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
192 #define HDSP_ADGain1 (1<<26)
193 #define HDSP_DAGain0 (1<<27)
194 #define HDSP_DAGain1 (1<<28)
195 #define HDSP_PhoneGain0 (1<<29)
196 #define HDSP_PhoneGain1 (1<<30)
197 #define HDSP_QuadSpeed (1<<31)
198
199 /* RPM uses some of the registers for special purposes */
200 #define HDSP_RPM_Inp12 0x04A00
201 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
202 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
203 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
204 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
205 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
206
207 #define HDSP_RPM_Inp34 0x32000
208 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
209 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
210 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
211 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
212 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
213
214 #define HDSP_RPM_Bypass 0x01000
215
216 #define HDSP_RPM_Disconnect 0x00001
217
218 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
219 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
220 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
221 #define HDSP_ADGainLowGain 0
222
223 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
224 #define HDSP_DAGainHighGain HDSP_DAGainMask
225 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
226 #define HDSP_DAGainMinus10dBV 0
227
228 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
229 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
230 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
231 #define HDSP_PhoneGainMinus12dB 0
232
233 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
234 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
235
236 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
237 #define HDSP_SPDIFInputADAT1 0
238 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
239 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
240 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
241
242 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
243 #define HDSP_SyncRef_ADAT1 0
244 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
245 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
246 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
247 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
248 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
249
250 /* Sample Clock Sources */
251
252 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
253 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
254 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
255 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
256 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
257 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
258 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
259 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
260 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
261 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
262
263 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
264
265 #define HDSP_SYNC_FROM_WORD 0
266 #define HDSP_SYNC_FROM_SPDIF 1
267 #define HDSP_SYNC_FROM_ADAT1 2
268 #define HDSP_SYNC_FROM_ADAT_SYNC 3
269 #define HDSP_SYNC_FROM_ADAT2 4
270 #define HDSP_SYNC_FROM_ADAT3 5
271
272 /* SyncCheck status */
273
274 #define HDSP_SYNC_CHECK_NO_LOCK 0
275 #define HDSP_SYNC_CHECK_LOCK 1
276 #define HDSP_SYNC_CHECK_SYNC 2
277
278 /* AutoSync references - used by "autosync_ref" control switch */
279
280 #define HDSP_AUTOSYNC_FROM_WORD 0
281 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
282 #define HDSP_AUTOSYNC_FROM_SPDIF 2
283 #define HDSP_AUTOSYNC_FROM_NONE 3
284 #define HDSP_AUTOSYNC_FROM_ADAT1 4
285 #define HDSP_AUTOSYNC_FROM_ADAT2 5
286 #define HDSP_AUTOSYNC_FROM_ADAT3 6
287
288 /* Possible sources of S/PDIF input */
289
290 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
291 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
292 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
293 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
294
295 #define HDSP_Frequency32KHz HDSP_Frequency0
296 #define HDSP_Frequency44_1KHz HDSP_Frequency1
297 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
298 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
299 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
300 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
301 /* For H9632 cards */
302 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
303 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
304 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
305 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
306 return 104857600000000 / rate; // 100 MHz
307 return 110100480000000 / rate; // 105 MHz
308 */
309 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
310
311 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
312 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
313
314 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
315 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
316
317 /* Status Register bits */
318
319 #define HDSP_audioIRQPending (1<<0)
320 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
321 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
322 #define HDSP_Lock1 (1<<2)
323 #define HDSP_Lock0 (1<<3)
324 #define HDSP_SPDIFSync (1<<4)
325 #define HDSP_TimecodeLock (1<<5)
326 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
327 #define HDSP_Sync2 (1<<16)
328 #define HDSP_Sync1 (1<<17)
329 #define HDSP_Sync0 (1<<18)
330 #define HDSP_DoubleSpeedStatus (1<<19)
331 #define HDSP_ConfigError (1<<20)
332 #define HDSP_DllError (1<<21)
333 #define HDSP_spdifFrequency0 (1<<22)
334 #define HDSP_spdifFrequency1 (1<<23)
335 #define HDSP_spdifFrequency2 (1<<24)
336 #define HDSP_SPDIFErrorFlag (1<<25)
337 #define HDSP_BufferID (1<<26)
338 #define HDSP_TimecodeSync (1<<27)
339 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
340 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
341 #define HDSP_midi0IRQPending (1<<30)
342 #define HDSP_midi1IRQPending (1<<31)
343
344 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
345 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
346 HDSP_spdifFrequency1|\
347 HDSP_spdifFrequency2|\
348 HDSP_spdifFrequency3)
349
350 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
351 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
352 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
353
354 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
355 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
356 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
357
358 /* This is for H9632 cards */
359 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
360 HDSP_spdifFrequency1|\
361 HDSP_spdifFrequency2)
362 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
363 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
364
365 /* Status2 Register bits */
366
367 #define HDSP_version0 (1<<0)
368 #define HDSP_version1 (1<<1)
369 #define HDSP_version2 (1<<2)
370 #define HDSP_wc_lock (1<<3)
371 #define HDSP_wc_sync (1<<4)
372 #define HDSP_inp_freq0 (1<<5)
373 #define HDSP_inp_freq1 (1<<6)
374 #define HDSP_inp_freq2 (1<<7)
375 #define HDSP_SelSyncRef0 (1<<8)
376 #define HDSP_SelSyncRef1 (1<<9)
377 #define HDSP_SelSyncRef2 (1<<10)
378
379 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
380
381 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
382 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
383 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
384 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
385 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
386 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
387 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
388 /* FIXME : more values for 9632 cards ? */
389
390 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
391 #define HDSP_SelSyncRef_ADAT1 0
392 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
393 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
394 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
395 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
396 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
397
398 /* Card state flags */
399
400 #define HDSP_InitializationComplete (1<<0)
401 #define HDSP_FirmwareLoaded (1<<1)
402 #define HDSP_FirmwareCached (1<<2)
403
404 /* FIFO wait times, defined in terms of 1/10ths of msecs */
405
406 #define HDSP_LONG_WAIT 5000
407 #define HDSP_SHORT_WAIT 30
408
409 #define UNITY_GAIN 32768
410 #define MINUS_INFINITY_GAIN 0
411
412 /* the size of a substream (1 mono data stream) */
413
414 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
415 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
416
417 /* the size of the area we need to allocate for DMA transfers. the
418 size is the same regardless of the number of channels - the
419 Multiface still uses the same memory area.
420
421 Note that we allocate 1 more channel than is apparently needed
422 because the h/w seems to write 1 byte beyond the end of the last
423 page. Sigh.
424 */
425
426 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
427 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
428
429 #define HDSP_FIRMWARE_SIZE (24413 * 4)
430
431 struct hdsp_9632_meters {
432 u32 input_peak[16];
433 u32 playback_peak[16];
434 u32 output_peak[16];
435 u32 xxx_peak[16];
436 u32 padding[64];
437 u32 input_rms_low[16];
438 u32 playback_rms_low[16];
439 u32 output_rms_low[16];
440 u32 xxx_rms_low[16];
441 u32 input_rms_high[16];
442 u32 playback_rms_high[16];
443 u32 output_rms_high[16];
444 u32 xxx_rms_high[16];
445 };
446
447 struct hdsp_midi {
448 struct hdsp *hdsp;
449 int id;
450 struct snd_rawmidi *rmidi;
451 struct snd_rawmidi_substream *input;
452 struct snd_rawmidi_substream *output;
453 char istimer; /* timer in use */
454 struct timer_list timer;
455 spinlock_t lock;
456 int pending;
457 };
458
459 struct hdsp {
460 spinlock_t lock;
461 struct snd_pcm_substream *capture_substream;
462 struct snd_pcm_substream *playback_substream;
463 struct hdsp_midi midi[2];
464 struct tasklet_struct midi_tasklet;
465 int use_midi_tasklet;
466 int precise_ptr;
467 u32 control_register; /* cached value */
468 u32 control2_register; /* cached value */
469 u32 creg_spdif;
470 u32 creg_spdif_stream;
471 int clock_source_locked;
472 char *card_name; /* digiface/multiface/rpm */
473 enum HDSP_IO_Type io_type; /* ditto, but for code use */
474 unsigned short firmware_rev;
475 unsigned short state; /* stores state bits */
476 const struct firmware *firmware;
477 u32 *fw_uploaded;
478 size_t period_bytes; /* guess what this is */
479 unsigned char max_channels;
480 unsigned char qs_in_channels; /* quad speed mode for H9632 */
481 unsigned char ds_in_channels;
482 unsigned char ss_in_channels; /* different for multiface/digiface */
483 unsigned char qs_out_channels;
484 unsigned char ds_out_channels;
485 unsigned char ss_out_channels;
486
487 struct snd_dma_buffer capture_dma_buf;
488 struct snd_dma_buffer playback_dma_buf;
489 unsigned char *capture_buffer; /* suitably aligned address */
490 unsigned char *playback_buffer; /* suitably aligned address */
491
492 pid_t capture_pid;
493 pid_t playback_pid;
494 int running;
495 int system_sample_rate;
496 char *channel_map;
497 int dev;
498 int irq;
499 unsigned long port;
500 void __iomem *iobase;
501 struct snd_card *card;
502 struct snd_pcm *pcm;
503 struct snd_hwdep *hwdep;
504 struct pci_dev *pci;
505 struct snd_kcontrol *spdif_ctl;
506 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
507 unsigned int dds_value; /* last value written to freq register */
508 };
509
510 /* These tables map the ALSA channels 1..N to the channels that we
511 need to use in order to find the relevant channel buffer. RME
512 refer to this kind of mapping as between "the ADAT channel and
513 the DMA channel." We index it using the logical audio channel,
514 and the value is the DMA channel (i.e. channel buffer number)
515 where the data for that channel can be read/written from/to.
516 */
517
518 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
519 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
520 18, 19, 20, 21, 22, 23, 24, 25
521 };
522
523 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
524 /* Analog */
525 0, 1, 2, 3, 4, 5, 6, 7,
526 /* ADAT 2 */
527 16, 17, 18, 19, 20, 21, 22, 23,
528 /* SPDIF */
529 24, 25,
530 -1, -1, -1, -1, -1, -1, -1, -1
531 };
532
533 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
534 /* ADAT channels are remapped */
535 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
536 /* channels 12 and 13 are S/PDIF */
537 24, 25,
538 /* others don't exist */
539 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
540 };
541
542 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
543 /* ADAT channels */
544 0, 1, 2, 3, 4, 5, 6, 7,
545 /* SPDIF */
546 8, 9,
547 /* Analog */
548 10, 11,
549 /* AO4S-192 and AI4S-192 extension boards */
550 12, 13, 14, 15,
551 /* others don't exist */
552 -1, -1, -1, -1, -1, -1, -1, -1,
553 -1, -1
554 };
555
556 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
557 /* ADAT */
558 1, 3, 5, 7,
559 /* SPDIF */
560 8, 9,
561 /* Analog */
562 10, 11,
563 /* AO4S-192 and AI4S-192 extension boards */
564 12, 13, 14, 15,
565 /* others don't exist */
566 -1, -1, -1, -1, -1, -1, -1, -1,
567 -1, -1, -1, -1, -1, -1
568 };
569
570 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
571 /* ADAT is disabled in this mode */
572 /* SPDIF */
573 8, 9,
574 /* Analog */
575 10, 11,
576 /* AO4S-192 and AI4S-192 extension boards */
577 12, 13, 14, 15,
578 /* others don't exist */
579 -1, -1, -1, -1, -1, -1, -1, -1,
580 -1, -1, -1, -1, -1, -1, -1, -1,
581 -1, -1
582 };
583
584 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
585 {
586 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
587 dmab->dev.dev = snd_dma_pci_data(pci);
588 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
589 size, dmab) < 0)
590 return -ENOMEM;
591 return 0;
592 }
593
594 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
595 {
596 if (dmab->area)
597 snd_dma_free_pages(dmab);
598 }
599
600
601 static const struct pci_device_id snd_hdsp_ids[] = {
602 {
603 .vendor = PCI_VENDOR_ID_XILINX,
604 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
605 .subvendor = PCI_ANY_ID,
606 .subdevice = PCI_ANY_ID,
607 }, /* RME Hammerfall-DSP */
608 { 0, },
609 };
610
611 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
612
613 /* prototypes */
614 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
615 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
616 static int snd_hdsp_enable_io (struct hdsp *hdsp);
617 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
618 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
619 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
620 static int hdsp_autosync_ref(struct hdsp *hdsp);
621 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
622 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
623
624 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
625 {
626 switch (hdsp->io_type) {
627 case Multiface:
628 case Digiface:
629 case RPM:
630 default:
631 if (hdsp->firmware_rev == 0xa)
632 return (64 * out) + (32 + (in));
633 else
634 return (52 * out) + (26 + (in));
635 case H9632:
636 return (32 * out) + (16 + (in));
637 case H9652:
638 return (52 * out) + (26 + (in));
639 }
640 }
641
642 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
643 {
644 switch (hdsp->io_type) {
645 case Multiface:
646 case Digiface:
647 case RPM:
648 default:
649 if (hdsp->firmware_rev == 0xa)
650 return (64 * out) + in;
651 else
652 return (52 * out) + in;
653 case H9632:
654 return (32 * out) + in;
655 case H9652:
656 return (52 * out) + in;
657 }
658 }
659
660 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
661 {
662 writel(val, hdsp->iobase + reg);
663 }
664
665 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
666 {
667 return readl (hdsp->iobase + reg);
668 }
669
670 static int hdsp_check_for_iobox (struct hdsp *hdsp)
671 {
672 int i;
673
674 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
675 for (i = 0; i < 500; i++) {
676 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
677 HDSP_ConfigError)) {
678 if (i) {
679 dev_dbg(hdsp->card->dev,
680 "IO box found after %d ms\n",
681 (20 * i));
682 }
683 return 0;
684 }
685 msleep(20);
686 }
687 dev_err(hdsp->card->dev, "no IO box connected!\n");
688 hdsp->state &= ~HDSP_FirmwareLoaded;
689 return -EIO;
690 }
691
692 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
693 unsigned int delay)
694 {
695 unsigned int i;
696
697 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
698 return 0;
699
700 for (i = 0; i != loops; ++i) {
701 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
702 msleep(delay);
703 else {
704 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
705 i * delay);
706 return 0;
707 }
708 }
709
710 dev_info(hdsp->card->dev, "no IO box connected!\n");
711 hdsp->state &= ~HDSP_FirmwareLoaded;
712 return -EIO;
713 }
714
715 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
716
717 int i;
718 unsigned long flags;
719 const u32 *cache;
720
721 if (hdsp->fw_uploaded)
722 cache = hdsp->fw_uploaded;
723 else {
724 if (!hdsp->firmware)
725 return -ENODEV;
726 cache = (u32 *)hdsp->firmware->data;
727 if (!cache)
728 return -ENODEV;
729 }
730
731 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
732
733 dev_info(hdsp->card->dev, "loading firmware\n");
734
735 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
736 hdsp_write (hdsp, HDSP_fifoData, 0);
737
738 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
739 dev_info(hdsp->card->dev,
740 "timeout waiting for download preparation\n");
741 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
742 return -EIO;
743 }
744
745 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
746
747 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
748 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
749 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
750 dev_info(hdsp->card->dev,
751 "timeout during firmware loading\n");
752 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
753 return -EIO;
754 }
755 }
756
757 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
758 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
759
760 ssleep(3);
761 #ifdef SNDRV_BIG_ENDIAN
762 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
763 #else
764 hdsp->control2_register = 0;
765 #endif
766 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
767 dev_info(hdsp->card->dev, "finished firmware loading\n");
768
769 }
770 if (hdsp->state & HDSP_InitializationComplete) {
771 dev_info(hdsp->card->dev,
772 "firmware loaded from cache, restoring defaults\n");
773 spin_lock_irqsave(&hdsp->lock, flags);
774 snd_hdsp_set_defaults(hdsp);
775 spin_unlock_irqrestore(&hdsp->lock, flags);
776 }
777
778 hdsp->state |= HDSP_FirmwareLoaded;
779
780 return 0;
781 }
782
783 static int hdsp_get_iobox_version (struct hdsp *hdsp)
784 {
785 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
786
787 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
788 hdsp_write(hdsp, HDSP_fifoData, 0);
789
790 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
791 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
792 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
793 }
794
795 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
796 hdsp_write (hdsp, HDSP_fifoData, 0);
797 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
798 hdsp->io_type = Multiface;
799 dev_info(hdsp->card->dev, "Multiface found\n");
800 return 0;
801 }
802
803 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
804 hdsp_write(hdsp, HDSP_fifoData, 0);
805 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
806 hdsp->io_type = Digiface;
807 dev_info(hdsp->card->dev, "Digiface found\n");
808 return 0;
809 }
810
811 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
812 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
813 hdsp_write(hdsp, HDSP_fifoData, 0);
814 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
815 hdsp->io_type = Multiface;
816 dev_info(hdsp->card->dev, "Multiface found\n");
817 return 0;
818 }
819
820 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
821 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
822 hdsp_write(hdsp, HDSP_fifoData, 0);
823 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
824 hdsp->io_type = Multiface;
825 dev_info(hdsp->card->dev, "Multiface found\n");
826 return 0;
827 }
828
829 hdsp->io_type = RPM;
830 dev_info(hdsp->card->dev, "RPM found\n");
831 return 0;
832 } else {
833 /* firmware was already loaded, get iobox type */
834 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
835 hdsp->io_type = RPM;
836 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
837 hdsp->io_type = Multiface;
838 else
839 hdsp->io_type = Digiface;
840 }
841 return 0;
842 }
843
844
845 static int hdsp_request_fw_loader(struct hdsp *hdsp);
846
847 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
848 {
849 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
850 return 0;
851 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
852 hdsp->state &= ~HDSP_FirmwareLoaded;
853 if (! load_on_demand)
854 return -EIO;
855 dev_err(hdsp->card->dev, "firmware not present.\n");
856 /* try to load firmware */
857 if (! (hdsp->state & HDSP_FirmwareCached)) {
858 if (! hdsp_request_fw_loader(hdsp))
859 return 0;
860 dev_err(hdsp->card->dev,
861 "No firmware loaded nor cached, please upload firmware.\n");
862 return -EIO;
863 }
864 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
865 dev_err(hdsp->card->dev,
866 "Firmware loading from cache failed, please upload manually.\n");
867 return -EIO;
868 }
869 }
870 return 0;
871 }
872
873
874 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
875 {
876 int i;
877
878 /* the fifoStatus registers reports on how many words
879 are available in the command FIFO.
880 */
881
882 for (i = 0; i < timeout; i++) {
883
884 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
885 return 0;
886
887 /* not very friendly, but we only do this during a firmware
888 load and changing the mixer, so we just put up with it.
889 */
890
891 udelay (100);
892 }
893
894 dev_warn(hdsp->card->dev,
895 "wait for FIFO status <= %d failed after %d iterations\n",
896 count, timeout);
897 return -1;
898 }
899
900 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
901 {
902 if (addr >= HDSP_MATRIX_MIXER_SIZE)
903 return 0;
904
905 return hdsp->mixer_matrix[addr];
906 }
907
908 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
909 {
910 unsigned int ad;
911
912 if (addr >= HDSP_MATRIX_MIXER_SIZE)
913 return -1;
914
915 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
916
917 /* from martin bjornsen:
918
919 "You can only write dwords to the
920 mixer memory which contain two
921 mixer values in the low and high
922 word. So if you want to change
923 value 0 you have to read value 1
924 from the cache and write both to
925 the first dword in the mixer
926 memory."
927 */
928
929 if (hdsp->io_type == H9632 && addr >= 512)
930 return 0;
931
932 if (hdsp->io_type == H9652 && addr >= 1352)
933 return 0;
934
935 hdsp->mixer_matrix[addr] = data;
936
937
938 /* `addr' addresses a 16-bit wide address, but
939 the address space accessed via hdsp_write
940 uses byte offsets. put another way, addr
941 varies from 0 to 1351, but to access the
942 corresponding memory location, we need
943 to access 0 to 2703 ...
944 */
945 ad = addr/2;
946
947 hdsp_write (hdsp, 4096 + (ad*4),
948 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
949 hdsp->mixer_matrix[addr&0x7fe]);
950
951 return 0;
952
953 } else {
954
955 ad = (addr << 16) + data;
956
957 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
958 return -1;
959
960 hdsp_write (hdsp, HDSP_fifoData, ad);
961 hdsp->mixer_matrix[addr] = data;
962
963 }
964
965 return 0;
966 }
967
968 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
969 {
970 unsigned long flags;
971 int ret = 1;
972
973 spin_lock_irqsave(&hdsp->lock, flags);
974 if ((hdsp->playback_pid != hdsp->capture_pid) &&
975 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
976 ret = 0;
977 spin_unlock_irqrestore(&hdsp->lock, flags);
978 return ret;
979 }
980
981 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
982 {
983 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
984 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
985
986 /* For the 9632, the mask is different */
987 if (hdsp->io_type == H9632)
988 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
989
990 if (status & HDSP_SPDIFErrorFlag)
991 return 0;
992
993 switch (rate_bits) {
994 case HDSP_spdifFrequency32KHz: return 32000;
995 case HDSP_spdifFrequency44_1KHz: return 44100;
996 case HDSP_spdifFrequency48KHz: return 48000;
997 case HDSP_spdifFrequency64KHz: return 64000;
998 case HDSP_spdifFrequency88_2KHz: return 88200;
999 case HDSP_spdifFrequency96KHz: return 96000;
1000 case HDSP_spdifFrequency128KHz:
1001 if (hdsp->io_type == H9632) return 128000;
1002 break;
1003 case HDSP_spdifFrequency176_4KHz:
1004 if (hdsp->io_type == H9632) return 176400;
1005 break;
1006 case HDSP_spdifFrequency192KHz:
1007 if (hdsp->io_type == H9632) return 192000;
1008 break;
1009 default:
1010 break;
1011 }
1012 dev_warn(hdsp->card->dev,
1013 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
1014 rate_bits, status);
1015 return 0;
1016 }
1017
1018 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1019 {
1020 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1021 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1022
1023 /* For the 9632 card, there seems to be no bit for indicating external
1024 * sample rate greater than 96kHz. The card reports the corresponding
1025 * single speed. So the best means seems to get spdif rate when
1026 * autosync reference is spdif */
1027 if (hdsp->io_type == H9632 &&
1028 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1029 return hdsp_spdif_sample_rate(hdsp);
1030
1031 switch (rate_bits) {
1032 case HDSP_systemFrequency32: return 32000;
1033 case HDSP_systemFrequency44_1: return 44100;
1034 case HDSP_systemFrequency48: return 48000;
1035 case HDSP_systemFrequency64: return 64000;
1036 case HDSP_systemFrequency88_2: return 88200;
1037 case HDSP_systemFrequency96: return 96000;
1038 default:
1039 return 0;
1040 }
1041 }
1042
1043 static void hdsp_compute_period_size(struct hdsp *hdsp)
1044 {
1045 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1046 }
1047
1048 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1049 {
1050 int position;
1051
1052 position = hdsp_read(hdsp, HDSP_statusRegister);
1053
1054 if (!hdsp->precise_ptr)
1055 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1056
1057 position &= HDSP_BufferPositionMask;
1058 position /= 4;
1059 position &= (hdsp->period_bytes/2) - 1;
1060 return position;
1061 }
1062
1063 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1064 {
1065 hdsp_write (hdsp, HDSP_resetPointer, 0);
1066 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1067 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1068 * requires (?) to write again DDS value after a reset pointer
1069 * (at least, it works like this) */
1070 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1071 }
1072
1073 static void hdsp_start_audio(struct hdsp *s)
1074 {
1075 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1076 hdsp_write(s, HDSP_controlRegister, s->control_register);
1077 }
1078
1079 static void hdsp_stop_audio(struct hdsp *s)
1080 {
1081 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1082 hdsp_write(s, HDSP_controlRegister, s->control_register);
1083 }
1084
1085 static void hdsp_silence_playback(struct hdsp *hdsp)
1086 {
1087 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1088 }
1089
1090 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1091 {
1092 int n;
1093
1094 spin_lock_irq(&s->lock);
1095
1096 frames >>= 7;
1097 n = 0;
1098 while (frames) {
1099 n++;
1100 frames >>= 1;
1101 }
1102
1103 s->control_register &= ~HDSP_LatencyMask;
1104 s->control_register |= hdsp_encode_latency(n);
1105
1106 hdsp_write(s, HDSP_controlRegister, s->control_register);
1107
1108 hdsp_compute_period_size(s);
1109
1110 spin_unlock_irq(&s->lock);
1111
1112 return 0;
1113 }
1114
1115 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1116 {
1117 u64 n;
1118
1119 if (rate >= 112000)
1120 rate /= 4;
1121 else if (rate >= 56000)
1122 rate /= 2;
1123
1124 n = DDS_NUMERATOR;
1125 n = div_u64(n, rate);
1126 /* n should be less than 2^32 for being written to FREQ register */
1127 snd_BUG_ON(n >> 32);
1128 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1129 value to write it after a reset */
1130 hdsp->dds_value = n;
1131 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1132 }
1133
1134 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1135 {
1136 int reject_if_open = 0;
1137 int current_rate;
1138 int rate_bits;
1139
1140 /* ASSUMPTION: hdsp->lock is either held, or
1141 there is no need for it (e.g. during module
1142 initialization).
1143 */
1144
1145 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1146 if (called_internally) {
1147 /* request from ctl or card initialization */
1148 dev_err(hdsp->card->dev,
1149 "device is not running as a clock master: cannot set sample rate.\n");
1150 return -1;
1151 } else {
1152 /* hw_param request while in AutoSync mode */
1153 int external_freq = hdsp_external_sample_rate(hdsp);
1154 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1155
1156 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1157 dev_info(hdsp->card->dev,
1158 "Detected ADAT in double speed mode\n");
1159 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1160 dev_info(hdsp->card->dev,
1161 "Detected ADAT in quad speed mode\n");
1162 else if (rate != external_freq) {
1163 dev_info(hdsp->card->dev,
1164 "No AutoSync source for requested rate\n");
1165 return -1;
1166 }
1167 }
1168 }
1169
1170 current_rate = hdsp->system_sample_rate;
1171
1172 /* Changing from a "single speed" to a "double speed" rate is
1173 not allowed if any substreams are open. This is because
1174 such a change causes a shift in the location of
1175 the DMA buffers and a reduction in the number of available
1176 buffers.
1177
1178 Note that a similar but essentially insoluble problem
1179 exists for externally-driven rate changes. All we can do
1180 is to flag rate changes in the read/write routines. */
1181
1182 if (rate > 96000 && hdsp->io_type != H9632)
1183 return -EINVAL;
1184
1185 switch (rate) {
1186 case 32000:
1187 if (current_rate > 48000)
1188 reject_if_open = 1;
1189 rate_bits = HDSP_Frequency32KHz;
1190 break;
1191 case 44100:
1192 if (current_rate > 48000)
1193 reject_if_open = 1;
1194 rate_bits = HDSP_Frequency44_1KHz;
1195 break;
1196 case 48000:
1197 if (current_rate > 48000)
1198 reject_if_open = 1;
1199 rate_bits = HDSP_Frequency48KHz;
1200 break;
1201 case 64000:
1202 if (current_rate <= 48000 || current_rate > 96000)
1203 reject_if_open = 1;
1204 rate_bits = HDSP_Frequency64KHz;
1205 break;
1206 case 88200:
1207 if (current_rate <= 48000 || current_rate > 96000)
1208 reject_if_open = 1;
1209 rate_bits = HDSP_Frequency88_2KHz;
1210 break;
1211 case 96000:
1212 if (current_rate <= 48000 || current_rate > 96000)
1213 reject_if_open = 1;
1214 rate_bits = HDSP_Frequency96KHz;
1215 break;
1216 case 128000:
1217 if (current_rate < 128000)
1218 reject_if_open = 1;
1219 rate_bits = HDSP_Frequency128KHz;
1220 break;
1221 case 176400:
1222 if (current_rate < 128000)
1223 reject_if_open = 1;
1224 rate_bits = HDSP_Frequency176_4KHz;
1225 break;
1226 case 192000:
1227 if (current_rate < 128000)
1228 reject_if_open = 1;
1229 rate_bits = HDSP_Frequency192KHz;
1230 break;
1231 default:
1232 return -EINVAL;
1233 }
1234
1235 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1236 dev_warn(hdsp->card->dev,
1237 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1238 hdsp->capture_pid,
1239 hdsp->playback_pid);
1240 return -EBUSY;
1241 }
1242
1243 hdsp->control_register &= ~HDSP_FrequencyMask;
1244 hdsp->control_register |= rate_bits;
1245 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1246
1247 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1248 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1249 hdsp_set_dds_value(hdsp, rate);
1250
1251 if (rate >= 128000) {
1252 hdsp->channel_map = channel_map_H9632_qs;
1253 } else if (rate > 48000) {
1254 if (hdsp->io_type == H9632)
1255 hdsp->channel_map = channel_map_H9632_ds;
1256 else
1257 hdsp->channel_map = channel_map_ds;
1258 } else {
1259 switch (hdsp->io_type) {
1260 case RPM:
1261 case Multiface:
1262 hdsp->channel_map = channel_map_mf_ss;
1263 break;
1264 case Digiface:
1265 case H9652:
1266 hdsp->channel_map = channel_map_df_ss;
1267 break;
1268 case H9632:
1269 hdsp->channel_map = channel_map_H9632_ss;
1270 break;
1271 default:
1272 /* should never happen */
1273 break;
1274 }
1275 }
1276
1277 hdsp->system_sample_rate = rate;
1278
1279 return 0;
1280 }
1281
1282 /*----------------------------------------------------------------------------
1283 MIDI
1284 ----------------------------------------------------------------------------*/
1285
1286 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1287 {
1288 /* the hardware already does the relevant bit-mask with 0xff */
1289 if (id)
1290 return hdsp_read(hdsp, HDSP_midiDataIn1);
1291 else
1292 return hdsp_read(hdsp, HDSP_midiDataIn0);
1293 }
1294
1295 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1296 {
1297 /* the hardware already does the relevant bit-mask with 0xff */
1298 if (id)
1299 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1300 else
1301 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1302 }
1303
1304 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1305 {
1306 if (id)
1307 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1308 else
1309 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1310 }
1311
1312 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1313 {
1314 int fifo_bytes_used;
1315
1316 if (id)
1317 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1318 else
1319 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1320
1321 if (fifo_bytes_used < 128)
1322 return 128 - fifo_bytes_used;
1323 else
1324 return 0;
1325 }
1326
1327 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1328 {
1329 while (snd_hdsp_midi_input_available (hdsp, id))
1330 snd_hdsp_midi_read_byte (hdsp, id);
1331 }
1332
1333 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1334 {
1335 unsigned long flags;
1336 int n_pending;
1337 int to_write;
1338 int i;
1339 unsigned char buf[128];
1340
1341 /* Output is not interrupt driven */
1342
1343 spin_lock_irqsave (&hmidi->lock, flags);
1344 if (hmidi->output) {
1345 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1346 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1347 if (n_pending > (int)sizeof (buf))
1348 n_pending = sizeof (buf);
1349
1350 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1351 for (i = 0; i < to_write; ++i)
1352 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1353 }
1354 }
1355 }
1356 }
1357 spin_unlock_irqrestore (&hmidi->lock, flags);
1358 return 0;
1359 }
1360
1361 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1362 {
1363 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1364 unsigned long flags;
1365 int n_pending;
1366 int i;
1367
1368 spin_lock_irqsave (&hmidi->lock, flags);
1369 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1370 if (hmidi->input) {
1371 if (n_pending > (int)sizeof (buf))
1372 n_pending = sizeof (buf);
1373 for (i = 0; i < n_pending; ++i)
1374 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1375 if (n_pending)
1376 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1377 } else {
1378 /* flush the MIDI input FIFO */
1379 while (--n_pending)
1380 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1381 }
1382 }
1383 hmidi->pending = 0;
1384 if (hmidi->id)
1385 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1386 else
1387 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1388 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1389 spin_unlock_irqrestore (&hmidi->lock, flags);
1390 return snd_hdsp_midi_output_write (hmidi);
1391 }
1392
1393 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1394 {
1395 struct hdsp *hdsp;
1396 struct hdsp_midi *hmidi;
1397 unsigned long flags;
1398 u32 ie;
1399
1400 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1401 hdsp = hmidi->hdsp;
1402 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1403 spin_lock_irqsave (&hdsp->lock, flags);
1404 if (up) {
1405 if (!(hdsp->control_register & ie)) {
1406 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1407 hdsp->control_register |= ie;
1408 }
1409 } else {
1410 hdsp->control_register &= ~ie;
1411 tasklet_kill(&hdsp->midi_tasklet);
1412 }
1413
1414 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1415 spin_unlock_irqrestore (&hdsp->lock, flags);
1416 }
1417
1418 static void snd_hdsp_midi_output_timer(unsigned long data)
1419 {
1420 struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1421 unsigned long flags;
1422
1423 snd_hdsp_midi_output_write(hmidi);
1424 spin_lock_irqsave (&hmidi->lock, flags);
1425
1426 /* this does not bump hmidi->istimer, because the
1427 kernel automatically removed the timer when it
1428 expired, and we are now adding it back, thus
1429 leaving istimer wherever it was set before.
1430 */
1431
1432 if (hmidi->istimer)
1433 mod_timer(&hmidi->timer, 1 + jiffies);
1434
1435 spin_unlock_irqrestore (&hmidi->lock, flags);
1436 }
1437
1438 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1439 {
1440 struct hdsp_midi *hmidi;
1441 unsigned long flags;
1442
1443 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1444 spin_lock_irqsave (&hmidi->lock, flags);
1445 if (up) {
1446 if (!hmidi->istimer) {
1447 setup_timer(&hmidi->timer, snd_hdsp_midi_output_timer,
1448 (unsigned long) hmidi);
1449 mod_timer(&hmidi->timer, 1 + jiffies);
1450 hmidi->istimer++;
1451 }
1452 } else {
1453 if (hmidi->istimer && --hmidi->istimer <= 0)
1454 del_timer (&hmidi->timer);
1455 }
1456 spin_unlock_irqrestore (&hmidi->lock, flags);
1457 if (up)
1458 snd_hdsp_midi_output_write(hmidi);
1459 }
1460
1461 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1462 {
1463 struct hdsp_midi *hmidi;
1464
1465 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1466 spin_lock_irq (&hmidi->lock);
1467 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1468 hmidi->input = substream;
1469 spin_unlock_irq (&hmidi->lock);
1470
1471 return 0;
1472 }
1473
1474 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1475 {
1476 struct hdsp_midi *hmidi;
1477
1478 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1479 spin_lock_irq (&hmidi->lock);
1480 hmidi->output = substream;
1481 spin_unlock_irq (&hmidi->lock);
1482
1483 return 0;
1484 }
1485
1486 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1487 {
1488 struct hdsp_midi *hmidi;
1489
1490 snd_hdsp_midi_input_trigger (substream, 0);
1491
1492 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1493 spin_lock_irq (&hmidi->lock);
1494 hmidi->input = NULL;
1495 spin_unlock_irq (&hmidi->lock);
1496
1497 return 0;
1498 }
1499
1500 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1501 {
1502 struct hdsp_midi *hmidi;
1503
1504 snd_hdsp_midi_output_trigger (substream, 0);
1505
1506 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1507 spin_lock_irq (&hmidi->lock);
1508 hmidi->output = NULL;
1509 spin_unlock_irq (&hmidi->lock);
1510
1511 return 0;
1512 }
1513
1514 static struct snd_rawmidi_ops snd_hdsp_midi_output =
1515 {
1516 .open = snd_hdsp_midi_output_open,
1517 .close = snd_hdsp_midi_output_close,
1518 .trigger = snd_hdsp_midi_output_trigger,
1519 };
1520
1521 static struct snd_rawmidi_ops snd_hdsp_midi_input =
1522 {
1523 .open = snd_hdsp_midi_input_open,
1524 .close = snd_hdsp_midi_input_close,
1525 .trigger = snd_hdsp_midi_input_trigger,
1526 };
1527
1528 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1529 {
1530 char buf[40];
1531
1532 hdsp->midi[id].id = id;
1533 hdsp->midi[id].rmidi = NULL;
1534 hdsp->midi[id].input = NULL;
1535 hdsp->midi[id].output = NULL;
1536 hdsp->midi[id].hdsp = hdsp;
1537 hdsp->midi[id].istimer = 0;
1538 hdsp->midi[id].pending = 0;
1539 spin_lock_init (&hdsp->midi[id].lock);
1540
1541 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1542 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1543 return -1;
1544
1545 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1546 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1547
1548 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1549 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1550
1551 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1552 SNDRV_RAWMIDI_INFO_INPUT |
1553 SNDRV_RAWMIDI_INFO_DUPLEX;
1554
1555 return 0;
1556 }
1557
1558 /*-----------------------------------------------------------------------------
1559 Control Interface
1560 ----------------------------------------------------------------------------*/
1561
1562 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1563 {
1564 u32 val = 0;
1565 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1566 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1567 if (val & HDSP_SPDIFProfessional)
1568 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1569 else
1570 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1571 return val;
1572 }
1573
1574 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1575 {
1576 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1577 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1578 if (val & HDSP_SPDIFProfessional)
1579 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1580 else
1581 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1582 }
1583
1584 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1585 {
1586 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1587 uinfo->count = 1;
1588 return 0;
1589 }
1590
1591 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1592 {
1593 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1594
1595 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1596 return 0;
1597 }
1598
1599 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1600 {
1601 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1602 int change;
1603 u32 val;
1604
1605 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1606 spin_lock_irq(&hdsp->lock);
1607 change = val != hdsp->creg_spdif;
1608 hdsp->creg_spdif = val;
1609 spin_unlock_irq(&hdsp->lock);
1610 return change;
1611 }
1612
1613 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1614 {
1615 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1616 uinfo->count = 1;
1617 return 0;
1618 }
1619
1620 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1621 {
1622 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1623
1624 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1625 return 0;
1626 }
1627
1628 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1629 {
1630 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1631 int change;
1632 u32 val;
1633
1634 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1635 spin_lock_irq(&hdsp->lock);
1636 change = val != hdsp->creg_spdif_stream;
1637 hdsp->creg_spdif_stream = val;
1638 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1639 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1640 spin_unlock_irq(&hdsp->lock);
1641 return change;
1642 }
1643
1644 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1645 {
1646 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1647 uinfo->count = 1;
1648 return 0;
1649 }
1650
1651 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1652 {
1653 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1654 return 0;
1655 }
1656
1657 #define HDSP_SPDIF_IN(xname, xindex) \
1658 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1659 .name = xname, \
1660 .index = xindex, \
1661 .info = snd_hdsp_info_spdif_in, \
1662 .get = snd_hdsp_get_spdif_in, \
1663 .put = snd_hdsp_put_spdif_in }
1664
1665 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1666 {
1667 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1668 }
1669
1670 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1671 {
1672 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1673 hdsp->control_register |= hdsp_encode_spdif_in(in);
1674 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1675 return 0;
1676 }
1677
1678 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1679 {
1680 static const char * const texts[4] = {
1681 "Optical", "Coaxial", "Internal", "AES"
1682 };
1683 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1684
1685 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1686 texts);
1687 }
1688
1689 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1690 {
1691 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1692
1693 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1694 return 0;
1695 }
1696
1697 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1698 {
1699 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1700 int change;
1701 unsigned int val;
1702
1703 if (!snd_hdsp_use_is_exclusive(hdsp))
1704 return -EBUSY;
1705 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1706 spin_lock_irq(&hdsp->lock);
1707 change = val != hdsp_spdif_in(hdsp);
1708 if (change)
1709 hdsp_set_spdif_input(hdsp, val);
1710 spin_unlock_irq(&hdsp->lock);
1711 return change;
1712 }
1713
1714 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1715 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1716 .name = xname, \
1717 .private_value = xindex, \
1718 .info = snd_hdsp_info_toggle_setting, \
1719 .get = snd_hdsp_get_toggle_setting, \
1720 .put = snd_hdsp_put_toggle_setting \
1721 }
1722
1723 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1724 {
1725 return (hdsp->control_register & regmask) ? 1 : 0;
1726 }
1727
1728 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1729 {
1730 if (out)
1731 hdsp->control_register |= regmask;
1732 else
1733 hdsp->control_register &= ~regmask;
1734 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1735
1736 return 0;
1737 }
1738
1739 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1740
1741 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1742 struct snd_ctl_elem_value *ucontrol)
1743 {
1744 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1745 u32 regmask = kcontrol->private_value;
1746
1747 spin_lock_irq(&hdsp->lock);
1748 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1749 spin_unlock_irq(&hdsp->lock);
1750 return 0;
1751 }
1752
1753 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1754 struct snd_ctl_elem_value *ucontrol)
1755 {
1756 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1757 u32 regmask = kcontrol->private_value;
1758 int change;
1759 unsigned int val;
1760
1761 if (!snd_hdsp_use_is_exclusive(hdsp))
1762 return -EBUSY;
1763 val = ucontrol->value.integer.value[0] & 1;
1764 spin_lock_irq(&hdsp->lock);
1765 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1766 if (change)
1767 hdsp_set_toggle_setting(hdsp, regmask, val);
1768 spin_unlock_irq(&hdsp->lock);
1769 return change;
1770 }
1771
1772 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1773 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1774 .name = xname, \
1775 .index = xindex, \
1776 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1777 .info = snd_hdsp_info_spdif_sample_rate, \
1778 .get = snd_hdsp_get_spdif_sample_rate \
1779 }
1780
1781 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1782 {
1783 static const char * const texts[] = {
1784 "32000", "44100", "48000", "64000", "88200", "96000",
1785 "None", "128000", "176400", "192000"
1786 };
1787 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1788
1789 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1790 texts);
1791 }
1792
1793 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1794 {
1795 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1796
1797 switch (hdsp_spdif_sample_rate(hdsp)) {
1798 case 32000:
1799 ucontrol->value.enumerated.item[0] = 0;
1800 break;
1801 case 44100:
1802 ucontrol->value.enumerated.item[0] = 1;
1803 break;
1804 case 48000:
1805 ucontrol->value.enumerated.item[0] = 2;
1806 break;
1807 case 64000:
1808 ucontrol->value.enumerated.item[0] = 3;
1809 break;
1810 case 88200:
1811 ucontrol->value.enumerated.item[0] = 4;
1812 break;
1813 case 96000:
1814 ucontrol->value.enumerated.item[0] = 5;
1815 break;
1816 case 128000:
1817 ucontrol->value.enumerated.item[0] = 7;
1818 break;
1819 case 176400:
1820 ucontrol->value.enumerated.item[0] = 8;
1821 break;
1822 case 192000:
1823 ucontrol->value.enumerated.item[0] = 9;
1824 break;
1825 default:
1826 ucontrol->value.enumerated.item[0] = 6;
1827 }
1828 return 0;
1829 }
1830
1831 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1832 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1833 .name = xname, \
1834 .index = xindex, \
1835 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1836 .info = snd_hdsp_info_system_sample_rate, \
1837 .get = snd_hdsp_get_system_sample_rate \
1838 }
1839
1840 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1841 {
1842 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1843 uinfo->count = 1;
1844 return 0;
1845 }
1846
1847 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1848 {
1849 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1850
1851 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1852 return 0;
1853 }
1854
1855 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1856 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1857 .name = xname, \
1858 .index = xindex, \
1859 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1860 .info = snd_hdsp_info_autosync_sample_rate, \
1861 .get = snd_hdsp_get_autosync_sample_rate \
1862 }
1863
1864 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1865 {
1866 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1867 static const char * const texts[] = {
1868 "32000", "44100", "48000", "64000", "88200", "96000",
1869 "None", "128000", "176400", "192000"
1870 };
1871
1872 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1873 texts);
1874 }
1875
1876 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1877 {
1878 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1879
1880 switch (hdsp_external_sample_rate(hdsp)) {
1881 case 32000:
1882 ucontrol->value.enumerated.item[0] = 0;
1883 break;
1884 case 44100:
1885 ucontrol->value.enumerated.item[0] = 1;
1886 break;
1887 case 48000:
1888 ucontrol->value.enumerated.item[0] = 2;
1889 break;
1890 case 64000:
1891 ucontrol->value.enumerated.item[0] = 3;
1892 break;
1893 case 88200:
1894 ucontrol->value.enumerated.item[0] = 4;
1895 break;
1896 case 96000:
1897 ucontrol->value.enumerated.item[0] = 5;
1898 break;
1899 case 128000:
1900 ucontrol->value.enumerated.item[0] = 7;
1901 break;
1902 case 176400:
1903 ucontrol->value.enumerated.item[0] = 8;
1904 break;
1905 case 192000:
1906 ucontrol->value.enumerated.item[0] = 9;
1907 break;
1908 default:
1909 ucontrol->value.enumerated.item[0] = 6;
1910 }
1911 return 0;
1912 }
1913
1914 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1915 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1916 .name = xname, \
1917 .index = xindex, \
1918 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1919 .info = snd_hdsp_info_system_clock_mode, \
1920 .get = snd_hdsp_get_system_clock_mode \
1921 }
1922
1923 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1924 {
1925 if (hdsp->control_register & HDSP_ClockModeMaster)
1926 return 0;
1927 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1928 return 0;
1929 return 1;
1930 }
1931
1932 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1933 {
1934 static const char * const texts[] = {"Master", "Slave" };
1935
1936 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1937 }
1938
1939 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1940 {
1941 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1942
1943 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1944 return 0;
1945 }
1946
1947 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1948 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1949 .name = xname, \
1950 .index = xindex, \
1951 .info = snd_hdsp_info_clock_source, \
1952 .get = snd_hdsp_get_clock_source, \
1953 .put = snd_hdsp_put_clock_source \
1954 }
1955
1956 static int hdsp_clock_source(struct hdsp *hdsp)
1957 {
1958 if (hdsp->control_register & HDSP_ClockModeMaster) {
1959 switch (hdsp->system_sample_rate) {
1960 case 32000:
1961 return 1;
1962 case 44100:
1963 return 2;
1964 case 48000:
1965 return 3;
1966 case 64000:
1967 return 4;
1968 case 88200:
1969 return 5;
1970 case 96000:
1971 return 6;
1972 case 128000:
1973 return 7;
1974 case 176400:
1975 return 8;
1976 case 192000:
1977 return 9;
1978 default:
1979 return 3;
1980 }
1981 } else {
1982 return 0;
1983 }
1984 }
1985
1986 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1987 {
1988 int rate;
1989 switch (mode) {
1990 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1991 if (hdsp_external_sample_rate(hdsp) != 0) {
1992 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1993 hdsp->control_register &= ~HDSP_ClockModeMaster;
1994 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1995 return 0;
1996 }
1997 }
1998 return -1;
1999 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2000 rate = 32000;
2001 break;
2002 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2003 rate = 44100;
2004 break;
2005 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2006 rate = 48000;
2007 break;
2008 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2009 rate = 64000;
2010 break;
2011 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2012 rate = 88200;
2013 break;
2014 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2015 rate = 96000;
2016 break;
2017 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2018 rate = 128000;
2019 break;
2020 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2021 rate = 176400;
2022 break;
2023 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2024 rate = 192000;
2025 break;
2026 default:
2027 rate = 48000;
2028 }
2029 hdsp->control_register |= HDSP_ClockModeMaster;
2030 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2031 hdsp_set_rate(hdsp, rate, 1);
2032 return 0;
2033 }
2034
2035 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2036 {
2037 static const char * const texts[] = {
2038 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2039 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2040 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2041 "Internal 192.0 KHz"
2042 };
2043 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2044
2045 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2046 texts);
2047 }
2048
2049 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2050 {
2051 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2052
2053 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2054 return 0;
2055 }
2056
2057 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2058 {
2059 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2060 int change;
2061 int val;
2062
2063 if (!snd_hdsp_use_is_exclusive(hdsp))
2064 return -EBUSY;
2065 val = ucontrol->value.enumerated.item[0];
2066 if (val < 0) val = 0;
2067 if (hdsp->io_type == H9632) {
2068 if (val > 9)
2069 val = 9;
2070 } else {
2071 if (val > 6)
2072 val = 6;
2073 }
2074 spin_lock_irq(&hdsp->lock);
2075 if (val != hdsp_clock_source(hdsp))
2076 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2077 else
2078 change = 0;
2079 spin_unlock_irq(&hdsp->lock);
2080 return change;
2081 }
2082
2083 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2084
2085 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2086 {
2087 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2088
2089 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2090 return 0;
2091 }
2092
2093 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2094 {
2095 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2096 int change;
2097
2098 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2099 if (change)
2100 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2101 return change;
2102 }
2103
2104 #define HDSP_DA_GAIN(xname, xindex) \
2105 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2106 .name = xname, \
2107 .index = xindex, \
2108 .info = snd_hdsp_info_da_gain, \
2109 .get = snd_hdsp_get_da_gain, \
2110 .put = snd_hdsp_put_da_gain \
2111 }
2112
2113 static int hdsp_da_gain(struct hdsp *hdsp)
2114 {
2115 switch (hdsp->control_register & HDSP_DAGainMask) {
2116 case HDSP_DAGainHighGain:
2117 return 0;
2118 case HDSP_DAGainPlus4dBu:
2119 return 1;
2120 case HDSP_DAGainMinus10dBV:
2121 return 2;
2122 default:
2123 return 1;
2124 }
2125 }
2126
2127 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2128 {
2129 hdsp->control_register &= ~HDSP_DAGainMask;
2130 switch (mode) {
2131 case 0:
2132 hdsp->control_register |= HDSP_DAGainHighGain;
2133 break;
2134 case 1:
2135 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2136 break;
2137 case 2:
2138 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2139 break;
2140 default:
2141 return -1;
2142
2143 }
2144 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2145 return 0;
2146 }
2147
2148 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2149 {
2150 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2151
2152 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2153 }
2154
2155 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2156 {
2157 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2158
2159 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2160 return 0;
2161 }
2162
2163 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2164 {
2165 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2166 int change;
2167 int val;
2168
2169 if (!snd_hdsp_use_is_exclusive(hdsp))
2170 return -EBUSY;
2171 val = ucontrol->value.enumerated.item[0];
2172 if (val < 0) val = 0;
2173 if (val > 2) val = 2;
2174 spin_lock_irq(&hdsp->lock);
2175 if (val != hdsp_da_gain(hdsp))
2176 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2177 else
2178 change = 0;
2179 spin_unlock_irq(&hdsp->lock);
2180 return change;
2181 }
2182
2183 #define HDSP_AD_GAIN(xname, xindex) \
2184 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2185 .name = xname, \
2186 .index = xindex, \
2187 .info = snd_hdsp_info_ad_gain, \
2188 .get = snd_hdsp_get_ad_gain, \
2189 .put = snd_hdsp_put_ad_gain \
2190 }
2191
2192 static int hdsp_ad_gain(struct hdsp *hdsp)
2193 {
2194 switch (hdsp->control_register & HDSP_ADGainMask) {
2195 case HDSP_ADGainMinus10dBV:
2196 return 0;
2197 case HDSP_ADGainPlus4dBu:
2198 return 1;
2199 case HDSP_ADGainLowGain:
2200 return 2;
2201 default:
2202 return 1;
2203 }
2204 }
2205
2206 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2207 {
2208 hdsp->control_register &= ~HDSP_ADGainMask;
2209 switch (mode) {
2210 case 0:
2211 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2212 break;
2213 case 1:
2214 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2215 break;
2216 case 2:
2217 hdsp->control_register |= HDSP_ADGainLowGain;
2218 break;
2219 default:
2220 return -1;
2221
2222 }
2223 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2224 return 0;
2225 }
2226
2227 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2228 {
2229 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2230
2231 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2232 }
2233
2234 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2235 {
2236 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2237
2238 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2239 return 0;
2240 }
2241
2242 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2243 {
2244 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2245 int change;
2246 int val;
2247
2248 if (!snd_hdsp_use_is_exclusive(hdsp))
2249 return -EBUSY;
2250 val = ucontrol->value.enumerated.item[0];
2251 if (val < 0) val = 0;
2252 if (val > 2) val = 2;
2253 spin_lock_irq(&hdsp->lock);
2254 if (val != hdsp_ad_gain(hdsp))
2255 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2256 else
2257 change = 0;
2258 spin_unlock_irq(&hdsp->lock);
2259 return change;
2260 }
2261
2262 #define HDSP_PHONE_GAIN(xname, xindex) \
2263 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2264 .name = xname, \
2265 .index = xindex, \
2266 .info = snd_hdsp_info_phone_gain, \
2267 .get = snd_hdsp_get_phone_gain, \
2268 .put = snd_hdsp_put_phone_gain \
2269 }
2270
2271 static int hdsp_phone_gain(struct hdsp *hdsp)
2272 {
2273 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2274 case HDSP_PhoneGain0dB:
2275 return 0;
2276 case HDSP_PhoneGainMinus6dB:
2277 return 1;
2278 case HDSP_PhoneGainMinus12dB:
2279 return 2;
2280 default:
2281 return 0;
2282 }
2283 }
2284
2285 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2286 {
2287 hdsp->control_register &= ~HDSP_PhoneGainMask;
2288 switch (mode) {
2289 case 0:
2290 hdsp->control_register |= HDSP_PhoneGain0dB;
2291 break;
2292 case 1:
2293 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2294 break;
2295 case 2:
2296 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2297 break;
2298 default:
2299 return -1;
2300
2301 }
2302 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2303 return 0;
2304 }
2305
2306 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2307 {
2308 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2309
2310 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2311 }
2312
2313 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2314 {
2315 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2316
2317 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2318 return 0;
2319 }
2320
2321 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2322 {
2323 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2324 int change;
2325 int val;
2326
2327 if (!snd_hdsp_use_is_exclusive(hdsp))
2328 return -EBUSY;
2329 val = ucontrol->value.enumerated.item[0];
2330 if (val < 0) val = 0;
2331 if (val > 2) val = 2;
2332 spin_lock_irq(&hdsp->lock);
2333 if (val != hdsp_phone_gain(hdsp))
2334 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2335 else
2336 change = 0;
2337 spin_unlock_irq(&hdsp->lock);
2338 return change;
2339 }
2340
2341 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2342 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2343 .name = xname, \
2344 .index = xindex, \
2345 .info = snd_hdsp_info_pref_sync_ref, \
2346 .get = snd_hdsp_get_pref_sync_ref, \
2347 .put = snd_hdsp_put_pref_sync_ref \
2348 }
2349
2350 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2351 {
2352 /* Notice that this looks at the requested sync source,
2353 not the one actually in use.
2354 */
2355
2356 switch (hdsp->control_register & HDSP_SyncRefMask) {
2357 case HDSP_SyncRef_ADAT1:
2358 return HDSP_SYNC_FROM_ADAT1;
2359 case HDSP_SyncRef_ADAT2:
2360 return HDSP_SYNC_FROM_ADAT2;
2361 case HDSP_SyncRef_ADAT3:
2362 return HDSP_SYNC_FROM_ADAT3;
2363 case HDSP_SyncRef_SPDIF:
2364 return HDSP_SYNC_FROM_SPDIF;
2365 case HDSP_SyncRef_WORD:
2366 return HDSP_SYNC_FROM_WORD;
2367 case HDSP_SyncRef_ADAT_SYNC:
2368 return HDSP_SYNC_FROM_ADAT_SYNC;
2369 default:
2370 return HDSP_SYNC_FROM_WORD;
2371 }
2372 return 0;
2373 }
2374
2375 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2376 {
2377 hdsp->control_register &= ~HDSP_SyncRefMask;
2378 switch (pref) {
2379 case HDSP_SYNC_FROM_ADAT1:
2380 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2381 break;
2382 case HDSP_SYNC_FROM_ADAT2:
2383 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2384 break;
2385 case HDSP_SYNC_FROM_ADAT3:
2386 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2387 break;
2388 case HDSP_SYNC_FROM_SPDIF:
2389 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2390 break;
2391 case HDSP_SYNC_FROM_WORD:
2392 hdsp->control_register |= HDSP_SyncRef_WORD;
2393 break;
2394 case HDSP_SYNC_FROM_ADAT_SYNC:
2395 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2396 break;
2397 default:
2398 return -1;
2399 }
2400 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2401 return 0;
2402 }
2403
2404 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2405 {
2406 static const char * const texts[] = {
2407 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2408 };
2409 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2410 int num_items;
2411
2412 switch (hdsp->io_type) {
2413 case Digiface:
2414 case H9652:
2415 num_items = 6;
2416 break;
2417 case Multiface:
2418 num_items = 4;
2419 break;
2420 case H9632:
2421 num_items = 3;
2422 break;
2423 default:
2424 return -EINVAL;
2425 }
2426
2427 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2428 }
2429
2430 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2431 {
2432 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2433
2434 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2435 return 0;
2436 }
2437
2438 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2439 {
2440 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2441 int change, max;
2442 unsigned int val;
2443
2444 if (!snd_hdsp_use_is_exclusive(hdsp))
2445 return -EBUSY;
2446
2447 switch (hdsp->io_type) {
2448 case Digiface:
2449 case H9652:
2450 max = 6;
2451 break;
2452 case Multiface:
2453 max = 4;
2454 break;
2455 case H9632:
2456 max = 3;
2457 break;
2458 default:
2459 return -EIO;
2460 }
2461
2462 val = ucontrol->value.enumerated.item[0] % max;
2463 spin_lock_irq(&hdsp->lock);
2464 change = (int)val != hdsp_pref_sync_ref(hdsp);
2465 hdsp_set_pref_sync_ref(hdsp, val);
2466 spin_unlock_irq(&hdsp->lock);
2467 return change;
2468 }
2469
2470 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2471 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2472 .name = xname, \
2473 .index = xindex, \
2474 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2475 .info = snd_hdsp_info_autosync_ref, \
2476 .get = snd_hdsp_get_autosync_ref, \
2477 }
2478
2479 static int hdsp_autosync_ref(struct hdsp *hdsp)
2480 {
2481 /* This looks at the autosync selected sync reference */
2482 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2483
2484 switch (status2 & HDSP_SelSyncRefMask) {
2485 case HDSP_SelSyncRef_WORD:
2486 return HDSP_AUTOSYNC_FROM_WORD;
2487 case HDSP_SelSyncRef_ADAT_SYNC:
2488 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2489 case HDSP_SelSyncRef_SPDIF:
2490 return HDSP_AUTOSYNC_FROM_SPDIF;
2491 case HDSP_SelSyncRefMask:
2492 return HDSP_AUTOSYNC_FROM_NONE;
2493 case HDSP_SelSyncRef_ADAT1:
2494 return HDSP_AUTOSYNC_FROM_ADAT1;
2495 case HDSP_SelSyncRef_ADAT2:
2496 return HDSP_AUTOSYNC_FROM_ADAT2;
2497 case HDSP_SelSyncRef_ADAT3:
2498 return HDSP_AUTOSYNC_FROM_ADAT3;
2499 default:
2500 return HDSP_AUTOSYNC_FROM_WORD;
2501 }
2502 return 0;
2503 }
2504
2505 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2506 {
2507 static const char * const texts[] = {
2508 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2509 };
2510
2511 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2512 }
2513
2514 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2515 {
2516 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2517
2518 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2519 return 0;
2520 }
2521
2522 #define HDSP_PRECISE_POINTER(xname, xindex) \
2523 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2524 .name = xname, \
2525 .index = xindex, \
2526 .info = snd_hdsp_info_precise_pointer, \
2527 .get = snd_hdsp_get_precise_pointer, \
2528 .put = snd_hdsp_put_precise_pointer \
2529 }
2530
2531 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2532 {
2533 if (precise)
2534 hdsp->precise_ptr = 1;
2535 else
2536 hdsp->precise_ptr = 0;
2537 return 0;
2538 }
2539
2540 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2541
2542 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2543 {
2544 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2545
2546 spin_lock_irq(&hdsp->lock);
2547 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2548 spin_unlock_irq(&hdsp->lock);
2549 return 0;
2550 }
2551
2552 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2553 {
2554 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2555 int change;
2556 unsigned int val;
2557
2558 if (!snd_hdsp_use_is_exclusive(hdsp))
2559 return -EBUSY;
2560 val = ucontrol->value.integer.value[0] & 1;
2561 spin_lock_irq(&hdsp->lock);
2562 change = (int)val != hdsp->precise_ptr;
2563 hdsp_set_precise_pointer(hdsp, val);
2564 spin_unlock_irq(&hdsp->lock);
2565 return change;
2566 }
2567
2568 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2569 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2570 .name = xname, \
2571 .index = xindex, \
2572 .info = snd_hdsp_info_use_midi_tasklet, \
2573 .get = snd_hdsp_get_use_midi_tasklet, \
2574 .put = snd_hdsp_put_use_midi_tasklet \
2575 }
2576
2577 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2578 {
2579 if (use_tasklet)
2580 hdsp->use_midi_tasklet = 1;
2581 else
2582 hdsp->use_midi_tasklet = 0;
2583 return 0;
2584 }
2585
2586 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
2587
2588 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2589 {
2590 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2591
2592 spin_lock_irq(&hdsp->lock);
2593 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2594 spin_unlock_irq(&hdsp->lock);
2595 return 0;
2596 }
2597
2598 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2599 {
2600 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2601 int change;
2602 unsigned int val;
2603
2604 if (!snd_hdsp_use_is_exclusive(hdsp))
2605 return -EBUSY;
2606 val = ucontrol->value.integer.value[0] & 1;
2607 spin_lock_irq(&hdsp->lock);
2608 change = (int)val != hdsp->use_midi_tasklet;
2609 hdsp_set_use_midi_tasklet(hdsp, val);
2610 spin_unlock_irq(&hdsp->lock);
2611 return change;
2612 }
2613
2614 #define HDSP_MIXER(xname, xindex) \
2615 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2616 .name = xname, \
2617 .index = xindex, \
2618 .device = 0, \
2619 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2620 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2621 .info = snd_hdsp_info_mixer, \
2622 .get = snd_hdsp_get_mixer, \
2623 .put = snd_hdsp_put_mixer \
2624 }
2625
2626 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2627 {
2628 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2629 uinfo->count = 3;
2630 uinfo->value.integer.min = 0;
2631 uinfo->value.integer.max = 65536;
2632 uinfo->value.integer.step = 1;
2633 return 0;
2634 }
2635
2636 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2637 {
2638 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2639 int source;
2640 int destination;
2641 int addr;
2642
2643 source = ucontrol->value.integer.value[0];
2644 destination = ucontrol->value.integer.value[1];
2645
2646 if (source >= hdsp->max_channels)
2647 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2648 else
2649 addr = hdsp_input_to_output_key(hdsp,source, destination);
2650
2651 spin_lock_irq(&hdsp->lock);
2652 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2653 spin_unlock_irq(&hdsp->lock);
2654 return 0;
2655 }
2656
2657 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2658 {
2659 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2660 int change;
2661 int source;
2662 int destination;
2663 int gain;
2664 int addr;
2665
2666 if (!snd_hdsp_use_is_exclusive(hdsp))
2667 return -EBUSY;
2668
2669 source = ucontrol->value.integer.value[0];
2670 destination = ucontrol->value.integer.value[1];
2671
2672 if (source >= hdsp->max_channels)
2673 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2674 else
2675 addr = hdsp_input_to_output_key(hdsp,source, destination);
2676
2677 gain = ucontrol->value.integer.value[2];
2678
2679 spin_lock_irq(&hdsp->lock);
2680 change = gain != hdsp_read_gain(hdsp, addr);
2681 if (change)
2682 hdsp_write_gain(hdsp, addr, gain);
2683 spin_unlock_irq(&hdsp->lock);
2684 return change;
2685 }
2686
2687 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2688 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2689 .name = xname, \
2690 .index = xindex, \
2691 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2692 .info = snd_hdsp_info_sync_check, \
2693 .get = snd_hdsp_get_wc_sync_check \
2694 }
2695
2696 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2697 {
2698 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2699
2700 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2701 }
2702
2703 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2704 {
2705 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2706 if (status2 & HDSP_wc_lock) {
2707 if (status2 & HDSP_wc_sync)
2708 return 2;
2709 else
2710 return 1;
2711 } else
2712 return 0;
2713 return 0;
2714 }
2715
2716 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2717 {
2718 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2719
2720 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2721 return 0;
2722 }
2723
2724 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2725 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2726 .name = xname, \
2727 .index = xindex, \
2728 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2729 .info = snd_hdsp_info_sync_check, \
2730 .get = snd_hdsp_get_spdif_sync_check \
2731 }
2732
2733 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2734 {
2735 int status = hdsp_read(hdsp, HDSP_statusRegister);
2736 if (status & HDSP_SPDIFErrorFlag)
2737 return 0;
2738 else {
2739 if (status & HDSP_SPDIFSync)
2740 return 2;
2741 else
2742 return 1;
2743 }
2744 return 0;
2745 }
2746
2747 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2748 {
2749 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2750
2751 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2752 return 0;
2753 }
2754
2755 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2756 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2757 .name = xname, \
2758 .index = xindex, \
2759 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2760 .info = snd_hdsp_info_sync_check, \
2761 .get = snd_hdsp_get_adatsync_sync_check \
2762 }
2763
2764 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2765 {
2766 int status = hdsp_read(hdsp, HDSP_statusRegister);
2767 if (status & HDSP_TimecodeLock) {
2768 if (status & HDSP_TimecodeSync)
2769 return 2;
2770 else
2771 return 1;
2772 } else
2773 return 0;
2774 }
2775
2776 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2777 {
2778 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2779
2780 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2781 return 0;
2782 }
2783
2784 #define HDSP_ADAT_SYNC_CHECK \
2785 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2786 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2787 .info = snd_hdsp_info_sync_check, \
2788 .get = snd_hdsp_get_adat_sync_check \
2789 }
2790
2791 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2792 {
2793 int status = hdsp_read(hdsp, HDSP_statusRegister);
2794
2795 if (status & (HDSP_Lock0>>idx)) {
2796 if (status & (HDSP_Sync0>>idx))
2797 return 2;
2798 else
2799 return 1;
2800 } else
2801 return 0;
2802 }
2803
2804 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2805 {
2806 int offset;
2807 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2808
2809 offset = ucontrol->id.index - 1;
2810 if (snd_BUG_ON(offset < 0))
2811 return -EINVAL;
2812
2813 switch (hdsp->io_type) {
2814 case Digiface:
2815 case H9652:
2816 if (offset >= 3)
2817 return -EINVAL;
2818 break;
2819 case Multiface:
2820 case H9632:
2821 if (offset >= 1)
2822 return -EINVAL;
2823 break;
2824 default:
2825 return -EIO;
2826 }
2827
2828 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2829 return 0;
2830 }
2831
2832 #define HDSP_DDS_OFFSET(xname, xindex) \
2833 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2834 .name = xname, \
2835 .index = xindex, \
2836 .info = snd_hdsp_info_dds_offset, \
2837 .get = snd_hdsp_get_dds_offset, \
2838 .put = snd_hdsp_put_dds_offset \
2839 }
2840
2841 static int hdsp_dds_offset(struct hdsp *hdsp)
2842 {
2843 u64 n;
2844 unsigned int dds_value = hdsp->dds_value;
2845 int system_sample_rate = hdsp->system_sample_rate;
2846
2847 if (!dds_value)
2848 return 0;
2849
2850 n = DDS_NUMERATOR;
2851 /*
2852 * dds_value = n / rate
2853 * rate = n / dds_value
2854 */
2855 n = div_u64(n, dds_value);
2856 if (system_sample_rate >= 112000)
2857 n *= 4;
2858 else if (system_sample_rate >= 56000)
2859 n *= 2;
2860 return ((int)n) - system_sample_rate;
2861 }
2862
2863 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2864 {
2865 int rate = hdsp->system_sample_rate + offset_hz;
2866 hdsp_set_dds_value(hdsp, rate);
2867 return 0;
2868 }
2869
2870 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2871 {
2872 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2873 uinfo->count = 1;
2874 uinfo->value.integer.min = -5000;
2875 uinfo->value.integer.max = 5000;
2876 return 0;
2877 }
2878
2879 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2880 {
2881 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2882
2883 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2884 return 0;
2885 }
2886
2887 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2888 {
2889 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2890 int change;
2891 int val;
2892
2893 if (!snd_hdsp_use_is_exclusive(hdsp))
2894 return -EBUSY;
2895 val = ucontrol->value.integer.value[0];
2896 spin_lock_irq(&hdsp->lock);
2897 if (val != hdsp_dds_offset(hdsp))
2898 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2899 else
2900 change = 0;
2901 spin_unlock_irq(&hdsp->lock);
2902 return change;
2903 }
2904
2905 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2906 HDSP_DA_GAIN("DA Gain", 0),
2907 HDSP_AD_GAIN("AD Gain", 0),
2908 HDSP_PHONE_GAIN("Phones Gain", 0),
2909 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2910 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2911 };
2912
2913 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2914 {
2915 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2916 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2917 .info = snd_hdsp_control_spdif_info,
2918 .get = snd_hdsp_control_spdif_get,
2919 .put = snd_hdsp_control_spdif_put,
2920 },
2921 {
2922 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2923 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2924 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2925 .info = snd_hdsp_control_spdif_stream_info,
2926 .get = snd_hdsp_control_spdif_stream_get,
2927 .put = snd_hdsp_control_spdif_stream_put,
2928 },
2929 {
2930 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2931 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2932 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2933 .info = snd_hdsp_control_spdif_mask_info,
2934 .get = snd_hdsp_control_spdif_mask_get,
2935 .private_value = IEC958_AES0_NONAUDIO |
2936 IEC958_AES0_PROFESSIONAL |
2937 IEC958_AES0_CON_EMPHASIS,
2938 },
2939 {
2940 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2941 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2942 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2943 .info = snd_hdsp_control_spdif_mask_info,
2944 .get = snd_hdsp_control_spdif_mask_get,
2945 .private_value = IEC958_AES0_NONAUDIO |
2946 IEC958_AES0_PROFESSIONAL |
2947 IEC958_AES0_PRO_EMPHASIS,
2948 },
2949 HDSP_MIXER("Mixer", 0),
2950 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2951 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2952 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2953 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2954 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2955 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2956 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2957 {
2958 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2959 .name = "Sample Clock Source Locking",
2960 .info = snd_hdsp_info_clock_source_lock,
2961 .get = snd_hdsp_get_clock_source_lock,
2962 .put = snd_hdsp_put_clock_source_lock,
2963 },
2964 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2965 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2966 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2967 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2968 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2969 /* 'External Rate' complies with the alsa control naming scheme */
2970 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2971 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2972 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2973 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2974 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2975 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2976 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2977 };
2978
2979
2980 static int hdsp_rpm_input12(struct hdsp *hdsp)
2981 {
2982 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2983 case HDSP_RPM_Inp12_Phon_6dB:
2984 return 0;
2985 case HDSP_RPM_Inp12_Phon_n6dB:
2986 return 2;
2987 case HDSP_RPM_Inp12_Line_0dB:
2988 return 3;
2989 case HDSP_RPM_Inp12_Line_n6dB:
2990 return 4;
2991 }
2992 return 1;
2993 }
2994
2995
2996 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2997 {
2998 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2999
3000 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
3001 return 0;
3002 }
3003
3004
3005 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
3006 {
3007 hdsp->control_register &= ~HDSP_RPM_Inp12;
3008 switch (mode) {
3009 case 0:
3010 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
3011 break;
3012 case 1:
3013 break;
3014 case 2:
3015 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3016 break;
3017 case 3:
3018 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3019 break;
3020 case 4:
3021 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3022 break;
3023 default:
3024 return -1;
3025 }
3026
3027 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3028 return 0;
3029 }
3030
3031
3032 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3033 {
3034 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3035 int change;
3036 int val;
3037
3038 if (!snd_hdsp_use_is_exclusive(hdsp))
3039 return -EBUSY;
3040 val = ucontrol->value.enumerated.item[0];
3041 if (val < 0)
3042 val = 0;
3043 if (val > 4)
3044 val = 4;
3045 spin_lock_irq(&hdsp->lock);
3046 if (val != hdsp_rpm_input12(hdsp))
3047 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3048 else
3049 change = 0;
3050 spin_unlock_irq(&hdsp->lock);
3051 return change;
3052 }
3053
3054
3055 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3056 {
3057 static const char * const texts[] = {
3058 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3059 };
3060
3061 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3062 }
3063
3064
3065 static int hdsp_rpm_input34(struct hdsp *hdsp)
3066 {
3067 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3068 case HDSP_RPM_Inp34_Phon_6dB:
3069 return 0;
3070 case HDSP_RPM_Inp34_Phon_n6dB:
3071 return 2;
3072 case HDSP_RPM_Inp34_Line_0dB:
3073 return 3;
3074 case HDSP_RPM_Inp34_Line_n6dB:
3075 return 4;
3076 }
3077 return 1;
3078 }
3079
3080
3081 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3082 {
3083 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3084
3085 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3086 return 0;
3087 }
3088
3089
3090 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3091 {
3092 hdsp->control_register &= ~HDSP_RPM_Inp34;
3093 switch (mode) {
3094 case 0:
3095 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3096 break;
3097 case 1:
3098 break;
3099 case 2:
3100 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3101 break;
3102 case 3:
3103 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3104 break;
3105 case 4:
3106 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3107 break;
3108 default:
3109 return -1;
3110 }
3111
3112 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3113 return 0;
3114 }
3115
3116
3117 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3118 {
3119 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3120 int change;
3121 int val;
3122
3123 if (!snd_hdsp_use_is_exclusive(hdsp))
3124 return -EBUSY;
3125 val = ucontrol->value.enumerated.item[0];
3126 if (val < 0)
3127 val = 0;
3128 if (val > 4)
3129 val = 4;
3130 spin_lock_irq(&hdsp->lock);
3131 if (val != hdsp_rpm_input34(hdsp))
3132 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3133 else
3134 change = 0;
3135 spin_unlock_irq(&hdsp->lock);
3136 return change;
3137 }
3138
3139
3140 /* RPM Bypass switch */
3141 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3142 {
3143 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3144 }
3145
3146
3147 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3148 {
3149 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3150
3151 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3152 return 0;
3153 }
3154
3155
3156 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3157 {
3158 if (on)
3159 hdsp->control_register |= HDSP_RPM_Bypass;
3160 else
3161 hdsp->control_register &= ~HDSP_RPM_Bypass;
3162 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3163 return 0;
3164 }
3165
3166
3167 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3168 {
3169 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3170 int change;
3171 unsigned int val;
3172
3173 if (!snd_hdsp_use_is_exclusive(hdsp))
3174 return -EBUSY;
3175 val = ucontrol->value.integer.value[0] & 1;
3176 spin_lock_irq(&hdsp->lock);
3177 change = (int)val != hdsp_rpm_bypass(hdsp);
3178 hdsp_set_rpm_bypass(hdsp, val);
3179 spin_unlock_irq(&hdsp->lock);
3180 return change;
3181 }
3182
3183
3184 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3185 {
3186 static const char * const texts[] = {"On", "Off"};
3187
3188 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3189 }
3190
3191
3192 /* RPM Disconnect switch */
3193 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3194 {
3195 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3196 }
3197
3198
3199 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3200 {
3201 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3202
3203 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3204 return 0;
3205 }
3206
3207
3208 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3209 {
3210 if (on)
3211 hdsp->control_register |= HDSP_RPM_Disconnect;
3212 else
3213 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3214 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3215 return 0;
3216 }
3217
3218
3219 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3220 {
3221 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3222 int change;
3223 unsigned int val;
3224
3225 if (!snd_hdsp_use_is_exclusive(hdsp))
3226 return -EBUSY;
3227 val = ucontrol->value.integer.value[0] & 1;
3228 spin_lock_irq(&hdsp->lock);
3229 change = (int)val != hdsp_rpm_disconnect(hdsp);
3230 hdsp_set_rpm_disconnect(hdsp, val);
3231 spin_unlock_irq(&hdsp->lock);
3232 return change;
3233 }
3234
3235 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3236 {
3237 static const char * const texts[] = {"On", "Off"};
3238
3239 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3240 }
3241
3242 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3243 {
3244 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3245 .name = "RPM Bypass",
3246 .get = snd_hdsp_get_rpm_bypass,
3247 .put = snd_hdsp_put_rpm_bypass,
3248 .info = snd_hdsp_info_rpm_bypass
3249 },
3250 {
3251 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3252 .name = "RPM Disconnect",
3253 .get = snd_hdsp_get_rpm_disconnect,
3254 .put = snd_hdsp_put_rpm_disconnect,
3255 .info = snd_hdsp_info_rpm_disconnect
3256 },
3257 {
3258 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3259 .name = "Input 1/2",
3260 .get = snd_hdsp_get_rpm_input12,
3261 .put = snd_hdsp_put_rpm_input12,
3262 .info = snd_hdsp_info_rpm_input
3263 },
3264 {
3265 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3266 .name = "Input 3/4",
3267 .get = snd_hdsp_get_rpm_input34,
3268 .put = snd_hdsp_put_rpm_input34,
3269 .info = snd_hdsp_info_rpm_input
3270 },
3271 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3272 HDSP_MIXER("Mixer", 0)
3273 };
3274
3275 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3276 HDSP_TOGGLE_SETTING("Analog Extension Board",
3277 HDSP_AnalogExtensionBoard);
3278 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3279
3280 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3281 {
3282 unsigned int idx;
3283 int err;
3284 struct snd_kcontrol *kctl;
3285
3286 if (hdsp->io_type == RPM) {
3287 /* RPM Bypass, Disconnect and Input switches */
3288 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3289 err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3290 if (err < 0)
3291 return err;
3292 }
3293 return 0;
3294 }
3295
3296 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3297 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3298 return err;
3299 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3300 hdsp->spdif_ctl = kctl;
3301 }
3302
3303 /* ADAT SyncCheck status */
3304 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3305 snd_hdsp_adat_sync_check.index = 1;
3306 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3307 return err;
3308 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3309 for (idx = 1; idx < 3; ++idx) {
3310 snd_hdsp_adat_sync_check.index = idx+1;
3311 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3312 return err;
3313 }
3314 }
3315
3316 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3317 if (hdsp->io_type == H9632) {
3318 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3319 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3320 return err;
3321 }
3322 }
3323
3324 /* AEB control for H96xx card */
3325 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3326 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3327 return err;
3328 }
3329
3330 return 0;
3331 }
3332
3333 /*------------------------------------------------------------
3334 /proc interface
3335 ------------------------------------------------------------*/
3336
3337 static void
3338 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3339 {
3340 struct hdsp *hdsp = entry->private_data;
3341 unsigned int status;
3342 unsigned int status2;
3343 char *pref_sync_ref;
3344 char *autosync_ref;
3345 char *system_clock_mode;
3346 char *clock_source;
3347 int x;
3348
3349 status = hdsp_read(hdsp, HDSP_statusRegister);
3350 status2 = hdsp_read(hdsp, HDSP_status2Register);
3351
3352 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3353 hdsp->card->number + 1);
3354 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3355 hdsp->capture_buffer, hdsp->playback_buffer);
3356 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3357 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3358 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3359 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3360 hdsp->control2_register);
3361 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3362 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3363
3364 if (hdsp_check_for_iobox(hdsp)) {
3365 snd_iprintf(buffer, "No I/O box connected.\n"
3366 "Please connect one and upload firmware.\n");
3367 return;
3368 }
3369
3370 if (hdsp_check_for_firmware(hdsp, 0)) {
3371 if (hdsp->state & HDSP_FirmwareCached) {
3372 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3373 snd_iprintf(buffer, "Firmware loading from "
3374 "cache failed, "
3375 "please upload manually.\n");
3376 return;
3377 }
3378 } else {
3379 int err = -EINVAL;
3380 err = hdsp_request_fw_loader(hdsp);
3381 if (err < 0) {
3382 snd_iprintf(buffer,
3383 "No firmware loaded nor cached, "
3384 "please upload firmware.\n");
3385 return;
3386 }
3387 }
3388 }
3389
3390 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3391 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3392 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3393 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3394 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3395 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3396
3397 snd_iprintf(buffer, "\n");
3398
3399 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3400
3401 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3402 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3403 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3404 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3405
3406 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3407
3408 snd_iprintf(buffer, "\n");
3409
3410 switch (hdsp_clock_source(hdsp)) {
3411 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3412 clock_source = "AutoSync";
3413 break;
3414 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3415 clock_source = "Internal 32 kHz";
3416 break;
3417 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3418 clock_source = "Internal 44.1 kHz";
3419 break;
3420 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3421 clock_source = "Internal 48 kHz";
3422 break;
3423 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3424 clock_source = "Internal 64 kHz";
3425 break;
3426 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3427 clock_source = "Internal 88.2 kHz";
3428 break;
3429 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3430 clock_source = "Internal 96 kHz";
3431 break;
3432 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3433 clock_source = "Internal 128 kHz";
3434 break;
3435 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3436 clock_source = "Internal 176.4 kHz";
3437 break;
3438 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3439 clock_source = "Internal 192 kHz";
3440 break;
3441 default:
3442 clock_source = "Error";
3443 }
3444 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3445
3446 if (hdsp_system_clock_mode(hdsp))
3447 system_clock_mode = "Slave";
3448 else
3449 system_clock_mode = "Master";
3450
3451 switch (hdsp_pref_sync_ref (hdsp)) {
3452 case HDSP_SYNC_FROM_WORD:
3453 pref_sync_ref = "Word Clock";
3454 break;
3455 case HDSP_SYNC_FROM_ADAT_SYNC:
3456 pref_sync_ref = "ADAT Sync";
3457 break;
3458 case HDSP_SYNC_FROM_SPDIF:
3459 pref_sync_ref = "SPDIF";
3460 break;
3461 case HDSP_SYNC_FROM_ADAT1:
3462 pref_sync_ref = "ADAT1";
3463 break;
3464 case HDSP_SYNC_FROM_ADAT2:
3465 pref_sync_ref = "ADAT2";
3466 break;
3467 case HDSP_SYNC_FROM_ADAT3:
3468 pref_sync_ref = "ADAT3";
3469 break;
3470 default:
3471 pref_sync_ref = "Word Clock";
3472 break;
3473 }
3474 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3475
3476 switch (hdsp_autosync_ref (hdsp)) {
3477 case HDSP_AUTOSYNC_FROM_WORD:
3478 autosync_ref = "Word Clock";
3479 break;
3480 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3481 autosync_ref = "ADAT Sync";
3482 break;
3483 case HDSP_AUTOSYNC_FROM_SPDIF:
3484 autosync_ref = "SPDIF";
3485 break;
3486 case HDSP_AUTOSYNC_FROM_NONE:
3487 autosync_ref = "None";
3488 break;
3489 case HDSP_AUTOSYNC_FROM_ADAT1:
3490 autosync_ref = "ADAT1";
3491 break;
3492 case HDSP_AUTOSYNC_FROM_ADAT2:
3493 autosync_ref = "ADAT2";
3494 break;
3495 case HDSP_AUTOSYNC_FROM_ADAT3:
3496 autosync_ref = "ADAT3";
3497 break;
3498 default:
3499 autosync_ref = "---";
3500 break;
3501 }
3502 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3503
3504 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3505
3506 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3507
3508 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3509 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3510
3511 snd_iprintf(buffer, "\n");
3512
3513 if (hdsp->io_type != RPM) {
3514 switch (hdsp_spdif_in(hdsp)) {
3515 case HDSP_SPDIFIN_OPTICAL:
3516 snd_iprintf(buffer, "IEC958 input: Optical\n");
3517 break;
3518 case HDSP_SPDIFIN_COAXIAL:
3519 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3520 break;
3521 case HDSP_SPDIFIN_INTERNAL:
3522 snd_iprintf(buffer, "IEC958 input: Internal\n");
3523 break;
3524 case HDSP_SPDIFIN_AES:
3525 snd_iprintf(buffer, "IEC958 input: AES\n");
3526 break;
3527 default:
3528 snd_iprintf(buffer, "IEC958 input: ???\n");
3529 break;
3530 }
3531 }
3532
3533 if (RPM == hdsp->io_type) {
3534 if (hdsp->control_register & HDSP_RPM_Bypass)
3535 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3536 else
3537 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3538 if (hdsp->control_register & HDSP_RPM_Disconnect)
3539 snd_iprintf(buffer, "RPM disconnected\n");
3540 else
3541 snd_iprintf(buffer, "RPM connected\n");
3542
3543 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3544 case HDSP_RPM_Inp12_Phon_6dB:
3545 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3546 break;
3547 case HDSP_RPM_Inp12_Phon_0dB:
3548 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3549 break;
3550 case HDSP_RPM_Inp12_Phon_n6dB:
3551 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3552 break;
3553 case HDSP_RPM_Inp12_Line_0dB:
3554 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3555 break;
3556 case HDSP_RPM_Inp12_Line_n6dB:
3557 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3558 break;
3559 default:
3560 snd_iprintf(buffer, "Input 1/2: ???\n");
3561 }
3562
3563 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3564 case HDSP_RPM_Inp34_Phon_6dB:
3565 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3566 break;
3567 case HDSP_RPM_Inp34_Phon_0dB:
3568 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3569 break;
3570 case HDSP_RPM_Inp34_Phon_n6dB:
3571 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3572 break;
3573 case HDSP_RPM_Inp34_Line_0dB:
3574 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3575 break;
3576 case HDSP_RPM_Inp34_Line_n6dB:
3577 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3578 break;
3579 default:
3580 snd_iprintf(buffer, "Input 3/4: ???\n");
3581 }
3582
3583 } else {
3584 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3585 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3586 else
3587 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3588
3589 if (hdsp->control_register & HDSP_SPDIFProfessional)
3590 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3591 else
3592 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3593
3594 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3595 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3596 else
3597 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3598
3599 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3600 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3601 else
3602 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3603 x = hdsp_spdif_sample_rate(hdsp);
3604 if (x != 0)
3605 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3606 else
3607 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3608 }
3609 snd_iprintf(buffer, "\n");
3610
3611 /* Sync Check */
3612 x = status & HDSP_Sync0;
3613 if (status & HDSP_Lock0)
3614 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3615 else
3616 snd_iprintf(buffer, "ADAT1: No Lock\n");
3617
3618 switch (hdsp->io_type) {
3619 case Digiface:
3620 case H9652:
3621 x = status & HDSP_Sync1;
3622 if (status & HDSP_Lock1)
3623 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3624 else
3625 snd_iprintf(buffer, "ADAT2: No Lock\n");
3626 x = status & HDSP_Sync2;
3627 if (status & HDSP_Lock2)
3628 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3629 else
3630 snd_iprintf(buffer, "ADAT3: No Lock\n");
3631 break;
3632 default:
3633 /* relax */
3634 break;
3635 }
3636
3637 x = status & HDSP_SPDIFSync;
3638 if (status & HDSP_SPDIFErrorFlag)
3639 snd_iprintf (buffer, "SPDIF: No Lock\n");
3640 else
3641 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3642
3643 x = status2 & HDSP_wc_sync;
3644 if (status2 & HDSP_wc_lock)
3645 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3646 else
3647 snd_iprintf (buffer, "Word Clock: No Lock\n");
3648
3649 x = status & HDSP_TimecodeSync;
3650 if (status & HDSP_TimecodeLock)
3651 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3652 else
3653 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3654
3655 snd_iprintf(buffer, "\n");
3656
3657 /* Informations about H9632 specific controls */
3658 if (hdsp->io_type == H9632) {
3659 char *tmp;
3660
3661 switch (hdsp_ad_gain(hdsp)) {
3662 case 0:
3663 tmp = "-10 dBV";
3664 break;
3665 case 1:
3666 tmp = "+4 dBu";
3667 break;
3668 default:
3669 tmp = "Lo Gain";
3670 break;
3671 }
3672 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3673
3674 switch (hdsp_da_gain(hdsp)) {
3675 case 0:
3676 tmp = "Hi Gain";
3677 break;
3678 case 1:
3679 tmp = "+4 dBu";
3680 break;
3681 default:
3682 tmp = "-10 dBV";
3683 break;
3684 }
3685 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3686
3687 switch (hdsp_phone_gain(hdsp)) {
3688 case 0:
3689 tmp = "0 dB";
3690 break;
3691 case 1:
3692 tmp = "-6 dB";
3693 break;
3694 default:
3695 tmp = "-12 dB";
3696 break;
3697 }
3698 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3699
3700 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3701 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3702 "yes" : "no");
3703
3704 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3705 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3706 else
3707 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3708 snd_iprintf(buffer, "\n");
3709 }
3710
3711 }
3712
3713 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3714 {
3715 struct snd_info_entry *entry;
3716
3717 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3718 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3719 }
3720
3721 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3722 {
3723 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3724 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3725 }
3726
3727 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3728 {
3729 unsigned long pb_bus, cb_bus;
3730
3731 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3732 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3733 if (hdsp->capture_dma_buf.area)
3734 snd_dma_free_pages(&hdsp->capture_dma_buf);
3735 dev_err(hdsp->card->dev,
3736 "%s: no buffers available\n", hdsp->card_name);
3737 return -ENOMEM;
3738 }
3739
3740 /* Align to bus-space 64K boundary */
3741
3742 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3743 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3744
3745 /* Tell the card where it is */
3746
3747 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3748 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3749
3750 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3751 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3752
3753 return 0;
3754 }
3755
3756 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3757 {
3758 unsigned int i;
3759
3760 /* ASSUMPTION: hdsp->lock is either held, or
3761 there is no need to hold it (e.g. during module
3762 initialization).
3763 */
3764
3765 /* set defaults:
3766
3767 SPDIF Input via Coax
3768 Master clock mode
3769 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3770 which implies 2 4096 sample, 32Kbyte periods).
3771 Enable line out.
3772 */
3773
3774 hdsp->control_register = HDSP_ClockModeMaster |
3775 HDSP_SPDIFInputCoaxial |
3776 hdsp_encode_latency(7) |
3777 HDSP_LineOut;
3778
3779
3780 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3781
3782 #ifdef SNDRV_BIG_ENDIAN
3783 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3784 #else
3785 hdsp->control2_register = 0;
3786 #endif
3787 if (hdsp->io_type == H9652)
3788 snd_hdsp_9652_enable_mixer (hdsp);
3789 else
3790 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3791
3792 hdsp_reset_hw_pointer(hdsp);
3793 hdsp_compute_period_size(hdsp);
3794
3795 /* silence everything */
3796
3797 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3798 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3799
3800 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3801 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3802 return -EIO;
3803 }
3804
3805 /* H9632 specific defaults */
3806 if (hdsp->io_type == H9632) {
3807 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3808 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3809 }
3810
3811 /* set a default rate so that the channel map is set up.
3812 */
3813
3814 hdsp_set_rate(hdsp, 48000, 1);
3815
3816 return 0;
3817 }
3818
3819 static void hdsp_midi_tasklet(unsigned long arg)
3820 {
3821 struct hdsp *hdsp = (struct hdsp *)arg;
3822
3823 if (hdsp->midi[0].pending)
3824 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3825 if (hdsp->midi[1].pending)
3826 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3827 }
3828
3829 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3830 {
3831 struct hdsp *hdsp = (struct hdsp *) dev_id;
3832 unsigned int status;
3833 int audio;
3834 int midi0;
3835 int midi1;
3836 unsigned int midi0status;
3837 unsigned int midi1status;
3838 int schedule = 0;
3839
3840 status = hdsp_read(hdsp, HDSP_statusRegister);
3841
3842 audio = status & HDSP_audioIRQPending;
3843 midi0 = status & HDSP_midi0IRQPending;
3844 midi1 = status & HDSP_midi1IRQPending;
3845
3846 if (!audio && !midi0 && !midi1)
3847 return IRQ_NONE;
3848
3849 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3850
3851 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3852 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3853
3854 if (!(hdsp->state & HDSP_InitializationComplete))
3855 return IRQ_HANDLED;
3856
3857 if (audio) {
3858 if (hdsp->capture_substream)
3859 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3860
3861 if (hdsp->playback_substream)
3862 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3863 }
3864
3865 if (midi0 && midi0status) {
3866 if (hdsp->use_midi_tasklet) {
3867 /* we disable interrupts for this input until processing is done */
3868 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3869 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3870 hdsp->midi[0].pending = 1;
3871 schedule = 1;
3872 } else {
3873 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3874 }
3875 }
3876 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3877 if (hdsp->use_midi_tasklet) {
3878 /* we disable interrupts for this input until processing is done */
3879 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3880 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3881 hdsp->midi[1].pending = 1;
3882 schedule = 1;
3883 } else {
3884 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3885 }
3886 }
3887 if (hdsp->use_midi_tasklet && schedule)
3888 tasklet_schedule(&hdsp->midi_tasklet);
3889 return IRQ_HANDLED;
3890 }
3891
3892 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3893 {
3894 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3895 return hdsp_hw_pointer(hdsp);
3896 }
3897
3898 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3899 int stream,
3900 int channel)
3901
3902 {
3903 int mapped_channel;
3904
3905 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3906 return NULL;
3907
3908 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3909 return NULL;
3910
3911 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3912 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3913 else
3914 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3915 }
3916
3917 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
3918 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3919 {
3920 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3921 char *channel_buf;
3922
3923 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3924 return -EINVAL;
3925
3926 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3927 if (snd_BUG_ON(!channel_buf))
3928 return -EIO;
3929 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3930 return -EFAULT;
3931 return count;
3932 }
3933
3934 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
3935 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3936 {
3937 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3938 char *channel_buf;
3939
3940 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3941 return -EINVAL;
3942
3943 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3944 if (snd_BUG_ON(!channel_buf))
3945 return -EIO;
3946 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3947 return -EFAULT;
3948 return count;
3949 }
3950
3951 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
3952 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3953 {
3954 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3955 char *channel_buf;
3956
3957 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3958 if (snd_BUG_ON(!channel_buf))
3959 return -EIO;
3960 memset(channel_buf + pos * 4, 0, count * 4);
3961 return count;
3962 }
3963
3964 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3965 {
3966 struct snd_pcm_runtime *runtime = substream->runtime;
3967 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3968 struct snd_pcm_substream *other;
3969 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3970 other = hdsp->capture_substream;
3971 else
3972 other = hdsp->playback_substream;
3973 if (hdsp->running)
3974 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3975 else
3976 runtime->status->hw_ptr = 0;
3977 if (other) {
3978 struct snd_pcm_substream *s;
3979 struct snd_pcm_runtime *oruntime = other->runtime;
3980 snd_pcm_group_for_each_entry(s, substream) {
3981 if (s == other) {
3982 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3983 break;
3984 }
3985 }
3986 }
3987 return 0;
3988 }
3989
3990 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3991 struct snd_pcm_hw_params *params)
3992 {
3993 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3994 int err;
3995 pid_t this_pid;
3996 pid_t other_pid;
3997
3998 if (hdsp_check_for_iobox (hdsp))
3999 return -EIO;
4000
4001 if (hdsp_check_for_firmware(hdsp, 1))
4002 return -EIO;
4003
4004 spin_lock_irq(&hdsp->lock);
4005
4006 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4007 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4008 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4009 this_pid = hdsp->playback_pid;
4010 other_pid = hdsp->capture_pid;
4011 } else {
4012 this_pid = hdsp->capture_pid;
4013 other_pid = hdsp->playback_pid;
4014 }
4015
4016 if ((other_pid > 0) && (this_pid != other_pid)) {
4017
4018 /* The other stream is open, and not by the same
4019 task as this one. Make sure that the parameters
4020 that matter are the same.
4021 */
4022
4023 if (params_rate(params) != hdsp->system_sample_rate) {
4024 spin_unlock_irq(&hdsp->lock);
4025 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4026 return -EBUSY;
4027 }
4028
4029 if (params_period_size(params) != hdsp->period_bytes / 4) {
4030 spin_unlock_irq(&hdsp->lock);
4031 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4032 return -EBUSY;
4033 }
4034
4035 /* We're fine. */
4036
4037 spin_unlock_irq(&hdsp->lock);
4038 return 0;
4039
4040 } else {
4041 spin_unlock_irq(&hdsp->lock);
4042 }
4043
4044 /* how to make sure that the rate matches an externally-set one ?
4045 */
4046
4047 spin_lock_irq(&hdsp->lock);
4048 if (! hdsp->clock_source_locked) {
4049 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4050 spin_unlock_irq(&hdsp->lock);
4051 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4052 return err;
4053 }
4054 }
4055 spin_unlock_irq(&hdsp->lock);
4056
4057 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4058 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4059 return err;
4060 }
4061
4062 return 0;
4063 }
4064
4065 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4066 struct snd_pcm_channel_info *info)
4067 {
4068 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4069 unsigned int channel = info->channel;
4070
4071 if (snd_BUG_ON(channel >= hdsp->max_channels))
4072 return -EINVAL;
4073 channel = array_index_nospec(channel, hdsp->max_channels);
4074
4075 if (hdsp->channel_map[channel] < 0)
4076 return -EINVAL;
4077
4078 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4079 info->first = 0;
4080 info->step = 32;
4081 return 0;
4082 }
4083
4084 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4085 unsigned int cmd, void *arg)
4086 {
4087 switch (cmd) {
4088 case SNDRV_PCM_IOCTL1_RESET:
4089 return snd_hdsp_reset(substream);
4090 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4091 return snd_hdsp_channel_info(substream, arg);
4092 default:
4093 break;
4094 }
4095
4096 return snd_pcm_lib_ioctl(substream, cmd, arg);
4097 }
4098
4099 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4100 {
4101 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4102 struct snd_pcm_substream *other;
4103 int running;
4104
4105 if (hdsp_check_for_iobox (hdsp))
4106 return -EIO;
4107
4108 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4109 return -EIO;
4110
4111 spin_lock(&hdsp->lock);
4112 running = hdsp->running;
4113 switch (cmd) {
4114 case SNDRV_PCM_TRIGGER_START:
4115 running |= 1 << substream->stream;
4116 break;
4117 case SNDRV_PCM_TRIGGER_STOP:
4118 running &= ~(1 << substream->stream);
4119 break;
4120 default:
4121 snd_BUG();
4122 spin_unlock(&hdsp->lock);
4123 return -EINVAL;
4124 }
4125 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4126 other = hdsp->capture_substream;
4127 else
4128 other = hdsp->playback_substream;
4129
4130 if (other) {
4131 struct snd_pcm_substream *s;
4132 snd_pcm_group_for_each_entry(s, substream) {
4133 if (s == other) {
4134 snd_pcm_trigger_done(s, substream);
4135 if (cmd == SNDRV_PCM_TRIGGER_START)
4136 running |= 1 << s->stream;
4137 else
4138 running &= ~(1 << s->stream);
4139 goto _ok;
4140 }
4141 }
4142 if (cmd == SNDRV_PCM_TRIGGER_START) {
4143 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4144 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4145 hdsp_silence_playback(hdsp);
4146 } else {
4147 if (running &&
4148 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4149 hdsp_silence_playback(hdsp);
4150 }
4151 } else {
4152 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4153 hdsp_silence_playback(hdsp);
4154 }
4155 _ok:
4156 snd_pcm_trigger_done(substream, substream);
4157 if (!hdsp->running && running)
4158 hdsp_start_audio(hdsp);
4159 else if (hdsp->running && !running)
4160 hdsp_stop_audio(hdsp);
4161 hdsp->running = running;
4162 spin_unlock(&hdsp->lock);
4163
4164 return 0;
4165 }
4166
4167 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4168 {
4169 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4170 int result = 0;
4171
4172 if (hdsp_check_for_iobox (hdsp))
4173 return -EIO;
4174
4175 if (hdsp_check_for_firmware(hdsp, 1))
4176 return -EIO;
4177
4178 spin_lock_irq(&hdsp->lock);
4179 if (!hdsp->running)
4180 hdsp_reset_hw_pointer(hdsp);
4181 spin_unlock_irq(&hdsp->lock);
4182 return result;
4183 }
4184
4185 static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4186 {
4187 .info = (SNDRV_PCM_INFO_MMAP |
4188 SNDRV_PCM_INFO_MMAP_VALID |
4189 SNDRV_PCM_INFO_NONINTERLEAVED |
4190 SNDRV_PCM_INFO_SYNC_START |
4191 SNDRV_PCM_INFO_DOUBLE),
4192 #ifdef SNDRV_BIG_ENDIAN
4193 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4194 #else
4195 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4196 #endif
4197 .rates = (SNDRV_PCM_RATE_32000 |
4198 SNDRV_PCM_RATE_44100 |
4199 SNDRV_PCM_RATE_48000 |
4200 SNDRV_PCM_RATE_64000 |
4201 SNDRV_PCM_RATE_88200 |
4202 SNDRV_PCM_RATE_96000),
4203 .rate_min = 32000,
4204 .rate_max = 96000,
4205 .channels_min = 6,
4206 .channels_max = HDSP_MAX_CHANNELS,
4207 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4208 .period_bytes_min = (64 * 4) * 10,
4209 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4210 .periods_min = 2,
4211 .periods_max = 2,
4212 .fifo_size = 0
4213 };
4214
4215 static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4216 {
4217 .info = (SNDRV_PCM_INFO_MMAP |
4218 SNDRV_PCM_INFO_MMAP_VALID |
4219 SNDRV_PCM_INFO_NONINTERLEAVED |
4220 SNDRV_PCM_INFO_SYNC_START),
4221 #ifdef SNDRV_BIG_ENDIAN
4222 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4223 #else
4224 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4225 #endif
4226 .rates = (SNDRV_PCM_RATE_32000 |
4227 SNDRV_PCM_RATE_44100 |
4228 SNDRV_PCM_RATE_48000 |
4229 SNDRV_PCM_RATE_64000 |
4230 SNDRV_PCM_RATE_88200 |
4231 SNDRV_PCM_RATE_96000),
4232 .rate_min = 32000,
4233 .rate_max = 96000,
4234 .channels_min = 5,
4235 .channels_max = HDSP_MAX_CHANNELS,
4236 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4237 .period_bytes_min = (64 * 4) * 10,
4238 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4239 .periods_min = 2,
4240 .periods_max = 2,
4241 .fifo_size = 0
4242 };
4243
4244 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4245
4246 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4247 .count = ARRAY_SIZE(hdsp_period_sizes),
4248 .list = hdsp_period_sizes,
4249 .mask = 0
4250 };
4251
4252 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4253
4254 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4255 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4256 .list = hdsp_9632_sample_rates,
4257 .mask = 0
4258 };
4259
4260 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4261 struct snd_pcm_hw_rule *rule)
4262 {
4263 struct hdsp *hdsp = rule->private;
4264 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4265 if (hdsp->io_type == H9632) {
4266 unsigned int list[3];
4267 list[0] = hdsp->qs_in_channels;
4268 list[1] = hdsp->ds_in_channels;
4269 list[2] = hdsp->ss_in_channels;
4270 return snd_interval_list(c, 3, list, 0);
4271 } else {
4272 unsigned int list[2];
4273 list[0] = hdsp->ds_in_channels;
4274 list[1] = hdsp->ss_in_channels;
4275 return snd_interval_list(c, 2, list, 0);
4276 }
4277 }
4278
4279 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4280 struct snd_pcm_hw_rule *rule)
4281 {
4282 unsigned int list[3];
4283 struct hdsp *hdsp = rule->private;
4284 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4285 if (hdsp->io_type == H9632) {
4286 list[0] = hdsp->qs_out_channels;
4287 list[1] = hdsp->ds_out_channels;
4288 list[2] = hdsp->ss_out_channels;
4289 return snd_interval_list(c, 3, list, 0);
4290 } else {
4291 list[0] = hdsp->ds_out_channels;
4292 list[1] = hdsp->ss_out_channels;
4293 }
4294 return snd_interval_list(c, 2, list, 0);
4295 }
4296
4297 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4298 struct snd_pcm_hw_rule *rule)
4299 {
4300 struct hdsp *hdsp = rule->private;
4301 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4302 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4303 if (r->min > 96000 && hdsp->io_type == H9632) {
4304 struct snd_interval t = {
4305 .min = hdsp->qs_in_channels,
4306 .max = hdsp->qs_in_channels,
4307 .integer = 1,
4308 };
4309 return snd_interval_refine(c, &t);
4310 } else if (r->min > 48000 && r->max <= 96000) {
4311 struct snd_interval t = {
4312 .min = hdsp->ds_in_channels,
4313 .max = hdsp->ds_in_channels,
4314 .integer = 1,
4315 };
4316 return snd_interval_refine(c, &t);
4317 } else if (r->max < 64000) {
4318 struct snd_interval t = {
4319 .min = hdsp->ss_in_channels,
4320 .max = hdsp->ss_in_channels,
4321 .integer = 1,
4322 };
4323 return snd_interval_refine(c, &t);
4324 }
4325 return 0;
4326 }
4327
4328 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4329 struct snd_pcm_hw_rule *rule)
4330 {
4331 struct hdsp *hdsp = rule->private;
4332 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4333 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4334 if (r->min > 96000 && hdsp->io_type == H9632) {
4335 struct snd_interval t = {
4336 .min = hdsp->qs_out_channels,
4337 .max = hdsp->qs_out_channels,
4338 .integer = 1,
4339 };
4340 return snd_interval_refine(c, &t);
4341 } else if (r->min > 48000 && r->max <= 96000) {
4342 struct snd_interval t = {
4343 .min = hdsp->ds_out_channels,
4344 .max = hdsp->ds_out_channels,
4345 .integer = 1,
4346 };
4347 return snd_interval_refine(c, &t);
4348 } else if (r->max < 64000) {
4349 struct snd_interval t = {
4350 .min = hdsp->ss_out_channels,
4351 .max = hdsp->ss_out_channels,
4352 .integer = 1,
4353 };
4354 return snd_interval_refine(c, &t);
4355 }
4356 return 0;
4357 }
4358
4359 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4360 struct snd_pcm_hw_rule *rule)
4361 {
4362 struct hdsp *hdsp = rule->private;
4363 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4364 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4365 if (c->min >= hdsp->ss_out_channels) {
4366 struct snd_interval t = {
4367 .min = 32000,
4368 .max = 48000,
4369 .integer = 1,
4370 };
4371 return snd_interval_refine(r, &t);
4372 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4373 struct snd_interval t = {
4374 .min = 128000,
4375 .max = 192000,
4376 .integer = 1,
4377 };
4378 return snd_interval_refine(r, &t);
4379 } else if (c->max <= hdsp->ds_out_channels) {
4380 struct snd_interval t = {
4381 .min = 64000,
4382 .max = 96000,
4383 .integer = 1,
4384 };
4385 return snd_interval_refine(r, &t);
4386 }
4387 return 0;
4388 }
4389
4390 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4391 struct snd_pcm_hw_rule *rule)
4392 {
4393 struct hdsp *hdsp = rule->private;
4394 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4395 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4396 if (c->min >= hdsp->ss_in_channels) {
4397 struct snd_interval t = {
4398 .min = 32000,
4399 .max = 48000,
4400 .integer = 1,
4401 };
4402 return snd_interval_refine(r, &t);
4403 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4404 struct snd_interval t = {
4405 .min = 128000,
4406 .max = 192000,
4407 .integer = 1,
4408 };
4409 return snd_interval_refine(r, &t);
4410 } else if (c->max <= hdsp->ds_in_channels) {
4411 struct snd_interval t = {
4412 .min = 64000,
4413 .max = 96000,
4414 .integer = 1,
4415 };
4416 return snd_interval_refine(r, &t);
4417 }
4418 return 0;
4419 }
4420
4421 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4422 {
4423 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4424 struct snd_pcm_runtime *runtime = substream->runtime;
4425
4426 if (hdsp_check_for_iobox (hdsp))
4427 return -EIO;
4428
4429 if (hdsp_check_for_firmware(hdsp, 1))
4430 return -EIO;
4431
4432 spin_lock_irq(&hdsp->lock);
4433
4434 snd_pcm_set_sync(substream);
4435
4436 runtime->hw = snd_hdsp_playback_subinfo;
4437 runtime->dma_area = hdsp->playback_buffer;
4438 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4439
4440 hdsp->playback_pid = current->pid;
4441 hdsp->playback_substream = substream;
4442
4443 spin_unlock_irq(&hdsp->lock);
4444
4445 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4446 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4447 if (hdsp->clock_source_locked) {
4448 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4449 } else if (hdsp->io_type == H9632) {
4450 runtime->hw.rate_max = 192000;
4451 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4452 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4453 }
4454 if (hdsp->io_type == H9632) {
4455 runtime->hw.channels_min = hdsp->qs_out_channels;
4456 runtime->hw.channels_max = hdsp->ss_out_channels;
4457 }
4458
4459 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4460 snd_hdsp_hw_rule_out_channels, hdsp,
4461 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4462 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4463 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4464 SNDRV_PCM_HW_PARAM_RATE, -1);
4465 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4466 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4467 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4468
4469 if (RPM != hdsp->io_type) {
4470 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4471 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4472 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4473 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4474 }
4475 return 0;
4476 }
4477
4478 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4479 {
4480 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4481
4482 spin_lock_irq(&hdsp->lock);
4483
4484 hdsp->playback_pid = -1;
4485 hdsp->playback_substream = NULL;
4486
4487 spin_unlock_irq(&hdsp->lock);
4488
4489 if (RPM != hdsp->io_type) {
4490 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4491 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4492 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4493 }
4494 return 0;
4495 }
4496
4497
4498 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4499 {
4500 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4501 struct snd_pcm_runtime *runtime = substream->runtime;
4502
4503 if (hdsp_check_for_iobox (hdsp))
4504 return -EIO;
4505
4506 if (hdsp_check_for_firmware(hdsp, 1))
4507 return -EIO;
4508
4509 spin_lock_irq(&hdsp->lock);
4510
4511 snd_pcm_set_sync(substream);
4512
4513 runtime->hw = snd_hdsp_capture_subinfo;
4514 runtime->dma_area = hdsp->capture_buffer;
4515 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4516
4517 hdsp->capture_pid = current->pid;
4518 hdsp->capture_substream = substream;
4519
4520 spin_unlock_irq(&hdsp->lock);
4521
4522 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4523 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4524 if (hdsp->io_type == H9632) {
4525 runtime->hw.channels_min = hdsp->qs_in_channels;
4526 runtime->hw.channels_max = hdsp->ss_in_channels;
4527 runtime->hw.rate_max = 192000;
4528 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4529 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4530 }
4531 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4532 snd_hdsp_hw_rule_in_channels, hdsp,
4533 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4534 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4535 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4536 SNDRV_PCM_HW_PARAM_RATE, -1);
4537 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4538 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4539 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4540 return 0;
4541 }
4542
4543 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4544 {
4545 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4546
4547 spin_lock_irq(&hdsp->lock);
4548
4549 hdsp->capture_pid = -1;
4550 hdsp->capture_substream = NULL;
4551
4552 spin_unlock_irq(&hdsp->lock);
4553 return 0;
4554 }
4555
4556 /* helper functions for copying meter values */
4557 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4558 {
4559 u32 val = readl(src);
4560 return copy_to_user(dest, &val, 4);
4561 }
4562
4563 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4564 {
4565 u32 rms_low, rms_high;
4566 u64 rms;
4567 rms_low = readl(src_low);
4568 rms_high = readl(src_high);
4569 rms = ((u64)rms_high << 32) | rms_low;
4570 return copy_to_user(dest, &rms, 8);
4571 }
4572
4573 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4574 {
4575 u32 rms_low, rms_high;
4576 u64 rms;
4577 rms_low = readl(src_low) & 0xffffff00;
4578 rms_high = readl(src_high) & 0xffffff00;
4579 rms = ((u64)rms_high << 32) | rms_low;
4580 return copy_to_user(dest, &rms, 8);
4581 }
4582
4583 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4584 {
4585 int doublespeed = 0;
4586 int i, j, channels, ofs;
4587
4588 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4589 doublespeed = 1;
4590 channels = doublespeed ? 14 : 26;
4591 for (i = 0, j = 0; i < 26; ++i) {
4592 if (doublespeed && (i & 4))
4593 continue;
4594 ofs = HDSP_9652_peakBase - j * 4;
4595 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4596 return -EFAULT;
4597 ofs -= channels * 4;
4598 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4599 return -EFAULT;
4600 ofs -= channels * 4;
4601 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4602 return -EFAULT;
4603 ofs = HDSP_9652_rmsBase + j * 8;
4604 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4605 hdsp->iobase + ofs + 4))
4606 return -EFAULT;
4607 ofs += channels * 8;
4608 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4609 hdsp->iobase + ofs + 4))
4610 return -EFAULT;
4611 ofs += channels * 8;
4612 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4613 hdsp->iobase + ofs + 4))
4614 return -EFAULT;
4615 j++;
4616 }
4617 return 0;
4618 }
4619
4620 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4621 {
4622 int i, j;
4623 struct hdsp_9632_meters __iomem *m;
4624 int doublespeed = 0;
4625
4626 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4627 doublespeed = 1;
4628 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4629 for (i = 0, j = 0; i < 16; ++i, ++j) {
4630 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4631 return -EFAULT;
4632 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4633 return -EFAULT;
4634 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4635 return -EFAULT;
4636 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4637 &m->input_rms_high[j]))
4638 return -EFAULT;
4639 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4640 &m->playback_rms_high[j]))
4641 return -EFAULT;
4642 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4643 &m->output_rms_high[j]))
4644 return -EFAULT;
4645 if (doublespeed && i == 3) i += 4;
4646 }
4647 return 0;
4648 }
4649
4650 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4651 {
4652 int i;
4653
4654 for (i = 0; i < 26; i++) {
4655 if (copy_u32_le(&peak_rms->playback_peaks[i],
4656 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4657 return -EFAULT;
4658 if (copy_u32_le(&peak_rms->input_peaks[i],
4659 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4660 return -EFAULT;
4661 }
4662 for (i = 0; i < 28; i++) {
4663 if (copy_u32_le(&peak_rms->output_peaks[i],
4664 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4665 return -EFAULT;
4666 }
4667 for (i = 0; i < 26; ++i) {
4668 if (copy_u64_le(&peak_rms->playback_rms[i],
4669 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4670 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4671 return -EFAULT;
4672 if (copy_u64_le(&peak_rms->input_rms[i],
4673 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4674 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4675 return -EFAULT;
4676 }
4677 return 0;
4678 }
4679
4680 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4681 {
4682 struct hdsp *hdsp = hw->private_data;
4683 void __user *argp = (void __user *)arg;
4684 int err;
4685
4686 switch (cmd) {
4687 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4688 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4689
4690 err = hdsp_check_for_iobox(hdsp);
4691 if (err < 0)
4692 return err;
4693
4694 err = hdsp_check_for_firmware(hdsp, 1);
4695 if (err < 0)
4696 return err;
4697
4698 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4699 dev_err(hdsp->card->dev,
4700 "firmware needs to be uploaded to the card.\n");
4701 return -EINVAL;
4702 }
4703
4704 switch (hdsp->io_type) {
4705 case H9652:
4706 return hdsp_9652_get_peak(hdsp, peak_rms);
4707 case H9632:
4708 return hdsp_9632_get_peak(hdsp, peak_rms);
4709 default:
4710 return hdsp_get_peak(hdsp, peak_rms);
4711 }
4712 }
4713 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4714 struct hdsp_config_info info;
4715 unsigned long flags;
4716 int i;
4717
4718 err = hdsp_check_for_iobox(hdsp);
4719 if (err < 0)
4720 return err;
4721
4722 err = hdsp_check_for_firmware(hdsp, 1);
4723 if (err < 0)
4724 return err;
4725
4726 memset(&info, 0, sizeof(info));
4727 spin_lock_irqsave(&hdsp->lock, flags);
4728 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4729 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4730 if (hdsp->io_type != H9632)
4731 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4732 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4733 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4734 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4735 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4736 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4737 HDSP_SPDIFOpticalOut);
4738 info.spdif_professional = (unsigned char)
4739 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4740 info.spdif_emphasis = (unsigned char)
4741 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4742 info.spdif_nonaudio = (unsigned char)
4743 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4744 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4745 info.system_sample_rate = hdsp->system_sample_rate;
4746 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4747 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4748 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4749 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4750 info.line_out = (unsigned char)
4751 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4752 if (hdsp->io_type == H9632) {
4753 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4754 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4755 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4756 info.xlr_breakout_cable =
4757 (unsigned char)hdsp_toggle_setting(hdsp,
4758 HDSP_XLRBreakoutCable);
4759
4760 } else if (hdsp->io_type == RPM) {
4761 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4762 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4763 }
4764 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4765 info.analog_extension_board =
4766 (unsigned char)hdsp_toggle_setting(hdsp,
4767 HDSP_AnalogExtensionBoard);
4768 spin_unlock_irqrestore(&hdsp->lock, flags);
4769 if (copy_to_user(argp, &info, sizeof(info)))
4770 return -EFAULT;
4771 break;
4772 }
4773 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4774 struct hdsp_9632_aeb h9632_aeb;
4775
4776 if (hdsp->io_type != H9632) return -EINVAL;
4777 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4778 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4779 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4780 return -EFAULT;
4781 break;
4782 }
4783 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4784 struct hdsp_version hdsp_version;
4785 int err;
4786
4787 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4788 if (hdsp->io_type == Undefined) {
4789 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4790 return err;
4791 }
4792 memset(&hdsp_version, 0, sizeof(hdsp_version));
4793 hdsp_version.io_type = hdsp->io_type;
4794 hdsp_version.firmware_rev = hdsp->firmware_rev;
4795 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4796 return -EFAULT;
4797 break;
4798 }
4799 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4800 struct hdsp_firmware __user *firmware;
4801 u32 __user *firmware_data;
4802 int err;
4803
4804 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4805 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4806 if (hdsp->io_type == Undefined) return -EINVAL;
4807
4808 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4809 return -EBUSY;
4810
4811 dev_info(hdsp->card->dev,
4812 "initializing firmware upload\n");
4813 firmware = (struct hdsp_firmware __user *)argp;
4814
4815 if (get_user(firmware_data, &firmware->firmware_data))
4816 return -EFAULT;
4817
4818 if (hdsp_check_for_iobox (hdsp))
4819 return -EIO;
4820
4821 if (!hdsp->fw_uploaded) {
4822 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4823 if (!hdsp->fw_uploaded)
4824 return -ENOMEM;
4825 }
4826
4827 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4828 HDSP_FIRMWARE_SIZE)) {
4829 vfree(hdsp->fw_uploaded);
4830 hdsp->fw_uploaded = NULL;
4831 return -EFAULT;
4832 }
4833
4834 hdsp->state |= HDSP_FirmwareCached;
4835
4836 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4837 return err;
4838
4839 if (!(hdsp->state & HDSP_InitializationComplete)) {
4840 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4841 return err;
4842
4843 snd_hdsp_initialize_channels(hdsp);
4844 snd_hdsp_initialize_midi_flush(hdsp);
4845
4846 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4847 dev_err(hdsp->card->dev,
4848 "error creating alsa devices\n");
4849 return err;
4850 }
4851 }
4852 break;
4853 }
4854 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4855 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4856 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4857 return -EFAULT;
4858 break;
4859 }
4860 default:
4861 return -EINVAL;
4862 }
4863 return 0;
4864 }
4865
4866 static struct snd_pcm_ops snd_hdsp_playback_ops = {
4867 .open = snd_hdsp_playback_open,
4868 .close = snd_hdsp_playback_release,
4869 .ioctl = snd_hdsp_ioctl,
4870 .hw_params = snd_hdsp_hw_params,
4871 .prepare = snd_hdsp_prepare,
4872 .trigger = snd_hdsp_trigger,
4873 .pointer = snd_hdsp_hw_pointer,
4874 .copy = snd_hdsp_playback_copy,
4875 .silence = snd_hdsp_hw_silence,
4876 };
4877
4878 static struct snd_pcm_ops snd_hdsp_capture_ops = {
4879 .open = snd_hdsp_capture_open,
4880 .close = snd_hdsp_capture_release,
4881 .ioctl = snd_hdsp_ioctl,
4882 .hw_params = snd_hdsp_hw_params,
4883 .prepare = snd_hdsp_prepare,
4884 .trigger = snd_hdsp_trigger,
4885 .pointer = snd_hdsp_hw_pointer,
4886 .copy = snd_hdsp_capture_copy,
4887 };
4888
4889 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4890 {
4891 struct snd_hwdep *hw;
4892 int err;
4893
4894 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4895 return err;
4896
4897 hdsp->hwdep = hw;
4898 hw->private_data = hdsp;
4899 strcpy(hw->name, "HDSP hwdep interface");
4900
4901 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4902 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4903
4904 return 0;
4905 }
4906
4907 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4908 {
4909 struct snd_pcm *pcm;
4910 int err;
4911
4912 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4913 return err;
4914
4915 hdsp->pcm = pcm;
4916 pcm->private_data = hdsp;
4917 strcpy(pcm->name, hdsp->card_name);
4918
4919 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4920 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4921
4922 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4923
4924 return 0;
4925 }
4926
4927 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4928 {
4929 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4930 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4931 }
4932
4933 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4934 {
4935 int i;
4936
4937 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4938 dev_err(hdsp->card->dev,
4939 "enable_io fifo_wait failed\n");
4940 return -EIO;
4941 }
4942
4943 for (i = 0; i < hdsp->max_channels; ++i) {
4944 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4945 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4946 }
4947
4948 return 0;
4949 }
4950
4951 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4952 {
4953 int status, aebi_channels, aebo_channels;
4954
4955 switch (hdsp->io_type) {
4956 case Digiface:
4957 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4958 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4959 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4960 break;
4961
4962 case H9652:
4963 hdsp->card_name = "RME Hammerfall HDSP 9652";
4964 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4965 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4966 break;
4967
4968 case H9632:
4969 status = hdsp_read(hdsp, HDSP_statusRegister);
4970 /* HDSP_AEBx bits are low when AEB are connected */
4971 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4972 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4973 hdsp->card_name = "RME Hammerfall HDSP 9632";
4974 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4975 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4976 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4977 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4978 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4979 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4980 break;
4981
4982 case Multiface:
4983 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4984 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4985 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4986 break;
4987
4988 case RPM:
4989 hdsp->card_name = "RME Hammerfall DSP + RPM";
4990 hdsp->ss_in_channels = RPM_CHANNELS-1;
4991 hdsp->ss_out_channels = RPM_CHANNELS;
4992 hdsp->ds_in_channels = RPM_CHANNELS-1;
4993 hdsp->ds_out_channels = RPM_CHANNELS;
4994 break;
4995
4996 default:
4997 /* should never get here */
4998 break;
4999 }
5000 }
5001
5002 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5003 {
5004 snd_hdsp_flush_midi_input (hdsp, 0);
5005 snd_hdsp_flush_midi_input (hdsp, 1);
5006 }
5007
5008 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5009 {
5010 int err;
5011
5012 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5013 dev_err(card->dev,
5014 "Error creating pcm interface\n");
5015 return err;
5016 }
5017
5018
5019 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5020 dev_err(card->dev,
5021 "Error creating first midi interface\n");
5022 return err;
5023 }
5024
5025 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5026 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5027 dev_err(card->dev,
5028 "Error creating second midi interface\n");
5029 return err;
5030 }
5031 }
5032
5033 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5034 dev_err(card->dev,
5035 "Error creating ctl interface\n");
5036 return err;
5037 }
5038
5039 snd_hdsp_proc_init(hdsp);
5040
5041 hdsp->system_sample_rate = -1;
5042 hdsp->playback_pid = -1;
5043 hdsp->capture_pid = -1;
5044 hdsp->capture_substream = NULL;
5045 hdsp->playback_substream = NULL;
5046
5047 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5048 dev_err(card->dev,
5049 "Error setting default values\n");
5050 return err;
5051 }
5052
5053 if (!(hdsp->state & HDSP_InitializationComplete)) {
5054 strcpy(card->shortname, "Hammerfall DSP");
5055 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5056 hdsp->port, hdsp->irq);
5057
5058 if ((err = snd_card_register(card)) < 0) {
5059 dev_err(card->dev,
5060 "error registering card\n");
5061 return err;
5062 }
5063 hdsp->state |= HDSP_InitializationComplete;
5064 }
5065
5066 return 0;
5067 }
5068
5069 /* load firmware via hotplug fw loader */
5070 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5071 {
5072 const char *fwfile;
5073 const struct firmware *fw;
5074 int err;
5075
5076 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5077 return 0;
5078 if (hdsp->io_type == Undefined) {
5079 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5080 return err;
5081 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5082 return 0;
5083 }
5084
5085 /* caution: max length of firmware filename is 30! */
5086 switch (hdsp->io_type) {
5087 case RPM:
5088 fwfile = "rpm_firmware.bin";
5089 break;
5090 case Multiface:
5091 if (hdsp->firmware_rev == 0xa)
5092 fwfile = "multiface_firmware.bin";
5093 else
5094 fwfile = "multiface_firmware_rev11.bin";
5095 break;
5096 case Digiface:
5097 if (hdsp->firmware_rev == 0xa)
5098 fwfile = "digiface_firmware.bin";
5099 else
5100 fwfile = "digiface_firmware_rev11.bin";
5101 break;
5102 default:
5103 dev_err(hdsp->card->dev,
5104 "invalid io_type %d\n", hdsp->io_type);
5105 return -EINVAL;
5106 }
5107
5108 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5109 dev_err(hdsp->card->dev,
5110 "cannot load firmware %s\n", fwfile);
5111 return -ENOENT;
5112 }
5113 if (fw->size < HDSP_FIRMWARE_SIZE) {
5114 dev_err(hdsp->card->dev,
5115 "too short firmware size %d (expected %d)\n",
5116 (int)fw->size, HDSP_FIRMWARE_SIZE);
5117 release_firmware(fw);
5118 return -EINVAL;
5119 }
5120
5121 hdsp->firmware = fw;
5122
5123 hdsp->state |= HDSP_FirmwareCached;
5124
5125 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5126 return err;
5127
5128 if (!(hdsp->state & HDSP_InitializationComplete)) {
5129 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5130 return err;
5131
5132 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5133 dev_err(hdsp->card->dev,
5134 "error creating hwdep device\n");
5135 return err;
5136 }
5137 snd_hdsp_initialize_channels(hdsp);
5138 snd_hdsp_initialize_midi_flush(hdsp);
5139 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5140 dev_err(hdsp->card->dev,
5141 "error creating alsa devices\n");
5142 return err;
5143 }
5144 }
5145 return 0;
5146 }
5147
5148 static int snd_hdsp_create(struct snd_card *card,
5149 struct hdsp *hdsp)
5150 {
5151 struct pci_dev *pci = hdsp->pci;
5152 int err;
5153 int is_9652 = 0;
5154 int is_9632 = 0;
5155
5156 hdsp->irq = -1;
5157 hdsp->state = 0;
5158 hdsp->midi[0].rmidi = NULL;
5159 hdsp->midi[1].rmidi = NULL;
5160 hdsp->midi[0].input = NULL;
5161 hdsp->midi[1].input = NULL;
5162 hdsp->midi[0].output = NULL;
5163 hdsp->midi[1].output = NULL;
5164 hdsp->midi[0].pending = 0;
5165 hdsp->midi[1].pending = 0;
5166 spin_lock_init(&hdsp->midi[0].lock);
5167 spin_lock_init(&hdsp->midi[1].lock);
5168 hdsp->iobase = NULL;
5169 hdsp->control_register = 0;
5170 hdsp->control2_register = 0;
5171 hdsp->io_type = Undefined;
5172 hdsp->max_channels = 26;
5173
5174 hdsp->card = card;
5175
5176 spin_lock_init(&hdsp->lock);
5177
5178 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5179
5180 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5181 hdsp->firmware_rev &= 0xff;
5182
5183 /* From Martin Bjoernsen :
5184 "It is important that the card's latency timer register in
5185 the PCI configuration space is set to a value much larger
5186 than 0 by the computer's BIOS or the driver.
5187 The windows driver always sets this 8 bit register [...]
5188 to its maximum 255 to avoid problems with some computers."
5189 */
5190 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5191
5192 strcpy(card->driver, "H-DSP");
5193 strcpy(card->mixername, "Xilinx FPGA");
5194
5195 if (hdsp->firmware_rev < 0xa)
5196 return -ENODEV;
5197 else if (hdsp->firmware_rev < 0x64)
5198 hdsp->card_name = "RME Hammerfall DSP";
5199 else if (hdsp->firmware_rev < 0x96) {
5200 hdsp->card_name = "RME HDSP 9652";
5201 is_9652 = 1;
5202 } else {
5203 hdsp->card_name = "RME HDSP 9632";
5204 hdsp->max_channels = 16;
5205 is_9632 = 1;
5206 }
5207
5208 if ((err = pci_enable_device(pci)) < 0)
5209 return err;
5210
5211 pci_set_master(hdsp->pci);
5212
5213 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5214 return err;
5215 hdsp->port = pci_resource_start(pci, 0);
5216 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5217 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5218 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5219 return -EBUSY;
5220 }
5221
5222 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5223 KBUILD_MODNAME, hdsp)) {
5224 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5225 return -EBUSY;
5226 }
5227
5228 hdsp->irq = pci->irq;
5229 hdsp->precise_ptr = 0;
5230 hdsp->use_midi_tasklet = 1;
5231 hdsp->dds_value = 0;
5232
5233 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5234 return err;
5235
5236 if (!is_9652 && !is_9632) {
5237 /* we wait a maximum of 10 seconds to let freshly
5238 * inserted cardbus cards do their hardware init */
5239 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5240
5241 if (err < 0)
5242 return err;
5243
5244 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5245 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5246 /* we don't fail as this can happen
5247 if userspace is not ready for
5248 firmware upload
5249 */
5250 dev_err(hdsp->card->dev,
5251 "couldn't get firmware from userspace. try using hdsploader\n");
5252 else
5253 /* init is complete, we return */
5254 return 0;
5255 /* we defer initialization */
5256 dev_info(hdsp->card->dev,
5257 "card initialization pending : waiting for firmware\n");
5258 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5259 return err;
5260 return 0;
5261 } else {
5262 dev_info(hdsp->card->dev,
5263 "Firmware already present, initializing card.\n");
5264 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5265 hdsp->io_type = RPM;
5266 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5267 hdsp->io_type = Multiface;
5268 else
5269 hdsp->io_type = Digiface;
5270 }
5271 }
5272
5273 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5274 return err;
5275
5276 if (is_9652)
5277 hdsp->io_type = H9652;
5278
5279 if (is_9632)
5280 hdsp->io_type = H9632;
5281
5282 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5283 return err;
5284
5285 snd_hdsp_initialize_channels(hdsp);
5286 snd_hdsp_initialize_midi_flush(hdsp);
5287
5288 hdsp->state |= HDSP_FirmwareLoaded;
5289
5290 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5291 return err;
5292
5293 return 0;
5294 }
5295
5296 static int snd_hdsp_free(struct hdsp *hdsp)
5297 {
5298 if (hdsp->port) {
5299 /* stop the audio, and cancel all interrupts */
5300 tasklet_kill(&hdsp->midi_tasklet);
5301 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5302 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5303 }
5304
5305 if (hdsp->irq >= 0)
5306 free_irq(hdsp->irq, (void *)hdsp);
5307
5308 snd_hdsp_free_buffers(hdsp);
5309
5310 release_firmware(hdsp->firmware);
5311 vfree(hdsp->fw_uploaded);
5312 iounmap(hdsp->iobase);
5313
5314 if (hdsp->port)
5315 pci_release_regions(hdsp->pci);
5316
5317 pci_disable_device(hdsp->pci);
5318 return 0;
5319 }
5320
5321 static void snd_hdsp_card_free(struct snd_card *card)
5322 {
5323 struct hdsp *hdsp = card->private_data;
5324
5325 if (hdsp)
5326 snd_hdsp_free(hdsp);
5327 }
5328
5329 static int snd_hdsp_probe(struct pci_dev *pci,
5330 const struct pci_device_id *pci_id)
5331 {
5332 static int dev;
5333 struct hdsp *hdsp;
5334 struct snd_card *card;
5335 int err;
5336
5337 if (dev >= SNDRV_CARDS)
5338 return -ENODEV;
5339 if (!enable[dev]) {
5340 dev++;
5341 return -ENOENT;
5342 }
5343
5344 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5345 sizeof(struct hdsp), &card);
5346 if (err < 0)
5347 return err;
5348
5349 hdsp = card->private_data;
5350 card->private_free = snd_hdsp_card_free;
5351 hdsp->dev = dev;
5352 hdsp->pci = pci;
5353
5354 if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5355 snd_card_free(card);
5356 return err;
5357 }
5358
5359 strcpy(card->shortname, "Hammerfall DSP");
5360 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5361 hdsp->port, hdsp->irq);
5362
5363 if ((err = snd_card_register(card)) < 0) {
5364 snd_card_free(card);
5365 return err;
5366 }
5367 pci_set_drvdata(pci, card);
5368 dev++;
5369 return 0;
5370 }
5371
5372 static void snd_hdsp_remove(struct pci_dev *pci)
5373 {
5374 snd_card_free(pci_get_drvdata(pci));
5375 }
5376
5377 static struct pci_driver hdsp_driver = {
5378 .name = KBUILD_MODNAME,
5379 .id_table = snd_hdsp_ids,
5380 .probe = snd_hdsp_probe,
5381 .remove = snd_hdsp_remove,
5382 };
5383
5384 module_pci_driver(hdsp_driver);
Linux with added FPC-III support