| blob | 90d09eddd5b27368e358efd44ab552db8330d39c |
1 /*
2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
4 *
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
28 #include <asm/ptrace.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cache.h>
31 #include <asm/cputype.h>
32 #include <asm/memory.h>
33 #include <asm/thread_info.h>
34 #include <asm/pgtable-hwdef.h>
35 #include <asm/pgtable.h>
36 #include <asm/page.h>
37 #include <asm/virt.h>
39 #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
41 #if (TEXT_OFFSET & 0xfff) != 0
42 #error TEXT_OFFSET must be at least 4KB aligned
43 #elif (PAGE_OFFSET & 0x1fffff) != 0
44 #error PAGE_OFFSET must be at least 2MB aligned
45 #elif TEXT_OFFSET > 0x1fffff
46 #error TEXT_OFFSET must be less than 2MB
47 #endif
49 #ifdef CONFIG_ARM64_64K_PAGES
50 #define BLOCK_SHIFT PAGE_SHIFT
51 #define BLOCK_SIZE PAGE_SIZE
52 #define TABLE_SHIFT PMD_SHIFT
53 #else
54 #define BLOCK_SHIFT SECTION_SHIFT
55 #define BLOCK_SIZE SECTION_SIZE
56 #define TABLE_SHIFT PUD_SHIFT
57 #endif
59 #define KERNEL_START _text
60 #define KERNEL_END _end
62 /*
63 * Initial memory map attributes.
64 */
65 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
66 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
68 #ifdef CONFIG_ARM64_64K_PAGES
69 #define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
70 #else
71 #define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
72 #endif
74 /*
75 * Kernel startup entry point.
76 * ---------------------------
77 *
78 * The requirements are:
79 * MMU = off, D-cache = off, I-cache = on or off,
80 * x0 = physical address to the FDT blob.
81 *
82 * This code is mostly position independent so you call this at
83 * __pa(PAGE_OFFSET + TEXT_OFFSET).
84 *
85 * Note that the callee-saved registers are used for storing variables
86 * that are useful before the MMU is enabled. The allocations are described
87 * in the entry routines.
88 */
89 __HEAD
91 /*
92 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
93 */
94 #ifdef CONFIG_EFI
95 efi_head:
96 /*
97 * This add instruction has no meaningful effect except that
98 * its opcode forms the magic "MZ" signature required by UEFI.
99 */
100 add x13, x18, #0x16
101 b stext
102 #else
103 b stext // branch to kernel start, magic
104 .long 0 // reserved
105 #endif
106 .quad _kernel_offset_le // Image load offset from start of RAM, little-endian
107 .quad _kernel_size_le // Effective size of kernel image, little-endian
108 .quad _kernel_flags_le // Informative flags, little-endian
109 .quad 0 // reserved
110 .quad 0 // reserved
111 .quad 0 // reserved
112 .byte 0x41 // Magic number, "ARM\x64"
113 .byte 0x52
114 .byte 0x4d
115 .byte 0x64
116 #ifdef CONFIG_EFI
117 .long pe_header - efi_head // Offset to the PE header.
118 #else
119 .word 0 // reserved
120 #endif
122 #ifdef CONFIG_EFI
123 .globl stext_offset
124 .set stext_offset, stext - efi_head
125 .align 3
126 pe_header:
127 .ascii "PE"
128 .short 0
129 coff_header:
130 .short 0xaa64 // AArch64
131 .short 2 // nr_sections
132 .long 0 // TimeDateStamp
133 .long 0 // PointerToSymbolTable
134 .long 1 // NumberOfSymbols
135 .short section_table - optional_header // SizeOfOptionalHeader
136 .short 0x206 // Characteristics.
137 // IMAGE_FILE_DEBUG_STRIPPED |
138 // IMAGE_FILE_EXECUTABLE_IMAGE |
139 // IMAGE_FILE_LINE_NUMS_STRIPPED
140 optional_header:
141 .short 0x20b // PE32+ format
142 .byte 0x02 // MajorLinkerVersion
143 .byte 0x14 // MinorLinkerVersion
144 .long _end - stext // SizeOfCode
145 .long 0 // SizeOfInitializedData
146 .long 0 // SizeOfUninitializedData
147 .long efi_stub_entry - efi_head // AddressOfEntryPoint
148 .long stext_offset // BaseOfCode
150 extra_header_fields:
151 .quad 0 // ImageBase
152 .long 0x1000 // SectionAlignment
153 .long PECOFF_FILE_ALIGNMENT // FileAlignment
154 .short 0 // MajorOperatingSystemVersion
155 .short 0 // MinorOperatingSystemVersion
156 .short 0 // MajorImageVersion
157 .short 0 // MinorImageVersion
158 .short 0 // MajorSubsystemVersion
159 .short 0 // MinorSubsystemVersion
160 .long 0 // Win32VersionValue
162 .long _end - efi_head // SizeOfImage
164 // Everything before the kernel image is considered part of the header
165 .long stext_offset // SizeOfHeaders
166 .long 0 // CheckSum
167 .short 0xa // Subsystem (EFI application)
168 .short 0 // DllCharacteristics
169 .quad 0 // SizeOfStackReserve
170 .quad 0 // SizeOfStackCommit
171 .quad 0 // SizeOfHeapReserve
172 .quad 0 // SizeOfHeapCommit
173 .long 0 // LoaderFlags
174 .long 0x6 // NumberOfRvaAndSizes
176 .quad 0 // ExportTable
177 .quad 0 // ImportTable
178 .quad 0 // ResourceTable
179 .quad 0 // ExceptionTable
180 .quad 0 // CertificationTable
181 .quad 0 // BaseRelocationTable
183 // Section table
184 section_table:
186 /*
187 * The EFI application loader requires a relocation section
188 * because EFI applications must be relocatable. This is a
189 * dummy section as far as we are concerned.
190 */
191 .ascii ".reloc"
192 .byte 0
193 .byte 0 // end of 0 padding of section name
194 .long 0
195 .long 0
196 .long 0 // SizeOfRawData
197 .long 0 // PointerToRawData
198 .long 0 // PointerToRelocations
199 .long 0 // PointerToLineNumbers
200 .short 0 // NumberOfRelocations
201 .short 0 // NumberOfLineNumbers
202 .long 0x42100040 // Characteristics (section flags)
205 .ascii ".text"
206 .byte 0
207 .byte 0
208 .byte 0 // end of 0 padding of section name
209 .long _end - stext // VirtualSize
210 .long stext_offset // VirtualAddress
211 .long _edata - stext // SizeOfRawData
212 .long stext_offset // PointerToRawData
214 .long 0 // PointerToRelocations (0 for executables)
215 .long 0 // PointerToLineNumbers (0 for executables)
216 .short 0 // NumberOfRelocations (0 for executables)
217 .short 0 // NumberOfLineNumbers (0 for executables)
218 .long 0xe0500020 // Characteristics (section flags)
220 /*
221 * EFI will load stext onwards at the 4k section alignment
222 * described in the PE/COFF header. To ensure that instruction
223 * sequences using an adrp and a :lo12: immediate will function
224 * correctly at this alignment, we must ensure that stext is
225 * placed at a 4k boundary in the Image to begin with.
226 */
227 .align 12
228 #endif
230 ENTRY(stext)
231 bl preserve_boot_args
232 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
233 adrp x24, __PHYS_OFFSET
234 bl set_cpu_boot_mode_flag
235 bl __create_page_tables // x25=TTBR0, x26=TTBR1
236 /*
237 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
238 * details.
239 * On return, the CPU will be ready for the MMU to be turned on and
240 * the TCR will have been set.
241 */
242 ldr x27, =__mmap_switched // address to jump to after
243 // MMU has been enabled
244 adr_l lr, __enable_mmu // return (PIC) address
245 b __cpu_setup // initialise processor
246 ENDPROC(stext)
248 /*
249 * Preserve the arguments passed by the bootloader in x0 .. x3
250 */
251 preserve_boot_args:
252 mov x21, x0 // x21=FDT
254 adr_l x0, boot_args // record the contents of
255 stp x21, x1, [x0] // x0 .. x3 at kernel entry
256 stp x2, x3, [x0, #16]
258 dmb sy // needed before dc ivac with
259 // MMU off
261 add x1, x0, #0x20 // 4 x 8 bytes
262 b __inval_cache_range // tail call
263 ENDPROC(preserve_boot_args)
265 /*
266 * Macro to create a table entry to the next page.
267 *
268 * tbl: page table address
269 * virt: virtual address
270 * shift: #imm page table shift
271 * ptrs: #imm pointers per table page
272 *
273 * Preserves: virt
274 * Corrupts: tmp1, tmp2
275 * Returns: tbl -> next level table page address
276 */
277 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
278 lsr \tmp1, \virt, #\shift
279 and \tmp1, \tmp1, #\ptrs - 1 // table index
280 add \tmp2, \tbl, #PAGE_SIZE
281 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
282 str \tmp2, [\tbl, \tmp1, lsl #3]
283 add \tbl, \tbl, #PAGE_SIZE // next level table page
284 .endm
286 /*
287 * Macro to populate the PGD (and possibily PUD) for the corresponding
288 * block entry in the next level (tbl) for the given virtual address.
289 *
290 * Preserves: tbl, next, virt
291 * Corrupts: tmp1, tmp2
292 */
293 .macro create_pgd_entry, tbl, virt, tmp1, tmp2
294 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
295 #if SWAPPER_PGTABLE_LEVELS == 3
296 create_table_entry \tbl, \virt, TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
297 #endif
298 .endm
300 /*
301 * Macro to populate block entries in the page table for the start..end
302 * virtual range (inclusive).
303 *
304 * Preserves: tbl, flags
305 * Corrupts: phys, start, end, pstate
306 */
307 .macro create_block_map, tbl, flags, phys, start, end
308 lsr \phys, \phys, #BLOCK_SHIFT
309 lsr \start, \start, #BLOCK_SHIFT
310 and \start, \start, #PTRS_PER_PTE - 1 // table index
311 orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
312 lsr \end, \end, #BLOCK_SHIFT
313 and \end, \end, #PTRS_PER_PTE - 1 // table end index
314 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
315 add \start, \start, #1 // next entry
316 add \phys, \phys, #BLOCK_SIZE // next block
317 cmp \start, \end
318 b.ls 9999b
319 .endm
321 /*
322 * Setup the initial page tables. We only setup the barest amount which is
323 * required to get the kernel running. The following sections are required:
324 * - identity mapping to enable the MMU (low address, TTBR0)
325 * - first few MB of the kernel linear mapping to jump to once the MMU has
326 * been enabled
327 */
328 __create_page_tables:
329 adrp x25, idmap_pg_dir
330 adrp x26, swapper_pg_dir
331 mov x27, lr
333 /*
334 * Invalidate the idmap and swapper page tables to avoid potential
335 * dirty cache lines being evicted.
336 */
337 mov x0, x25
338 add x1, x26, #SWAPPER_DIR_SIZE
339 bl __inval_cache_range
341 /*
342 * Clear the idmap and swapper page tables.
343 */
344 mov x0, x25
345 add x6, x26, #SWAPPER_DIR_SIZE
346 1: stp xzr, xzr, [x0], #16
347 stp xzr, xzr, [x0], #16
348 stp xzr, xzr, [x0], #16
349 stp xzr, xzr, [x0], #16
350 cmp x0, x6
351 b.lo 1b
353 ldr x7, =MM_MMUFLAGS
355 /*
356 * Create the identity mapping.
357 */
358 mov x0, x25 // idmap_pg_dir
359 adrp x3, __idmap_text_start // __pa(__idmap_text_start)
361 #ifndef CONFIG_ARM64_VA_BITS_48
362 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
363 #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT))
365 /*
366 * If VA_BITS < 48, it may be too small to allow for an ID mapping to be
367 * created that covers system RAM if that is located sufficiently high
368 * in the physical address space. So for the ID map, use an extended
369 * virtual range in that case, by configuring an additional translation
370 * level.
371 * First, we have to verify our assumption that the current value of
372 * VA_BITS was chosen such that all translation levels are fully
373 * utilised, and that lowering T0SZ will always result in an additional
374 * translation level to be configured.
375 */
376 #if VA_BITS != EXTRA_SHIFT
377 #error "Mismatch between VA_BITS and page size/number of translation levels"
378 #endif
380 /*
381 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
382 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
383 * this number conveniently equals the number of leading zeroes in
384 * the physical address of __idmap_text_end.
385 */
386 adrp x5, __idmap_text_end
387 clz x5, x5
388 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
389 b.ge 1f // .. then skip additional level
391 adr_l x6, idmap_t0sz
392 str x5, [x6]
393 dmb sy
394 dc ivac, x6 // Invalidate potentially stale cache line
396 create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6
397 1:
398 #endif
400 create_pgd_entry x0, x3, x5, x6
401 mov x5, x3 // __pa(__idmap_text_start)
402 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
403 create_block_map x0, x7, x3, x5, x6
405 /*
406 * Map the kernel image (starting with PHYS_OFFSET).
407 */
408 mov x0, x26 // swapper_pg_dir
409 mov x5, #PAGE_OFFSET
410 create_pgd_entry x0, x5, x3, x6
411 ldr x6, =KERNEL_END // __va(KERNEL_END)
412 mov x3, x24 // phys offset
413 create_block_map x0, x7, x3, x5, x6
415 /*
416 * Since the page tables have been populated with non-cacheable
417 * accesses (MMU disabled), invalidate the idmap and swapper page
418 * tables again to remove any speculatively loaded cache lines.
419 */
420 mov x0, x25
421 add x1, x26, #SWAPPER_DIR_SIZE
422 dmb sy
423 bl __inval_cache_range
425 mov lr, x27
426 ret
427 ENDPROC(__create_page_tables)
428 .ltorg
430 /*
431 * The following fragment of code is executed with the MMU enabled.
432 */
433 .set initial_sp, init_thread_union + THREAD_START_SP
434 __mmap_switched:
435 adr_l x6, __bss_start
436 adr_l x7, __bss_stop
438 1: cmp x6, x7
439 b.hs 2f
440 str xzr, [x6], #8 // Clear BSS
441 b 1b
442 2:
443 adr_l sp, initial_sp, x4
444 str_l x21, __fdt_pointer, x5 // Save FDT pointer
445 str_l x24, memstart_addr, x6 // Save PHYS_OFFSET
446 mov x29, #0
447 b start_kernel
448 ENDPROC(__mmap_switched)
450 /*
451 * end early head section, begin head code that is also used for
452 * hotplug and needs to have the same protections as the text region
453 */
454 .section ".text","ax"
455 /*
456 * If we're fortunate enough to boot at EL2, ensure that the world is
457 * sane before dropping to EL1.
458 *
459 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
460 * booted in EL1 or EL2 respectively.
461 */
462 ENTRY(el2_setup)
463 mrs x0, CurrentEL
464 cmp x0, #CurrentEL_EL2
465 b.ne 1f
466 mrs x0, sctlr_el2
467 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
468 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
469 msr sctlr_el2, x0
470 b 2f
471 1: mrs x0, sctlr_el1
472 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
473 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
474 msr sctlr_el1, x0
475 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
476 isb
477 ret
479 /* Hyp configuration. */
480 2: mov x0, #(1 << 31) // 64-bit EL1
481 msr hcr_el2, x0
483 /* Generic timers. */
484 mrs x0, cnthctl_el2
485 orr x0, x0, #3 // Enable EL1 physical timers
486 msr cnthctl_el2, x0
487 msr cntvoff_el2, xzr // Clear virtual offset
489 #ifdef CONFIG_ARM_GIC_V3
490 /* GICv3 system register access */
491 mrs x0, id_aa64pfr0_el1
492 ubfx x0, x0, #24, #4
493 cmp x0, #1
494 b.ne 3f
496 mrs_s x0, ICC_SRE_EL2
497 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
498 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
499 msr_s ICC_SRE_EL2, x0
500 isb // Make sure SRE is now set
501 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
503 3:
504 #endif
506 /* Populate ID registers. */
507 mrs x0, midr_el1
508 mrs x1, mpidr_el1
509 msr vpidr_el2, x0
510 msr vmpidr_el2, x1
512 /* sctlr_el1 */
513 mov x0, #0x0800 // Set/clear RES{1,0} bits
514 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
515 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
516 msr sctlr_el1, x0
518 /* Coprocessor traps. */
519 mov x0, #0x33ff
520 msr cptr_el2, x0 // Disable copro. traps to EL2
522 #ifdef CONFIG_COMPAT
523 msr hstr_el2, xzr // Disable CP15 traps to EL2
524 #endif
526 /* EL2 debug */
527 mrs x0, pmcr_el0 // Disable debug access traps
528 ubfx x0, x0, #11, #5 // to EL2 and allow access to
529 msr mdcr_el2, x0 // all PMU counters from EL1
531 /* Stage-2 translation */
532 msr vttbr_el2, xzr
534 /* Hypervisor stub */
535 adrp x0, __hyp_stub_vectors
536 add x0, x0, #:lo12:__hyp_stub_vectors
537 msr vbar_el2, x0
539 /* spsr */
540 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
541 PSR_MODE_EL1h)
542 msr spsr_el2, x0
543 msr elr_el2, lr
544 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
545 eret
546 ENDPROC(el2_setup)
548 /*
549 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
550 * in x20. See arch/arm64/include/asm/virt.h for more info.
551 */
552 ENTRY(set_cpu_boot_mode_flag)
553 adr_l x1, __boot_cpu_mode
554 cmp w20, #BOOT_CPU_MODE_EL2
555 b.ne 1f
556 add x1, x1, #4
557 1: str w20, [x1] // This CPU has booted in EL1
558 dmb sy
559 dc ivac, x1 // Invalidate potentially stale cache line
560 ret
561 ENDPROC(set_cpu_boot_mode_flag)
563 /*
564 * We need to find out the CPU boot mode long after boot, so we need to
565 * store it in a writable variable.
566 *
567 * This is not in .bss, because we set it sufficiently early that the boot-time
568 * zeroing of .bss would clobber it.
569 */
570 .pushsection .data..cacheline_aligned
571 .align L1_CACHE_SHIFT
572 ENTRY(__boot_cpu_mode)
573 .long BOOT_CPU_MODE_EL2
574 .long BOOT_CPU_MODE_EL1
575 .popsection
577 /*
578 * This provides a "holding pen" for platforms to hold all secondary
579 * cores are held until we're ready for them to initialise.
580 */
581 ENTRY(secondary_holding_pen)
582 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
583 bl set_cpu_boot_mode_flag
584 mrs x0, mpidr_el1
585 ldr x1, =MPIDR_HWID_BITMASK
586 and x0, x0, x1
587 adr_l x3, secondary_holding_pen_release
588 pen: ldr x4, [x3]
589 cmp x4, x0
590 b.eq secondary_startup
591 wfe
592 b pen
593 ENDPROC(secondary_holding_pen)
595 /*
596 * Secondary entry point that jumps straight into the kernel. Only to
597 * be used where CPUs are brought online dynamically by the kernel.
598 */
599 ENTRY(secondary_entry)
600 bl el2_setup // Drop to EL1
601 bl set_cpu_boot_mode_flag
602 b secondary_startup
603 ENDPROC(secondary_entry)
605 ENTRY(secondary_startup)
606 /*
607 * Common entry point for secondary CPUs.
608 */
609 adrp x25, idmap_pg_dir
610 adrp x26, swapper_pg_dir
611 bl __cpu_setup // initialise processor
613 ldr x21, =secondary_data
614 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
615 b __enable_mmu
616 ENDPROC(secondary_startup)
618 ENTRY(__secondary_switched)
619 ldr x0, [x21] // get secondary_data.stack
620 mov sp, x0
621 mov x29, #0
622 b secondary_start_kernel
623 ENDPROC(__secondary_switched)
625 /*
626 * Enable the MMU.
627 *
628 * x0 = SCTLR_EL1 value for turning on the MMU.
629 * x27 = *virtual* address to jump to upon completion
630 *
631 * other registers depend on the function called upon completion
632 */
633 .section ".idmap.text", "ax"
634 __enable_mmu:
635 ldr x5, =vectors
636 msr vbar_el1, x5
637 msr ttbr0_el1, x25 // load TTBR0
638 msr ttbr1_el1, x26 // load TTBR1
639 isb
640 msr sctlr_el1, x0
641 isb
642 /*
643 * Invalidate the local I-cache so that any instructions fetched
644 * speculatively from the PoC are discarded, since they may have
645 * been dynamically patched at the PoU.
646 */
647 ic iallu
648 dsb nsh
649 isb
650 br x27
651 ENDPROC(__enable_mmu)