include/asm-mips/tx4938/tx4938.h

   1 /*
   2  * linux/include/asm-mips/tx4938/tx4938.h
   3  * Definitions for TX4937/TX4938
   4  * Copyright (C) 2000-2001 Toshiba Corporation
   5  *
   6  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
   7  * terms of the GNU General Public License version 2. This program is
   8  * licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  *
  11  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  12  */
  13 #ifndef __ASM_TX_BOARDS_TX4938_H
  14 #define __ASM_TX_BOARDS_TX4938_H
  15
  16 #define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
  17 #define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
  18
  19 #define TX4938_NR_IRQ_LOCAL     TX4938_IRQ_PIC_BEG
  20
  21 #define TX4938_IRQ_IRC_PCIC     (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC)
  22 #define TX4938_IRQ_IRC_PCIERR   (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR)
  23
  24 #define TX4938_PCIIO_0 0x10000000
  25 #define TX4938_PCIIO_1 0x01010000
  26 #define TX4938_PCIMEM_0 0x08000000
  27 #define TX4938_PCIMEM_1 0x11000000
  28
  29 #define TX4938_PCIIO_SIZE_0 0x01000000
  30 #define TX4938_PCIIO_SIZE_1 0x00010000
  31 #define TX4938_PCIMEM_SIZE_0 0x08000000
  32 #define TX4938_PCIMEM_SIZE_1 0x00010000
  33
  34 #define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
  35 #define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
  36
  37 /* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
  38 #define TX4938_NDFMC_REG        (TX4938_REG_BASE + 0x5000)
  39 #define TX4938_SRAMC_REG        (TX4938_REG_BASE + 0x6000)
  40 #define TX4938_PCIC1_REG        (TX4938_REG_BASE + 0x7000)
  41 #define TX4938_SDRAMC_REG       (TX4938_REG_BASE + 0x8000)
  42 #define TX4938_EBUSC_REG        (TX4938_REG_BASE + 0x9000)
  43 #define TX4938_DMA_REG(ch)      (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
  44 #define TX4938_PCIC_REG         (TX4938_REG_BASE + 0xd000)
  45 #define TX4938_CCFG_REG         (TX4938_REG_BASE + 0xe000)
  46 #define TX4938_NR_TMR   3
  47 #define TX4938_TMR_REG(ch)      ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
  48 #define TX4938_NR_SIO   2
  49 #define TX4938_SIO_REG(ch)      ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
  50 #define TX4938_PIO_REG          (TX4938_REG_BASE + 0xf500)
  51 #define TX4938_IRC_REG          (TX4938_REG_BASE + 0xf600)
  52 #define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
  53 #define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
  54
  55 #ifdef __ASSEMBLY__
  56 #define _CONST64(c)     c
  57 #else
  58 #define _CONST64(c)     c##ull
  59
  60 #include <asm/byteorder.h>
  61
  62 #ifdef __BIG_ENDIAN
  63 #define endian_def_l2(e1, e2)   \
  64         volatile unsigned long e1, e2
  65 #define endian_def_s2(e1, e2)   \
  66         volatile unsigned short e1, e2
  67 #define endian_def_sb2(e1, e2, e3)      \
  68         volatile unsigned short e1;volatile unsigned char e2, e3
  69 #define endian_def_b2s(e1, e2, e3)      \
  70         volatile unsigned char e1, e2;volatile unsigned short e3
  71 #define endian_def_b4(e1, e2, e3, e4)   \
  72         volatile unsigned char e1, e2, e3, e4
  73 #else
  74 #define endian_def_l2(e1, e2)   \
  75         volatile unsigned long e2, e1
  76 #define endian_def_s2(e1, e2)   \
  77         volatile unsigned short e2, e1
  78 #define endian_def_sb2(e1, e2, e3)      \
  79         volatile unsigned char e3, e2;volatile unsigned short e1
  80 #define endian_def_b2s(e1, e2, e3)      \
  81         volatile unsigned short e3;volatile unsigned char e2, e1
  82 #define endian_def_b4(e1, e2, e3, e4)   \
  83         volatile unsigned char e4, e3, e2, e1
  84 #endif
  85
  86
  87 struct tx4938_sdramc_reg {
  88         volatile unsigned long long cr[4];
  89         volatile unsigned long long unused0[4];
  90         volatile unsigned long long tr;
  91         volatile unsigned long long unused1[2];
  92         volatile unsigned long long cmd;
  93         volatile unsigned long long sfcmd;
  94 };
  95
  96 struct tx4938_ebusc_reg {
  97         volatile unsigned long long cr[8];
  98 };
  99
 100 struct tx4938_dma_reg {
 101         struct tx4938_dma_ch_reg {
 102                 volatile unsigned long long cha;
 103                 volatile unsigned long long sar;
 104                 volatile unsigned long long dar;
 105                 endian_def_l2(unused0, cntr);
 106                 endian_def_l2(unused1, sair);
 107                 endian_def_l2(unused2, dair);
 108                 endian_def_l2(unused3, ccr);
 109                 endian_def_l2(unused4, csr);
 110         } ch[4];
 111         volatile unsigned long long dbr[8];
 112         volatile unsigned long long tdhr;
 113         volatile unsigned long long midr;
 114         endian_def_l2(unused0, mcr);
 115 };
 116
 117 struct tx4938_pcic_reg {
 118         volatile unsigned long pciid;
 119         volatile unsigned long pcistatus;
 120         volatile unsigned long pciccrev;
 121         volatile unsigned long pcicfg1;
 122         volatile unsigned long p2gm0plbase;             /* +10 */
 123         volatile unsigned long p2gm0pubase;
 124         volatile unsigned long p2gm1plbase;
 125         volatile unsigned long p2gm1pubase;
 126         volatile unsigned long p2gm2pbase;              /* +20 */
 127         volatile unsigned long p2giopbase;
 128         volatile unsigned long unused0;
 129         volatile unsigned long pcisid;
 130         volatile unsigned long unused1;         /* +30 */
 131         volatile unsigned long pcicapptr;
 132         volatile unsigned long unused2;
 133         volatile unsigned long pcicfg2;
 134         volatile unsigned long g2ptocnt;                /* +40 */
 135         volatile unsigned long unused3[15];
 136         volatile unsigned long g2pstatus;               /* +80 */
 137         volatile unsigned long g2pmask;
 138         volatile unsigned long pcisstatus;
 139         volatile unsigned long pcimask;
 140         volatile unsigned long p2gcfg;          /* +90 */
 141         volatile unsigned long p2gstatus;
 142         volatile unsigned long p2gmask;
 143         volatile unsigned long p2gccmd;
 144         volatile unsigned long unused4[24];             /* +a0 */
 145         volatile unsigned long pbareqport;              /* +100 */
 146         volatile unsigned long pbacfg;
 147         volatile unsigned long pbastatus;
 148         volatile unsigned long pbamask;
 149         volatile unsigned long pbabm;           /* +110 */
 150         volatile unsigned long pbacreq;
 151         volatile unsigned long pbacgnt;
 152         volatile unsigned long pbacstate;
 153         volatile unsigned long long g2pmgbase[3];               /* +120 */
 154         volatile unsigned long long g2piogbase;
 155         volatile unsigned long g2pmmask[3];             /* +140 */
 156         volatile unsigned long g2piomask;
 157         volatile unsigned long long g2pmpbase[3];               /* +150 */
 158         volatile unsigned long long g2piopbase;
 159         volatile unsigned long pciccfg;         /* +170 */
 160         volatile unsigned long pcicstatus;
 161         volatile unsigned long pcicmask;
 162         volatile unsigned long unused5;
 163         volatile unsigned long long p2gmgbase[3];               /* +180 */
 164         volatile unsigned long long p2giogbase;
 165         volatile unsigned long g2pcfgadrs;              /* +1a0 */
 166         volatile unsigned long g2pcfgdata;
 167         volatile unsigned long unused6[8];
 168         volatile unsigned long g2pintack;
 169         volatile unsigned long g2pspc;
 170         volatile unsigned long unused7[12];             /* +1d0 */
 171         volatile unsigned long long pdmca;              /* +200 */
 172         volatile unsigned long long pdmga;
 173         volatile unsigned long long pdmpa;
 174         volatile unsigned long long pdmctr;
 175         volatile unsigned long long pdmcfg;             /* +220 */
 176         volatile unsigned long long pdmsts;
 177 };
 178
 179 struct tx4938_aclc_reg {
 180         volatile unsigned long acctlen;
 181         volatile unsigned long acctldis;
 182         volatile unsigned long acregacc;
 183         volatile unsigned long unused0;
 184         volatile unsigned long acintsts;
 185         volatile unsigned long acintmsts;
 186         volatile unsigned long acinten;
 187         volatile unsigned long acintdis;
 188         volatile unsigned long acsemaph;
 189         volatile unsigned long unused1[7];
 190         volatile unsigned long acgpidat;
 191         volatile unsigned long acgpodat;
 192         volatile unsigned long acslten;
 193         volatile unsigned long acsltdis;
 194         volatile unsigned long acfifosts;
 195         volatile unsigned long unused2[11];
 196         volatile unsigned long acdmasts;
 197         volatile unsigned long acdmasel;
 198         volatile unsigned long unused3[6];
 199         volatile unsigned long acaudodat;
 200         volatile unsigned long acsurrdat;
 201         volatile unsigned long accentdat;
 202         volatile unsigned long aclfedat;
 203         volatile unsigned long acaudiat;
 204         volatile unsigned long unused4;
 205         volatile unsigned long acmodoat;
 206         volatile unsigned long acmodidat;
 207         volatile unsigned long unused5[15];
 208         volatile unsigned long acrevid;
 209 };
 210
 211
 212 struct tx4938_tmr_reg {
 213         volatile unsigned long tcr;
 214         volatile unsigned long tisr;
 215         volatile unsigned long cpra;
 216         volatile unsigned long cprb;
 217         volatile unsigned long itmr;
 218         volatile unsigned long unused0[3];
 219         volatile unsigned long ccdr;
 220         volatile unsigned long unused1[3];
 221         volatile unsigned long pgmr;
 222         volatile unsigned long unused2[3];
 223         volatile unsigned long wtmr;
 224         volatile unsigned long unused3[43];
 225         volatile unsigned long trr;
 226 };
 227
 228 struct tx4938_sio_reg {
 229         volatile unsigned long lcr;
 230         volatile unsigned long dicr;
 231         volatile unsigned long disr;
 232         volatile unsigned long cisr;
 233         volatile unsigned long fcr;
 234         volatile unsigned long flcr;
 235         volatile unsigned long bgr;
 236         volatile unsigned long tfifo;
 237         volatile unsigned long rfifo;
 238 };
 239
 240 struct tx4938_ndfmc_reg {
 241         endian_def_l2(unused0, dtr);
 242         endian_def_l2(unused1, mcr);
 243         endian_def_l2(unused2, sr);
 244         endian_def_l2(unused3, isr);
 245         endian_def_l2(unused4, imr);
 246         endian_def_l2(unused5, spr);
 247         endian_def_l2(unused6, rstr);
 248 };
 249
 250 struct tx4938_spi_reg {
 251         volatile unsigned long mcr;
 252         volatile unsigned long cr0;
 253         volatile unsigned long cr1;
 254         volatile unsigned long fs;
 255         volatile unsigned long unused1;
 256         volatile unsigned long sr;
 257         volatile unsigned long dr;
 258         volatile unsigned long unused2;
 259 };
 260
 261 struct tx4938_sramc_reg {
 262         volatile unsigned long long cr;
 263 };
 264
 265 struct tx4938_ccfg_reg {
 266         volatile unsigned long long ccfg;
 267         volatile unsigned long long crir;
 268         volatile unsigned long long pcfg;
 269         volatile unsigned long long tear;
 270         volatile unsigned long long clkctr;
 271         volatile unsigned long long unused0;
 272         volatile unsigned long long garbc;
 273         volatile unsigned long long unused1;
 274         volatile unsigned long long unused2;
 275         volatile unsigned long long ramp;
 276         volatile unsigned long long unused3;
 277         volatile unsigned long long jmpadr;
 278 };
 279
 280 #undef endian_def_l2
 281 #undef endian_def_s2
 282 #undef endian_def_sb2
 283 #undef endian_def_b2s
 284 #undef endian_def_b4
 285
 286 #endif /* __ASSEMBLY__ */
 287
 288 /*
 289  * NDFMC
 290  */
 291
 292 /* NDFMCR : NDFMC Mode Control */
 293 #define TX4938_NDFMCR_WE        0x80
 294 #define TX4938_NDFMCR_ECC_ALL   0x60
 295 #define TX4938_NDFMCR_ECC_RESET 0x60
 296 #define TX4938_NDFMCR_ECC_READ  0x40
 297 #define TX4938_NDFMCR_ECC_ON    0x20
 298 #define TX4938_NDFMCR_ECC_OFF   0x00
 299 #define TX4938_NDFMCR_CE        0x10
 300 #define TX4938_NDFMCR_BSPRT     0x04
 301 #define TX4938_NDFMCR_ALE       0x02
 302 #define TX4938_NDFMCR_CLE       0x01
 303
 304 /* NDFMCR : NDFMC Status */
 305 #define TX4938_NDFSR_BUSY       0x80
 306
 307 /* NDFMCR : NDFMC Reset */
 308 #define TX4938_NDFRSTR_RST      0x01
 309
 310 /*
 311  * IRC
 312  */
 313
 314 #define TX4938_IR_ECCERR        0
 315 #define TX4938_IR_WTOERR        1
 316 #define TX4938_NUM_IR_INT       6
 317 #define TX4938_IR_INT(n)        (2 + (n))
 318 #define TX4938_NUM_IR_SIO       2
 319 #define TX4938_IR_SIO(n)        (8 + (n))
 320 #define TX4938_NUM_IR_DMA       4
 321 #define TX4938_IR_DMA(ch, n)    ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
 322 #define TX4938_IR_PIO   14
 323 #define TX4938_IR_PDMAC 15
 324 #define TX4938_IR_PCIC  16
 325 #define TX4938_NUM_IR_TMR       3
 326 #define TX4938_IR_TMR(n)        (17 + (n))
 327 #define TX4938_IR_NDFMC 21
 328 #define TX4938_IR_PCIERR        22
 329 #define TX4938_IR_PCIPME        23
 330 #define TX4938_IR_ACLC  24
 331 #define TX4938_IR_ACLCPME       25
 332 #define TX4938_IR_PCIC1 26
 333 #define TX4938_IR_SPI   31
 334 #define TX4938_NUM_IR   32
 335 /* multiplex */
 336 #define TX4938_IR_ETH0  TX4938_IR_INT(4)
 337 #define TX4938_IR_ETH1  TX4938_IR_INT(3)
 338
 339 /*
 340  * CCFG
 341  */
 342 /* CCFG : Chip Configuration */
 343 #define TX4938_CCFG_WDRST       _CONST64(0x0000020000000000)
 344 #define TX4938_CCFG_WDREXEN     _CONST64(0x0000010000000000)
 345 #define TX4938_CCFG_BCFG_MASK   _CONST64(0x000000ff00000000)
 346 #define TX4938_CCFG_TINTDIS     0x01000000
 347 #define TX4938_CCFG_PCI66       0x00800000
 348 #define TX4938_CCFG_PCIMODE     0x00400000
 349 #define TX4938_CCFG_PCI1_66     0x00200000
 350 #define TX4938_CCFG_DIVMODE_MASK        0x001e0000
 351 #define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
 352 #define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
 353 #define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
 354 #define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
 355 #define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
 356 #define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
 357 #define TX4938_CCFG_DIVMODE_10  (0xb << 17)
 358 #define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
 359 #define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
 360 #define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
 361 #define TX4938_CCFG_BEOW        0x00010000
 362 #define TX4938_CCFG_WR  0x00008000
 363 #define TX4938_CCFG_TOE 0x00004000
 364 #define TX4938_CCFG_PCIXARB     0x00002000
 365 #define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
 366 #define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
 367 #define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
 368 #define TX4938_CCFG_PCIDIVMODE_5        (0x5 << 10)
 369 #define TX4938_CCFG_PCIDIVMODE_5_5      (0x7 << 10)
 370 #define TX4938_CCFG_PCIDIVMODE_8        (0x0 << 10)
 371 #define TX4938_CCFG_PCIDIVMODE_9        (0x2 << 10)
 372 #define TX4938_CCFG_PCIDIVMODE_10       (0x4 << 10)
 373 #define TX4938_CCFG_PCIDIVMODE_11       (0x6 << 10)
 374 #define TX4938_CCFG_PCI1DMD     0x00000100
 375 #define TX4938_CCFG_SYSSP_MASK  0x000000c0
 376 #define TX4938_CCFG_ENDIAN      0x00000004
 377 #define TX4938_CCFG_HALT        0x00000002
 378 #define TX4938_CCFG_ACEHOLD     0x00000001
 379
 380 /* PCFG : Pin Configuration */
 381 #define TX4938_PCFG_ETH0_SEL    _CONST64(0x8000000000000000)
 382 #define TX4938_PCFG_ETH1_SEL    _CONST64(0x4000000000000000)
 383 #define TX4938_PCFG_ATA_SEL     _CONST64(0x2000000000000000)
 384 #define TX4938_PCFG_ISA_SEL     _CONST64(0x1000000000000000)
 385 #define TX4938_PCFG_SPI_SEL     _CONST64(0x0800000000000000)
 386 #define TX4938_PCFG_NDF_SEL     _CONST64(0x0400000000000000)
 387 #define TX4938_PCFG_SDCLKDLY_MASK       0x30000000
 388 #define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
 389 #define TX4938_PCFG_SYSCLKEN    0x08000000
 390 #define TX4938_PCFG_SDCLKEN_ALL 0x07800000
 391 #define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
 392 #define TX4938_PCFG_PCICLKEN_ALL        0x003f0000
 393 #define TX4938_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
 394 #define TX4938_PCFG_SEL2        0x00000200
 395 #define TX4938_PCFG_SEL1        0x00000100
 396 #define TX4938_PCFG_DMASEL_ALL  0x0000000f
 397 #define TX4938_PCFG_DMASEL0_DRQ0        0x00000000
 398 #define TX4938_PCFG_DMASEL0_SIO1        0x00000001
 399 #define TX4938_PCFG_DMASEL1_DRQ1        0x00000000
 400 #define TX4938_PCFG_DMASEL1_SIO1        0x00000002
 401 #define TX4938_PCFG_DMASEL2_DRQ2        0x00000000
 402 #define TX4938_PCFG_DMASEL2_SIO0        0x00000004
 403 #define TX4938_PCFG_DMASEL3_DRQ3        0x00000000
 404 #define TX4938_PCFG_DMASEL3_SIO0        0x00000008
 405
 406 /* CLKCTR : Clock Control */
 407 #define TX4938_CLKCTR_NDFCKD    _CONST64(0x0001000000000000)
 408 #define TX4938_CLKCTR_NDFRST    _CONST64(0x0000000100000000)
 409 #define TX4938_CLKCTR_ETH1CKD   0x80000000
 410 #define TX4938_CLKCTR_ETH0CKD   0x40000000
 411 #define TX4938_CLKCTR_SPICKD    0x20000000
 412 #define TX4938_CLKCTR_SRAMCKD   0x10000000
 413 #define TX4938_CLKCTR_PCIC1CKD  0x08000000
 414 #define TX4938_CLKCTR_DMA1CKD   0x04000000
 415 #define TX4938_CLKCTR_ACLCKD    0x02000000
 416 #define TX4938_CLKCTR_PIOCKD    0x01000000
 417 #define TX4938_CLKCTR_DMACKD    0x00800000
 418 #define TX4938_CLKCTR_PCICKD    0x00400000
 419 #define TX4938_CLKCTR_TM0CKD    0x00100000
 420 #define TX4938_CLKCTR_TM1CKD    0x00080000
 421 #define TX4938_CLKCTR_TM2CKD    0x00040000
 422 #define TX4938_CLKCTR_SIO0CKD   0x00020000
 423 #define TX4938_CLKCTR_SIO1CKD   0x00010000
 424 #define TX4938_CLKCTR_ETH1RST   0x00008000
 425 #define TX4938_CLKCTR_ETH0RST   0x00004000
 426 #define TX4938_CLKCTR_SPIRST    0x00002000
 427 #define TX4938_CLKCTR_SRAMRST   0x00001000
 428 #define TX4938_CLKCTR_PCIC1RST  0x00000800
 429 #define TX4938_CLKCTR_DMA1RST   0x00000400
 430 #define TX4938_CLKCTR_ACLRST    0x00000200
 431 #define TX4938_CLKCTR_PIORST    0x00000100
 432 #define TX4938_CLKCTR_DMARST    0x00000080
 433 #define TX4938_CLKCTR_PCIRST    0x00000040
 434 #define TX4938_CLKCTR_TM0RST    0x00000010
 435 #define TX4938_CLKCTR_TM1RST    0x00000008
 436 #define TX4938_CLKCTR_TM2RST    0x00000004
 437 #define TX4938_CLKCTR_SIO0RST   0x00000002
 438 #define TX4938_CLKCTR_SIO1RST   0x00000001
 439
 440 /* bits for G2PSTATUS/G2PMASK */
 441 #define TX4938_PCIC_G2PSTATUS_ALL       0x00000003
 442 #define TX4938_PCIC_G2PSTATUS_TTOE      0x00000002
 443 #define TX4938_PCIC_G2PSTATUS_RTOE      0x00000001
 444
 445 /* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
 446 #define TX4938_PCIC_PCISTATUS_ALL       0x0000f900
 447
 448 /* bits for PBACFG */
 449 #define TX4938_PCIC_PBACFG_FIXPA        0x00000008
 450 #define TX4938_PCIC_PBACFG_RPBA 0x00000004
 451 #define TX4938_PCIC_PBACFG_PBAEN        0x00000002
 452 #define TX4938_PCIC_PBACFG_BMCEN        0x00000001
 453
 454 /* bits for G2PMnGBASE */
 455 #define TX4938_PCIC_G2PMnGBASE_BSDIS    _CONST64(0x0000002000000000)
 456 #define TX4938_PCIC_G2PMnGBASE_ECHG     _CONST64(0x0000001000000000)
 457
 458 /* bits for G2PIOGBASE */
 459 #define TX4938_PCIC_G2PIOGBASE_BSDIS    _CONST64(0x0000002000000000)
 460 #define TX4938_PCIC_G2PIOGBASE_ECHG     _CONST64(0x0000001000000000)
 461
 462 /* bits for PCICSTATUS/PCICMASK */
 463 #define TX4938_PCIC_PCICSTATUS_ALL      0x000007b8
 464 #define TX4938_PCIC_PCICSTATUS_PME      0x00000400
 465 #define TX4938_PCIC_PCICSTATUS_TLB      0x00000200
 466 #define TX4938_PCIC_PCICSTATUS_NIB      0x00000100
 467 #define TX4938_PCIC_PCICSTATUS_ZIB      0x00000080
 468 #define TX4938_PCIC_PCICSTATUS_PERR     0x00000020
 469 #define TX4938_PCIC_PCICSTATUS_SERR     0x00000010
 470 #define TX4938_PCIC_PCICSTATUS_GBE      0x00000008
 471 #define TX4938_PCIC_PCICSTATUS_IWB      0x00000002
 472 #define TX4938_PCIC_PCICSTATUS_E2PDONE  0x00000001
 473
 474 /* bits for PCICCFG */
 475 #define TX4938_PCIC_PCICCFG_GBWC_MASK   0x0fff0000
 476 #define TX4938_PCIC_PCICCFG_HRST        0x00000800
 477 #define TX4938_PCIC_PCICCFG_SRST        0x00000400
 478 #define TX4938_PCIC_PCICCFG_IRBER       0x00000200
 479 #define TX4938_PCIC_PCICCFG_G2PMEN(ch)  (0x00000100>>(ch))
 480 #define TX4938_PCIC_PCICCFG_G2PM0EN     0x00000100
 481 #define TX4938_PCIC_PCICCFG_G2PM1EN     0x00000080
 482 #define TX4938_PCIC_PCICCFG_G2PM2EN     0x00000040
 483 #define TX4938_PCIC_PCICCFG_G2PIOEN     0x00000020
 484 #define TX4938_PCIC_PCICCFG_TCAR        0x00000010
 485 #define TX4938_PCIC_PCICCFG_ICAEN       0x00000008
 486
 487 /* bits for P2GMnGBASE */
 488 #define TX4938_PCIC_P2GMnGBASE_TMEMEN   _CONST64(0x0000004000000000)
 489 #define TX4938_PCIC_P2GMnGBASE_TBSDIS   _CONST64(0x0000002000000000)
 490 #define TX4938_PCIC_P2GMnGBASE_TECHG    _CONST64(0x0000001000000000)
 491
 492 /* bits for P2GIOGBASE */
 493 #define TX4938_PCIC_P2GIOGBASE_TIOEN    _CONST64(0x0000004000000000)
 494 #define TX4938_PCIC_P2GIOGBASE_TBSDIS   _CONST64(0x0000002000000000)
 495 #define TX4938_PCIC_P2GIOGBASE_TECHG    _CONST64(0x0000001000000000)
 496
 497 #define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
 498 #define TX4938_PCIC_MAX_DEVNU   TX4938_PCIC_IDSEL_AD_TO_SLOT(32)
 499
 500 /* bits for PDMCFG */
 501 #define TX4938_PCIC_PDMCFG_RSTFIFO      0x00200000
 502 #define TX4938_PCIC_PDMCFG_EXFER        0x00100000
 503 #define TX4938_PCIC_PDMCFG_REQDLY_MASK  0x00003800
 504 #define TX4938_PCIC_PDMCFG_REQDLY_NONE  (0 << 11)
 505 #define TX4938_PCIC_PDMCFG_REQDLY_16    (1 << 11)
 506 #define TX4938_PCIC_PDMCFG_REQDLY_32    (2 << 11)
 507 #define TX4938_PCIC_PDMCFG_REQDLY_64    (3 << 11)
 508 #define TX4938_PCIC_PDMCFG_REQDLY_128   (4 << 11)
 509 #define TX4938_PCIC_PDMCFG_REQDLY_256   (5 << 11)
 510 #define TX4938_PCIC_PDMCFG_REQDLY_512   (6 << 11)
 511 #define TX4938_PCIC_PDMCFG_REQDLY_1024  (7 << 11)
 512 #define TX4938_PCIC_PDMCFG_ERRIE        0x00000400
 513 #define TX4938_PCIC_PDMCFG_NCCMPIE      0x00000200
 514 #define TX4938_PCIC_PDMCFG_NTCMPIE      0x00000100
 515 #define TX4938_PCIC_PDMCFG_CHNEN        0x00000080
 516 #define TX4938_PCIC_PDMCFG_XFRACT       0x00000040
 517 #define TX4938_PCIC_PDMCFG_BSWAP        0x00000020
 518 #define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
 519 #define TX4938_PCIC_PDMCFG_XFRSIZE_1DW  0x00000000
 520 #define TX4938_PCIC_PDMCFG_XFRSIZE_1QW  0x00000004
 521 #define TX4938_PCIC_PDMCFG_XFRSIZE_4QW  0x00000008
 522 #define TX4938_PCIC_PDMCFG_XFRDIRC      0x00000002
 523 #define TX4938_PCIC_PDMCFG_CHRST        0x00000001
 524
 525 /* bits for PDMSTS */
 526 #define TX4938_PCIC_PDMSTS_REQCNT_MASK  0x3f000000
 527 #define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
 528 #define TX4938_PCIC_PDMSTS_FIFOWP_MASK  0x000c0000
 529 #define TX4938_PCIC_PDMSTS_FIFORP_MASK  0x00030000
 530 #define TX4938_PCIC_PDMSTS_ERRINT       0x00000800
 531 #define TX4938_PCIC_PDMSTS_DONEINT      0x00000400
 532 #define TX4938_PCIC_PDMSTS_CHNEN        0x00000200
 533 #define TX4938_PCIC_PDMSTS_XFRACT       0x00000100
 534 #define TX4938_PCIC_PDMSTS_ACCMP        0x00000080
 535 #define TX4938_PCIC_PDMSTS_NCCMP        0x00000040
 536 #define TX4938_PCIC_PDMSTS_NTCMP        0x00000020
 537 #define TX4938_PCIC_PDMSTS_CFGERR       0x00000008
 538 #define TX4938_PCIC_PDMSTS_PCIERR       0x00000004
 539 #define TX4938_PCIC_PDMSTS_CHNERR       0x00000002
 540 #define TX4938_PCIC_PDMSTS_DATAERR      0x00000001
 541 #define TX4938_PCIC_PDMSTS_ALL_CMP      0x000000e0
 542 #define TX4938_PCIC_PDMSTS_ALL_ERR      0x0000000f
 543
 544 /*
 545  * DMA
 546  */
 547 /* bits for MCR */
 548 #define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
 549 #define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
 550 #define TX4938_DMA_MCR_RSFIF    0x00000080
 551 #define TX4938_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
 552 #define TX4938_DMA_MCR_RPRT     0x00000002
 553 #define TX4938_DMA_MCR_MSTEN    0x00000001
 554
 555 /* bits for CCRn */
 556 #define TX4938_DMA_CCR_IMMCHN   0x20000000
 557 #define TX4938_DMA_CCR_USEXFSZ  0x10000000
 558 #define TX4938_DMA_CCR_LE       0x08000000
 559 #define TX4938_DMA_CCR_DBINH    0x04000000
 560 #define TX4938_DMA_CCR_SBINH    0x02000000
 561 #define TX4938_DMA_CCR_CHRST    0x01000000
 562 #define TX4938_DMA_CCR_RVBYTE   0x00800000
 563 #define TX4938_DMA_CCR_ACKPOL   0x00400000
 564 #define TX4938_DMA_CCR_REQPL    0x00200000
 565 #define TX4938_DMA_CCR_EGREQ    0x00100000
 566 #define TX4938_DMA_CCR_CHDN     0x00080000
 567 #define TX4938_DMA_CCR_DNCTL    0x00060000
 568 #define TX4938_DMA_CCR_EXTRQ    0x00010000
 569 #define TX4938_DMA_CCR_INTRQD   0x0000e000
 570 #define TX4938_DMA_CCR_INTENE   0x00001000
 571 #define TX4938_DMA_CCR_INTENC   0x00000800
 572 #define TX4938_DMA_CCR_INTENT   0x00000400
 573 #define TX4938_DMA_CCR_CHNEN    0x00000200
 574 #define TX4938_DMA_CCR_XFACT    0x00000100
 575 #define TX4938_DMA_CCR_SMPCHN   0x00000020
 576 #define TX4938_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
 577 #define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
 578 #define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
 579 #define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
 580 #define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
 581 #define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
 582 #define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
 583 #define TX4938_DMA_CCR_MEMIO    0x00000002
 584 #define TX4938_DMA_CCR_SNGAD    0x00000001
 585
 586 /* bits for CSRn */
 587 #define TX4938_DMA_CSR_CHNEN    0x00000400
 588 #define TX4938_DMA_CSR_STLXFER  0x00000200
 589 #define TX4938_DMA_CSR_CHNACT   0x00000100
 590 #define TX4938_DMA_CSR_ABCHC    0x00000080
 591 #define TX4938_DMA_CSR_NCHNC    0x00000040
 592 #define TX4938_DMA_CSR_NTRNFC   0x00000020
 593 #define TX4938_DMA_CSR_EXTDN    0x00000010
 594 #define TX4938_DMA_CSR_CFERR    0x00000008
 595 #define TX4938_DMA_CSR_CHERR    0x00000004
 596 #define TX4938_DMA_CSR_DESERR   0x00000002
 597 #define TX4938_DMA_CSR_SORERR   0x00000001
 598
 599 #ifndef __ASSEMBLY__
 600
 601 #define tx4938_sdramcptr        ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
 602 #define tx4938_ebuscptr         ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
 603 #define tx4938_dmaptr(ch)       ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
 604 #define tx4938_ndfmcptr         ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
 605 #define tx4938_pcicptr          ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
 606 #define tx4938_pcic1ptr         ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
 607 #define tx4938_ccfgptr          ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
 608 #define tx4938_sioptr(ch)       ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
 609 #define tx4938_pioptr           ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
 610 #define tx4938_aclcptr          ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
 611 #define tx4938_spiptr           ((struct tx4938_spi_reg *)TX4938_SPI_REG)
 612 #define tx4938_sramcptr         ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
 613
 614
 615 #define TX4938_REV_MAJ_MIN()    ((unsigned long)tx4938_ccfgptr->crir & 0x00ff)
 616 #define TX4938_REV_PCODE()      ((unsigned long)tx4938_ccfgptr->crir >> 16)
 617
 618 #define TX4938_SDRAMC_BA(ch)    ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
 619 #define TX4938_SDRAMC_SIZE(ch)  (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
 620
 621 #define TX4938_EBUSC_BA(ch)     ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
 622 #define TX4938_EBUSC_SIZE(ch)   \
 623         (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
 624
 625
 626 #endif /* !__ASSEMBLY__ */
 627
 628 #endif