drivers/video/pnx4008/dum.h

   1 /*
   2  * linux/drivers/video/pnx4008/dum.h
   3  *
   4  * Internal header for SDUM
   5  *
   6  * 2005 (c) Koninklijke Philips N.V. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11
  12 #ifndef __PNX008_DUM_H__
  13 #define __PNX008_DUM_H__
  14
  15 #include <mach/platform.h>
  16
  17 #define PNX4008_DUMCONF_VA_BASE         IO_ADDRESS(PNX4008_DUMCONF_BASE)
  18 #define PNX4008_DUM_MAIN_VA_BASE        IO_ADDRESS(PNX4008_DUM_MAINCFG_BASE)
  19
  20 /* DUM CFG ADDRESSES */
  21 #define DUM_CH_BASE_ADR         (PNX4008_DUMCONF_VA_BASE + 0x00)
  22 #define DUM_CH_MIN_ADR          (PNX4008_DUMCONF_VA_BASE + 0x00)
  23 #define DUM_CH_MAX_ADR          (PNX4008_DUMCONF_VA_BASE + 0x04)
  24 #define DUM_CH_CONF_ADR         (PNX4008_DUMCONF_VA_BASE + 0x08)
  25 #define DUM_CH_STAT_ADR         (PNX4008_DUMCONF_VA_BASE + 0x0C)
  26 #define DUM_CH_CTRL_ADR         (PNX4008_DUMCONF_VA_BASE + 0x10)
  27
  28 #define CH_MARG         (0x100 / sizeof(u32))
  29 #define DUM_CH_MIN(i)   (*((volatile u32 *)DUM_CH_MIN_ADR + (i) * CH_MARG))
  30 #define DUM_CH_MAX(i)   (*((volatile u32 *)DUM_CH_MAX_ADR + (i) * CH_MARG))
  31 #define DUM_CH_CONF(i)  (*((volatile u32 *)DUM_CH_CONF_ADR + (i) * CH_MARG))
  32 #define DUM_CH_STAT(i)  (*((volatile u32 *)DUM_CH_STAT_ADR + (i) * CH_MARG))
  33 #define DUM_CH_CTRL(i)  (*((volatile u32 *)DUM_CH_CTRL_ADR + (i) * CH_MARG))
  34
  35 #define DUM_CONF_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x00)
  36 #define DUM_CTRL_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x04)
  37 #define DUM_STAT_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x08)
  38 #define DUM_DECODE_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x0C)
  39 #define DUM_COM_BASE_ADR      (PNX4008_DUM_MAIN_VA_BASE + 0x10)
  40 #define DUM_SYNC_C_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x14)
  41 #define DUM_CLK_DIV_ADR       (PNX4008_DUM_MAIN_VA_BASE + 0x18)
  42 #define DUM_DIRTY_LOW_ADR     (PNX4008_DUM_MAIN_VA_BASE + 0x20)
  43 #define DUM_DIRTY_HIGH_ADR    (PNX4008_DUM_MAIN_VA_BASE + 0x24)
  44 #define DUM_FORMAT_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x28)
  45 #define DUM_WTCFG1_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x30)
  46 #define DUM_RTCFG1_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x34)
  47 #define DUM_WTCFG2_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x38)
  48 #define DUM_RTCFG2_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x3C)
  49 #define DUM_TCFG_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x40)
  50 #define DUM_OUTP_FORMAT1_ADR  (PNX4008_DUM_MAIN_VA_BASE + 0x44)
  51 #define DUM_OUTP_FORMAT2_ADR  (PNX4008_DUM_MAIN_VA_BASE + 0x48)
  52 #define DUM_SYNC_MODE_ADR     (PNX4008_DUM_MAIN_VA_BASE + 0x4C)
  53 #define DUM_SYNC_OUT_C_ADR    (PNX4008_DUM_MAIN_VA_BASE + 0x50)
  54
  55 #define DUM_CONF              (*(volatile u32 *)(DUM_CONF_ADR))
  56 #define DUM_CTRL              (*(volatile u32 *)(DUM_CTRL_ADR))
  57 #define DUM_STAT              (*(volatile u32 *)(DUM_STAT_ADR))
  58 #define DUM_DECODE            (*(volatile u32 *)(DUM_DECODE_ADR))
  59 #define DUM_COM_BASE          (*(volatile u32 *)(DUM_COM_BASE_ADR))
  60 #define DUM_SYNC_C            (*(volatile u32 *)(DUM_SYNC_C_ADR))
  61 #define DUM_CLK_DIV           (*(volatile u32 *)(DUM_CLK_DIV_ADR))
  62 #define DUM_DIRTY_LOW         (*(volatile u32 *)(DUM_DIRTY_LOW_ADR))
  63 #define DUM_DIRTY_HIGH        (*(volatile u32 *)(DUM_DIRTY_HIGH_ADR))
  64 #define DUM_FORMAT            (*(volatile u32 *)(DUM_FORMAT_ADR))
  65 #define DUM_WTCFG1            (*(volatile u32 *)(DUM_WTCFG1_ADR))
  66 #define DUM_RTCFG1            (*(volatile u32 *)(DUM_RTCFG1_ADR))
  67 #define DUM_WTCFG2            (*(volatile u32 *)(DUM_WTCFG2_ADR))
  68 #define DUM_RTCFG2            (*(volatile u32 *)(DUM_RTCFG2_ADR))
  69 #define DUM_TCFG              (*(volatile u32 *)(DUM_TCFG_ADR))
  70 #define DUM_OUTP_FORMAT1      (*(volatile u32 *)(DUM_OUTP_FORMAT1_ADR))
  71 #define DUM_OUTP_FORMAT2      (*(volatile u32 *)(DUM_OUTP_FORMAT2_ADR))
  72 #define DUM_SYNC_MODE         (*(volatile u32 *)(DUM_SYNC_MODE_ADR))
  73 #define DUM_SYNC_OUT_C        (*(volatile u32 *)(DUM_SYNC_OUT_C_ADR))
  74
  75 /* DUM SLAVE ADDRESSES */
  76 #define DUM_SLAVE_WRITE_ADR      (PNX4008_DUM_MAINCFG_BASE + 0x0000000)
  77 #define DUM_SLAVE_READ1_I_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x1000000)
  78 #define DUM_SLAVE_READ1_R_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x1000004)
  79 #define DUM_SLAVE_READ2_I_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x1000008)
  80 #define DUM_SLAVE_READ2_R_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x100000C)
  81
  82 #define DUM_SLAVE_WRITE_W  ((volatile u32 *)(DUM_SLAVE_WRITE_ADR))
  83 #define DUM_SLAVE_WRITE_HW ((volatile u16 *)(DUM_SLAVE_WRITE_ADR))
  84 #define DUM_SLAVE_READ1_I  ((volatile u8 *)(DUM_SLAVE_READ1_I_ADR))
  85 #define DUM_SLAVE_READ1_R  ((volatile u16 *)(DUM_SLAVE_READ1_R_ADR))
  86 #define DUM_SLAVE_READ2_I  ((volatile u8 *)(DUM_SLAVE_READ2_I_ADR))
  87 #define DUM_SLAVE_READ2_R  ((volatile u16 *)(DUM_SLAVE_READ2_R_ADR))
  88
  89 /* Sony display register addresses */
  90 #define DISP_0_REG            (0x00)
  91 #define DISP_1_REG            (0x01)
  92 #define DISP_CAL_REG          (0x20)
  93 #define DISP_ID_REG           (0x2A)
  94 #define DISP_XMIN_L_REG       (0x30)
  95 #define DISP_XMIN_H_REG       (0x31)
  96 #define DISP_YMIN_REG         (0x32)
  97 #define DISP_XMAX_L_REG       (0x34)
  98 #define DISP_XMAX_H_REG       (0x35)
  99 #define DISP_YMAX_REG         (0x36)
 100 #define DISP_SYNC_EN_REG      (0x38)
 101 #define DISP_SYNC_RISE_L_REG  (0x3C)
 102 #define DISP_SYNC_RISE_H_REG  (0x3D)
 103 #define DISP_SYNC_FALL_L_REG  (0x3E)
 104 #define DISP_SYNC_FALL_H_REG  (0x3F)
 105 #define DISP_PIXEL_REG        (0x0B)
 106 #define DISP_DUMMY1_REG       (0x28)
 107 #define DISP_DUMMY2_REG       (0x29)
 108 #define DISP_TIMING_REG       (0x98)
 109 #define DISP_DUMP_REG         (0x99)
 110
 111 /* Sony display constants */
 112 #define SONY_ID1              (0x22)
 113 #define SONY_ID2              (0x23)
 114
 115 /* Philips display register addresses */
 116 #define PH_DISP_ORIENT_REG    (0x003)
 117 #define PH_DISP_YPOINT_REG    (0x200)
 118 #define PH_DISP_XPOINT_REG    (0x201)
 119 #define PH_DISP_PIXEL_REG     (0x202)
 120 #define PH_DISP_YMIN_REG      (0x406)
 121 #define PH_DISP_YMAX_REG      (0x407)
 122 #define PH_DISP_XMIN_REG      (0x408)
 123 #define PH_DISP_XMAX_REG      (0x409)
 124
 125 /* Misc constants */
 126 #define NO_VALID_DISPLAY_FOUND      (0)
 127 #define DISPLAY2_IS_NOT_CONNECTED   (0)
 128
 129 /* register values */
 130 #define V_BAC_ENABLE            (BIT(0))
 131 #define V_BAC_DISABLE_IDLE      (BIT(1))
 132 #define V_BAC_DISABLE_TRIG      (BIT(2))
 133 #define V_DUM_RESET             (BIT(3))
 134 #define V_MUX_RESET             (BIT(4))
 135 #define BAC_ENABLED             (BIT(0))
 136 #define BAC_DISABLED            0
 137
 138 /* Sony LCD commands */
 139 #define V_LCD_STANDBY_OFF       ((BIT(25)) | (0 << 16) | DISP_0_REG)
 140 #define V_LCD_USE_9BIT_BUS      ((BIT(25)) | (2 << 16) | DISP_1_REG)
 141 #define V_LCD_SYNC_RISE_L       ((BIT(25)) | (0 << 16) | DISP_SYNC_RISE_L_REG)
 142 #define V_LCD_SYNC_RISE_H       ((BIT(25)) | (0 << 16) | DISP_SYNC_RISE_H_REG)
 143 #define V_LCD_SYNC_FALL_L       ((BIT(25)) | (160 << 16) | DISP_SYNC_FALL_L_REG)
 144 #define V_LCD_SYNC_FALL_H       ((BIT(25)) | (0 << 16) | DISP_SYNC_FALL_H_REG)
 145 #define V_LCD_SYNC_ENABLE       ((BIT(25)) | (128 << 16) | DISP_SYNC_EN_REG)
 146 #define V_LCD_DISPLAY_ON        ((BIT(25)) | (64 << 16) | DISP_0_REG)
 147
 148 enum {
 149         PAD_NONE,
 150         PAD_512,
 151         PAD_1024
 152 };
 153
 154 enum {
 155         RGB888,
 156         RGB666,
 157         RGB565,
 158         BGR565,
 159         ARGB1555,
 160         ABGR1555,
 161         ARGB4444,
 162         ABGR4444
 163 };
 164
 165 struct dum_setup {
 166         int sync_neg_edge;
 167         int round_robin;
 168         int mux_int;
 169         int synced_dirty_flag_int;
 170         int dirty_flag_int;
 171         int error_int;
 172         int pf_empty_int;
 173         int sf_empty_int;
 174         int bac_dis_int;
 175         u32 dirty_base_adr;
 176         u32 command_base_adr;
 177         u32 sync_clk_div;
 178         int sync_output;
 179         u32 sync_restart_val;
 180         u32 set_sync_high;
 181         u32 set_sync_low;
 182 };
 183
 184 struct dum_ch_setup {
 185         int disp_no;
 186         u32 xmin;
 187         u32 ymin;
 188         u32 xmax;
 189         u32 ymax;
 190         int xmirror;
 191         int ymirror;
 192         int rotate;
 193         u32 minadr;
 194         u32 maxadr;
 195         u32 dirtybuffer;
 196         int pad;
 197         int format;
 198         int hwdirty;
 199         int slave_trans;
 200 };
 201
 202 struct disp_window {
 203         u32 xmin_l;
 204         u32 xmin_h;
 205         u32 ymin;
 206         u32 xmax_l;
 207         u32 xmax_h;
 208         u32 ymax;
 209 };
 210
 211 #endif                          /* #ifndef __PNX008_DUM_H__ */