Merge tag 'for-usb-next-2012-07-11' of git://git.kernel.org/pub/scm/linux/kernel...
[linux/fpc-iii.git] / drivers / usb / host / xhci-hub.c
blob74bfc868b7ade609dc67cea66195bd499f92b067
1 /*
2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/gfp.h>
24 #include <asm/unaligned.h>
26 #include "xhci.h"
28 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
29 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
30 PORT_RC | PORT_PLC | PORT_PE)
32 /* usb 1.1 root hub device descriptor */
33 static u8 usb_bos_descriptor [] = {
34 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
35 USB_DT_BOS, /* __u8 bDescriptorType */
36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
37 0x1, /* __u8 bNumDeviceCaps */
38 /* First device capability */
39 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
40 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
41 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
42 0x00, /* bmAttributes, LTM off by default */
43 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
44 0x03, /* bFunctionalitySupport,
45 USB 3.0 speed only */
46 0x00, /* bU1DevExitLat, set later. */
47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
51 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
52 struct usb_hub_descriptor *desc, int ports)
54 u16 temp;
56 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
57 desc->bHubContrCurrent = 0;
59 desc->bNbrPorts = ports;
60 temp = 0;
61 /* Bits 1:0 - support per-port power switching, or power always on */
62 if (HCC_PPC(xhci->hcc_params))
63 temp |= HUB_CHAR_INDV_PORT_LPSM;
64 else
65 temp |= HUB_CHAR_NO_LPSM;
66 /* Bit 2 - root hubs are not part of a compound device */
67 /* Bits 4:3 - individual port over current protection */
68 temp |= HUB_CHAR_INDV_PORT_OCPM;
69 /* Bits 6:5 - no TTs in root ports */
70 /* Bit 7 - no port indicators */
71 desc->wHubCharacteristics = cpu_to_le16(temp);
74 /* Fill in the USB 2.0 roothub descriptor */
75 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
76 struct usb_hub_descriptor *desc)
78 int ports;
79 u16 temp;
80 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
81 u32 portsc;
82 unsigned int i;
84 ports = xhci->num_usb2_ports;
86 xhci_common_hub_descriptor(xhci, desc, ports);
87 desc->bDescriptorType = USB_DT_HUB;
88 temp = 1 + (ports / 8);
89 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
91 /* The Device Removable bits are reported on a byte granularity.
92 * If the port doesn't exist within that byte, the bit is set to 0.
94 memset(port_removable, 0, sizeof(port_removable));
95 for (i = 0; i < ports; i++) {
96 portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
97 /* If a device is removable, PORTSC reports a 0, same as in the
98 * hub descriptor DeviceRemovable bits.
100 if (portsc & PORT_DEV_REMOVE)
101 /* This math is hairy because bit 0 of DeviceRemovable
102 * is reserved, and bit 1 is for port 1, etc.
104 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
107 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
108 * ports on it. The USB 2.0 specification says that there are two
109 * variable length fields at the end of the hub descriptor:
110 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
111 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
112 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
113 * 0xFF, so we initialize the both arrays (DeviceRemovable and
114 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
115 * set of ports that actually exist.
117 memset(desc->u.hs.DeviceRemovable, 0xff,
118 sizeof(desc->u.hs.DeviceRemovable));
119 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
120 sizeof(desc->u.hs.PortPwrCtrlMask));
122 for (i = 0; i < (ports + 1 + 7) / 8; i++)
123 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
124 sizeof(__u8));
127 /* Fill in the USB 3.0 roothub descriptor */
128 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
129 struct usb_hub_descriptor *desc)
131 int ports;
132 u16 port_removable;
133 u32 portsc;
134 unsigned int i;
136 ports = xhci->num_usb3_ports;
137 xhci_common_hub_descriptor(xhci, desc, ports);
138 desc->bDescriptorType = USB_DT_SS_HUB;
139 desc->bDescLength = USB_DT_SS_HUB_SIZE;
141 /* header decode latency should be zero for roothubs,
142 * see section 4.23.5.2.
144 desc->u.ss.bHubHdrDecLat = 0;
145 desc->u.ss.wHubDelay = 0;
147 port_removable = 0;
148 /* bit 0 is reserved, bit 1 is for port 1, etc. */
149 for (i = 0; i < ports; i++) {
150 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
151 if (portsc & PORT_DEV_REMOVE)
152 port_removable |= 1 << (i + 1);
154 memset(&desc->u.ss.DeviceRemovable,
155 (__force __u16) cpu_to_le16(port_removable),
156 sizeof(__u16));
159 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
160 struct usb_hub_descriptor *desc)
163 if (hcd->speed == HCD_USB3)
164 xhci_usb3_hub_descriptor(hcd, xhci, desc);
165 else
166 xhci_usb2_hub_descriptor(hcd, xhci, desc);
170 static unsigned int xhci_port_speed(unsigned int port_status)
172 if (DEV_LOWSPEED(port_status))
173 return USB_PORT_STAT_LOW_SPEED;
174 if (DEV_HIGHSPEED(port_status))
175 return USB_PORT_STAT_HIGH_SPEED;
177 * FIXME: Yes, we should check for full speed, but the core uses that as
178 * a default in portspeed() in usb/core/hub.c (which is the only place
179 * USB_PORT_STAT_*_SPEED is used).
181 return 0;
185 * These bits are Read Only (RO) and should be saved and written to the
186 * registers: 0, 3, 10:13, 30
187 * connect status, over-current status, port speed, and device removable.
188 * connect status and port speed are also sticky - meaning they're in
189 * the AUX well and they aren't changed by a hot, warm, or cold reset.
191 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
193 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
194 * bits 5:8, 9, 14:15, 25:27
195 * link state, port power, port indicator state, "wake on" enable state
197 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
199 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
200 * bit 4 (port reset)
202 #define XHCI_PORT_RW1S ((1<<4))
204 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
205 * bits 1, 17, 18, 19, 20, 21, 22, 23
206 * port enable/disable, and
207 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
208 * over-current, reset, link state, and L1 change
210 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
212 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
213 * latched in
215 #define XHCI_PORT_RW ((1<<16))
217 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
218 * bits 2, 24, 28:31
220 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
223 * Given a port state, this function returns a value that would result in the
224 * port being in the same state, if the value was written to the port status
225 * control register.
226 * Save Read Only (RO) bits and save read/write bits where
227 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
228 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
230 u32 xhci_port_state_to_neutral(u32 state)
232 /* Save read-only status and port state */
233 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
237 * find slot id based on port number.
238 * @port: The one-based port number from one of the two split roothubs.
240 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
241 u16 port)
243 int slot_id;
244 int i;
245 enum usb_device_speed speed;
247 slot_id = 0;
248 for (i = 0; i < MAX_HC_SLOTS; i++) {
249 if (!xhci->devs[i])
250 continue;
251 speed = xhci->devs[i]->udev->speed;
252 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
253 && xhci->devs[i]->fake_port == port) {
254 slot_id = i;
255 break;
259 return slot_id;
263 * Stop device
264 * It issues stop endpoint command for EP 0 to 30. And wait the last command
265 * to complete.
266 * suspend will set to 1, if suspend bit need to set in command.
268 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
270 struct xhci_virt_device *virt_dev;
271 struct xhci_command *cmd;
272 unsigned long flags;
273 int timeleft;
274 int ret;
275 int i;
277 ret = 0;
278 virt_dev = xhci->devs[slot_id];
279 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
280 if (!cmd) {
281 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
282 return -ENOMEM;
285 spin_lock_irqsave(&xhci->lock, flags);
286 for (i = LAST_EP_INDEX; i > 0; i--) {
287 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
288 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
290 cmd->command_trb = xhci->cmd_ring->enqueue;
291 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
292 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
293 xhci_ring_cmd_db(xhci);
294 spin_unlock_irqrestore(&xhci->lock, flags);
296 /* Wait for last stop endpoint command to finish */
297 timeleft = wait_for_completion_interruptible_timeout(
298 cmd->completion,
299 USB_CTRL_SET_TIMEOUT);
300 if (timeleft <= 0) {
301 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
302 timeleft == 0 ? "Timeout" : "Signal");
303 spin_lock_irqsave(&xhci->lock, flags);
304 /* The timeout might have raced with the event ring handler, so
305 * only delete from the list if the item isn't poisoned.
307 if (cmd->cmd_list.next != LIST_POISON1)
308 list_del(&cmd->cmd_list);
309 spin_unlock_irqrestore(&xhci->lock, flags);
310 ret = -ETIME;
311 goto command_cleanup;
314 command_cleanup:
315 xhci_free_command(xhci, cmd);
316 return ret;
320 * Ring device, it rings the all doorbells unconditionally.
322 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
324 int i;
326 for (i = 0; i < LAST_EP_INDEX + 1; i++)
327 if (xhci->devs[slot_id]->eps[i].ring &&
328 xhci->devs[slot_id]->eps[i].ring->dequeue)
329 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
331 return;
334 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
335 u16 wIndex, __le32 __iomem *addr, u32 port_status)
337 /* Don't allow the USB core to disable SuperSpeed ports. */
338 if (hcd->speed == HCD_USB3) {
339 xhci_dbg(xhci, "Ignoring request to disable "
340 "SuperSpeed port.\n");
341 return;
344 /* Write 1 to disable the port */
345 xhci_writel(xhci, port_status | PORT_PE, addr);
346 port_status = xhci_readl(xhci, addr);
347 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
348 wIndex, port_status);
351 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
352 u16 wIndex, __le32 __iomem *addr, u32 port_status)
354 char *port_change_bit;
355 u32 status;
357 switch (wValue) {
358 case USB_PORT_FEAT_C_RESET:
359 status = PORT_RC;
360 port_change_bit = "reset";
361 break;
362 case USB_PORT_FEAT_C_BH_PORT_RESET:
363 status = PORT_WRC;
364 port_change_bit = "warm(BH) reset";
365 break;
366 case USB_PORT_FEAT_C_CONNECTION:
367 status = PORT_CSC;
368 port_change_bit = "connect";
369 break;
370 case USB_PORT_FEAT_C_OVER_CURRENT:
371 status = PORT_OCC;
372 port_change_bit = "over-current";
373 break;
374 case USB_PORT_FEAT_C_ENABLE:
375 status = PORT_PEC;
376 port_change_bit = "enable/disable";
377 break;
378 case USB_PORT_FEAT_C_SUSPEND:
379 status = PORT_PLC;
380 port_change_bit = "suspend/resume";
381 break;
382 case USB_PORT_FEAT_C_PORT_LINK_STATE:
383 status = PORT_PLC;
384 port_change_bit = "link state";
385 break;
386 default:
387 /* Should never happen */
388 return;
390 /* Change bits are all write 1 to clear */
391 xhci_writel(xhci, port_status | status, addr);
392 port_status = xhci_readl(xhci, addr);
393 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
394 port_change_bit, wIndex, port_status);
397 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
399 int max_ports;
400 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
402 if (hcd->speed == HCD_USB3) {
403 max_ports = xhci->num_usb3_ports;
404 *port_array = xhci->usb3_ports;
405 } else {
406 max_ports = xhci->num_usb2_ports;
407 *port_array = xhci->usb2_ports;
410 return max_ports;
413 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
414 int port_id, u32 link_state)
416 u32 temp;
418 temp = xhci_readl(xhci, port_array[port_id]);
419 temp = xhci_port_state_to_neutral(temp);
420 temp &= ~PORT_PLS_MASK;
421 temp |= PORT_LINK_STROBE | link_state;
422 xhci_writel(xhci, temp, port_array[port_id]);
425 void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
426 __le32 __iomem **port_array, int port_id, u16 wake_mask)
428 u32 temp;
430 temp = xhci_readl(xhci, port_array[port_id]);
431 temp = xhci_port_state_to_neutral(temp);
433 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
434 temp |= PORT_WKCONN_E;
435 else
436 temp &= ~PORT_WKCONN_E;
438 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
439 temp |= PORT_WKDISC_E;
440 else
441 temp &= ~PORT_WKDISC_E;
443 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
444 temp |= PORT_WKOC_E;
445 else
446 temp &= ~PORT_WKOC_E;
448 xhci_writel(xhci, temp, port_array[port_id]);
451 /* Test and clear port RWC bit */
452 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
453 int port_id, u32 port_bit)
455 u32 temp;
457 temp = xhci_readl(xhci, port_array[port_id]);
458 if (temp & port_bit) {
459 temp = xhci_port_state_to_neutral(temp);
460 temp |= port_bit;
461 xhci_writel(xhci, temp, port_array[port_id]);
465 /* Updates Link Status for super Speed port */
466 static void xhci_hub_report_link_state(u32 *status, u32 status_reg)
468 u32 pls = status_reg & PORT_PLS_MASK;
470 /* resume state is a xHCI internal state.
471 * Do not report it to usb core.
473 if (pls == XDEV_RESUME)
474 return;
476 /* When the CAS bit is set then warm reset
477 * should be performed on port
479 if (status_reg & PORT_CAS) {
480 /* The CAS bit can be set while the port is
481 * in any link state.
482 * Only roothubs have CAS bit, so we
483 * pretend to be in compliance mode
484 * unless we're already in compliance
485 * or the inactive state.
487 if (pls != USB_SS_PORT_LS_COMP_MOD &&
488 pls != USB_SS_PORT_LS_SS_INACTIVE) {
489 pls = USB_SS_PORT_LS_COMP_MOD;
491 /* Return also connection bit -
492 * hub state machine resets port
493 * when this bit is set.
495 pls |= USB_PORT_STAT_CONNECTION;
497 /* update status field */
498 *status |= pls;
501 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
502 u16 wIndex, char *buf, u16 wLength)
504 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
505 int max_ports;
506 unsigned long flags;
507 u32 temp, status;
508 int retval = 0;
509 __le32 __iomem **port_array;
510 int slot_id;
511 struct xhci_bus_state *bus_state;
512 u16 link_state = 0;
513 u16 wake_mask = 0;
514 u16 timeout = 0;
516 max_ports = xhci_get_ports(hcd, &port_array);
517 bus_state = &xhci->bus_state[hcd_index(hcd)];
519 spin_lock_irqsave(&xhci->lock, flags);
520 switch (typeReq) {
521 case GetHubStatus:
522 /* No power source, over-current reported per port */
523 memset(buf, 0, 4);
524 break;
525 case GetHubDescriptor:
526 /* Check to make sure userspace is asking for the USB 3.0 hub
527 * descriptor for the USB 3.0 roothub. If not, we stall the
528 * endpoint, like external hubs do.
530 if (hcd->speed == HCD_USB3 &&
531 (wLength < USB_DT_SS_HUB_SIZE ||
532 wValue != (USB_DT_SS_HUB << 8))) {
533 xhci_dbg(xhci, "Wrong hub descriptor type for "
534 "USB 3.0 roothub.\n");
535 goto error;
537 xhci_hub_descriptor(hcd, xhci,
538 (struct usb_hub_descriptor *) buf);
539 break;
540 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
541 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
542 goto error;
544 if (hcd->speed != HCD_USB3)
545 goto error;
547 /* Set the U1 and U2 exit latencies. */
548 memcpy(buf, &usb_bos_descriptor,
549 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
550 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
551 buf[12] = HCS_U1_LATENCY(temp);
552 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
554 /* Indicate whether the host has LTM support. */
555 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
556 if (HCC_LTC(temp))
557 buf[8] |= USB_LTM_SUPPORT;
559 spin_unlock_irqrestore(&xhci->lock, flags);
560 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
561 case GetPortStatus:
562 if (!wIndex || wIndex > max_ports)
563 goto error;
564 wIndex--;
565 status = 0;
566 temp = xhci_readl(xhci, port_array[wIndex]);
567 if (temp == 0xffffffff) {
568 retval = -ENODEV;
569 break;
571 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
573 /* wPortChange bits */
574 if (temp & PORT_CSC)
575 status |= USB_PORT_STAT_C_CONNECTION << 16;
576 if (temp & PORT_PEC)
577 status |= USB_PORT_STAT_C_ENABLE << 16;
578 if ((temp & PORT_OCC))
579 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
580 if ((temp & PORT_RC))
581 status |= USB_PORT_STAT_C_RESET << 16;
582 /* USB3.0 only */
583 if (hcd->speed == HCD_USB3) {
584 if ((temp & PORT_PLC))
585 status |= USB_PORT_STAT_C_LINK_STATE << 16;
586 if ((temp & PORT_WRC))
587 status |= USB_PORT_STAT_C_BH_RESET << 16;
590 if (hcd->speed != HCD_USB3) {
591 if ((temp & PORT_PLS_MASK) == XDEV_U3
592 && (temp & PORT_POWER))
593 status |= USB_PORT_STAT_SUSPEND;
595 if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
596 !DEV_SUPERSPEED(temp)) {
597 if ((temp & PORT_RESET) || !(temp & PORT_PE))
598 goto error;
599 if (time_after_eq(jiffies,
600 bus_state->resume_done[wIndex])) {
601 xhci_dbg(xhci, "Resume USB2 port %d\n",
602 wIndex + 1);
603 bus_state->resume_done[wIndex] = 0;
604 clear_bit(wIndex, &bus_state->resuming_ports);
605 xhci_set_link_state(xhci, port_array, wIndex,
606 XDEV_U0);
607 xhci_dbg(xhci, "set port %d resume\n",
608 wIndex + 1);
609 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
610 wIndex + 1);
611 if (!slot_id) {
612 xhci_dbg(xhci, "slot_id is zero\n");
613 goto error;
615 xhci_ring_device(xhci, slot_id);
616 bus_state->port_c_suspend |= 1 << wIndex;
617 bus_state->suspended_ports &= ~(1 << wIndex);
618 } else {
620 * The resume has been signaling for less than
621 * 20ms. Report the port status as SUSPEND,
622 * let the usbcore check port status again
623 * and clear resume signaling later.
625 status |= USB_PORT_STAT_SUSPEND;
628 if ((temp & PORT_PLS_MASK) == XDEV_U0
629 && (temp & PORT_POWER)
630 && (bus_state->suspended_ports & (1 << wIndex))) {
631 bus_state->suspended_ports &= ~(1 << wIndex);
632 if (hcd->speed != HCD_USB3)
633 bus_state->port_c_suspend |= 1 << wIndex;
635 if (temp & PORT_CONNECT) {
636 status |= USB_PORT_STAT_CONNECTION;
637 status |= xhci_port_speed(temp);
639 if (temp & PORT_PE)
640 status |= USB_PORT_STAT_ENABLE;
641 if (temp & PORT_OC)
642 status |= USB_PORT_STAT_OVERCURRENT;
643 if (temp & PORT_RESET)
644 status |= USB_PORT_STAT_RESET;
645 if (temp & PORT_POWER) {
646 if (hcd->speed == HCD_USB3)
647 status |= USB_SS_PORT_STAT_POWER;
648 else
649 status |= USB_PORT_STAT_POWER;
651 /* Update Port Link State for super speed ports*/
652 if (hcd->speed == HCD_USB3) {
653 xhci_hub_report_link_state(&status, temp);
655 if (bus_state->port_c_suspend & (1 << wIndex))
656 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
657 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
658 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
659 break;
660 case SetPortFeature:
661 if (wValue == USB_PORT_FEAT_LINK_STATE)
662 link_state = (wIndex & 0xff00) >> 3;
663 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
664 wake_mask = wIndex & 0xff00;
665 /* The MSB of wIndex is the U1/U2 timeout */
666 timeout = (wIndex & 0xff00) >> 8;
667 wIndex &= 0xff;
668 if (!wIndex || wIndex > max_ports)
669 goto error;
670 wIndex--;
671 temp = xhci_readl(xhci, port_array[wIndex]);
672 if (temp == 0xffffffff) {
673 retval = -ENODEV;
674 break;
676 temp = xhci_port_state_to_neutral(temp);
677 /* FIXME: What new port features do we need to support? */
678 switch (wValue) {
679 case USB_PORT_FEAT_SUSPEND:
680 temp = xhci_readl(xhci, port_array[wIndex]);
681 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
682 /* Resume the port to U0 first */
683 xhci_set_link_state(xhci, port_array, wIndex,
684 XDEV_U0);
685 spin_unlock_irqrestore(&xhci->lock, flags);
686 msleep(10);
687 spin_lock_irqsave(&xhci->lock, flags);
689 /* In spec software should not attempt to suspend
690 * a port unless the port reports that it is in the
691 * enabled (PED = ‘1’,PLS < ‘3’) state.
693 temp = xhci_readl(xhci, port_array[wIndex]);
694 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
695 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
696 xhci_warn(xhci, "USB core suspending device "
697 "not in U0/U1/U2.\n");
698 goto error;
701 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
702 wIndex + 1);
703 if (!slot_id) {
704 xhci_warn(xhci, "slot_id is zero\n");
705 goto error;
707 /* unlock to execute stop endpoint commands */
708 spin_unlock_irqrestore(&xhci->lock, flags);
709 xhci_stop_device(xhci, slot_id, 1);
710 spin_lock_irqsave(&xhci->lock, flags);
712 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
714 spin_unlock_irqrestore(&xhci->lock, flags);
715 msleep(10); /* wait device to enter */
716 spin_lock_irqsave(&xhci->lock, flags);
718 temp = xhci_readl(xhci, port_array[wIndex]);
719 bus_state->suspended_ports |= 1 << wIndex;
720 break;
721 case USB_PORT_FEAT_LINK_STATE:
722 temp = xhci_readl(xhci, port_array[wIndex]);
723 /* Software should not attempt to set
724 * port link state above '5' (Rx.Detect) and the port
725 * must be enabled.
727 if ((temp & PORT_PE) == 0 ||
728 (link_state > USB_SS_PORT_LS_RX_DETECT)) {
729 xhci_warn(xhci, "Cannot set link state.\n");
730 goto error;
733 if (link_state == USB_SS_PORT_LS_U3) {
734 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
735 wIndex + 1);
736 if (slot_id) {
737 /* unlock to execute stop endpoint
738 * commands */
739 spin_unlock_irqrestore(&xhci->lock,
740 flags);
741 xhci_stop_device(xhci, slot_id, 1);
742 spin_lock_irqsave(&xhci->lock, flags);
746 xhci_set_link_state(xhci, port_array, wIndex,
747 link_state);
749 spin_unlock_irqrestore(&xhci->lock, flags);
750 msleep(20); /* wait device to enter */
751 spin_lock_irqsave(&xhci->lock, flags);
753 temp = xhci_readl(xhci, port_array[wIndex]);
754 if (link_state == USB_SS_PORT_LS_U3)
755 bus_state->suspended_ports |= 1 << wIndex;
756 break;
757 case USB_PORT_FEAT_POWER:
759 * Turn on ports, even if there isn't per-port switching.
760 * HC will report connect events even before this is set.
761 * However, khubd will ignore the roothub events until
762 * the roothub is registered.
764 xhci_writel(xhci, temp | PORT_POWER,
765 port_array[wIndex]);
767 temp = xhci_readl(xhci, port_array[wIndex]);
768 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
769 break;
770 case USB_PORT_FEAT_RESET:
771 temp = (temp | PORT_RESET);
772 xhci_writel(xhci, temp, port_array[wIndex]);
774 temp = xhci_readl(xhci, port_array[wIndex]);
775 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
776 break;
777 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
778 xhci_set_remote_wake_mask(xhci, port_array,
779 wIndex, wake_mask);
780 temp = xhci_readl(xhci, port_array[wIndex]);
781 xhci_dbg(xhci, "set port remote wake mask, "
782 "actual port %d status = 0x%x\n",
783 wIndex, temp);
784 break;
785 case USB_PORT_FEAT_BH_PORT_RESET:
786 temp |= PORT_WR;
787 xhci_writel(xhci, temp, port_array[wIndex]);
789 temp = xhci_readl(xhci, port_array[wIndex]);
790 break;
791 case USB_PORT_FEAT_U1_TIMEOUT:
792 if (hcd->speed != HCD_USB3)
793 goto error;
794 temp = xhci_readl(xhci, port_array[wIndex] + 1);
795 temp &= ~PORT_U1_TIMEOUT_MASK;
796 temp |= PORT_U1_TIMEOUT(timeout);
797 xhci_writel(xhci, temp, port_array[wIndex] + 1);
798 break;
799 case USB_PORT_FEAT_U2_TIMEOUT:
800 if (hcd->speed != HCD_USB3)
801 goto error;
802 temp = xhci_readl(xhci, port_array[wIndex] + 1);
803 temp &= ~PORT_U2_TIMEOUT_MASK;
804 temp |= PORT_U2_TIMEOUT(timeout);
805 xhci_writel(xhci, temp, port_array[wIndex] + 1);
806 break;
807 default:
808 goto error;
810 /* unblock any posted writes */
811 temp = xhci_readl(xhci, port_array[wIndex]);
812 break;
813 case ClearPortFeature:
814 if (!wIndex || wIndex > max_ports)
815 goto error;
816 wIndex--;
817 temp = xhci_readl(xhci, port_array[wIndex]);
818 if (temp == 0xffffffff) {
819 retval = -ENODEV;
820 break;
822 /* FIXME: What new port features do we need to support? */
823 temp = xhci_port_state_to_neutral(temp);
824 switch (wValue) {
825 case USB_PORT_FEAT_SUSPEND:
826 temp = xhci_readl(xhci, port_array[wIndex]);
827 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
828 xhci_dbg(xhci, "PORTSC %04x\n", temp);
829 if (temp & PORT_RESET)
830 goto error;
831 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
832 if ((temp & PORT_PE) == 0)
833 goto error;
835 xhci_set_link_state(xhci, port_array, wIndex,
836 XDEV_RESUME);
837 spin_unlock_irqrestore(&xhci->lock, flags);
838 msleep(20);
839 spin_lock_irqsave(&xhci->lock, flags);
840 xhci_set_link_state(xhci, port_array, wIndex,
841 XDEV_U0);
843 bus_state->port_c_suspend |= 1 << wIndex;
845 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
846 wIndex + 1);
847 if (!slot_id) {
848 xhci_dbg(xhci, "slot_id is zero\n");
849 goto error;
851 xhci_ring_device(xhci, slot_id);
852 break;
853 case USB_PORT_FEAT_C_SUSPEND:
854 bus_state->port_c_suspend &= ~(1 << wIndex);
855 case USB_PORT_FEAT_C_RESET:
856 case USB_PORT_FEAT_C_BH_PORT_RESET:
857 case USB_PORT_FEAT_C_CONNECTION:
858 case USB_PORT_FEAT_C_OVER_CURRENT:
859 case USB_PORT_FEAT_C_ENABLE:
860 case USB_PORT_FEAT_C_PORT_LINK_STATE:
861 xhci_clear_port_change_bit(xhci, wValue, wIndex,
862 port_array[wIndex], temp);
863 break;
864 case USB_PORT_FEAT_ENABLE:
865 xhci_disable_port(hcd, xhci, wIndex,
866 port_array[wIndex], temp);
867 break;
868 default:
869 goto error;
871 break;
872 default:
873 error:
874 /* "stall" on error */
875 retval = -EPIPE;
877 spin_unlock_irqrestore(&xhci->lock, flags);
878 return retval;
882 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
883 * Ports are 0-indexed from the HCD point of view,
884 * and 1-indexed from the USB core pointer of view.
886 * Note that the status change bits will be cleared as soon as a port status
887 * change event is generated, so we use the saved status from that event.
889 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
891 unsigned long flags;
892 u32 temp, status;
893 u32 mask;
894 int i, retval;
895 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
896 int max_ports;
897 __le32 __iomem **port_array;
898 struct xhci_bus_state *bus_state;
900 max_ports = xhci_get_ports(hcd, &port_array);
901 bus_state = &xhci->bus_state[hcd_index(hcd)];
903 /* Initial status is no changes */
904 retval = (max_ports + 8) / 8;
905 memset(buf, 0, retval);
908 * Inform the usbcore about resume-in-progress by returning
909 * a non-zero value even if there are no status changes.
911 status = bus_state->resuming_ports;
913 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
915 spin_lock_irqsave(&xhci->lock, flags);
916 /* For each port, did anything change? If so, set that bit in buf. */
917 for (i = 0; i < max_ports; i++) {
918 temp = xhci_readl(xhci, port_array[i]);
919 if (temp == 0xffffffff) {
920 retval = -ENODEV;
921 break;
923 if ((temp & mask) != 0 ||
924 (bus_state->port_c_suspend & 1 << i) ||
925 (bus_state->resume_done[i] && time_after_eq(
926 jiffies, bus_state->resume_done[i]))) {
927 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
928 status = 1;
931 spin_unlock_irqrestore(&xhci->lock, flags);
932 return status ? retval : 0;
935 #ifdef CONFIG_PM
937 int xhci_bus_suspend(struct usb_hcd *hcd)
939 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
940 int max_ports, port_index;
941 __le32 __iomem **port_array;
942 struct xhci_bus_state *bus_state;
943 unsigned long flags;
945 max_ports = xhci_get_ports(hcd, &port_array);
946 bus_state = &xhci->bus_state[hcd_index(hcd)];
948 spin_lock_irqsave(&xhci->lock, flags);
950 if (hcd->self.root_hub->do_remote_wakeup) {
951 if (bus_state->resuming_ports) {
952 spin_unlock_irqrestore(&xhci->lock, flags);
953 xhci_dbg(xhci, "suspend failed because "
954 "a port is resuming\n");
955 return -EBUSY;
959 port_index = max_ports;
960 bus_state->bus_suspended = 0;
961 while (port_index--) {
962 /* suspend the port if the port is not suspended */
963 u32 t1, t2;
964 int slot_id;
966 t1 = xhci_readl(xhci, port_array[port_index]);
967 t2 = xhci_port_state_to_neutral(t1);
969 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
970 xhci_dbg(xhci, "port %d not suspended\n", port_index);
971 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
972 port_index + 1);
973 if (slot_id) {
974 spin_unlock_irqrestore(&xhci->lock, flags);
975 xhci_stop_device(xhci, slot_id, 1);
976 spin_lock_irqsave(&xhci->lock, flags);
978 t2 &= ~PORT_PLS_MASK;
979 t2 |= PORT_LINK_STROBE | XDEV_U3;
980 set_bit(port_index, &bus_state->bus_suspended);
982 /* USB core sets remote wake mask for USB 3.0 hubs,
983 * including the USB 3.0 roothub, but only if CONFIG_USB_SUSPEND
984 * is enabled, so also enable remote wake here.
986 if (hcd->self.root_hub->do_remote_wakeup) {
987 if (t1 & PORT_CONNECT) {
988 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
989 t2 &= ~PORT_WKCONN_E;
990 } else {
991 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
992 t2 &= ~PORT_WKDISC_E;
994 } else
995 t2 &= ~PORT_WAKE_BITS;
997 t1 = xhci_port_state_to_neutral(t1);
998 if (t1 != t2)
999 xhci_writel(xhci, t2, port_array[port_index]);
1001 if (hcd->speed != HCD_USB3) {
1002 /* enable remote wake up for USB 2.0 */
1003 __le32 __iomem *addr;
1004 u32 tmp;
1006 /* Add one to the port status register address to get
1007 * the port power control register address.
1009 addr = port_array[port_index] + 1;
1010 tmp = xhci_readl(xhci, addr);
1011 tmp |= PORT_RWE;
1012 xhci_writel(xhci, tmp, addr);
1015 hcd->state = HC_STATE_SUSPENDED;
1016 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1017 spin_unlock_irqrestore(&xhci->lock, flags);
1018 return 0;
1021 int xhci_bus_resume(struct usb_hcd *hcd)
1023 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1024 int max_ports, port_index;
1025 __le32 __iomem **port_array;
1026 struct xhci_bus_state *bus_state;
1027 u32 temp;
1028 unsigned long flags;
1030 max_ports = xhci_get_ports(hcd, &port_array);
1031 bus_state = &xhci->bus_state[hcd_index(hcd)];
1033 if (time_before(jiffies, bus_state->next_statechange))
1034 msleep(5);
1036 spin_lock_irqsave(&xhci->lock, flags);
1037 if (!HCD_HW_ACCESSIBLE(hcd)) {
1038 spin_unlock_irqrestore(&xhci->lock, flags);
1039 return -ESHUTDOWN;
1042 /* delay the irqs */
1043 temp = xhci_readl(xhci, &xhci->op_regs->command);
1044 temp &= ~CMD_EIE;
1045 xhci_writel(xhci, temp, &xhci->op_regs->command);
1047 port_index = max_ports;
1048 while (port_index--) {
1049 /* Check whether need resume ports. If needed
1050 resume port and disable remote wakeup */
1051 u32 temp;
1052 int slot_id;
1054 temp = xhci_readl(xhci, port_array[port_index]);
1055 if (DEV_SUPERSPEED(temp))
1056 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1057 else
1058 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1059 if (test_bit(port_index, &bus_state->bus_suspended) &&
1060 (temp & PORT_PLS_MASK)) {
1061 if (DEV_SUPERSPEED(temp)) {
1062 xhci_set_link_state(xhci, port_array,
1063 port_index, XDEV_U0);
1064 } else {
1065 xhci_set_link_state(xhci, port_array,
1066 port_index, XDEV_RESUME);
1068 spin_unlock_irqrestore(&xhci->lock, flags);
1069 msleep(20);
1070 spin_lock_irqsave(&xhci->lock, flags);
1072 xhci_set_link_state(xhci, port_array,
1073 port_index, XDEV_U0);
1075 /* wait for the port to enter U0 and report port link
1076 * state change.
1078 spin_unlock_irqrestore(&xhci->lock, flags);
1079 msleep(20);
1080 spin_lock_irqsave(&xhci->lock, flags);
1082 /* Clear PLC */
1083 xhci_test_and_clear_bit(xhci, port_array, port_index,
1084 PORT_PLC);
1086 slot_id = xhci_find_slot_id_by_port(hcd,
1087 xhci, port_index + 1);
1088 if (slot_id)
1089 xhci_ring_device(xhci, slot_id);
1090 } else
1091 xhci_writel(xhci, temp, port_array[port_index]);
1093 if (hcd->speed != HCD_USB3) {
1094 /* disable remote wake up for USB 2.0 */
1095 __le32 __iomem *addr;
1096 u32 tmp;
1098 /* Add one to the port status register address to get
1099 * the port power control register address.
1101 addr = port_array[port_index] + 1;
1102 tmp = xhci_readl(xhci, addr);
1103 tmp &= ~PORT_RWE;
1104 xhci_writel(xhci, tmp, addr);
1108 (void) xhci_readl(xhci, &xhci->op_regs->command);
1110 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1111 /* re-enable irqs */
1112 temp = xhci_readl(xhci, &xhci->op_regs->command);
1113 temp |= CMD_EIE;
1114 xhci_writel(xhci, temp, &xhci->op_regs->command);
1115 temp = xhci_readl(xhci, &xhci->op_regs->command);
1117 spin_unlock_irqrestore(&xhci->lock, flags);
1118 return 0;
1121 #endif /* CONFIG_PM */