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block: move down direct IO plugging
[linux/fpc-iii.git] / arch / arm / mach-exynos / clock-exynos4.c
blob2f51293c18757712621bb26723f10d1ced8099dd
1 /*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4 - Clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/syscore_ops.h>
16
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
19 #include <plat/cpu.h>
20 #include <plat/pll.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
23 #include <plat/pm.h>
24
25 #include <mach/map.h>
26 #include <mach/regs-clock.h>
27 #include <mach/sysmmu.h>
28
29 #include "common.h"
30 #include "clock-exynos4.h"
31
32 #ifdef CONFIG_PM_SLEEP
33 static struct sleep_save exynos4_clock_save[] = {
34 SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
35 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
36 SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
37 SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
38 SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
39 SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
40 SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
41 SAVE_ITEM(EXYNOS4_CLKSRC_TV),
42 SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
43 SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
44 SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
45 SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
46 SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
47 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
48 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
49 SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
50 SAVE_ITEM(EXYNOS4_CLKDIV_TV),
51 SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
52 SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
53 SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
54 SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
55 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
56 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
57 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
58 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
59 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
60 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
61 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
62 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
63 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
64 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
65 SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
66 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
67 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
68 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
69 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
70 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
71 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
72 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
73 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
74 SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
75 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
76 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
77 SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
78 SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
79 SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
80 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
81 SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
82 SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
83 SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
84 SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
85 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
86 SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
87 SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
88 SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
89 SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
90 SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
91 SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
92 SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
93 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
94 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
95 };
96 #endif
97
98 static struct clk exynos4_clk_sclk_hdmi27m = {
99 .name = "sclk_hdmi27m",
100 .rate = 27000000,
101 };
102
103 static struct clk exynos4_clk_sclk_hdmiphy = {
104 .name = "sclk_hdmiphy",
105 };
106
107 static struct clk exynos4_clk_sclk_usbphy0 = {
108 .name = "sclk_usbphy0",
109 .rate = 27000000,
110 };
111
112 static struct clk exynos4_clk_sclk_usbphy1 = {
113 .name = "sclk_usbphy1",
114 };
115
116 static struct clk dummy_apb_pclk = {
117 .name = "apb_pclk",
118 .id = -1,
119 };
120
121 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
122 {
123 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
124 }
125
126 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
127 {
128 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
129 }
130
131 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
132 {
133 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
134 }
135
136 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
137 {
138 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
139 }
140
141 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
142 {
143 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
144 }
145
146 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
147 {
148 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
149 }
150
151 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
152 {
153 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
154 }
155
156 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
157 {
158 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
159 }
160
161 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
162 {
163 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
164 }
165
166 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
167 {
168 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
169 }
170
171 int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
172 {
173 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
174 }
175
176 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
177 {
178 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
179 }
180
181 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
182 {
183 return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
184 }
185
186 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
187 {
188 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
189 }
190
191 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
192 {
193 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
194 }
195
196 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
197 {
198 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
199 }
200
201 int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
202 {
203 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
204 }
205
206 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
207 {
208 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
209 }
210
211 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
212 {
213 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
214 }
215
216 /* Core list of CMU_CPU side */
217
218 static struct clksrc_clk exynos4_clk_mout_apll = {
219 .clk = {
220 .name = "mout_apll",
221 },
222 .sources = &clk_src_apll,
223 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
224 };
225
226 static struct clksrc_clk exynos4_clk_sclk_apll = {
227 .clk = {
228 .name = "sclk_apll",
229 .parent = &exynos4_clk_mout_apll.clk,
230 },
231 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
232 };
233
234 static struct clksrc_clk exynos4_clk_mout_epll = {
235 .clk = {
236 .name = "mout_epll",
237 },
238 .sources = &clk_src_epll,
239 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
240 };
241
242 struct clksrc_clk exynos4_clk_mout_mpll = {
243 .clk = {
244 .name = "mout_mpll",
245 },
246 .sources = &clk_src_mpll,
247
248 /* reg_src will be added in each SoCs' clock */
249 };
250
251 static struct clk *exynos4_clkset_moutcore_list[] = {
252 [0] = &exynos4_clk_mout_apll.clk,
253 [1] = &exynos4_clk_mout_mpll.clk,
254 };
255
256 static struct clksrc_sources exynos4_clkset_moutcore = {
257 .sources = exynos4_clkset_moutcore_list,
258 .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
259 };
260
261 static struct clksrc_clk exynos4_clk_moutcore = {
262 .clk = {
263 .name = "moutcore",
264 },
265 .sources = &exynos4_clkset_moutcore,
266 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
267 };
268
269 static struct clksrc_clk exynos4_clk_coreclk = {
270 .clk = {
271 .name = "core_clk",
272 .parent = &exynos4_clk_moutcore.clk,
273 },
274 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
275 };
276
277 static struct clksrc_clk exynos4_clk_armclk = {
278 .clk = {
279 .name = "armclk",
280 .parent = &exynos4_clk_coreclk.clk,
281 },
282 };
283
284 static struct clksrc_clk exynos4_clk_aclk_corem0 = {
285 .clk = {
286 .name = "aclk_corem0",
287 .parent = &exynos4_clk_coreclk.clk,
288 },
289 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
290 };
291
292 static struct clksrc_clk exynos4_clk_aclk_cores = {
293 .clk = {
294 .name = "aclk_cores",
295 .parent = &exynos4_clk_coreclk.clk,
296 },
297 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
298 };
299
300 static struct clksrc_clk exynos4_clk_aclk_corem1 = {
301 .clk = {
302 .name = "aclk_corem1",
303 .parent = &exynos4_clk_coreclk.clk,
304 },
305 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
306 };
307
308 static struct clksrc_clk exynos4_clk_periphclk = {
309 .clk = {
310 .name = "periphclk",
311 .parent = &exynos4_clk_coreclk.clk,
312 },
313 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
314 };
315
316 /* Core list of CMU_CORE side */
317
318 static struct clk *exynos4_clkset_corebus_list[] = {
319 [0] = &exynos4_clk_mout_mpll.clk,
320 [1] = &exynos4_clk_sclk_apll.clk,
321 };
322
323 struct clksrc_sources exynos4_clkset_mout_corebus = {
324 .sources = exynos4_clkset_corebus_list,
325 .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
326 };
327
328 static struct clksrc_clk exynos4_clk_mout_corebus = {
329 .clk = {
330 .name = "mout_corebus",
331 },
332 .sources = &exynos4_clkset_mout_corebus,
333 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
334 };
335
336 static struct clksrc_clk exynos4_clk_sclk_dmc = {
337 .clk = {
338 .name = "sclk_dmc",
339 .parent = &exynos4_clk_mout_corebus.clk,
340 },
341 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
342 };
343
344 static struct clksrc_clk exynos4_clk_aclk_cored = {
345 .clk = {
346 .name = "aclk_cored",
347 .parent = &exynos4_clk_sclk_dmc.clk,
348 },
349 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
350 };
351
352 static struct clksrc_clk exynos4_clk_aclk_corep = {
353 .clk = {
354 .name = "aclk_corep",
355 .parent = &exynos4_clk_aclk_cored.clk,
356 },
357 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
358 };
359
360 static struct clksrc_clk exynos4_clk_aclk_acp = {
361 .clk = {
362 .name = "aclk_acp",
363 .parent = &exynos4_clk_mout_corebus.clk,
364 },
365 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
366 };
367
368 static struct clksrc_clk exynos4_clk_pclk_acp = {
369 .clk = {
370 .name = "pclk_acp",
371 .parent = &exynos4_clk_aclk_acp.clk,
372 },
373 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
374 };
375
376 /* Core list of CMU_TOP side */
377
378 struct clk *exynos4_clkset_aclk_top_list[] = {
379 [0] = &exynos4_clk_mout_mpll.clk,
380 [1] = &exynos4_clk_sclk_apll.clk,
381 };
382
383 static struct clksrc_sources exynos4_clkset_aclk = {
384 .sources = exynos4_clkset_aclk_top_list,
385 .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
386 };
387
388 static struct clksrc_clk exynos4_clk_aclk_200 = {
389 .clk = {
390 .name = "aclk_200",
391 },
392 .sources = &exynos4_clkset_aclk,
393 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
394 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
395 };
396
397 static struct clksrc_clk exynos4_clk_aclk_100 = {
398 .clk = {
399 .name = "aclk_100",
400 },
401 .sources = &exynos4_clkset_aclk,
402 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
403 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
404 };
405
406 static struct clksrc_clk exynos4_clk_aclk_160 = {
407 .clk = {
408 .name = "aclk_160",
409 },
410 .sources = &exynos4_clkset_aclk,
411 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
412 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
413 };
414
415 struct clksrc_clk exynos4_clk_aclk_133 = {
416 .clk = {
417 .name = "aclk_133",
418 },
419 .sources = &exynos4_clkset_aclk,
420 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
421 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
422 };
423
424 static struct clk *exynos4_clkset_vpllsrc_list[] = {
425 [0] = &clk_fin_vpll,
426 [1] = &exynos4_clk_sclk_hdmi27m,
427 };
428
429 static struct clksrc_sources exynos4_clkset_vpllsrc = {
430 .sources = exynos4_clkset_vpllsrc_list,
431 .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
432 };
433
434 static struct clksrc_clk exynos4_clk_vpllsrc = {
435 .clk = {
436 .name = "vpll_src",
437 .enable = exynos4_clksrc_mask_top_ctrl,
438 .ctrlbit = (1 << 0),
439 },
440 .sources = &exynos4_clkset_vpllsrc,
441 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
442 };
443
444 static struct clk *exynos4_clkset_sclk_vpll_list[] = {
445 [0] = &exynos4_clk_vpllsrc.clk,
446 [1] = &clk_fout_vpll,
447 };
448
449 static struct clksrc_sources exynos4_clkset_sclk_vpll = {
450 .sources = exynos4_clkset_sclk_vpll_list,
451 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
452 };
453
454 static struct clksrc_clk exynos4_clk_sclk_vpll = {
455 .clk = {
456 .name = "sclk_vpll",
457 },
458 .sources = &exynos4_clkset_sclk_vpll,
459 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
460 };
461
462 static struct clk exynos4_init_clocks_off[] = {
463 {
464 .name = "timers",
465 .parent = &exynos4_clk_aclk_100.clk,
466 .enable = exynos4_clk_ip_peril_ctrl,
467 .ctrlbit = (1<<24),
468 }, {
469 .name = "csis",
470 .devname = "s5p-mipi-csis.0",
471 .enable = exynos4_clk_ip_cam_ctrl,
472 .ctrlbit = (1 << 4),
473 }, {
474 .name = "csis",
475 .devname = "s5p-mipi-csis.1",
476 .enable = exynos4_clk_ip_cam_ctrl,
477 .ctrlbit = (1 << 5),
478 }, {
479 .name = "jpeg",
480 .id = 0,
481 .enable = exynos4_clk_ip_cam_ctrl,
482 .ctrlbit = (1 << 6),
483 }, {
484 .name = "fimc",
485 .devname = "exynos4-fimc.0",
486 .enable = exynos4_clk_ip_cam_ctrl,
487 .ctrlbit = (1 << 0),
488 }, {
489 .name = "fimc",
490 .devname = "exynos4-fimc.1",
491 .enable = exynos4_clk_ip_cam_ctrl,
492 .ctrlbit = (1 << 1),
493 }, {
494 .name = "fimc",
495 .devname = "exynos4-fimc.2",
496 .enable = exynos4_clk_ip_cam_ctrl,
497 .ctrlbit = (1 << 2),
498 }, {
499 .name = "fimc",
500 .devname = "exynos4-fimc.3",
501 .enable = exynos4_clk_ip_cam_ctrl,
502 .ctrlbit = (1 << 3),
503 }, {
504 .name = "hsmmc",
505 .devname = "exynos4-sdhci.0",
506 .parent = &exynos4_clk_aclk_133.clk,
507 .enable = exynos4_clk_ip_fsys_ctrl,
508 .ctrlbit = (1 << 5),
509 }, {
510 .name = "hsmmc",
511 .devname = "exynos4-sdhci.1",
512 .parent = &exynos4_clk_aclk_133.clk,
513 .enable = exynos4_clk_ip_fsys_ctrl,
514 .ctrlbit = (1 << 6),
515 }, {
516 .name = "hsmmc",
517 .devname = "exynos4-sdhci.2",
518 .parent = &exynos4_clk_aclk_133.clk,
519 .enable = exynos4_clk_ip_fsys_ctrl,
520 .ctrlbit = (1 << 7),
521 }, {
522 .name = "hsmmc",
523 .devname = "exynos4-sdhci.3",
524 .parent = &exynos4_clk_aclk_133.clk,
525 .enable = exynos4_clk_ip_fsys_ctrl,
526 .ctrlbit = (1 << 8),
527 }, {
528 .name = "dwmmc",
529 .parent = &exynos4_clk_aclk_133.clk,
530 .enable = exynos4_clk_ip_fsys_ctrl,
531 .ctrlbit = (1 << 9),
532 }, {
533 .name = "dac",
534 .devname = "s5p-sdo",
535 .enable = exynos4_clk_ip_tv_ctrl,
536 .ctrlbit = (1 << 2),
537 }, {
538 .name = "mixer",
539 .devname = "s5p-mixer",
540 .enable = exynos4_clk_ip_tv_ctrl,
541 .ctrlbit = (1 << 1),
542 }, {
543 .name = "vp",
544 .devname = "s5p-mixer",
545 .enable = exynos4_clk_ip_tv_ctrl,
546 .ctrlbit = (1 << 0),
547 }, {
548 .name = "hdmi",
549 .devname = "exynos4-hdmi",
550 .enable = exynos4_clk_ip_tv_ctrl,
551 .ctrlbit = (1 << 3),
552 }, {
553 .name = "hdmiphy",
554 .devname = "exynos4-hdmi",
555 .enable = exynos4_clk_hdmiphy_ctrl,
556 .ctrlbit = (1 << 0),
557 }, {
558 .name = "dacphy",
559 .devname = "s5p-sdo",
560 .enable = exynos4_clk_dac_ctrl,
561 .ctrlbit = (1 << 0),
562 }, {
563 .name = "adc",
564 .enable = exynos4_clk_ip_peril_ctrl,
565 .ctrlbit = (1 << 15),
566 }, {
567 .name = "keypad",
568 .enable = exynos4_clk_ip_perir_ctrl,
569 .ctrlbit = (1 << 16),
570 }, {
571 .name = "rtc",
572 .enable = exynos4_clk_ip_perir_ctrl,
573 .ctrlbit = (1 << 15),
574 }, {
575 .name = "watchdog",
576 .parent = &exynos4_clk_aclk_100.clk,
577 .enable = exynos4_clk_ip_perir_ctrl,
578 .ctrlbit = (1 << 14),
579 }, {
580 .name = "usbhost",
581 .enable = exynos4_clk_ip_fsys_ctrl ,
582 .ctrlbit = (1 << 12),
583 }, {
584 .name = "otg",
585 .enable = exynos4_clk_ip_fsys_ctrl,
586 .ctrlbit = (1 << 13),
587 }, {
588 .name = "spi",
589 .devname = "exynos4210-spi.0",
590 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 16),
592 }, {
593 .name = "spi",
594 .devname = "exynos4210-spi.1",
595 .enable = exynos4_clk_ip_peril_ctrl,
596 .ctrlbit = (1 << 17),
597 }, {
598 .name = "spi",
599 .devname = "exynos4210-spi.2",
600 .enable = exynos4_clk_ip_peril_ctrl,
601 .ctrlbit = (1 << 18),
602 }, {
603 .name = "iis",
604 .devname = "samsung-i2s.0",
605 .enable = exynos4_clk_ip_peril_ctrl,
606 .ctrlbit = (1 << 19),
607 }, {
608 .name = "iis",
609 .devname = "samsung-i2s.1",
610 .enable = exynos4_clk_ip_peril_ctrl,
611 .ctrlbit = (1 << 20),
612 }, {
613 .name = "iis",
614 .devname = "samsung-i2s.2",
615 .enable = exynos4_clk_ip_peril_ctrl,
616 .ctrlbit = (1 << 21),
617 }, {
618 .name = "ac97",
619 .devname = "samsung-ac97",
620 .enable = exynos4_clk_ip_peril_ctrl,
621 .ctrlbit = (1 << 27),
622 }, {
623 .name = "mfc",
624 .devname = "s5p-mfc",
625 .enable = exynos4_clk_ip_mfc_ctrl,
626 .ctrlbit = (1 << 0),
627 }, {
628 .name = "i2c",
629 .devname = "s3c2440-i2c.0",
630 .parent = &exynos4_clk_aclk_100.clk,
631 .enable = exynos4_clk_ip_peril_ctrl,
632 .ctrlbit = (1 << 6),
633 }, {
634 .name = "i2c",
635 .devname = "s3c2440-i2c.1",
636 .parent = &exynos4_clk_aclk_100.clk,
637 .enable = exynos4_clk_ip_peril_ctrl,
638 .ctrlbit = (1 << 7),
639 }, {
640 .name = "i2c",
641 .devname = "s3c2440-i2c.2",
642 .parent = &exynos4_clk_aclk_100.clk,
643 .enable = exynos4_clk_ip_peril_ctrl,
644 .ctrlbit = (1 << 8),
645 }, {
646 .name = "i2c",
647 .devname = "s3c2440-i2c.3",
648 .parent = &exynos4_clk_aclk_100.clk,
649 .enable = exynos4_clk_ip_peril_ctrl,
650 .ctrlbit = (1 << 9),
651 }, {
652 .name = "i2c",
653 .devname = "s3c2440-i2c.4",
654 .parent = &exynos4_clk_aclk_100.clk,
655 .enable = exynos4_clk_ip_peril_ctrl,
656 .ctrlbit = (1 << 10),
657 }, {
658 .name = "i2c",
659 .devname = "s3c2440-i2c.5",
660 .parent = &exynos4_clk_aclk_100.clk,
661 .enable = exynos4_clk_ip_peril_ctrl,
662 .ctrlbit = (1 << 11),
663 }, {
664 .name = "i2c",
665 .devname = "s3c2440-i2c.6",
666 .parent = &exynos4_clk_aclk_100.clk,
667 .enable = exynos4_clk_ip_peril_ctrl,
668 .ctrlbit = (1 << 12),
669 }, {
670 .name = "i2c",
671 .devname = "s3c2440-i2c.7",
672 .parent = &exynos4_clk_aclk_100.clk,
673 .enable = exynos4_clk_ip_peril_ctrl,
674 .ctrlbit = (1 << 13),
675 }, {
676 .name = "i2c",
677 .devname = "s3c2440-hdmiphy-i2c",
678 .parent = &exynos4_clk_aclk_100.clk,
679 .enable = exynos4_clk_ip_peril_ctrl,
680 .ctrlbit = (1 << 14),
681 }, {
682 .name = SYSMMU_CLOCK_NAME,
683 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
684 .enable = exynos4_clk_ip_mfc_ctrl,
685 .ctrlbit = (1 << 1),
686 }, {
687 .name = SYSMMU_CLOCK_NAME,
688 .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
689 .enable = exynos4_clk_ip_mfc_ctrl,
690 .ctrlbit = (1 << 2),
691 }, {
692 .name = SYSMMU_CLOCK_NAME,
693 .devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
694 .enable = exynos4_clk_ip_tv_ctrl,
695 .ctrlbit = (1 << 4),
696 }, {
697 .name = SYSMMU_CLOCK_NAME,
698 .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
699 .enable = exynos4_clk_ip_cam_ctrl,
700 .ctrlbit = (1 << 11),
701 }, {
702 .name = SYSMMU_CLOCK_NAME,
703 .devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
704 .enable = exynos4_clk_ip_image_ctrl,
705 .ctrlbit = (1 << 4),
706 }, {
707 .name = SYSMMU_CLOCK_NAME,
708 .devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
709 .enable = exynos4_clk_ip_cam_ctrl,
710 .ctrlbit = (1 << 7),
711 }, {
712 .name = SYSMMU_CLOCK_NAME,
713 .devname = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
714 .enable = exynos4_clk_ip_cam_ctrl,
715 .ctrlbit = (1 << 8),
716 }, {
717 .name = SYSMMU_CLOCK_NAME,
718 .devname = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
719 .enable = exynos4_clk_ip_cam_ctrl,
720 .ctrlbit = (1 << 9),
721 }, {
722 .name = SYSMMU_CLOCK_NAME,
723 .devname = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
724 .enable = exynos4_clk_ip_cam_ctrl,
725 .ctrlbit = (1 << 10),
726 }, {
727 .name = SYSMMU_CLOCK_NAME,
728 .devname = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
729 .enable = exynos4_clk_ip_lcd0_ctrl,
730 .ctrlbit = (1 << 4),
731 }
732 };
733
734 static struct clk exynos4_init_clocks_on[] = {
735 {
736 .name = "uart",
737 .devname = "s5pv210-uart.0",
738 .enable = exynos4_clk_ip_peril_ctrl,
739 .ctrlbit = (1 << 0),
740 }, {
741 .name = "uart",
742 .devname = "s5pv210-uart.1",
743 .enable = exynos4_clk_ip_peril_ctrl,
744 .ctrlbit = (1 << 1),
745 }, {
746 .name = "uart",
747 .devname = "s5pv210-uart.2",
748 .enable = exynos4_clk_ip_peril_ctrl,
749 .ctrlbit = (1 << 2),
750 }, {
751 .name = "uart",
752 .devname = "s5pv210-uart.3",
753 .enable = exynos4_clk_ip_peril_ctrl,
754 .ctrlbit = (1 << 3),
755 }, {
756 .name = "uart",
757 .devname = "s5pv210-uart.4",
758 .enable = exynos4_clk_ip_peril_ctrl,
759 .ctrlbit = (1 << 4),
760 }, {
761 .name = "uart",
762 .devname = "s5pv210-uart.5",
763 .enable = exynos4_clk_ip_peril_ctrl,
764 .ctrlbit = (1 << 5),
765 }
766 };
767
768 static struct clk exynos4_clk_pdma0 = {
769 .name = "dma",
770 .devname = "dma-pl330.0",
771 .enable = exynos4_clk_ip_fsys_ctrl,
772 .ctrlbit = (1 << 0),
773 };
774
775 static struct clk exynos4_clk_pdma1 = {
776 .name = "dma",
777 .devname = "dma-pl330.1",
778 .enable = exynos4_clk_ip_fsys_ctrl,
779 .ctrlbit = (1 << 1),
780 };
781
782 static struct clk exynos4_clk_mdma1 = {
783 .name = "dma",
784 .devname = "dma-pl330.2",
785 .enable = exynos4_clk_ip_image_ctrl,
786 .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
787 };
788
789 static struct clk exynos4_clk_fimd0 = {
790 .name = "fimd",
791 .devname = "exynos4-fb.0",
792 .enable = exynos4_clk_ip_lcd0_ctrl,
793 .ctrlbit = (1 << 0),
794 };
795
796 struct clk *exynos4_clkset_group_list[] = {
797 [0] = &clk_ext_xtal_mux,
798 [1] = &clk_xusbxti,
799 [2] = &exynos4_clk_sclk_hdmi27m,
800 [3] = &exynos4_clk_sclk_usbphy0,
801 [4] = &exynos4_clk_sclk_usbphy1,
802 [5] = &exynos4_clk_sclk_hdmiphy,
803 [6] = &exynos4_clk_mout_mpll.clk,
804 [7] = &exynos4_clk_mout_epll.clk,
805 [8] = &exynos4_clk_sclk_vpll.clk,
806 };
807
808 struct clksrc_sources exynos4_clkset_group = {
809 .sources = exynos4_clkset_group_list,
810 .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
811 };
812
813 static struct clk *exynos4_clkset_mout_g2d0_list[] = {
814 [0] = &exynos4_clk_mout_mpll.clk,
815 [1] = &exynos4_clk_sclk_apll.clk,
816 };
817
818 struct clksrc_sources exynos4_clkset_mout_g2d0 = {
819 .sources = exynos4_clkset_mout_g2d0_list,
820 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
821 };
822
823 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
824 [0] = &exynos4_clk_mout_epll.clk,
825 [1] = &exynos4_clk_sclk_vpll.clk,
826 };
827
828 struct clksrc_sources exynos4_clkset_mout_g2d1 = {
829 .sources = exynos4_clkset_mout_g2d1_list,
830 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
831 };
832
833 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
834 [0] = &exynos4_clk_mout_mpll.clk,
835 [1] = &exynos4_clk_sclk_apll.clk,
836 };
837
838 static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
839 .sources = exynos4_clkset_mout_mfc0_list,
840 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
841 };
842
843 static struct clksrc_clk exynos4_clk_mout_mfc0 = {
844 .clk = {
845 .name = "mout_mfc0",
846 },
847 .sources = &exynos4_clkset_mout_mfc0,
848 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
849 };
850
851 static struct clk *exynos4_clkset_mout_mfc1_list[] = {
852 [0] = &exynos4_clk_mout_epll.clk,
853 [1] = &exynos4_clk_sclk_vpll.clk,
854 };
855
856 static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
857 .sources = exynos4_clkset_mout_mfc1_list,
858 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
859 };
860
861 static struct clksrc_clk exynos4_clk_mout_mfc1 = {
862 .clk = {
863 .name = "mout_mfc1",
864 },
865 .sources = &exynos4_clkset_mout_mfc1,
866 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
867 };
868
869 static struct clk *exynos4_clkset_mout_mfc_list[] = {
870 [0] = &exynos4_clk_mout_mfc0.clk,
871 [1] = &exynos4_clk_mout_mfc1.clk,
872 };
873
874 static struct clksrc_sources exynos4_clkset_mout_mfc = {
875 .sources = exynos4_clkset_mout_mfc_list,
876 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
877 };
878
879 static struct clk *exynos4_clkset_sclk_dac_list[] = {
880 [0] = &exynos4_clk_sclk_vpll.clk,
881 [1] = &exynos4_clk_sclk_hdmiphy,
882 };
883
884 static struct clksrc_sources exynos4_clkset_sclk_dac = {
885 .sources = exynos4_clkset_sclk_dac_list,
886 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
887 };
888
889 static struct clksrc_clk exynos4_clk_sclk_dac = {
890 .clk = {
891 .name = "sclk_dac",
892 .enable = exynos4_clksrc_mask_tv_ctrl,
893 .ctrlbit = (1 << 8),
894 },
895 .sources = &exynos4_clkset_sclk_dac,
896 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
897 };
898
899 static struct clksrc_clk exynos4_clk_sclk_pixel = {
900 .clk = {
901 .name = "sclk_pixel",
902 .parent = &exynos4_clk_sclk_vpll.clk,
903 },
904 .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
905 };
906
907 static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
908 [0] = &exynos4_clk_sclk_pixel.clk,
909 [1] = &exynos4_clk_sclk_hdmiphy,
910 };
911
912 static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
913 .sources = exynos4_clkset_sclk_hdmi_list,
914 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
915 };
916
917 static struct clksrc_clk exynos4_clk_sclk_hdmi = {
918 .clk = {
919 .name = "sclk_hdmi",
920 .enable = exynos4_clksrc_mask_tv_ctrl,
921 .ctrlbit = (1 << 0),
922 },
923 .sources = &exynos4_clkset_sclk_hdmi,
924 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
925 };
926
927 static struct clk *exynos4_clkset_sclk_mixer_list[] = {
928 [0] = &exynos4_clk_sclk_dac.clk,
929 [1] = &exynos4_clk_sclk_hdmi.clk,
930 };
931
932 static struct clksrc_sources exynos4_clkset_sclk_mixer = {
933 .sources = exynos4_clkset_sclk_mixer_list,
934 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
935 };
936
937 static struct clksrc_clk exynos4_clk_sclk_mixer = {
938 .clk = {
939 .name = "sclk_mixer",
940 .enable = exynos4_clksrc_mask_tv_ctrl,
941 .ctrlbit = (1 << 4),
942 },
943 .sources = &exynos4_clkset_sclk_mixer,
944 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
945 };
946
947 static struct clksrc_clk *exynos4_sclk_tv[] = {
948 &exynos4_clk_sclk_dac,
949 &exynos4_clk_sclk_pixel,
950 &exynos4_clk_sclk_hdmi,
951 &exynos4_clk_sclk_mixer,
952 };
953
954 static struct clksrc_clk exynos4_clk_dout_mmc0 = {
955 .clk = {
956 .name = "dout_mmc0",
957 },
958 .sources = &exynos4_clkset_group,
959 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
960 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
961 };
962
963 static struct clksrc_clk exynos4_clk_dout_mmc1 = {
964 .clk = {
965 .name = "dout_mmc1",
966 },
967 .sources = &exynos4_clkset_group,
968 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
969 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
970 };
971
972 static struct clksrc_clk exynos4_clk_dout_mmc2 = {
973 .clk = {
974 .name = "dout_mmc2",
975 },
976 .sources = &exynos4_clkset_group,
977 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
978 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
979 };
980
981 static struct clksrc_clk exynos4_clk_dout_mmc3 = {
982 .clk = {
983 .name = "dout_mmc3",
984 },
985 .sources = &exynos4_clkset_group,
986 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
987 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
988 };
989
990 static struct clksrc_clk exynos4_clk_dout_mmc4 = {
991 .clk = {
992 .name = "dout_mmc4",
993 },
994 .sources = &exynos4_clkset_group,
995 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
996 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
997 };
998
999 static struct clksrc_clk exynos4_clksrcs[] = {
1000 {
1001 .clk = {
1002 .name = "sclk_pwm",
1003 .enable = exynos4_clksrc_mask_peril0_ctrl,
1004 .ctrlbit = (1 << 24),
1005 },
1006 .sources = &exynos4_clkset_group,
1007 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1008 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1009 }, {
1010 .clk = {
1011 .name = "sclk_csis",
1012 .devname = "s5p-mipi-csis.0",
1013 .enable = exynos4_clksrc_mask_cam_ctrl,
1014 .ctrlbit = (1 << 24),
1015 },
1016 .sources = &exynos4_clkset_group,
1017 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1018 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1019 }, {
1020 .clk = {
1021 .name = "sclk_csis",
1022 .devname = "s5p-mipi-csis.1",
1023 .enable = exynos4_clksrc_mask_cam_ctrl,
1024 .ctrlbit = (1 << 28),
1025 },
1026 .sources = &exynos4_clkset_group,
1027 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1028 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1029 }, {
1030 .clk = {
1031 .name = "sclk_cam0",
1032 .enable = exynos4_clksrc_mask_cam_ctrl,
1033 .ctrlbit = (1 << 16),
1034 },
1035 .sources = &exynos4_clkset_group,
1036 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1037 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1038 }, {
1039 .clk = {
1040 .name = "sclk_cam1",
1041 .enable = exynos4_clksrc_mask_cam_ctrl,
1042 .ctrlbit = (1 << 20),
1043 },
1044 .sources = &exynos4_clkset_group,
1045 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1046 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1047 }, {
1048 .clk = {
1049 .name = "sclk_fimc",
1050 .devname = "exynos4-fimc.0",
1051 .enable = exynos4_clksrc_mask_cam_ctrl,
1052 .ctrlbit = (1 << 0),
1053 },
1054 .sources = &exynos4_clkset_group,
1055 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1056 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1057 }, {
1058 .clk = {
1059 .name = "sclk_fimc",
1060 .devname = "exynos4-fimc.1",
1061 .enable = exynos4_clksrc_mask_cam_ctrl,
1062 .ctrlbit = (1 << 4),
1063 },
1064 .sources = &exynos4_clkset_group,
1065 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1066 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1067 }, {
1068 .clk = {
1069 .name = "sclk_fimc",
1070 .devname = "exynos4-fimc.2",
1071 .enable = exynos4_clksrc_mask_cam_ctrl,
1072 .ctrlbit = (1 << 8),
1073 },
1074 .sources = &exynos4_clkset_group,
1075 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1076 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1077 }, {
1078 .clk = {
1079 .name = "sclk_fimc",
1080 .devname = "exynos4-fimc.3",
1081 .enable = exynos4_clksrc_mask_cam_ctrl,
1082 .ctrlbit = (1 << 12),
1083 },
1084 .sources = &exynos4_clkset_group,
1085 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1086 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1087 }, {
1088 .clk = {
1089 .name = "sclk_fimd",
1090 .devname = "exynos4-fb.0",
1091 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1092 .ctrlbit = (1 << 0),
1093 },
1094 .sources = &exynos4_clkset_group,
1095 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1096 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1097 }, {
1098 .clk = {
1099 .name = "sclk_mfc",
1100 .devname = "s5p-mfc",
1101 },
1102 .sources = &exynos4_clkset_mout_mfc,
1103 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1104 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1105 }, {
1106 .clk = {
1107 .name = "sclk_dwmmc",
1108 .parent = &exynos4_clk_dout_mmc4.clk,
1109 .enable = exynos4_clksrc_mask_fsys_ctrl,
1110 .ctrlbit = (1 << 16),
1111 },
1112 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1113 }
1114 };
1115
1116 static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1117 .clk = {
1118 .name = "uclk1",
1119 .devname = "exynos4210-uart.0",
1120 .enable = exynos4_clksrc_mask_peril0_ctrl,
1121 .ctrlbit = (1 << 0),
1122 },
1123 .sources = &exynos4_clkset_group,
1124 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1125 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1126 };
1127
1128 static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1129 .clk = {
1130 .name = "uclk1",
1131 .devname = "exynos4210-uart.1",
1132 .enable = exynos4_clksrc_mask_peril0_ctrl,
1133 .ctrlbit = (1 << 4),
1134 },
1135 .sources = &exynos4_clkset_group,
1136 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1137 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1138 };
1139
1140 static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1141 .clk = {
1142 .name = "uclk1",
1143 .devname = "exynos4210-uart.2",
1144 .enable = exynos4_clksrc_mask_peril0_ctrl,
1145 .ctrlbit = (1 << 8),
1146 },
1147 .sources = &exynos4_clkset_group,
1148 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1149 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1150 };
1151
1152 static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1153 .clk = {
1154 .name = "uclk1",
1155 .devname = "exynos4210-uart.3",
1156 .enable = exynos4_clksrc_mask_peril0_ctrl,
1157 .ctrlbit = (1 << 12),
1158 },
1159 .sources = &exynos4_clkset_group,
1160 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1161 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1162 };
1163
1164 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1165 .clk = {
1166 .name = "sclk_mmc",
1167 .devname = "exynos4-sdhci.0",
1168 .parent = &exynos4_clk_dout_mmc0.clk,
1169 .enable = exynos4_clksrc_mask_fsys_ctrl,
1170 .ctrlbit = (1 << 0),
1171 },
1172 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1173 };
1174
1175 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1176 .clk = {
1177 .name = "sclk_mmc",
1178 .devname = "exynos4-sdhci.1",
1179 .parent = &exynos4_clk_dout_mmc1.clk,
1180 .enable = exynos4_clksrc_mask_fsys_ctrl,
1181 .ctrlbit = (1 << 4),
1182 },
1183 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1184 };
1185
1186 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1187 .clk = {
1188 .name = "sclk_mmc",
1189 .devname = "exynos4-sdhci.2",
1190 .parent = &exynos4_clk_dout_mmc2.clk,
1191 .enable = exynos4_clksrc_mask_fsys_ctrl,
1192 .ctrlbit = (1 << 8),
1193 },
1194 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1195 };
1196
1197 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1198 .clk = {
1199 .name = "sclk_mmc",
1200 .devname = "exynos4-sdhci.3",
1201 .parent = &exynos4_clk_dout_mmc3.clk,
1202 .enable = exynos4_clksrc_mask_fsys_ctrl,
1203 .ctrlbit = (1 << 12),
1204 },
1205 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1206 };
1207
1208 static struct clksrc_clk exynos4_clk_mdout_spi0 = {
1209 .clk = {
1210 .name = "mdout_spi",
1211 .devname = "exynos4210-spi.0",
1212 },
1213 .sources = &exynos4_clkset_group,
1214 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1215 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1216 };
1217
1218 static struct clksrc_clk exynos4_clk_mdout_spi1 = {
1219 .clk = {
1220 .name = "mdout_spi",
1221 .devname = "exynos4210-spi.1",
1222 },
1223 .sources = &exynos4_clkset_group,
1224 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1225 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1226 };
1227
1228 static struct clksrc_clk exynos4_clk_mdout_spi2 = {
1229 .clk = {
1230 .name = "mdout_spi",
1231 .devname = "exynos4210-spi.2",
1232 },
1233 .sources = &exynos4_clkset_group,
1234 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1235 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1236 };
1237
1238 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1239 .clk = {
1240 .name = "sclk_spi",
1241 .devname = "exynos4210-spi.0",
1242 .parent = &exynos4_clk_mdout_spi0.clk,
1243 .enable = exynos4_clksrc_mask_peril1_ctrl,
1244 .ctrlbit = (1 << 16),
1245 },
1246 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
1247 };
1248
1249 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1250 .clk = {
1251 .name = "sclk_spi",
1252 .devname = "exynos4210-spi.1",
1253 .parent = &exynos4_clk_mdout_spi1.clk,
1254 .enable = exynos4_clksrc_mask_peril1_ctrl,
1255 .ctrlbit = (1 << 20),
1256 },
1257 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
1258 };
1259
1260 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1261 .clk = {
1262 .name = "sclk_spi",
1263 .devname = "exynos4210-spi.2",
1264 .parent = &exynos4_clk_mdout_spi2.clk,
1265 .enable = exynos4_clksrc_mask_peril1_ctrl,
1266 .ctrlbit = (1 << 24),
1267 },
1268 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
1269 };
1270
1271 /* Clock initialization code */
1272 static struct clksrc_clk *exynos4_sysclks[] = {
1273 &exynos4_clk_mout_apll,
1274 &exynos4_clk_sclk_apll,
1275 &exynos4_clk_mout_epll,
1276 &exynos4_clk_mout_mpll,
1277 &exynos4_clk_moutcore,
1278 &exynos4_clk_coreclk,
1279 &exynos4_clk_armclk,
1280 &exynos4_clk_aclk_corem0,
1281 &exynos4_clk_aclk_cores,
1282 &exynos4_clk_aclk_corem1,
1283 &exynos4_clk_periphclk,
1284 &exynos4_clk_mout_corebus,
1285 &exynos4_clk_sclk_dmc,
1286 &exynos4_clk_aclk_cored,
1287 &exynos4_clk_aclk_corep,
1288 &exynos4_clk_aclk_acp,
1289 &exynos4_clk_pclk_acp,
1290 &exynos4_clk_vpllsrc,
1291 &exynos4_clk_sclk_vpll,
1292 &exynos4_clk_aclk_200,
1293 &exynos4_clk_aclk_100,
1294 &exynos4_clk_aclk_160,
1295 &exynos4_clk_aclk_133,
1296 &exynos4_clk_dout_mmc0,
1297 &exynos4_clk_dout_mmc1,
1298 &exynos4_clk_dout_mmc2,
1299 &exynos4_clk_dout_mmc3,
1300 &exynos4_clk_dout_mmc4,
1301 &exynos4_clk_mout_mfc0,
1302 &exynos4_clk_mout_mfc1,
1303 };
1304
1305 static struct clk *exynos4_clk_cdev[] = {
1306 &exynos4_clk_pdma0,
1307 &exynos4_clk_pdma1,
1308 &exynos4_clk_mdma1,
1309 &exynos4_clk_fimd0,
1310 };
1311
1312 static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1313 &exynos4_clk_sclk_uart0,
1314 &exynos4_clk_sclk_uart1,
1315 &exynos4_clk_sclk_uart2,
1316 &exynos4_clk_sclk_uart3,
1317 &exynos4_clk_sclk_mmc0,
1318 &exynos4_clk_sclk_mmc1,
1319 &exynos4_clk_sclk_mmc2,
1320 &exynos4_clk_sclk_mmc3,
1321 &exynos4_clk_sclk_spi0,
1322 &exynos4_clk_sclk_spi1,
1323 &exynos4_clk_sclk_spi2,
1324 &exynos4_clk_mdout_spi0,
1325 &exynos4_clk_mdout_spi1,
1326 &exynos4_clk_mdout_spi2,
1327 };
1328
1329 static struct clk_lookup exynos4_clk_lookup[] = {
1330 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1331 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1332 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1333 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1334 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1335 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1336 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1337 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1338 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1339 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1340 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1341 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1342 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1343 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1344 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1345 };
1346
1347 static int xtal_rate;
1348
1349 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1350 {
1351 if (soc_is_exynos4210())
1352 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1353 pll_4508);
1354 else if (soc_is_exynos4212() || soc_is_exynos4412())
1355 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1356 else
1357 return 0;
1358 }
1359
1360 static struct clk_ops exynos4_fout_apll_ops = {
1361 .get_rate = exynos4_fout_apll_get_rate,
1362 };
1363
1364 static u32 exynos4_vpll_div[][8] = {
1365 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1366 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1367 };
1368
1369 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1370 {
1371 return clk->rate;
1372 }
1373
1374 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1375 {
1376 unsigned int vpll_con0, vpll_con1 = 0;
1377 unsigned int i;
1378
1379 /* Return if nothing changed */
1380 if (clk->rate == rate)
1381 return 0;
1382
1383 vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1384 vpll_con0 &= ~(0x1 << 27 | \
1385 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1386 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1387 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1388
1389 vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1390 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1391 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1392 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1393
1394 for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1395 if (exynos4_vpll_div[i][0] == rate) {
1396 vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1397 vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1398 vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1399 vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1400 vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1401 vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1402 vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1403 break;
1404 }
1405 }
1406
1407 if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1408 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1409 __func__);
1410 return -EINVAL;
1411 }
1412
1413 __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1414 __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1415
1416 /* Wait for VPLL lock */
1417 while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1418 continue;
1419
1420 clk->rate = rate;
1421 return 0;
1422 }
1423
1424 static struct clk_ops exynos4_vpll_ops = {
1425 .get_rate = exynos4_vpll_get_rate,
1426 .set_rate = exynos4_vpll_set_rate,
1427 };
1428
1429 void __init_or_cpufreq exynos4_setup_clocks(void)
1430 {
1431 struct clk *xtal_clk;
1432 unsigned long apll = 0;
1433 unsigned long mpll = 0;
1434 unsigned long epll = 0;
1435 unsigned long vpll = 0;
1436 unsigned long vpllsrc;
1437 unsigned long xtal;
1438 unsigned long armclk;
1439 unsigned long sclk_dmc;
1440 unsigned long aclk_200;
1441 unsigned long aclk_100;
1442 unsigned long aclk_160;
1443 unsigned long aclk_133;
1444 unsigned int ptr;
1445
1446 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1447
1448 xtal_clk = clk_get(NULL, "xtal");
1449 BUG_ON(IS_ERR(xtal_clk));
1450
1451 xtal = clk_get_rate(xtal_clk);
1452
1453 xtal_rate = xtal;
1454
1455 clk_put(xtal_clk);
1456
1457 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1458
1459 if (soc_is_exynos4210()) {
1460 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1461 pll_4508);
1462 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1463 pll_4508);
1464 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1465 __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1466
1467 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1468 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1469 __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1470 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1471 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1472 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1473 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1474 __raw_readl(EXYNOS4_EPLL_CON1));
1475
1476 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1477 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1478 __raw_readl(EXYNOS4_VPLL_CON1));
1479 } else {
1480 /* nothing */
1481 }
1482
1483 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1484 clk_fout_mpll.rate = mpll;
1485 clk_fout_epll.rate = epll;
1486 clk_fout_vpll.ops = &exynos4_vpll_ops;
1487 clk_fout_vpll.rate = vpll;
1488
1489 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1490 apll, mpll, epll, vpll);
1491
1492 armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1493 sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1494
1495 aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1496 aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1497 aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1498 aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1499
1500 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1501 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1502 armclk, sclk_dmc, aclk_200,
1503 aclk_100, aclk_160, aclk_133);
1504
1505 clk_f.rate = armclk;
1506 clk_h.rate = sclk_dmc;
1507 clk_p.rate = aclk_100;
1508
1509 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1510 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1511 }
1512
1513 static struct clk *exynos4_clks[] __initdata = {
1514 &exynos4_clk_sclk_hdmi27m,
1515 &exynos4_clk_sclk_hdmiphy,
1516 &exynos4_clk_sclk_usbphy0,
1517 &exynos4_clk_sclk_usbphy1,
1518 };
1519
1520 #ifdef CONFIG_PM_SLEEP
1521 static int exynos4_clock_suspend(void)
1522 {
1523 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1524 return 0;
1525 }
1526
1527 static void exynos4_clock_resume(void)
1528 {
1529 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1530 }
1531
1532 #else
1533 #define exynos4_clock_suspend NULL
1534 #define exynos4_clock_resume NULL
1535 #endif
1536
1537 static struct syscore_ops exynos4_clock_syscore_ops = {
1538 .suspend = exynos4_clock_suspend,
1539 .resume = exynos4_clock_resume,
1540 };
1541
1542 void __init exynos4_register_clocks(void)
1543 {
1544 int ptr;
1545
1546 s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1547
1548 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1549 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1550
1551 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1552 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1553
1554 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1555 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1556
1557 s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1558 s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1559
1560 s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1561 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1562 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1563
1564 s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1565 s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1566 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1567
1568 register_syscore_ops(&exynos4_clock_syscore_ops);
1569 s3c24xx_register_clock(&dummy_apb_pclk);
1570
1571 s3c_pwmclk_init();
1572 }
Linux with added FPC-III support