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block: move down direct IO plugging
[linux/fpc-iii.git] / arch / arm / mach-exynos / clock-exynos5.c
blob774533c670667c1a7a8e16986e7ababa841ee48e
1 /*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Clock support for EXYNOS5 SoCs
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/syscore_ops.h>
16
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
19 #include <plat/cpu.h>
20 #include <plat/pll.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
23 #include <plat/pm.h>
24
25 #include <mach/map.h>
26 #include <mach/regs-clock.h>
27 #include <mach/sysmmu.h>
28
29 #include "common.h"
30
31 #ifdef CONFIG_PM_SLEEP
32 static struct sleep_save exynos5_clock_save[] = {
33 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
34 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
35 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
36 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
37 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
38 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
39 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
40 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
41 SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
42 SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
43 SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
44 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
45 SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
46 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
47 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
48 SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
49 SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
50 SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
51 SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
52 SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
53 SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
54 SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
55 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
56 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
57 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
58 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
59 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
60 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
61 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
62 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
63 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
64 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
65 SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
66 SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
67 SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
68 SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
69 SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
70 SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
71 SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
72 SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
73 SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
74 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
75 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
76 SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
77 SAVE_ITEM(EXYNOS5_EPLL_CON0),
78 SAVE_ITEM(EXYNOS5_EPLL_CON1),
79 SAVE_ITEM(EXYNOS5_EPLL_CON2),
80 SAVE_ITEM(EXYNOS5_VPLL_CON0),
81 SAVE_ITEM(EXYNOS5_VPLL_CON1),
82 SAVE_ITEM(EXYNOS5_VPLL_CON2),
83 };
84 #endif
85
86 static struct clk exynos5_clk_sclk_dptxphy = {
87 .name = "sclk_dptx",
88 };
89
90 static struct clk exynos5_clk_sclk_hdmi24m = {
91 .name = "sclk_hdmi24m",
92 .rate = 24000000,
93 };
94
95 static struct clk exynos5_clk_sclk_hdmi27m = {
96 .name = "sclk_hdmi27m",
97 .rate = 27000000,
98 };
99
100 static struct clk exynos5_clk_sclk_hdmiphy = {
101 .name = "sclk_hdmiphy",
102 };
103
104 static struct clk exynos5_clk_sclk_usbphy = {
105 .name = "sclk_usbphy",
106 .rate = 48000000,
107 };
108
109 static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
110 {
111 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
112 }
113
114 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
115 {
116 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
117 }
118
119 static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
120 {
121 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
122 }
123
124 static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
125 {
126 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
127 }
128
129 static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
130 {
131 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
132 }
133
134 static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
135 {
136 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
137 }
138
139 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
140 {
141 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
142 }
143
144 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
145 {
146 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
147 }
148
149 static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
150 {
151 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
152 }
153
154 static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
155 {
156 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
157 }
158
159 static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
160 {
161 return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
162 }
163
164 static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
165 {
166 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
167 }
168
169 static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
170 {
171 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
172 }
173
174 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
175 {
176 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
177 }
178
179 static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
180 {
181 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
182 }
183
184 static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
185 {
186 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
187 }
188
189 static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
190 {
191 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
192 }
193
194 static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
195 {
196 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
197 }
198
199 static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
200 {
201 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
202 }
203
204 /* Core list of CMU_CPU side */
205
206 static struct clksrc_clk exynos5_clk_mout_apll = {
207 .clk = {
208 .name = "mout_apll",
209 },
210 .sources = &clk_src_apll,
211 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
212 };
213
214 static struct clksrc_clk exynos5_clk_sclk_apll = {
215 .clk = {
216 .name = "sclk_apll",
217 .parent = &exynos5_clk_mout_apll.clk,
218 },
219 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
220 };
221
222 static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
223 .clk = {
224 .name = "mout_bpll_fout",
225 },
226 .sources = &clk_src_bpll_fout,
227 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
228 };
229
230 static struct clk *exynos5_clk_src_bpll_list[] = {
231 [0] = &clk_fin_bpll,
232 [1] = &exynos5_clk_mout_bpll_fout.clk,
233 };
234
235 static struct clksrc_sources exynos5_clk_src_bpll = {
236 .sources = exynos5_clk_src_bpll_list,
237 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
238 };
239
240 static struct clksrc_clk exynos5_clk_mout_bpll = {
241 .clk = {
242 .name = "mout_bpll",
243 },
244 .sources = &exynos5_clk_src_bpll,
245 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
246 };
247
248 static struct clk *exynos5_clk_src_bpll_user_list[] = {
249 [0] = &clk_fin_mpll,
250 [1] = &exynos5_clk_mout_bpll.clk,
251 };
252
253 static struct clksrc_sources exynos5_clk_src_bpll_user = {
254 .sources = exynos5_clk_src_bpll_user_list,
255 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
256 };
257
258 static struct clksrc_clk exynos5_clk_mout_bpll_user = {
259 .clk = {
260 .name = "mout_bpll_user",
261 },
262 .sources = &exynos5_clk_src_bpll_user,
263 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
264 };
265
266 static struct clksrc_clk exynos5_clk_mout_cpll = {
267 .clk = {
268 .name = "mout_cpll",
269 },
270 .sources = &clk_src_cpll,
271 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
272 };
273
274 static struct clksrc_clk exynos5_clk_mout_epll = {
275 .clk = {
276 .name = "mout_epll",
277 },
278 .sources = &clk_src_epll,
279 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
280 };
281
282 static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
283 .clk = {
284 .name = "mout_mpll_fout",
285 },
286 .sources = &clk_src_mpll_fout,
287 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
288 };
289
290 static struct clk *exynos5_clk_src_mpll_list[] = {
291 [0] = &clk_fin_mpll,
292 [1] = &exynos5_clk_mout_mpll_fout.clk,
293 };
294
295 static struct clksrc_sources exynos5_clk_src_mpll = {
296 .sources = exynos5_clk_src_mpll_list,
297 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
298 };
299
300 struct clksrc_clk exynos5_clk_mout_mpll = {
301 .clk = {
302 .name = "mout_mpll",
303 },
304 .sources = &exynos5_clk_src_mpll,
305 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
306 };
307
308 static struct clk *exynos_clkset_vpllsrc_list[] = {
309 [0] = &clk_fin_vpll,
310 [1] = &exynos5_clk_sclk_hdmi27m,
311 };
312
313 static struct clksrc_sources exynos5_clkset_vpllsrc = {
314 .sources = exynos_clkset_vpllsrc_list,
315 .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
316 };
317
318 static struct clksrc_clk exynos5_clk_vpllsrc = {
319 .clk = {
320 .name = "vpll_src",
321 .enable = exynos5_clksrc_mask_top_ctrl,
322 .ctrlbit = (1 << 0),
323 },
324 .sources = &exynos5_clkset_vpllsrc,
325 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
326 };
327
328 static struct clk *exynos5_clkset_sclk_vpll_list[] = {
329 [0] = &exynos5_clk_vpllsrc.clk,
330 [1] = &clk_fout_vpll,
331 };
332
333 static struct clksrc_sources exynos5_clkset_sclk_vpll = {
334 .sources = exynos5_clkset_sclk_vpll_list,
335 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
336 };
337
338 static struct clksrc_clk exynos5_clk_sclk_vpll = {
339 .clk = {
340 .name = "sclk_vpll",
341 },
342 .sources = &exynos5_clkset_sclk_vpll,
343 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
344 };
345
346 static struct clksrc_clk exynos5_clk_sclk_pixel = {
347 .clk = {
348 .name = "sclk_pixel",
349 .parent = &exynos5_clk_sclk_vpll.clk,
350 },
351 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
352 };
353
354 static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
355 [0] = &exynos5_clk_sclk_pixel.clk,
356 [1] = &exynos5_clk_sclk_hdmiphy,
357 };
358
359 static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
360 .sources = exynos5_clkset_sclk_hdmi_list,
361 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
362 };
363
364 static struct clksrc_clk exynos5_clk_sclk_hdmi = {
365 .clk = {
366 .name = "sclk_hdmi",
367 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
368 .ctrlbit = (1 << 20),
369 },
370 .sources = &exynos5_clkset_sclk_hdmi,
371 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
372 };
373
374 static struct clksrc_clk *exynos5_sclk_tv[] = {
375 &exynos5_clk_sclk_pixel,
376 &exynos5_clk_sclk_hdmi,
377 };
378
379 static struct clk *exynos5_clk_src_mpll_user_list[] = {
380 [0] = &clk_fin_mpll,
381 [1] = &exynos5_clk_mout_mpll.clk,
382 };
383
384 static struct clksrc_sources exynos5_clk_src_mpll_user = {
385 .sources = exynos5_clk_src_mpll_user_list,
386 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
387 };
388
389 static struct clksrc_clk exynos5_clk_mout_mpll_user = {
390 .clk = {
391 .name = "mout_mpll_user",
392 },
393 .sources = &exynos5_clk_src_mpll_user,
394 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
395 };
396
397 static struct clk *exynos5_clkset_mout_cpu_list[] = {
398 [0] = &exynos5_clk_mout_apll.clk,
399 [1] = &exynos5_clk_mout_mpll.clk,
400 };
401
402 static struct clksrc_sources exynos5_clkset_mout_cpu = {
403 .sources = exynos5_clkset_mout_cpu_list,
404 .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
405 };
406
407 static struct clksrc_clk exynos5_clk_mout_cpu = {
408 .clk = {
409 .name = "mout_cpu",
410 },
411 .sources = &exynos5_clkset_mout_cpu,
412 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
413 };
414
415 static struct clksrc_clk exynos5_clk_dout_armclk = {
416 .clk = {
417 .name = "dout_armclk",
418 .parent = &exynos5_clk_mout_cpu.clk,
419 },
420 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
421 };
422
423 static struct clksrc_clk exynos5_clk_dout_arm2clk = {
424 .clk = {
425 .name = "dout_arm2clk",
426 .parent = &exynos5_clk_dout_armclk.clk,
427 },
428 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
429 };
430
431 static struct clk exynos5_clk_armclk = {
432 .name = "armclk",
433 .parent = &exynos5_clk_dout_arm2clk.clk,
434 };
435
436 /* Core list of CMU_CDREX side */
437
438 static struct clk *exynos5_clkset_cdrex_list[] = {
439 [0] = &exynos5_clk_mout_mpll.clk,
440 [1] = &exynos5_clk_mout_bpll.clk,
441 };
442
443 static struct clksrc_sources exynos5_clkset_cdrex = {
444 .sources = exynos5_clkset_cdrex_list,
445 .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
446 };
447
448 static struct clksrc_clk exynos5_clk_cdrex = {
449 .clk = {
450 .name = "clk_cdrex",
451 },
452 .sources = &exynos5_clkset_cdrex,
453 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
454 .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
455 };
456
457 static struct clksrc_clk exynos5_clk_aclk_acp = {
458 .clk = {
459 .name = "aclk_acp",
460 .parent = &exynos5_clk_mout_mpll.clk,
461 },
462 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
463 };
464
465 static struct clksrc_clk exynos5_clk_pclk_acp = {
466 .clk = {
467 .name = "pclk_acp",
468 .parent = &exynos5_clk_aclk_acp.clk,
469 },
470 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
471 };
472
473 /* Core list of CMU_TOP side */
474
475 struct clk *exynos5_clkset_aclk_top_list[] = {
476 [0] = &exynos5_clk_mout_mpll_user.clk,
477 [1] = &exynos5_clk_mout_bpll_user.clk,
478 };
479
480 struct clksrc_sources exynos5_clkset_aclk = {
481 .sources = exynos5_clkset_aclk_top_list,
482 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
483 };
484
485 static struct clksrc_clk exynos5_clk_aclk_400 = {
486 .clk = {
487 .name = "aclk_400",
488 },
489 .sources = &exynos5_clkset_aclk,
490 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
491 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
492 };
493
494 struct clk *exynos5_clkset_aclk_333_166_list[] = {
495 [0] = &exynos5_clk_mout_cpll.clk,
496 [1] = &exynos5_clk_mout_mpll_user.clk,
497 };
498
499 struct clksrc_sources exynos5_clkset_aclk_333_166 = {
500 .sources = exynos5_clkset_aclk_333_166_list,
501 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
502 };
503
504 static struct clksrc_clk exynos5_clk_aclk_333 = {
505 .clk = {
506 .name = "aclk_333",
507 },
508 .sources = &exynos5_clkset_aclk_333_166,
509 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
510 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
511 };
512
513 static struct clksrc_clk exynos5_clk_aclk_166 = {
514 .clk = {
515 .name = "aclk_166",
516 },
517 .sources = &exynos5_clkset_aclk_333_166,
518 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
519 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
520 };
521
522 static struct clksrc_clk exynos5_clk_aclk_266 = {
523 .clk = {
524 .name = "aclk_266",
525 .parent = &exynos5_clk_mout_mpll_user.clk,
526 },
527 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
528 };
529
530 static struct clksrc_clk exynos5_clk_aclk_200 = {
531 .clk = {
532 .name = "aclk_200",
533 },
534 .sources = &exynos5_clkset_aclk,
535 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
536 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
537 };
538
539 static struct clksrc_clk exynos5_clk_aclk_66_pre = {
540 .clk = {
541 .name = "aclk_66_pre",
542 .parent = &exynos5_clk_mout_mpll_user.clk,
543 },
544 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
545 };
546
547 static struct clksrc_clk exynos5_clk_aclk_66 = {
548 .clk = {
549 .name = "aclk_66",
550 .parent = &exynos5_clk_aclk_66_pre.clk,
551 },
552 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
553 };
554
555 static struct clk exynos5_init_clocks_off[] = {
556 {
557 .name = "timers",
558 .parent = &exynos5_clk_aclk_66.clk,
559 .enable = exynos5_clk_ip_peric_ctrl,
560 .ctrlbit = (1 << 24),
561 }, {
562 .name = "rtc",
563 .parent = &exynos5_clk_aclk_66.clk,
564 .enable = exynos5_clk_ip_peris_ctrl,
565 .ctrlbit = (1 << 20),
566 }, {
567 .name = "watchdog",
568 .parent = &exynos5_clk_aclk_66.clk,
569 .enable = exynos5_clk_ip_peris_ctrl,
570 .ctrlbit = (1 << 19),
571 }, {
572 .name = "hsmmc",
573 .devname = "exynos4-sdhci.0",
574 .parent = &exynos5_clk_aclk_200.clk,
575 .enable = exynos5_clk_ip_fsys_ctrl,
576 .ctrlbit = (1 << 12),
577 }, {
578 .name = "hsmmc",
579 .devname = "exynos4-sdhci.1",
580 .parent = &exynos5_clk_aclk_200.clk,
581 .enable = exynos5_clk_ip_fsys_ctrl,
582 .ctrlbit = (1 << 13),
583 }, {
584 .name = "hsmmc",
585 .devname = "exynos4-sdhci.2",
586 .parent = &exynos5_clk_aclk_200.clk,
587 .enable = exynos5_clk_ip_fsys_ctrl,
588 .ctrlbit = (1 << 14),
589 }, {
590 .name = "hsmmc",
591 .devname = "exynos4-sdhci.3",
592 .parent = &exynos5_clk_aclk_200.clk,
593 .enable = exynos5_clk_ip_fsys_ctrl,
594 .ctrlbit = (1 << 15),
595 }, {
596 .name = "dwmci",
597 .parent = &exynos5_clk_aclk_200.clk,
598 .enable = exynos5_clk_ip_fsys_ctrl,
599 .ctrlbit = (1 << 16),
600 }, {
601 .name = "sata",
602 .devname = "ahci",
603 .enable = exynos5_clk_ip_fsys_ctrl,
604 .ctrlbit = (1 << 6),
605 }, {
606 .name = "sata_phy",
607 .enable = exynos5_clk_ip_fsys_ctrl,
608 .ctrlbit = (1 << 24),
609 }, {
610 .name = "sata_phy_i2c",
611 .enable = exynos5_clk_ip_fsys_ctrl,
612 .ctrlbit = (1 << 25),
613 }, {
614 .name = "mfc",
615 .devname = "s5p-mfc",
616 .enable = exynos5_clk_ip_mfc_ctrl,
617 .ctrlbit = (1 << 0),
618 }, {
619 .name = "hdmi",
620 .devname = "exynos4-hdmi",
621 .enable = exynos5_clk_ip_disp1_ctrl,
622 .ctrlbit = (1 << 6),
623 }, {
624 .name = "mixer",
625 .devname = "s5p-mixer",
626 .enable = exynos5_clk_ip_disp1_ctrl,
627 .ctrlbit = (1 << 5),
628 }, {
629 .name = "jpeg",
630 .enable = exynos5_clk_ip_gen_ctrl,
631 .ctrlbit = (1 << 2),
632 }, {
633 .name = "dsim0",
634 .enable = exynos5_clk_ip_disp1_ctrl,
635 .ctrlbit = (1 << 3),
636 }, {
637 .name = "iis",
638 .devname = "samsung-i2s.1",
639 .enable = exynos5_clk_ip_peric_ctrl,
640 .ctrlbit = (1 << 20),
641 }, {
642 .name = "iis",
643 .devname = "samsung-i2s.2",
644 .enable = exynos5_clk_ip_peric_ctrl,
645 .ctrlbit = (1 << 21),
646 }, {
647 .name = "pcm",
648 .devname = "samsung-pcm.1",
649 .enable = exynos5_clk_ip_peric_ctrl,
650 .ctrlbit = (1 << 22),
651 }, {
652 .name = "pcm",
653 .devname = "samsung-pcm.2",
654 .enable = exynos5_clk_ip_peric_ctrl,
655 .ctrlbit = (1 << 23),
656 }, {
657 .name = "spdif",
658 .devname = "samsung-spdif",
659 .enable = exynos5_clk_ip_peric_ctrl,
660 .ctrlbit = (1 << 26),
661 }, {
662 .name = "ac97",
663 .devname = "samsung-ac97",
664 .enable = exynos5_clk_ip_peric_ctrl,
665 .ctrlbit = (1 << 27),
666 }, {
667 .name = "usbhost",
668 .enable = exynos5_clk_ip_fsys_ctrl ,
669 .ctrlbit = (1 << 18),
670 }, {
671 .name = "usbotg",
672 .enable = exynos5_clk_ip_fsys_ctrl,
673 .ctrlbit = (1 << 7),
674 }, {
675 .name = "gps",
676 .enable = exynos5_clk_ip_gps_ctrl,
677 .ctrlbit = ((1 << 3) | (1 << 2) | (1 << 0)),
678 }, {
679 .name = "nfcon",
680 .enable = exynos5_clk_ip_fsys_ctrl,
681 .ctrlbit = (1 << 22),
682 }, {
683 .name = "iop",
684 .enable = exynos5_clk_ip_fsys_ctrl,
685 .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
686 }, {
687 .name = "core_iop",
688 .enable = exynos5_clk_ip_core_ctrl,
689 .ctrlbit = ((1 << 21) | (1 << 3)),
690 }, {
691 .name = "mcu_iop",
692 .enable = exynos5_clk_ip_fsys_ctrl,
693 .ctrlbit = (1 << 0),
694 }, {
695 .name = "i2c",
696 .devname = "s3c2440-i2c.0",
697 .parent = &exynos5_clk_aclk_66.clk,
698 .enable = exynos5_clk_ip_peric_ctrl,
699 .ctrlbit = (1 << 6),
700 }, {
701 .name = "i2c",
702 .devname = "s3c2440-i2c.1",
703 .parent = &exynos5_clk_aclk_66.clk,
704 .enable = exynos5_clk_ip_peric_ctrl,
705 .ctrlbit = (1 << 7),
706 }, {
707 .name = "i2c",
708 .devname = "s3c2440-i2c.2",
709 .parent = &exynos5_clk_aclk_66.clk,
710 .enable = exynos5_clk_ip_peric_ctrl,
711 .ctrlbit = (1 << 8),
712 }, {
713 .name = "i2c",
714 .devname = "s3c2440-i2c.3",
715 .parent = &exynos5_clk_aclk_66.clk,
716 .enable = exynos5_clk_ip_peric_ctrl,
717 .ctrlbit = (1 << 9),
718 }, {
719 .name = "i2c",
720 .devname = "s3c2440-i2c.4",
721 .parent = &exynos5_clk_aclk_66.clk,
722 .enable = exynos5_clk_ip_peric_ctrl,
723 .ctrlbit = (1 << 10),
724 }, {
725 .name = "i2c",
726 .devname = "s3c2440-i2c.5",
727 .parent = &exynos5_clk_aclk_66.clk,
728 .enable = exynos5_clk_ip_peric_ctrl,
729 .ctrlbit = (1 << 11),
730 }, {
731 .name = "i2c",
732 .devname = "s3c2440-i2c.6",
733 .parent = &exynos5_clk_aclk_66.clk,
734 .enable = exynos5_clk_ip_peric_ctrl,
735 .ctrlbit = (1 << 12),
736 }, {
737 .name = "i2c",
738 .devname = "s3c2440-i2c.7",
739 .parent = &exynos5_clk_aclk_66.clk,
740 .enable = exynos5_clk_ip_peric_ctrl,
741 .ctrlbit = (1 << 13),
742 }, {
743 .name = "i2c",
744 .devname = "s3c2440-hdmiphy-i2c",
745 .parent = &exynos5_clk_aclk_66.clk,
746 .enable = exynos5_clk_ip_peric_ctrl,
747 .ctrlbit = (1 << 14),
748 }, {
749 .name = "spi",
750 .devname = "exynos4210-spi.0",
751 .parent = &exynos5_clk_aclk_66.clk,
752 .enable = exynos5_clk_ip_peric_ctrl,
753 .ctrlbit = (1 << 16),
754 }, {
755 .name = "spi",
756 .devname = "exynos4210-spi.1",
757 .parent = &exynos5_clk_aclk_66.clk,
758 .enable = exynos5_clk_ip_peric_ctrl,
759 .ctrlbit = (1 << 17),
760 }, {
761 .name = "spi",
762 .devname = "exynos4210-spi.2",
763 .parent = &exynos5_clk_aclk_66.clk,
764 .enable = exynos5_clk_ip_peric_ctrl,
765 .ctrlbit = (1 << 18),
766 }, {
767 .name = SYSMMU_CLOCK_NAME,
768 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
769 .enable = &exynos5_clk_ip_mfc_ctrl,
770 .ctrlbit = (1 << 1),
771 }, {
772 .name = SYSMMU_CLOCK_NAME,
773 .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
774 .enable = &exynos5_clk_ip_mfc_ctrl,
775 .ctrlbit = (1 << 2),
776 }, {
777 .name = SYSMMU_CLOCK_NAME,
778 .devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
779 .enable = &exynos5_clk_ip_disp1_ctrl,
780 .ctrlbit = (1 << 9)
781 }, {
782 .name = SYSMMU_CLOCK_NAME,
783 .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
784 .enable = &exynos5_clk_ip_gen_ctrl,
785 .ctrlbit = (1 << 7),
786 }, {
787 .name = SYSMMU_CLOCK_NAME,
788 .devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
789 .enable = &exynos5_clk_ip_gen_ctrl,
790 .ctrlbit = (1 << 6)
791 }, {
792 .name = SYSMMU_CLOCK_NAME,
793 .devname = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
794 .enable = &exynos5_clk_ip_gscl_ctrl,
795 .ctrlbit = (1 << 7),
796 }, {
797 .name = SYSMMU_CLOCK_NAME,
798 .devname = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
799 .enable = &exynos5_clk_ip_gscl_ctrl,
800 .ctrlbit = (1 << 8),
801 }, {
802 .name = SYSMMU_CLOCK_NAME,
803 .devname = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
804 .enable = &exynos5_clk_ip_gscl_ctrl,
805 .ctrlbit = (1 << 9),
806 }, {
807 .name = SYSMMU_CLOCK_NAME,
808 .devname = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
809 .enable = &exynos5_clk_ip_gscl_ctrl,
810 .ctrlbit = (1 << 10),
811 }, {
812 .name = SYSMMU_CLOCK_NAME,
813 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
814 .enable = &exynos5_clk_ip_isp0_ctrl,
815 .ctrlbit = (0x3F << 8),
816 }, {
817 .name = SYSMMU_CLOCK_NAME2,
818 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
819 .enable = &exynos5_clk_ip_isp1_ctrl,
820 .ctrlbit = (0xF << 4),
821 }, {
822 .name = SYSMMU_CLOCK_NAME,
823 .devname = SYSMMU_CLOCK_DEVNAME(camif0, 12),
824 .enable = &exynos5_clk_ip_gscl_ctrl,
825 .ctrlbit = (1 << 11),
826 }, {
827 .name = SYSMMU_CLOCK_NAME,
828 .devname = SYSMMU_CLOCK_DEVNAME(camif1, 13),
829 .enable = &exynos5_clk_ip_gscl_ctrl,
830 .ctrlbit = (1 << 12),
831 }, {
832 .name = SYSMMU_CLOCK_NAME,
833 .devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
834 .enable = &exynos5_clk_ip_acp_ctrl,
835 .ctrlbit = (1 << 7)
836 }
837 };
838
839 static struct clk exynos5_init_clocks_on[] = {
840 {
841 .name = "uart",
842 .devname = "s5pv210-uart.0",
843 .enable = exynos5_clk_ip_peric_ctrl,
844 .ctrlbit = (1 << 0),
845 }, {
846 .name = "uart",
847 .devname = "s5pv210-uart.1",
848 .enable = exynos5_clk_ip_peric_ctrl,
849 .ctrlbit = (1 << 1),
850 }, {
851 .name = "uart",
852 .devname = "s5pv210-uart.2",
853 .enable = exynos5_clk_ip_peric_ctrl,
854 .ctrlbit = (1 << 2),
855 }, {
856 .name = "uart",
857 .devname = "s5pv210-uart.3",
858 .enable = exynos5_clk_ip_peric_ctrl,
859 .ctrlbit = (1 << 3),
860 }, {
861 .name = "uart",
862 .devname = "s5pv210-uart.4",
863 .enable = exynos5_clk_ip_peric_ctrl,
864 .ctrlbit = (1 << 4),
865 }, {
866 .name = "uart",
867 .devname = "s5pv210-uart.5",
868 .enable = exynos5_clk_ip_peric_ctrl,
869 .ctrlbit = (1 << 5),
870 }
871 };
872
873 static struct clk exynos5_clk_pdma0 = {
874 .name = "dma",
875 .devname = "dma-pl330.0",
876 .enable = exynos5_clk_ip_fsys_ctrl,
877 .ctrlbit = (1 << 1),
878 };
879
880 static struct clk exynos5_clk_pdma1 = {
881 .name = "dma",
882 .devname = "dma-pl330.1",
883 .enable = exynos5_clk_ip_fsys_ctrl,
884 .ctrlbit = (1 << 2),
885 };
886
887 static struct clk exynos5_clk_mdma1 = {
888 .name = "dma",
889 .devname = "dma-pl330.2",
890 .enable = exynos5_clk_ip_gen_ctrl,
891 .ctrlbit = (1 << 4),
892 };
893
894 struct clk *exynos5_clkset_group_list[] = {
895 [0] = &clk_ext_xtal_mux,
896 [1] = NULL,
897 [2] = &exynos5_clk_sclk_hdmi24m,
898 [3] = &exynos5_clk_sclk_dptxphy,
899 [4] = &exynos5_clk_sclk_usbphy,
900 [5] = &exynos5_clk_sclk_hdmiphy,
901 [6] = &exynos5_clk_mout_mpll_user.clk,
902 [7] = &exynos5_clk_mout_epll.clk,
903 [8] = &exynos5_clk_sclk_vpll.clk,
904 [9] = &exynos5_clk_mout_cpll.clk,
905 };
906
907 struct clksrc_sources exynos5_clkset_group = {
908 .sources = exynos5_clkset_group_list,
909 .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
910 };
911
912 /* Possible clock sources for aclk_266_gscl_sub Mux */
913 static struct clk *clk_src_gscl_266_list[] = {
914 [0] = &clk_ext_xtal_mux,
915 [1] = &exynos5_clk_aclk_266.clk,
916 };
917
918 static struct clksrc_sources clk_src_gscl_266 = {
919 .sources = clk_src_gscl_266_list,
920 .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
921 };
922
923 static struct clksrc_clk exynos5_clk_dout_mmc0 = {
924 .clk = {
925 .name = "dout_mmc0",
926 },
927 .sources = &exynos5_clkset_group,
928 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
929 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
930 };
931
932 static struct clksrc_clk exynos5_clk_dout_mmc1 = {
933 .clk = {
934 .name = "dout_mmc1",
935 },
936 .sources = &exynos5_clkset_group,
937 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
938 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
939 };
940
941 static struct clksrc_clk exynos5_clk_dout_mmc2 = {
942 .clk = {
943 .name = "dout_mmc2",
944 },
945 .sources = &exynos5_clkset_group,
946 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
947 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
948 };
949
950 static struct clksrc_clk exynos5_clk_dout_mmc3 = {
951 .clk = {
952 .name = "dout_mmc3",
953 },
954 .sources = &exynos5_clkset_group,
955 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
956 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
957 };
958
959 static struct clksrc_clk exynos5_clk_dout_mmc4 = {
960 .clk = {
961 .name = "dout_mmc4",
962 },
963 .sources = &exynos5_clkset_group,
964 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
965 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
966 };
967
968 static struct clksrc_clk exynos5_clk_sclk_uart0 = {
969 .clk = {
970 .name = "uclk1",
971 .devname = "exynos4210-uart.0",
972 .enable = exynos5_clksrc_mask_peric0_ctrl,
973 .ctrlbit = (1 << 0),
974 },
975 .sources = &exynos5_clkset_group,
976 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
977 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
978 };
979
980 static struct clksrc_clk exynos5_clk_sclk_uart1 = {
981 .clk = {
982 .name = "uclk1",
983 .devname = "exynos4210-uart.1",
984 .enable = exynos5_clksrc_mask_peric0_ctrl,
985 .ctrlbit = (1 << 4),
986 },
987 .sources = &exynos5_clkset_group,
988 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
989 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
990 };
991
992 static struct clksrc_clk exynos5_clk_sclk_uart2 = {
993 .clk = {
994 .name = "uclk1",
995 .devname = "exynos4210-uart.2",
996 .enable = exynos5_clksrc_mask_peric0_ctrl,
997 .ctrlbit = (1 << 8),
998 },
999 .sources = &exynos5_clkset_group,
1000 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
1001 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
1002 };
1003
1004 static struct clksrc_clk exynos5_clk_sclk_uart3 = {
1005 .clk = {
1006 .name = "uclk1",
1007 .devname = "exynos4210-uart.3",
1008 .enable = exynos5_clksrc_mask_peric0_ctrl,
1009 .ctrlbit = (1 << 12),
1010 },
1011 .sources = &exynos5_clkset_group,
1012 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
1013 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
1014 };
1015
1016 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
1017 .clk = {
1018 .name = "sclk_mmc",
1019 .devname = "exynos4-sdhci.0",
1020 .parent = &exynos5_clk_dout_mmc0.clk,
1021 .enable = exynos5_clksrc_mask_fsys_ctrl,
1022 .ctrlbit = (1 << 0),
1023 },
1024 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1025 };
1026
1027 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1028 .clk = {
1029 .name = "sclk_mmc",
1030 .devname = "exynos4-sdhci.1",
1031 .parent = &exynos5_clk_dout_mmc1.clk,
1032 .enable = exynos5_clksrc_mask_fsys_ctrl,
1033 .ctrlbit = (1 << 4),
1034 },
1035 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1036 };
1037
1038 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1039 .clk = {
1040 .name = "sclk_mmc",
1041 .devname = "exynos4-sdhci.2",
1042 .parent = &exynos5_clk_dout_mmc2.clk,
1043 .enable = exynos5_clksrc_mask_fsys_ctrl,
1044 .ctrlbit = (1 << 8),
1045 },
1046 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1047 };
1048
1049 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1050 .clk = {
1051 .name = "sclk_mmc",
1052 .devname = "exynos4-sdhci.3",
1053 .parent = &exynos5_clk_dout_mmc3.clk,
1054 .enable = exynos5_clksrc_mask_fsys_ctrl,
1055 .ctrlbit = (1 << 12),
1056 },
1057 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1058 };
1059
1060 static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1061 .clk = {
1062 .name = "mdout_spi",
1063 .devname = "exynos4210-spi.0",
1064 },
1065 .sources = &exynos5_clkset_group,
1066 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1067 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1068 };
1069
1070 static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1071 .clk = {
1072 .name = "mdout_spi",
1073 .devname = "exynos4210-spi.1",
1074 },
1075 .sources = &exynos5_clkset_group,
1076 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1077 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1078 };
1079
1080 static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1081 .clk = {
1082 .name = "mdout_spi",
1083 .devname = "exynos4210-spi.2",
1084 },
1085 .sources = &exynos5_clkset_group,
1086 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1087 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1088 };
1089
1090 static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1091 .clk = {
1092 .name = "sclk_spi",
1093 .devname = "exynos4210-spi.0",
1094 .parent = &exynos5_clk_mdout_spi0.clk,
1095 .enable = exynos5_clksrc_mask_peric1_ctrl,
1096 .ctrlbit = (1 << 16),
1097 },
1098 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1099 };
1100
1101 static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1102 .clk = {
1103 .name = "sclk_spi",
1104 .devname = "exynos4210-spi.1",
1105 .parent = &exynos5_clk_mdout_spi1.clk,
1106 .enable = exynos5_clksrc_mask_peric1_ctrl,
1107 .ctrlbit = (1 << 20),
1108 },
1109 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1110 };
1111
1112 static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1113 .clk = {
1114 .name = "sclk_spi",
1115 .devname = "exynos4210-spi.2",
1116 .parent = &exynos5_clk_mdout_spi2.clk,
1117 .enable = exynos5_clksrc_mask_peric1_ctrl,
1118 .ctrlbit = (1 << 24),
1119 },
1120 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1121 };
1122
1123 static struct clksrc_clk exynos5_clksrcs[] = {
1124 {
1125 .clk = {
1126 .name = "sclk_dwmci",
1127 .parent = &exynos5_clk_dout_mmc4.clk,
1128 .enable = exynos5_clksrc_mask_fsys_ctrl,
1129 .ctrlbit = (1 << 16),
1130 },
1131 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1132 }, {
1133 .clk = {
1134 .name = "sclk_fimd",
1135 .devname = "s3cfb.1",
1136 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
1137 .ctrlbit = (1 << 0),
1138 },
1139 .sources = &exynos5_clkset_group,
1140 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1141 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1142 }, {
1143 .clk = {
1144 .name = "aclk_266_gscl",
1145 },
1146 .sources = &clk_src_gscl_266,
1147 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1148 }, {
1149 .clk = {
1150 .name = "sclk_g3d",
1151 .devname = "mali-t604.0",
1152 .enable = exynos5_clk_block_ctrl,
1153 .ctrlbit = (1 << 1),
1154 },
1155 .sources = &exynos5_clkset_aclk,
1156 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1157 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1158 }, {
1159 .clk = {
1160 .name = "sclk_gscl_wrap",
1161 .devname = "s5p-mipi-csis.0",
1162 .enable = exynos5_clksrc_mask_gscl_ctrl,
1163 .ctrlbit = (1 << 24),
1164 },
1165 .sources = &exynos5_clkset_group,
1166 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1167 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1168 }, {
1169 .clk = {
1170 .name = "sclk_gscl_wrap",
1171 .devname = "s5p-mipi-csis.1",
1172 .enable = exynos5_clksrc_mask_gscl_ctrl,
1173 .ctrlbit = (1 << 28),
1174 },
1175 .sources = &exynos5_clkset_group,
1176 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1177 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1178 }, {
1179 .clk = {
1180 .name = "sclk_cam0",
1181 .enable = exynos5_clksrc_mask_gscl_ctrl,
1182 .ctrlbit = (1 << 16),
1183 },
1184 .sources = &exynos5_clkset_group,
1185 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1186 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1187 }, {
1188 .clk = {
1189 .name = "sclk_cam1",
1190 .enable = exynos5_clksrc_mask_gscl_ctrl,
1191 .ctrlbit = (1 << 20),
1192 },
1193 .sources = &exynos5_clkset_group,
1194 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1195 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1196 }, {
1197 .clk = {
1198 .name = "sclk_jpeg",
1199 .parent = &exynos5_clk_mout_cpll.clk,
1200 },
1201 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1202 },
1203 };
1204
1205 /* Clock initialization code */
1206 static struct clksrc_clk *exynos5_sysclks[] = {
1207 &exynos5_clk_mout_apll,
1208 &exynos5_clk_sclk_apll,
1209 &exynos5_clk_mout_bpll,
1210 &exynos5_clk_mout_bpll_fout,
1211 &exynos5_clk_mout_bpll_user,
1212 &exynos5_clk_mout_cpll,
1213 &exynos5_clk_mout_epll,
1214 &exynos5_clk_mout_mpll,
1215 &exynos5_clk_mout_mpll_fout,
1216 &exynos5_clk_mout_mpll_user,
1217 &exynos5_clk_vpllsrc,
1218 &exynos5_clk_sclk_vpll,
1219 &exynos5_clk_mout_cpu,
1220 &exynos5_clk_dout_armclk,
1221 &exynos5_clk_dout_arm2clk,
1222 &exynos5_clk_cdrex,
1223 &exynos5_clk_aclk_400,
1224 &exynos5_clk_aclk_333,
1225 &exynos5_clk_aclk_266,
1226 &exynos5_clk_aclk_200,
1227 &exynos5_clk_aclk_166,
1228 &exynos5_clk_aclk_66_pre,
1229 &exynos5_clk_aclk_66,
1230 &exynos5_clk_dout_mmc0,
1231 &exynos5_clk_dout_mmc1,
1232 &exynos5_clk_dout_mmc2,
1233 &exynos5_clk_dout_mmc3,
1234 &exynos5_clk_dout_mmc4,
1235 &exynos5_clk_aclk_acp,
1236 &exynos5_clk_pclk_acp,
1237 &exynos5_clk_sclk_spi0,
1238 &exynos5_clk_sclk_spi1,
1239 &exynos5_clk_sclk_spi2,
1240 &exynos5_clk_mdout_spi0,
1241 &exynos5_clk_mdout_spi1,
1242 &exynos5_clk_mdout_spi2,
1243 };
1244
1245 static struct clk *exynos5_clk_cdev[] = {
1246 &exynos5_clk_pdma0,
1247 &exynos5_clk_pdma1,
1248 &exynos5_clk_mdma1,
1249 };
1250
1251 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1252 &exynos5_clk_sclk_uart0,
1253 &exynos5_clk_sclk_uart1,
1254 &exynos5_clk_sclk_uart2,
1255 &exynos5_clk_sclk_uart3,
1256 &exynos5_clk_sclk_mmc0,
1257 &exynos5_clk_sclk_mmc1,
1258 &exynos5_clk_sclk_mmc2,
1259 &exynos5_clk_sclk_mmc3,
1260 };
1261
1262 static struct clk_lookup exynos5_clk_lookup[] = {
1263 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1264 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1265 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1266 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1267 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1268 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1269 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1270 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1271 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1272 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1273 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1274 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1275 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1276 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1277 };
1278
1279 static unsigned long exynos5_epll_get_rate(struct clk *clk)
1280 {
1281 return clk->rate;
1282 }
1283
1284 static struct clk *exynos5_clks[] __initdata = {
1285 &exynos5_clk_sclk_hdmi27m,
1286 &exynos5_clk_sclk_hdmiphy,
1287 &clk_fout_bpll,
1288 &clk_fout_bpll_div2,
1289 &clk_fout_cpll,
1290 &clk_fout_mpll_div2,
1291 &exynos5_clk_armclk,
1292 };
1293
1294 static u32 epll_div[][6] = {
1295 { 192000000, 0, 48, 3, 1, 0 },
1296 { 180000000, 0, 45, 3, 1, 0 },
1297 { 73728000, 1, 73, 3, 3, 47710 },
1298 { 67737600, 1, 90, 4, 3, 20762 },
1299 { 49152000, 0, 49, 3, 3, 9961 },
1300 { 45158400, 0, 45, 3, 3, 10381 },
1301 { 180633600, 0, 45, 3, 1, 10381 },
1302 };
1303
1304 static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1305 {
1306 unsigned int epll_con, epll_con_k;
1307 unsigned int i;
1308 unsigned int tmp;
1309 unsigned int epll_rate;
1310 unsigned int locktime;
1311 unsigned int lockcnt;
1312
1313 /* Return if nothing changed */
1314 if (clk->rate == rate)
1315 return 0;
1316
1317 if (clk->parent)
1318 epll_rate = clk_get_rate(clk->parent);
1319 else
1320 epll_rate = clk_ext_xtal_mux.rate;
1321
1322 if (epll_rate != 24000000) {
1323 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1324 return -EINVAL;
1325 }
1326
1327 epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1328 epll_con &= ~(0x1 << 27 | \
1329 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1330 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1331 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1332
1333 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1334 if (epll_div[i][0] == rate) {
1335 epll_con_k = epll_div[i][5] << 0;
1336 epll_con |= epll_div[i][1] << 27;
1337 epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1338 epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1339 epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1340 break;
1341 }
1342 }
1343
1344 if (i == ARRAY_SIZE(epll_div)) {
1345 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1346 __func__);
1347 return -EINVAL;
1348 }
1349
1350 epll_rate /= 1000000;
1351
1352 /* 3000 max_cycls : specification data */
1353 locktime = 3000 / epll_rate * epll_div[i][3];
1354 lockcnt = locktime * 10000 / (10000 / epll_rate);
1355
1356 __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1357
1358 __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1359 __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1360
1361 do {
1362 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1363 } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1364
1365 clk->rate = rate;
1366
1367 return 0;
1368 }
1369
1370 static struct clk_ops exynos5_epll_ops = {
1371 .get_rate = exynos5_epll_get_rate,
1372 .set_rate = exynos5_epll_set_rate,
1373 };
1374
1375 static int xtal_rate;
1376
1377 static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1378 {
1379 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1380 }
1381
1382 static struct clk_ops exynos5_fout_apll_ops = {
1383 .get_rate = exynos5_fout_apll_get_rate,
1384 };
1385
1386 #ifdef CONFIG_PM
1387 static int exynos5_clock_suspend(void)
1388 {
1389 s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1390
1391 return 0;
1392 }
1393
1394 static void exynos5_clock_resume(void)
1395 {
1396 s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1397 }
1398 #else
1399 #define exynos5_clock_suspend NULL
1400 #define exynos5_clock_resume NULL
1401 #endif
1402
1403 struct syscore_ops exynos5_clock_syscore_ops = {
1404 .suspend = exynos5_clock_suspend,
1405 .resume = exynos5_clock_resume,
1406 };
1407
1408 void __init_or_cpufreq exynos5_setup_clocks(void)
1409 {
1410 struct clk *xtal_clk;
1411 unsigned long apll;
1412 unsigned long bpll;
1413 unsigned long cpll;
1414 unsigned long mpll;
1415 unsigned long epll;
1416 unsigned long vpll;
1417 unsigned long vpllsrc;
1418 unsigned long xtal;
1419 unsigned long armclk;
1420 unsigned long mout_cdrex;
1421 unsigned long aclk_400;
1422 unsigned long aclk_333;
1423 unsigned long aclk_266;
1424 unsigned long aclk_200;
1425 unsigned long aclk_166;
1426 unsigned long aclk_66;
1427 unsigned int ptr;
1428
1429 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1430
1431 xtal_clk = clk_get(NULL, "xtal");
1432 BUG_ON(IS_ERR(xtal_clk));
1433
1434 xtal = clk_get_rate(xtal_clk);
1435
1436 xtal_rate = xtal;
1437
1438 clk_put(xtal_clk);
1439
1440 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1441
1442 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1443 bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1444 cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1445 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1446 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1447 __raw_readl(EXYNOS5_EPLL_CON1));
1448
1449 vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1450 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1451 __raw_readl(EXYNOS5_VPLL_CON1));
1452
1453 clk_fout_apll.ops = &exynos5_fout_apll_ops;
1454 clk_fout_bpll.rate = bpll;
1455 clk_fout_bpll_div2.rate = bpll >> 1;
1456 clk_fout_cpll.rate = cpll;
1457 clk_fout_mpll.rate = mpll;
1458 clk_fout_mpll_div2.rate = mpll >> 1;
1459 clk_fout_epll.rate = epll;
1460 clk_fout_vpll.rate = vpll;
1461
1462 printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1463 "M=%ld, E=%ld V=%ld",
1464 apll, bpll, cpll, mpll, epll, vpll);
1465
1466 armclk = clk_get_rate(&exynos5_clk_armclk);
1467 mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1468
1469 aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1470 aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1471 aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1472 aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1473 aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1474 aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1475
1476 printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1477 "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1478 "ACLK166=%ld, ACLK66=%ld\n",
1479 armclk, mout_cdrex, aclk_400,
1480 aclk_333, aclk_266, aclk_200,
1481 aclk_166, aclk_66);
1482
1483
1484 clk_fout_epll.ops = &exynos5_epll_ops;
1485
1486 if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1487 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1488 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1489
1490 clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1491 clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1492
1493 clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1494 clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1495
1496 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1497 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1498 }
1499
1500 void __init exynos5_register_clocks(void)
1501 {
1502 int ptr;
1503
1504 s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1505
1506 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1507 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1508
1509 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1510 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1511
1512 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1513 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1514
1515 s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1516 s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1517
1518 s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1519 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1520 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1521
1522 s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1523 s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1524 clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1525
1526 register_syscore_ops(&exynos5_clock_syscore_ops);
1527 s3c_pwmclk_init();
1528 }
Linux with added FPC-III support