arch/arm/mach-mxs/timer.c

   1 /*
   2  *  Copyright (C) 2000-2001 Deep Blue Solutions
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
   5  *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
   6  *  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA 02110-1301, USA.
  21  */
  22
  23 #include <linux/err.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/clockchips.h>
  27 #include <linux/clk.h>
  28
  29 #include <asm/mach/time.h>
  30 #include <mach/mxs.h>
  31 #include <mach/common.h>
  32
  33 /*
  34  * There are 2 versions of the timrot on Freescale MXS-based SoCs.
  35  * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
  36  * extends the counter to 32 bits.
  37  *
  38  * The implementation uses two timers, one for clock_event and
  39  * another for clocksource. MX28 uses timrot 0 and 1, while MX23
  40  * uses 0 and 2.
  41  */
  42
  43 #define MX23_TIMROT_VERSION_OFFSET      0x0a0
  44 #define MX28_TIMROT_VERSION_OFFSET      0x120
  45 #define BP_TIMROT_MAJOR_VERSION         24
  46 #define BV_TIMROT_VERSION_1             0x01
  47 #define BV_TIMROT_VERSION_2             0x02
  48 #define timrot_is_v1()  (timrot_major_version == BV_TIMROT_VERSION_1)
  49
  50 /*
  51  * There are 4 registers for each timrotv2 instance, and 2 registers
  52  * for each timrotv1. So address step 0x40 in macros below strides
  53  * one instance of timrotv2 while two instances of timrotv1.
  54  *
  55  * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
  56  * on MX28 while timrot2 on MX23.
  57  */
  58 /* common between v1 and v2 */
  59 #define HW_TIMROT_ROTCTRL               0x00
  60 #define HW_TIMROT_TIMCTRLn(n)           (0x20 + (n) * 0x40)
  61 /* v1 only */
  62 #define HW_TIMROT_TIMCOUNTn(n)          (0x30 + (n) * 0x40)
  63 /* v2 only */
  64 #define HW_TIMROT_RUNNING_COUNTn(n)     (0x30 + (n) * 0x40)
  65 #define HW_TIMROT_FIXED_COUNTn(n)       (0x40 + (n) * 0x40)
  66
  67 #define BM_TIMROT_TIMCTRLn_RELOAD       (1 << 6)
  68 #define BM_TIMROT_TIMCTRLn_UPDATE       (1 << 7)
  69 #define BM_TIMROT_TIMCTRLn_IRQ_EN       (1 << 14)
  70 #define BM_TIMROT_TIMCTRLn_IRQ          (1 << 15)
  71 #define BP_TIMROT_TIMCTRLn_SELECT       0
  72 #define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
  73 #define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
  74
  75 static struct clock_event_device mxs_clockevent_device;
  76 static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
  77
  78 static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
  79 static u32 timrot_major_version;
  80
  81 static inline void timrot_irq_disable(void)
  82 {
  83         __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
  84                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
  85 }
  86
  87 static inline void timrot_irq_enable(void)
  88 {
  89         __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
  90                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
  91 }
  92
  93 static void timrot_irq_acknowledge(void)
  94 {
  95         __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
  96                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
  97 }
  98
  99 static cycle_t timrotv1_get_cycles(struct clocksource *cs)
 100 {
 101         return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
 102                         & 0xffff0000) >> 16);
 103 }
 104
 105 static int timrotv1_set_next_event(unsigned long evt,
 106                                         struct clock_event_device *dev)
 107 {
 108         /* timrot decrements the count */
 109         __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
 110
 111         return 0;
 112 }
 113
 114 static int timrotv2_set_next_event(unsigned long evt,
 115                                         struct clock_event_device *dev)
 116 {
 117         /* timrot decrements the count */
 118         __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
 119
 120         return 0;
 121 }
 122
 123 static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
 124 {
 125         struct clock_event_device *evt = dev_id;
 126
 127         timrot_irq_acknowledge();
 128         evt->event_handler(evt);
 129
 130         return IRQ_HANDLED;
 131 }
 132
 133 static struct irqaction mxs_timer_irq = {
 134         .name           = "MXS Timer Tick",
 135         .dev_id         = &mxs_clockevent_device,
 136         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 137         .handler        = mxs_timer_interrupt,
 138 };
 139
 140 #ifdef DEBUG
 141 static const char *clock_event_mode_label[] const = {
 142         [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
 143         [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
 144         [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
 145         [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
 146 };
 147 #endif /* DEBUG */
 148
 149 static void mxs_set_mode(enum clock_event_mode mode,
 150                                 struct clock_event_device *evt)
 151 {
 152         /* Disable interrupt in timer module */
 153         timrot_irq_disable();
 154
 155         if (mode != mxs_clockevent_mode) {
 156                 /* Set event time into the furthest future */
 157                 if (timrot_is_v1())
 158                         __raw_writel(0xffff,
 159                                 mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
 160                 else
 161                         __raw_writel(0xffffffff,
 162                                 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
 163
 164                 /* Clear pending interrupt */
 165                 timrot_irq_acknowledge();
 166         }
 167
 168 #ifdef DEBUG
 169         pr_info("%s: changing mode from %s to %s\n", __func__,
 170                 clock_event_mode_label[mxs_clockevent_mode],
 171                 clock_event_mode_label[mode]);
 172 #endif /* DEBUG */
 173
 174         /* Remember timer mode */
 175         mxs_clockevent_mode = mode;
 176
 177         switch (mode) {
 178         case CLOCK_EVT_MODE_PERIODIC:
 179                 pr_err("%s: Periodic mode is not implemented\n", __func__);
 180                 break;
 181         case CLOCK_EVT_MODE_ONESHOT:
 182                 timrot_irq_enable();
 183                 break;
 184         case CLOCK_EVT_MODE_SHUTDOWN:
 185         case CLOCK_EVT_MODE_UNUSED:
 186         case CLOCK_EVT_MODE_RESUME:
 187                 /* Left event sources disabled, no more interrupts appear */
 188                 break;
 189         }
 190 }
 191
 192 static struct clock_event_device mxs_clockevent_device = {
 193         .name           = "mxs_timrot",
 194         .features       = CLOCK_EVT_FEAT_ONESHOT,
 195         .shift          = 32,
 196         .set_mode       = mxs_set_mode,
 197         .set_next_event = timrotv2_set_next_event,
 198         .rating         = 200,
 199 };
 200
 201 static int __init mxs_clockevent_init(struct clk *timer_clk)
 202 {
 203         unsigned int c = clk_get_rate(timer_clk);
 204
 205         mxs_clockevent_device.mult =
 206                 div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift);
 207         mxs_clockevent_device.cpumask = cpumask_of(0);
 208         if (timrot_is_v1()) {
 209                 mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
 210                 mxs_clockevent_device.max_delta_ns =
 211                         clockevent_delta2ns(0xfffe, &mxs_clockevent_device);
 212                 mxs_clockevent_device.min_delta_ns =
 213                         clockevent_delta2ns(0xf, &mxs_clockevent_device);
 214         } else {
 215                 mxs_clockevent_device.max_delta_ns =
 216                         clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device);
 217                 mxs_clockevent_device.min_delta_ns =
 218                         clockevent_delta2ns(0xf, &mxs_clockevent_device);
 219         }
 220
 221         clockevents_register_device(&mxs_clockevent_device);
 222
 223         return 0;
 224 }
 225
 226 static struct clocksource clocksource_mxs = {
 227         .name           = "mxs_timer",
 228         .rating         = 200,
 229         .read           = timrotv1_get_cycles,
 230         .mask           = CLOCKSOURCE_MASK(16),
 231         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 232 };
 233
 234 static int __init mxs_clocksource_init(struct clk *timer_clk)
 235 {
 236         unsigned int c = clk_get_rate(timer_clk);
 237
 238         if (timrot_is_v1())
 239                 clocksource_register_hz(&clocksource_mxs, c);
 240         else
 241                 clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
 242                         "mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
 243
 244         return 0;
 245 }
 246
 247 void __init mxs_timer_init(int irq)
 248 {
 249         struct clk *timer_clk;
 250
 251         timer_clk = clk_get_sys("timrot", NULL);
 252         if (IS_ERR(timer_clk)) {
 253                 pr_err("%s: failed to get clk\n", __func__);
 254                 return;
 255         }
 256
 257         clk_prepare_enable(timer_clk);
 258
 259         /*
 260          * Initialize timers to a known state
 261          */
 262         mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
 263
 264         /* get timrot version */
 265         timrot_major_version = __raw_readl(mxs_timrot_base +
 266                                 (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
 267                                                 MX28_TIMROT_VERSION_OFFSET));
 268         timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
 269
 270         /* one for clock_event */
 271         __raw_writel((timrot_is_v1() ?
 272                         BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
 273                         BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
 274                         BM_TIMROT_TIMCTRLn_UPDATE |
 275                         BM_TIMROT_TIMCTRLn_IRQ_EN,
 276                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
 277
 278         /* another for clocksource */
 279         __raw_writel((timrot_is_v1() ?
 280                         BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
 281                         BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
 282                         BM_TIMROT_TIMCTRLn_RELOAD,
 283                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
 284
 285         /* set clocksource timer fixed count to the maximum */
 286         if (timrot_is_v1())
 287                 __raw_writel(0xffff,
 288                         mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
 289         else
 290                 __raw_writel(0xffffffff,
 291                         mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
 292
 293         /* init and register the timer to the framework */
 294         mxs_clocksource_init(timer_clk);
 295         mxs_clockevent_init(timer_clk);
 296
 297         /* Make irqs happen */
 298         setup_irq(irq, &mxs_timer_irq);
 299 }