arch/arm/mach-shmobile/setup-sh7367.c

   1 /*
   2  * sh7367 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uio_driver.h>
  26 #include <linux/delay.h>
  27 #include <linux/input.h>
  28 #include <linux/io.h>
  29 #include <linux/serial_sci.h>
  30 #include <linux/sh_timer.h>
  31 #include <mach/hardware.h>
  32 #include <mach/common.h>
  33 #include <mach/irqs.h>
  34 #include <asm/mach-types.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/map.h>
  37 #include <asm/mach/time.h>
  38
  39 static struct map_desc sh7367_io_desc[] __initdata = {
  40         /* create a 1:1 entity map for 0xe6xxxxxx
  41          * used by CPGA, INTC and PFC.
  42          */
  43         {
  44                 .virtual        = 0xe6000000,
  45                 .pfn            = __phys_to_pfn(0xe6000000),
  46                 .length         = 256 << 20,
  47                 .type           = MT_DEVICE_NONSHARED
  48         },
  49 };
  50
  51 void __init sh7367_map_io(void)
  52 {
  53         iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc));
  54 }
  55
  56 /* SCIFA0 */
  57 static struct plat_sci_port scif0_platform_data = {
  58         .mapbase        = 0xe6c40000,
  59         .flags          = UPF_BOOT_AUTOCONF,
  60         .scscr          = SCSCR_RE | SCSCR_TE,
  61         .scbrr_algo_id  = SCBRR_ALGO_4,
  62         .type           = PORT_SCIFA,
  63         .irqs           = { evt2irq(0xc00), evt2irq(0xc00),
  64                             evt2irq(0xc00), evt2irq(0xc00) },
  65 };
  66
  67 static struct platform_device scif0_device = {
  68         .name           = "sh-sci",
  69         .id             = 0,
  70         .dev            = {
  71                 .platform_data  = &scif0_platform_data,
  72         },
  73 };
  74
  75 /* SCIFA1 */
  76 static struct plat_sci_port scif1_platform_data = {
  77         .mapbase        = 0xe6c50000,
  78         .flags          = UPF_BOOT_AUTOCONF,
  79         .scscr          = SCSCR_RE | SCSCR_TE,
  80         .scbrr_algo_id  = SCBRR_ALGO_4,
  81         .type           = PORT_SCIFA,
  82         .irqs           = { evt2irq(0xc20), evt2irq(0xc20),
  83                             evt2irq(0xc20), evt2irq(0xc20) },
  84 };
  85
  86 static struct platform_device scif1_device = {
  87         .name           = "sh-sci",
  88         .id             = 1,
  89         .dev            = {
  90                 .platform_data  = &scif1_platform_data,
  91         },
  92 };
  93
  94 /* SCIFA2 */
  95 static struct plat_sci_port scif2_platform_data = {
  96         .mapbase        = 0xe6c60000,
  97         .flags          = UPF_BOOT_AUTOCONF,
  98         .scscr          = SCSCR_RE | SCSCR_TE,
  99         .scbrr_algo_id  = SCBRR_ALGO_4,
 100         .type           = PORT_SCIFA,
 101         .irqs           = { evt2irq(0xc40), evt2irq(0xc40),
 102                             evt2irq(0xc40), evt2irq(0xc40) },
 103 };
 104
 105 static struct platform_device scif2_device = {
 106         .name           = "sh-sci",
 107         .id             = 2,
 108         .dev            = {
 109                 .platform_data  = &scif2_platform_data,
 110         },
 111 };
 112
 113 /* SCIFA3 */
 114 static struct plat_sci_port scif3_platform_data = {
 115         .mapbase        = 0xe6c70000,
 116         .flags          = UPF_BOOT_AUTOCONF,
 117         .scscr          = SCSCR_RE | SCSCR_TE,
 118         .scbrr_algo_id  = SCBRR_ALGO_4,
 119         .type           = PORT_SCIFA,
 120         .irqs           = { evt2irq(0xc60), evt2irq(0xc60),
 121                             evt2irq(0xc60), evt2irq(0xc60) },
 122 };
 123
 124 static struct platform_device scif3_device = {
 125         .name           = "sh-sci",
 126         .id             = 3,
 127         .dev            = {
 128                 .platform_data  = &scif3_platform_data,
 129         },
 130 };
 131
 132 /* SCIFA4 */
 133 static struct plat_sci_port scif4_platform_data = {
 134         .mapbase        = 0xe6c80000,
 135         .flags          = UPF_BOOT_AUTOCONF,
 136         .scscr          = SCSCR_RE | SCSCR_TE,
 137         .scbrr_algo_id  = SCBRR_ALGO_4,
 138         .type           = PORT_SCIFA,
 139         .irqs           = { evt2irq(0xd20), evt2irq(0xd20),
 140                             evt2irq(0xd20), evt2irq(0xd20) },
 141 };
 142
 143 static struct platform_device scif4_device = {
 144         .name           = "sh-sci",
 145         .id             = 4,
 146         .dev            = {
 147                 .platform_data  = &scif4_platform_data,
 148         },
 149 };
 150
 151 /* SCIFA5 */
 152 static struct plat_sci_port scif5_platform_data = {
 153         .mapbase        = 0xe6cb0000,
 154         .flags          = UPF_BOOT_AUTOCONF,
 155         .scscr          = SCSCR_RE | SCSCR_TE,
 156         .scbrr_algo_id  = SCBRR_ALGO_4,
 157         .type           = PORT_SCIFA,
 158         .irqs           = { evt2irq(0xd40), evt2irq(0xd40),
 159                             evt2irq(0xd40), evt2irq(0xd40) },
 160 };
 161
 162 static struct platform_device scif5_device = {
 163         .name           = "sh-sci",
 164         .id             = 5,
 165         .dev            = {
 166                 .platform_data  = &scif5_platform_data,
 167         },
 168 };
 169
 170 /* SCIFB */
 171 static struct plat_sci_port scif6_platform_data = {
 172         .mapbase        = 0xe6c30000,
 173         .flags          = UPF_BOOT_AUTOCONF,
 174         .scscr          = SCSCR_RE | SCSCR_TE,
 175         .scbrr_algo_id  = SCBRR_ALGO_4,
 176         .type           = PORT_SCIFB,
 177         .irqs           = { evt2irq(0xd60), evt2irq(0xd60),
 178                             evt2irq(0xd60), evt2irq(0xd60) },
 179 };
 180
 181 static struct platform_device scif6_device = {
 182         .name           = "sh-sci",
 183         .id             = 6,
 184         .dev            = {
 185                 .platform_data  = &scif6_platform_data,
 186         },
 187 };
 188
 189 static struct sh_timer_config cmt10_platform_data = {
 190         .name = "CMT10",
 191         .channel_offset = 0x10,
 192         .timer_bit = 0,
 193         .clockevent_rating = 125,
 194         .clocksource_rating = 125,
 195 };
 196
 197 static struct resource cmt10_resources[] = {
 198         [0] = {
 199                 .name   = "CMT10",
 200                 .start  = 0xe6138010,
 201                 .end    = 0xe613801b,
 202                 .flags  = IORESOURCE_MEM,
 203         },
 204         [1] = {
 205                 .start  = evt2irq(0xb00), /* CMT1_CMT10 */
 206                 .flags  = IORESOURCE_IRQ,
 207         },
 208 };
 209
 210 static struct platform_device cmt10_device = {
 211         .name           = "sh_cmt",
 212         .id             = 10,
 213         .dev = {
 214                 .platform_data  = &cmt10_platform_data,
 215         },
 216         .resource       = cmt10_resources,
 217         .num_resources  = ARRAY_SIZE(cmt10_resources),
 218 };
 219
 220 /* VPU */
 221 static struct uio_info vpu_platform_data = {
 222         .name = "VPU5",
 223         .version = "0",
 224         .irq = intcs_evt2irq(0x980),
 225 };
 226
 227 static struct resource vpu_resources[] = {
 228         [0] = {
 229                 .name   = "VPU",
 230                 .start  = 0xfe900000,
 231                 .end    = 0xfe902807,
 232                 .flags  = IORESOURCE_MEM,
 233         },
 234 };
 235
 236 static struct platform_device vpu_device = {
 237         .name           = "uio_pdrv_genirq",
 238         .id             = 0,
 239         .dev = {
 240                 .platform_data  = &vpu_platform_data,
 241         },
 242         .resource       = vpu_resources,
 243         .num_resources  = ARRAY_SIZE(vpu_resources),
 244 };
 245
 246 /* VEU0 */
 247 static struct uio_info veu0_platform_data = {
 248         .name = "VEU0",
 249         .version = "0",
 250         .irq = intcs_evt2irq(0x700),
 251 };
 252
 253 static struct resource veu0_resources[] = {
 254         [0] = {
 255                 .name   = "VEU0",
 256                 .start  = 0xfe920000,
 257                 .end    = 0xfe9200b7,
 258                 .flags  = IORESOURCE_MEM,
 259         },
 260 };
 261
 262 static struct platform_device veu0_device = {
 263         .name           = "uio_pdrv_genirq",
 264         .id             = 1,
 265         .dev = {
 266                 .platform_data  = &veu0_platform_data,
 267         },
 268         .resource       = veu0_resources,
 269         .num_resources  = ARRAY_SIZE(veu0_resources),
 270 };
 271
 272 /* VEU1 */
 273 static struct uio_info veu1_platform_data = {
 274         .name = "VEU1",
 275         .version = "0",
 276         .irq = intcs_evt2irq(0x720),
 277 };
 278
 279 static struct resource veu1_resources[] = {
 280         [0] = {
 281                 .name   = "VEU1",
 282                 .start  = 0xfe924000,
 283                 .end    = 0xfe9240b7,
 284                 .flags  = IORESOURCE_MEM,
 285         },
 286 };
 287
 288 static struct platform_device veu1_device = {
 289         .name           = "uio_pdrv_genirq",
 290         .id             = 2,
 291         .dev = {
 292                 .platform_data  = &veu1_platform_data,
 293         },
 294         .resource       = veu1_resources,
 295         .num_resources  = ARRAY_SIZE(veu1_resources),
 296 };
 297
 298 /* VEU2 */
 299 static struct uio_info veu2_platform_data = {
 300         .name = "VEU2",
 301         .version = "0",
 302         .irq = intcs_evt2irq(0x740),
 303 };
 304
 305 static struct resource veu2_resources[] = {
 306         [0] = {
 307                 .name   = "VEU2",
 308                 .start  = 0xfe928000,
 309                 .end    = 0xfe9280b7,
 310                 .flags  = IORESOURCE_MEM,
 311         },
 312 };
 313
 314 static struct platform_device veu2_device = {
 315         .name           = "uio_pdrv_genirq",
 316         .id             = 3,
 317         .dev = {
 318                 .platform_data  = &veu2_platform_data,
 319         },
 320         .resource       = veu2_resources,
 321         .num_resources  = ARRAY_SIZE(veu2_resources),
 322 };
 323
 324 /* VEU3 */
 325 static struct uio_info veu3_platform_data = {
 326         .name = "VEU3",
 327         .version = "0",
 328         .irq = intcs_evt2irq(0x760),
 329 };
 330
 331 static struct resource veu3_resources[] = {
 332         [0] = {
 333                 .name   = "VEU3",
 334                 .start  = 0xfe92c000,
 335                 .end    = 0xfe92c0b7,
 336                 .flags  = IORESOURCE_MEM,
 337         },
 338 };
 339
 340 static struct platform_device veu3_device = {
 341         .name           = "uio_pdrv_genirq",
 342         .id             = 4,
 343         .dev = {
 344                 .platform_data  = &veu3_platform_data,
 345         },
 346         .resource       = veu3_resources,
 347         .num_resources  = ARRAY_SIZE(veu3_resources),
 348 };
 349
 350 /* VEU2H */
 351 static struct uio_info veu2h_platform_data = {
 352         .name = "VEU2H",
 353         .version = "0",
 354         .irq = intcs_evt2irq(0x520),
 355 };
 356
 357 static struct resource veu2h_resources[] = {
 358         [0] = {
 359                 .name   = "VEU2H",
 360                 .start  = 0xfe93c000,
 361                 .end    = 0xfe93c27b,
 362                 .flags  = IORESOURCE_MEM,
 363         },
 364 };
 365
 366 static struct platform_device veu2h_device = {
 367         .name           = "uio_pdrv_genirq",
 368         .id             = 5,
 369         .dev = {
 370                 .platform_data  = &veu2h_platform_data,
 371         },
 372         .resource       = veu2h_resources,
 373         .num_resources  = ARRAY_SIZE(veu2h_resources),
 374 };
 375
 376 /* JPU */
 377 static struct uio_info jpu_platform_data = {
 378         .name = "JPU",
 379         .version = "0",
 380         .irq = intcs_evt2irq(0x560),
 381 };
 382
 383 static struct resource jpu_resources[] = {
 384         [0] = {
 385                 .name   = "JPU",
 386                 .start  = 0xfe980000,
 387                 .end    = 0xfe9902d3,
 388                 .flags  = IORESOURCE_MEM,
 389         },
 390 };
 391
 392 static struct platform_device jpu_device = {
 393         .name           = "uio_pdrv_genirq",
 394         .id             = 6,
 395         .dev = {
 396                 .platform_data  = &jpu_platform_data,
 397         },
 398         .resource       = jpu_resources,
 399         .num_resources  = ARRAY_SIZE(jpu_resources),
 400 };
 401
 402 /* SPU1 */
 403 static struct uio_info spu1_platform_data = {
 404         .name = "SPU1",
 405         .version = "0",
 406         .irq = evt2irq(0xfc0),
 407 };
 408
 409 static struct resource spu1_resources[] = {
 410         [0] = {
 411                 .name   = "SPU1",
 412                 .start  = 0xfe300000,
 413                 .end    = 0xfe3fffff,
 414                 .flags  = IORESOURCE_MEM,
 415         },
 416 };
 417
 418 static struct platform_device spu1_device = {
 419         .name           = "uio_pdrv_genirq",
 420         .id             = 7,
 421         .dev = {
 422                 .platform_data  = &spu1_platform_data,
 423         },
 424         .resource       = spu1_resources,
 425         .num_resources  = ARRAY_SIZE(spu1_resources),
 426 };
 427
 428 static struct platform_device *sh7367_early_devices[] __initdata = {
 429         &scif0_device,
 430         &scif1_device,
 431         &scif2_device,
 432         &scif3_device,
 433         &scif4_device,
 434         &scif5_device,
 435         &scif6_device,
 436         &cmt10_device,
 437 };
 438
 439 static struct platform_device *sh7367_devices[] __initdata = {
 440         &vpu_device,
 441         &veu0_device,
 442         &veu1_device,
 443         &veu2_device,
 444         &veu3_device,
 445         &veu2h_device,
 446         &jpu_device,
 447         &spu1_device,
 448 };
 449
 450 void __init sh7367_add_standard_devices(void)
 451 {
 452         platform_add_devices(sh7367_early_devices,
 453                              ARRAY_SIZE(sh7367_early_devices));
 454
 455         platform_add_devices(sh7367_devices,
 456                             ARRAY_SIZE(sh7367_devices));
 457 }
 458
 459 static void __init sh7367_earlytimer_init(void)
 460 {
 461         sh7367_clock_init();
 462         shmobile_earlytimer_init();
 463 }
 464
 465 #define SYMSTPCR2 0xe6158048
 466 #define SYMSTPCR2_CMT1 (1 << 29)
 467
 468 void __init sh7367_add_early_devices(void)
 469 {
 470         /* enable clock to CMT1 */
 471         __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
 472
 473         early_platform_add_devices(sh7367_early_devices,
 474                                    ARRAY_SIZE(sh7367_early_devices));
 475
 476         /* setup early console here as well */
 477         shmobile_setup_console();
 478
 479         /* override timer setup with soc-specific code */
 480         shmobile_timer.init = sh7367_earlytimer_init;
 481 }