arch/arm/plat-omap/counter_32k.c

   1 /*
   2  * OMAP 32ksynctimer/counter_32k-related code
   3  *
   4  * Copyright (C) 2009 Texas Instruments
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Tony Lindgren <tony@atomide.com>
   7  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20 #include <linux/clocksource.h>
  21
  22 #include <asm/mach/time.h>
  23 #include <asm/sched_clock.h>
  24
  25 #include <plat/hardware.h>
  26 #include <plat/common.h>
  27 #include <plat/board.h>
  28
  29 #include <plat/clock.h>
  30
  31 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
  32 #define OMAP2_32KSYNCNT_REV_OFF         0x0
  33 #define OMAP2_32KSYNCNT_REV_SCHEME      (0x3 << 30)
  34 #define OMAP2_32KSYNCNT_CR_OFF_LOW      0x10
  35 #define OMAP2_32KSYNCNT_CR_OFF_HIGH     0x30
  36
  37 /*
  38  * 32KHz clocksource ... always available, on pretty most chips except
  39  * OMAP 730 and 1510.  Other timers could be used as clocksources, with
  40  * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
  41  * but systems won't necessarily want to spend resources that way.
  42  */
  43 static void __iomem *sync32k_cnt_reg;
  44
  45 static u32 notrace omap_32k_read_sched_clock(void)
  46 {
  47         return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
  48 }
  49
  50 /**
  51  * omap_read_persistent_clock -  Return time from a persistent clock.
  52  *
  53  * Reads the time from a source which isn't disabled during PM, the
  54  * 32k sync timer.  Convert the cycles elapsed since last read into
  55  * nsecs and adds to a monotonically increasing timespec.
  56  */
  57 static struct timespec persistent_ts;
  58 static cycles_t cycles, last_cycles;
  59 static unsigned int persistent_mult, persistent_shift;
  60 static void omap_read_persistent_clock(struct timespec *ts)
  61 {
  62         unsigned long long nsecs;
  63         cycles_t delta;
  64         struct timespec *tsp = &persistent_ts;
  65
  66         last_cycles = cycles;
  67         cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
  68         delta = cycles - last_cycles;
  69
  70         nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift);
  71
  72         timespec_add_ns(tsp, nsecs);
  73         *ts = *tsp;
  74 }
  75
  76 /**
  77  * omap_init_clocksource_32k - setup and register counter 32k as a
  78  * kernel clocksource
  79  * @pbase: base addr of counter_32k module
  80  * @size: size of counter_32k to map
  81  *
  82  * Returns 0 upon success or negative error code upon failure.
  83  *
  84  */
  85 int __init omap_init_clocksource_32k(void __iomem *vbase)
  86 {
  87         int ret;
  88
  89         /*
  90          * 32k sync Counter IP register offsets vary between the
  91          * highlander version and the legacy ones.
  92          * The 'SCHEME' bits(30-31) of the revision register is used
  93          * to identify the version.
  94          */
  95         if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
  96                                                 OMAP2_32KSYNCNT_REV_SCHEME)
  97                 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
  98         else
  99                 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
 100
 101         /*
 102          * 120000 rough estimate from the calculations in
 103          * __clocksource_updatefreq_scale.
 104          */
 105         clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
 106                         32768, NSEC_PER_SEC, 120000);
 107
 108         ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
 109                                 250, 32, clocksource_mmio_readl_up);
 110         if (ret) {
 111                 pr_err("32k_counter: can't register clocksource\n");
 112                 return ret;
 113         }
 114
 115         setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
 116         register_persistent_clock(NULL, omap_read_persistent_clock);
 117         pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
 118
 119         return 0;
 120 }