arch/arm/plat-spear/time.c

   1 /*
   2  * arch/arm/plat-spear/time.c
   3  *
   4  * Copyright (C) 2010 ST Microelectronics
   5  * Shiraz Hashim<shiraz.hashim@st.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clockchips.h>
  14 #include <linux/clocksource.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/ioport.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_address.h>
  23 #include <linux/time.h>
  24 #include <linux/irq.h>
  25 #include <asm/mach/time.h>
  26 #include <mach/generic.h>
  27
  28 /*
  29  * We would use TIMER0 and TIMER1 as clockevent and clocksource.
  30  * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
  31  * they share same functional clock. Any change in one's functional clock will
  32  * also affect other timer.
  33  */
  34
  35 #define CLKEVT  0       /* gpt0, channel0 as clockevent */
  36 #define CLKSRC  1       /* gpt0, channel1 as clocksource */
  37
  38 /* Register offsets, x is channel number */
  39 #define CR(x)           ((x) * 0x80 + 0x80)
  40 #define IR(x)           ((x) * 0x80 + 0x84)
  41 #define LOAD(x)         ((x) * 0x80 + 0x88)
  42 #define COUNT(x)        ((x) * 0x80 + 0x8C)
  43
  44 /* Reg bit definitions */
  45 #define CTRL_INT_ENABLE         0x0100
  46 #define CTRL_ENABLE             0x0020
  47 #define CTRL_ONE_SHOT           0x0010
  48
  49 #define CTRL_PRESCALER1         0x0
  50 #define CTRL_PRESCALER2         0x1
  51 #define CTRL_PRESCALER4         0x2
  52 #define CTRL_PRESCALER8         0x3
  53 #define CTRL_PRESCALER16        0x4
  54 #define CTRL_PRESCALER32        0x5
  55 #define CTRL_PRESCALER64        0x6
  56 #define CTRL_PRESCALER128       0x7
  57 #define CTRL_PRESCALER256       0x8
  58
  59 #define INT_STATUS              0x1
  60
  61 /*
  62  * Minimum clocksource/clockevent timer range in seconds
  63  */
  64 #define SPEAR_MIN_RANGE 4
  65
  66 static __iomem void *gpt_base;
  67 static struct clk *gpt_clk;
  68
  69 static void clockevent_set_mode(enum clock_event_mode mode,
  70                                 struct clock_event_device *clk_event_dev);
  71 static int clockevent_next_event(unsigned long evt,
  72                                  struct clock_event_device *clk_event_dev);
  73
  74 static void spear_clocksource_init(void)
  75 {
  76         u32 tick_rate;
  77         u16 val;
  78
  79         /* program the prescaler (/256)*/
  80         writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
  81
  82         /* find out actual clock driving Timer */
  83         tick_rate = clk_get_rate(gpt_clk);
  84         tick_rate >>= CTRL_PRESCALER256;
  85
  86         writew(0xFFFF, gpt_base + LOAD(CLKSRC));
  87
  88         val = readw(gpt_base + CR(CLKSRC));
  89         val &= ~CTRL_ONE_SHOT;  /* autoreload mode */
  90         val |= CTRL_ENABLE ;
  91         writew(val, gpt_base + CR(CLKSRC));
  92
  93         /* register the clocksource */
  94         clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
  95                 200, 16, clocksource_mmio_readw_up);
  96 }
  97
  98 static struct clock_event_device clkevt = {
  99         .name = "tmr0",
 100         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 101         .set_mode = clockevent_set_mode,
 102         .set_next_event = clockevent_next_event,
 103         .shift = 0,     /* to be computed */
 104 };
 105
 106 static void clockevent_set_mode(enum clock_event_mode mode,
 107                                 struct clock_event_device *clk_event_dev)
 108 {
 109         u32 period;
 110         u16 val;
 111
 112         /* stop the timer */
 113         val = readw(gpt_base + CR(CLKEVT));
 114         val &= ~CTRL_ENABLE;
 115         writew(val, gpt_base + CR(CLKEVT));
 116
 117         switch (mode) {
 118         case CLOCK_EVT_MODE_PERIODIC:
 119                 period = clk_get_rate(gpt_clk) / HZ;
 120                 period >>= CTRL_PRESCALER16;
 121                 writew(period, gpt_base + LOAD(CLKEVT));
 122
 123                 val = readw(gpt_base + CR(CLKEVT));
 124                 val &= ~CTRL_ONE_SHOT;
 125                 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
 126                 writew(val, gpt_base + CR(CLKEVT));
 127
 128                 break;
 129         case CLOCK_EVT_MODE_ONESHOT:
 130                 val = readw(gpt_base + CR(CLKEVT));
 131                 val |= CTRL_ONE_SHOT;
 132                 writew(val, gpt_base + CR(CLKEVT));
 133
 134                 break;
 135         case CLOCK_EVT_MODE_UNUSED:
 136         case CLOCK_EVT_MODE_SHUTDOWN:
 137         case CLOCK_EVT_MODE_RESUME:
 138
 139                 break;
 140         default:
 141                 pr_err("Invalid mode requested\n");
 142                 break;
 143         }
 144 }
 145
 146 static int clockevent_next_event(unsigned long cycles,
 147                                  struct clock_event_device *clk_event_dev)
 148 {
 149         u16 val = readw(gpt_base + CR(CLKEVT));
 150
 151         if (val & CTRL_ENABLE)
 152                 writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
 153
 154         writew(cycles, gpt_base + LOAD(CLKEVT));
 155
 156         val |= CTRL_ENABLE | CTRL_INT_ENABLE;
 157         writew(val, gpt_base + CR(CLKEVT));
 158
 159         return 0;
 160 }
 161
 162 static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
 163 {
 164         struct clock_event_device *evt = &clkevt;
 165
 166         writew(INT_STATUS, gpt_base + IR(CLKEVT));
 167
 168         evt->event_handler(evt);
 169
 170         return IRQ_HANDLED;
 171 }
 172
 173 static struct irqaction spear_timer_irq = {
 174         .name = "timer",
 175         .flags = IRQF_DISABLED | IRQF_TIMER,
 176         .handler = spear_timer_interrupt
 177 };
 178
 179 static void __init spear_clockevent_init(int irq)
 180 {
 181         u32 tick_rate;
 182
 183         /* program the prescaler */
 184         writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
 185
 186         tick_rate = clk_get_rate(gpt_clk);
 187         tick_rate >>= CTRL_PRESCALER16;
 188
 189         clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE);
 190
 191         clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
 192                         &clkevt);
 193         clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt);
 194
 195         clkevt.cpumask = cpumask_of(0);
 196
 197         clockevents_register_device(&clkevt);
 198
 199         setup_irq(irq, &spear_timer_irq);
 200 }
 201
 202 const static struct of_device_id timer_of_match[] __initconst = {
 203         { .compatible = "st,spear-timer", },
 204         { },
 205 };
 206
 207 void __init spear_setup_of_timer(void)
 208 {
 209         struct device_node *np;
 210         int irq, ret;
 211
 212         np = of_find_matching_node(NULL, timer_of_match);
 213         if (!np) {
 214                 pr_err("%s: No timer passed via DT\n", __func__);
 215                 return;
 216         }
 217
 218         irq = irq_of_parse_and_map(np, 0);
 219         if (!irq) {
 220                 pr_err("%s: No irq passed for timer via DT\n", __func__);
 221                 return;
 222         }
 223
 224         gpt_base = of_iomap(np, 0);
 225         if (!gpt_base) {
 226                 pr_err("%s: of iomap failed\n", __func__);
 227                 return;
 228         }
 229
 230         gpt_clk = clk_get_sys("gpt0", NULL);
 231         if (!gpt_clk) {
 232                 pr_err("%s:couldn't get clk for gpt\n", __func__);
 233                 goto err_iomap;
 234         }
 235
 236         ret = clk_prepare_enable(gpt_clk);
 237         if (ret < 0) {
 238                 pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
 239                 goto err_prepare_enable_clk;
 240         }
 241
 242         spear_clockevent_init(irq);
 243         spear_clocksource_init();
 244
 245         return;
 246
 247 err_prepare_enable_clk:
 248         clk_put(gpt_clk);
 249 err_iomap:
 250         iounmap(gpt_base);
 251 }