2 * Intel GTT (Graphics Translation Table) routines
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
15 * /fairy-tale-mode off
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <linux/delay.h>
27 #include "intel-agp.h"
28 #include <drm/intel-gtt.h>
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
34 * Only newer chipsets need to bother with this, of course.
36 #ifdef CONFIG_INTEL_IOMMU
37 #define USE_PCI_DMA_API 1
39 #define USE_PCI_DMA_API 0
42 struct intel_gtt_driver
{
44 unsigned int is_g33
: 1;
45 unsigned int is_pineview
: 1;
46 unsigned int is_ironlake
: 1;
47 unsigned int has_pgtbl_enable
: 1;
48 unsigned int dma_mask_size
: 8;
49 /* Chipset specific GTT setup */
51 /* This should undo anything done in ->setup() save the unmapping
52 * of the mmio register file, that's done in the generic code. */
53 void (*cleanup
)(void);
54 void (*write_entry
)(dma_addr_t addr
, unsigned int entry
, unsigned int flags
);
55 /* Flags is a more or less chipset specific opaque value.
56 * For chipsets that need to support old ums (non-gem) code, this
57 * needs to be identical to the various supported agp memory types! */
58 bool (*check_flags
)(unsigned int flags
);
59 void (*chipset_flush
)(void);
62 static struct _intel_private
{
63 struct intel_gtt base
;
64 const struct intel_gtt_driver
*driver
;
65 struct pci_dev
*pcidev
; /* device one */
66 struct pci_dev
*bridge_dev
;
67 u8 __iomem
*registers
;
68 phys_addr_t gtt_bus_addr
;
70 u32 __iomem
*gtt
; /* I915G */
71 bool clear_fake_agp
; /* on first access via agp, fill with scratch */
72 int num_dcache_entries
;
73 void __iomem
*i9xx_flush_page
;
75 struct resource ifp_resource
;
77 struct page
*scratch_page
;
81 #define INTEL_GTT_GEN intel_private.driver->gen
82 #define IS_G33 intel_private.driver->is_g33
83 #define IS_PINEVIEW intel_private.driver->is_pineview
84 #define IS_IRONLAKE intel_private.driver->is_ironlake
85 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
87 int intel_gtt_map_memory(struct page
**pages
, unsigned int num_entries
,
88 struct scatterlist
**sg_list
, int *num_sg
)
91 struct scatterlist
*sg
;
95 return 0; /* already mapped (for e.g. resume */
97 DBG("try mapping %lu pages\n", (unsigned long)num_entries
);
99 if (sg_alloc_table(&st
, num_entries
, GFP_KERNEL
))
102 *sg_list
= sg
= st
.sgl
;
104 for (i
= 0 ; i
< num_entries
; i
++, sg
= sg_next(sg
))
105 sg_set_page(sg
, pages
[i
], PAGE_SIZE
, 0);
107 *num_sg
= pci_map_sg(intel_private
.pcidev
, *sg_list
,
108 num_entries
, PCI_DMA_BIDIRECTIONAL
);
109 if (unlikely(!*num_sg
))
118 EXPORT_SYMBOL(intel_gtt_map_memory
);
120 void intel_gtt_unmap_memory(struct scatterlist
*sg_list
, int num_sg
)
123 DBG("try unmapping %lu pages\n", (unsigned long)mem
->page_count
);
125 pci_unmap_sg(intel_private
.pcidev
, sg_list
,
126 num_sg
, PCI_DMA_BIDIRECTIONAL
);
129 st
.orig_nents
= st
.nents
= num_sg
;
133 EXPORT_SYMBOL(intel_gtt_unmap_memory
);
135 static void intel_fake_agp_enable(struct agp_bridge_data
*bridge
, u32 mode
)
140 /* Exists to support ARGB cursors */
141 static struct page
*i8xx_alloc_pages(void)
145 page
= alloc_pages(GFP_KERNEL
| GFP_DMA32
, 2);
149 if (set_pages_uc(page
, 4) < 0) {
150 set_pages_wb(page
, 4);
151 __free_pages(page
, 2);
155 atomic_inc(&agp_bridge
->current_memory_agp
);
159 static void i8xx_destroy_pages(struct page
*page
)
164 set_pages_wb(page
, 4);
166 __free_pages(page
, 2);
167 atomic_dec(&agp_bridge
->current_memory_agp
);
170 #define I810_GTT_ORDER 4
171 static int i810_setup(void)
176 /* i81x does not preallocate the gtt. It's always 64kb in size. */
177 gtt_table
= alloc_gatt_pages(I810_GTT_ORDER
);
178 if (gtt_table
== NULL
)
180 intel_private
.i81x_gtt_table
= gtt_table
;
182 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, ®_addr
);
183 reg_addr
&= 0xfff80000;
185 intel_private
.registers
= ioremap(reg_addr
, KB(64));
186 if (!intel_private
.registers
)
189 writel(virt_to_phys(gtt_table
) | I810_PGETBL_ENABLED
,
190 intel_private
.registers
+I810_PGETBL_CTL
);
192 intel_private
.gtt_bus_addr
= reg_addr
+ I810_PTE_BASE
;
194 if ((readl(intel_private
.registers
+I810_DRAM_CTL
)
195 & I810_DRAM_ROW_0
) == I810_DRAM_ROW_0_SDRAM
) {
196 dev_info(&intel_private
.pcidev
->dev
,
197 "detected 4MB dedicated video ram\n");
198 intel_private
.num_dcache_entries
= 1024;
204 static void i810_cleanup(void)
206 writel(0, intel_private
.registers
+I810_PGETBL_CTL
);
207 free_gatt_pages(intel_private
.i81x_gtt_table
, I810_GTT_ORDER
);
210 static int i810_insert_dcache_entries(struct agp_memory
*mem
, off_t pg_start
,
215 if ((pg_start
+ mem
->page_count
)
216 > intel_private
.num_dcache_entries
)
219 if (!mem
->is_flushed
)
220 global_cache_flush();
222 for (i
= pg_start
; i
< (pg_start
+ mem
->page_count
); i
++) {
223 dma_addr_t addr
= i
<< PAGE_SHIFT
;
224 intel_private
.driver
->write_entry(addr
,
227 readl(intel_private
.gtt
+i
-1);
233 * The i810/i830 requires a physical address to program its mouse
234 * pointer into hardware.
235 * However the Xserver still writes to it through the agp aperture.
237 static struct agp_memory
*alloc_agpphysmem_i8xx(size_t pg_count
, int type
)
239 struct agp_memory
*new;
243 case 1: page
= agp_bridge
->driver
->agp_alloc_page(agp_bridge
);
246 /* kludge to get 4 physical pages for ARGB cursor */
247 page
= i8xx_alloc_pages();
256 new = agp_create_memory(pg_count
);
260 new->pages
[0] = page
;
262 /* kludge to get 4 physical pages for ARGB cursor */
263 new->pages
[1] = new->pages
[0] + 1;
264 new->pages
[2] = new->pages
[1] + 1;
265 new->pages
[3] = new->pages
[2] + 1;
267 new->page_count
= pg_count
;
268 new->num_scratch_pages
= pg_count
;
269 new->type
= AGP_PHYS_MEMORY
;
270 new->physical
= page_to_phys(new->pages
[0]);
274 static void intel_i810_free_by_type(struct agp_memory
*curr
)
276 agp_free_key(curr
->key
);
277 if (curr
->type
== AGP_PHYS_MEMORY
) {
278 if (curr
->page_count
== 4)
279 i8xx_destroy_pages(curr
->pages
[0]);
281 agp_bridge
->driver
->agp_destroy_page(curr
->pages
[0],
282 AGP_PAGE_DESTROY_UNMAP
);
283 agp_bridge
->driver
->agp_destroy_page(curr
->pages
[0],
284 AGP_PAGE_DESTROY_FREE
);
286 agp_free_page_array(curr
);
291 static int intel_gtt_setup_scratch_page(void)
296 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
300 set_pages_uc(page
, 1);
302 if (intel_private
.base
.needs_dmar
) {
303 dma_addr
= pci_map_page(intel_private
.pcidev
, page
, 0,
304 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
305 if (pci_dma_mapping_error(intel_private
.pcidev
, dma_addr
))
308 intel_private
.base
.scratch_page_dma
= dma_addr
;
310 intel_private
.base
.scratch_page_dma
= page_to_phys(page
);
312 intel_private
.scratch_page
= page
;
317 static void i810_write_entry(dma_addr_t addr
, unsigned int entry
,
320 u32 pte_flags
= I810_PTE_VALID
;
323 case AGP_DCACHE_MEMORY
:
324 pte_flags
|= I810_PTE_LOCAL
;
326 case AGP_USER_CACHED_MEMORY
:
327 pte_flags
|= I830_PTE_SYSTEM_CACHED
;
331 writel(addr
| pte_flags
, intel_private
.gtt
+ entry
);
334 static const struct aper_size_info_fixed intel_fake_agp_sizes
[] = {
342 static unsigned int intel_gtt_stolen_size(void)
347 static const int ddt
[4] = { 0, 16, 32, 64 };
348 unsigned int stolen_size
= 0;
350 if (INTEL_GTT_GEN
== 1)
351 return 0; /* no stolen mem on i81x */
353 pci_read_config_word(intel_private
.bridge_dev
,
354 I830_GMCH_CTRL
, &gmch_ctrl
);
356 if (intel_private
.bridge_dev
->device
== PCI_DEVICE_ID_INTEL_82830_HB
||
357 intel_private
.bridge_dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
) {
358 switch (gmch_ctrl
& I830_GMCH_GMS_MASK
) {
359 case I830_GMCH_GMS_STOLEN_512
:
360 stolen_size
= KB(512);
362 case I830_GMCH_GMS_STOLEN_1024
:
365 case I830_GMCH_GMS_STOLEN_8192
:
368 case I830_GMCH_GMS_LOCAL
:
369 rdct
= readb(intel_private
.registers
+I830_RDRAM_CHANNEL_TYPE
);
370 stolen_size
= (I830_RDRAM_ND(rdct
) + 1) *
371 MB(ddt
[I830_RDRAM_DDT(rdct
)]);
378 } else if (INTEL_GTT_GEN
== 6) {
380 * SandyBridge has new memory control reg at 0x50.w
383 pci_read_config_word(intel_private
.pcidev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
384 switch (snb_gmch_ctl
& SNB_GMCH_GMS_STOLEN_MASK
) {
385 case SNB_GMCH_GMS_STOLEN_32M
:
386 stolen_size
= MB(32);
388 case SNB_GMCH_GMS_STOLEN_64M
:
389 stolen_size
= MB(64);
391 case SNB_GMCH_GMS_STOLEN_96M
:
392 stolen_size
= MB(96);
394 case SNB_GMCH_GMS_STOLEN_128M
:
395 stolen_size
= MB(128);
397 case SNB_GMCH_GMS_STOLEN_160M
:
398 stolen_size
= MB(160);
400 case SNB_GMCH_GMS_STOLEN_192M
:
401 stolen_size
= MB(192);
403 case SNB_GMCH_GMS_STOLEN_224M
:
404 stolen_size
= MB(224);
406 case SNB_GMCH_GMS_STOLEN_256M
:
407 stolen_size
= MB(256);
409 case SNB_GMCH_GMS_STOLEN_288M
:
410 stolen_size
= MB(288);
412 case SNB_GMCH_GMS_STOLEN_320M
:
413 stolen_size
= MB(320);
415 case SNB_GMCH_GMS_STOLEN_352M
:
416 stolen_size
= MB(352);
418 case SNB_GMCH_GMS_STOLEN_384M
:
419 stolen_size
= MB(384);
421 case SNB_GMCH_GMS_STOLEN_416M
:
422 stolen_size
= MB(416);
424 case SNB_GMCH_GMS_STOLEN_448M
:
425 stolen_size
= MB(448);
427 case SNB_GMCH_GMS_STOLEN_480M
:
428 stolen_size
= MB(480);
430 case SNB_GMCH_GMS_STOLEN_512M
:
431 stolen_size
= MB(512);
435 switch (gmch_ctrl
& I855_GMCH_GMS_MASK
) {
436 case I855_GMCH_GMS_STOLEN_1M
:
439 case I855_GMCH_GMS_STOLEN_4M
:
442 case I855_GMCH_GMS_STOLEN_8M
:
445 case I855_GMCH_GMS_STOLEN_16M
:
446 stolen_size
= MB(16);
448 case I855_GMCH_GMS_STOLEN_32M
:
449 stolen_size
= MB(32);
451 case I915_GMCH_GMS_STOLEN_48M
:
452 stolen_size
= MB(48);
454 case I915_GMCH_GMS_STOLEN_64M
:
455 stolen_size
= MB(64);
457 case G33_GMCH_GMS_STOLEN_128M
:
458 stolen_size
= MB(128);
460 case G33_GMCH_GMS_STOLEN_256M
:
461 stolen_size
= MB(256);
463 case INTEL_GMCH_GMS_STOLEN_96M
:
464 stolen_size
= MB(96);
466 case INTEL_GMCH_GMS_STOLEN_160M
:
467 stolen_size
= MB(160);
469 case INTEL_GMCH_GMS_STOLEN_224M
:
470 stolen_size
= MB(224);
472 case INTEL_GMCH_GMS_STOLEN_352M
:
473 stolen_size
= MB(352);
481 if (stolen_size
> 0) {
482 dev_info(&intel_private
.bridge_dev
->dev
, "detected %dK %s memory\n",
483 stolen_size
/ KB(1), local
? "local" : "stolen");
485 dev_info(&intel_private
.bridge_dev
->dev
,
486 "no pre-allocated video memory detected\n");
493 static void i965_adjust_pgetbl_size(unsigned int size_flag
)
495 u32 pgetbl_ctl
, pgetbl_ctl2
;
497 /* ensure that ppgtt is disabled */
498 pgetbl_ctl2
= readl(intel_private
.registers
+I965_PGETBL_CTL2
);
499 pgetbl_ctl2
&= ~I810_PGETBL_ENABLED
;
500 writel(pgetbl_ctl2
, intel_private
.registers
+I965_PGETBL_CTL2
);
502 /* write the new ggtt size */
503 pgetbl_ctl
= readl(intel_private
.registers
+I810_PGETBL_CTL
);
504 pgetbl_ctl
&= ~I965_PGETBL_SIZE_MASK
;
505 pgetbl_ctl
|= size_flag
;
506 writel(pgetbl_ctl
, intel_private
.registers
+I810_PGETBL_CTL
);
509 static unsigned int i965_gtt_total_entries(void)
515 pci_read_config_word(intel_private
.bridge_dev
,
516 I830_GMCH_CTRL
, &gmch_ctl
);
518 if (INTEL_GTT_GEN
== 5) {
519 switch (gmch_ctl
& G4x_GMCH_SIZE_MASK
) {
520 case G4x_GMCH_SIZE_1M
:
521 case G4x_GMCH_SIZE_VT_1M
:
522 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB
);
524 case G4x_GMCH_SIZE_VT_1_5M
:
525 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB
);
527 case G4x_GMCH_SIZE_2M
:
528 case G4x_GMCH_SIZE_VT_2M
:
529 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB
);
534 pgetbl_ctl
= readl(intel_private
.registers
+I810_PGETBL_CTL
);
536 switch (pgetbl_ctl
& I965_PGETBL_SIZE_MASK
) {
537 case I965_PGETBL_SIZE_128KB
:
540 case I965_PGETBL_SIZE_256KB
:
543 case I965_PGETBL_SIZE_512KB
:
546 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
547 case I965_PGETBL_SIZE_1MB
:
550 case I965_PGETBL_SIZE_2MB
:
553 case I965_PGETBL_SIZE_1_5MB
:
554 size
= KB(1024 + 512);
557 dev_info(&intel_private
.pcidev
->dev
,
558 "unknown page table size, assuming 512KB\n");
565 static unsigned int intel_gtt_total_entries(void)
569 if (IS_G33
|| INTEL_GTT_GEN
== 4 || INTEL_GTT_GEN
== 5)
570 return i965_gtt_total_entries();
571 else if (INTEL_GTT_GEN
== 6) {
574 pci_read_config_word(intel_private
.pcidev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
575 switch (snb_gmch_ctl
& SNB_GTT_SIZE_MASK
) {
577 case SNB_GTT_SIZE_0M
:
578 printk(KERN_ERR
"Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl
);
581 case SNB_GTT_SIZE_1M
:
584 case SNB_GTT_SIZE_2M
:
590 /* On previous hardware, the GTT size was just what was
591 * required to map the aperture.
593 return intel_private
.base
.gtt_mappable_entries
;
597 static unsigned int intel_gtt_mappable_entries(void)
599 unsigned int aperture_size
;
601 if (INTEL_GTT_GEN
== 1) {
604 pci_read_config_dword(intel_private
.bridge_dev
,
605 I810_SMRAM_MISCC
, &smram_miscc
);
607 if ((smram_miscc
& I810_GFX_MEM_WIN_SIZE
)
608 == I810_GFX_MEM_WIN_32M
)
609 aperture_size
= MB(32);
611 aperture_size
= MB(64);
612 } else if (INTEL_GTT_GEN
== 2) {
615 pci_read_config_word(intel_private
.bridge_dev
,
616 I830_GMCH_CTRL
, &gmch_ctrl
);
618 if ((gmch_ctrl
& I830_GMCH_MEM_MASK
) == I830_GMCH_MEM_64M
)
619 aperture_size
= MB(64);
621 aperture_size
= MB(128);
623 /* 9xx supports large sizes, just look at the length */
624 aperture_size
= pci_resource_len(intel_private
.pcidev
, 2);
627 return aperture_size
>> PAGE_SHIFT
;
630 static void intel_gtt_teardown_scratch_page(void)
632 set_pages_wb(intel_private
.scratch_page
, 1);
633 pci_unmap_page(intel_private
.pcidev
, intel_private
.base
.scratch_page_dma
,
634 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
635 put_page(intel_private
.scratch_page
);
636 __free_page(intel_private
.scratch_page
);
639 static void intel_gtt_cleanup(void)
641 intel_private
.driver
->cleanup();
643 iounmap(intel_private
.gtt
);
644 iounmap(intel_private
.registers
);
646 intel_gtt_teardown_scratch_page();
649 static int intel_gtt_init(void)
655 ret
= intel_private
.driver
->setup();
659 intel_private
.base
.gtt_mappable_entries
= intel_gtt_mappable_entries();
660 intel_private
.base
.gtt_total_entries
= intel_gtt_total_entries();
662 /* save the PGETBL reg for resume */
663 intel_private
.PGETBL_save
=
664 readl(intel_private
.registers
+I810_PGETBL_CTL
)
665 & ~I810_PGETBL_ENABLED
;
666 /* we only ever restore the register when enabling the PGTBL... */
668 intel_private
.PGETBL_save
|= I810_PGETBL_ENABLED
;
670 dev_info(&intel_private
.bridge_dev
->dev
,
671 "detected gtt size: %dK total, %dK mappable\n",
672 intel_private
.base
.gtt_total_entries
* 4,
673 intel_private
.base
.gtt_mappable_entries
* 4);
675 gtt_map_size
= intel_private
.base
.gtt_total_entries
* 4;
677 intel_private
.gtt
= ioremap(intel_private
.gtt_bus_addr
,
679 if (!intel_private
.gtt
) {
680 intel_private
.driver
->cleanup();
681 iounmap(intel_private
.registers
);
684 intel_private
.base
.gtt
= intel_private
.gtt
;
686 global_cache_flush(); /* FIXME: ? */
688 intel_private
.base
.stolen_size
= intel_gtt_stolen_size();
690 intel_private
.base
.needs_dmar
= USE_PCI_DMA_API
&& INTEL_GTT_GEN
> 2;
692 ret
= intel_gtt_setup_scratch_page();
698 if (INTEL_GTT_GEN
<= 2)
699 pci_read_config_dword(intel_private
.pcidev
, I810_GMADDR
,
702 pci_read_config_dword(intel_private
.pcidev
, I915_GMADDR
,
705 intel_private
.base
.gma_bus_addr
= (gma_addr
& PCI_BASE_ADDRESS_MEM_MASK
);
710 static int intel_fake_agp_fetch_size(void)
712 int num_sizes
= ARRAY_SIZE(intel_fake_agp_sizes
);
713 unsigned int aper_size
;
716 aper_size
= (intel_private
.base
.gtt_mappable_entries
<< PAGE_SHIFT
)
719 for (i
= 0; i
< num_sizes
; i
++) {
720 if (aper_size
== intel_fake_agp_sizes
[i
].size
) {
721 agp_bridge
->current_size
=
722 (void *) (intel_fake_agp_sizes
+ i
);
730 static void i830_cleanup(void)
734 /* The chipset_flush interface needs to get data that has already been
735 * flushed out of the CPU all the way out to main memory, because the GPU
736 * doesn't snoop those buffers.
738 * The 8xx series doesn't have the same lovely interface for flushing the
739 * chipset write buffers that the later chips do. According to the 865
740 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
741 * that buffer out, we just fill 1KB and clflush it out, on the assumption
742 * that it'll push whatever was in there out. It appears to work.
744 static void i830_chipset_flush(void)
746 unsigned long timeout
= jiffies
+ msecs_to_jiffies(1000);
748 /* Forcibly evict everything from the CPU write buffers.
749 * clflush appears to be insufficient.
751 wbinvd_on_all_cpus();
753 /* Now we've only seen documents for this magic bit on 855GM,
754 * we hope it exists for the other gen2 chipsets...
756 * Also works as advertised on my 845G.
758 writel(readl(intel_private
.registers
+I830_HIC
) | (1<<31),
759 intel_private
.registers
+I830_HIC
);
761 while (readl(intel_private
.registers
+I830_HIC
) & (1<<31)) {
762 if (time_after(jiffies
, timeout
))
769 static void i830_write_entry(dma_addr_t addr
, unsigned int entry
,
772 u32 pte_flags
= I810_PTE_VALID
;
774 if (flags
== AGP_USER_CACHED_MEMORY
)
775 pte_flags
|= I830_PTE_SYSTEM_CACHED
;
777 writel(addr
| pte_flags
, intel_private
.gtt
+ entry
);
780 bool intel_enable_gtt(void)
784 if (INTEL_GTT_GEN
>= 6)
787 if (INTEL_GTT_GEN
== 2) {
790 pci_read_config_word(intel_private
.bridge_dev
,
791 I830_GMCH_CTRL
, &gmch_ctrl
);
792 gmch_ctrl
|= I830_GMCH_ENABLED
;
793 pci_write_config_word(intel_private
.bridge_dev
,
794 I830_GMCH_CTRL
, gmch_ctrl
);
796 pci_read_config_word(intel_private
.bridge_dev
,
797 I830_GMCH_CTRL
, &gmch_ctrl
);
798 if ((gmch_ctrl
& I830_GMCH_ENABLED
) == 0) {
799 dev_err(&intel_private
.pcidev
->dev
,
800 "failed to enable the GTT: GMCH_CTRL=%x\n",
806 /* On the resume path we may be adjusting the PGTBL value, so
807 * be paranoid and flush all chipset write buffers...
809 if (INTEL_GTT_GEN
>= 3)
810 writel(0, intel_private
.registers
+GFX_FLSH_CNTL
);
812 reg
= intel_private
.registers
+I810_PGETBL_CTL
;
813 writel(intel_private
.PGETBL_save
, reg
);
814 if (HAS_PGTBL_EN
&& (readl(reg
) & I810_PGETBL_ENABLED
) == 0) {
815 dev_err(&intel_private
.pcidev
->dev
,
816 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
817 readl(reg
), intel_private
.PGETBL_save
);
821 if (INTEL_GTT_GEN
>= 3)
822 writel(0, intel_private
.registers
+GFX_FLSH_CNTL
);
826 EXPORT_SYMBOL(intel_enable_gtt
);
828 static int i830_setup(void)
832 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, ®_addr
);
833 reg_addr
&= 0xfff80000;
835 intel_private
.registers
= ioremap(reg_addr
, KB(64));
836 if (!intel_private
.registers
)
839 intel_private
.gtt_bus_addr
= reg_addr
+ I810_PTE_BASE
;
844 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data
*bridge
)
846 agp_bridge
->gatt_table_real
= NULL
;
847 agp_bridge
->gatt_table
= NULL
;
848 agp_bridge
->gatt_bus_addr
= 0;
853 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data
*bridge
)
858 static int intel_fake_agp_configure(void)
860 if (!intel_enable_gtt())
863 intel_private
.clear_fake_agp
= true;
864 agp_bridge
->gart_bus_addr
= intel_private
.base
.gma_bus_addr
;
869 static bool i830_check_flags(unsigned int flags
)
873 case AGP_PHYS_MEMORY
:
874 case AGP_USER_CACHED_MEMORY
:
875 case AGP_USER_MEMORY
:
882 void intel_gtt_insert_sg_entries(struct scatterlist
*sg_list
,
884 unsigned int pg_start
,
887 struct scatterlist
*sg
;
893 /* sg may merge pages, but we have to separate
894 * per-page addr for GTT */
895 for_each_sg(sg_list
, sg
, sg_len
, i
) {
896 len
= sg_dma_len(sg
) >> PAGE_SHIFT
;
897 for (m
= 0; m
< len
; m
++) {
898 dma_addr_t addr
= sg_dma_address(sg
) + (m
<< PAGE_SHIFT
);
899 intel_private
.driver
->write_entry(addr
,
904 readl(intel_private
.gtt
+j
-1);
906 EXPORT_SYMBOL(intel_gtt_insert_sg_entries
);
908 void intel_gtt_insert_pages(unsigned int first_entry
, unsigned int num_entries
,
909 struct page
**pages
, unsigned int flags
)
913 for (i
= 0, j
= first_entry
; i
< num_entries
; i
++, j
++) {
914 dma_addr_t addr
= page_to_phys(pages
[i
]);
915 intel_private
.driver
->write_entry(addr
,
918 readl(intel_private
.gtt
+j
-1);
920 EXPORT_SYMBOL(intel_gtt_insert_pages
);
922 static int intel_fake_agp_insert_entries(struct agp_memory
*mem
,
923 off_t pg_start
, int type
)
927 if (intel_private
.base
.do_idle_maps
)
930 if (intel_private
.clear_fake_agp
) {
931 int start
= intel_private
.base
.stolen_size
/ PAGE_SIZE
;
932 int end
= intel_private
.base
.gtt_mappable_entries
;
933 intel_gtt_clear_range(start
, end
- start
);
934 intel_private
.clear_fake_agp
= false;
937 if (INTEL_GTT_GEN
== 1 && type
== AGP_DCACHE_MEMORY
)
938 return i810_insert_dcache_entries(mem
, pg_start
, type
);
940 if (mem
->page_count
== 0)
943 if (pg_start
+ mem
->page_count
> intel_private
.base
.gtt_total_entries
)
946 if (type
!= mem
->type
)
949 if (!intel_private
.driver
->check_flags(type
))
952 if (!mem
->is_flushed
)
953 global_cache_flush();
955 if (intel_private
.base
.needs_dmar
) {
956 ret
= intel_gtt_map_memory(mem
->pages
, mem
->page_count
,
957 &mem
->sg_list
, &mem
->num_sg
);
961 intel_gtt_insert_sg_entries(mem
->sg_list
, mem
->num_sg
,
964 intel_gtt_insert_pages(pg_start
, mem
->page_count
, mem
->pages
,
970 mem
->is_flushed
= true;
974 void intel_gtt_clear_range(unsigned int first_entry
, unsigned int num_entries
)
978 for (i
= first_entry
; i
< (first_entry
+ num_entries
); i
++) {
979 intel_private
.driver
->write_entry(intel_private
.base
.scratch_page_dma
,
982 readl(intel_private
.gtt
+i
-1);
984 EXPORT_SYMBOL(intel_gtt_clear_range
);
986 static int intel_fake_agp_remove_entries(struct agp_memory
*mem
,
987 off_t pg_start
, int type
)
989 if (mem
->page_count
== 0)
992 if (intel_private
.base
.do_idle_maps
)
995 intel_gtt_clear_range(pg_start
, mem
->page_count
);
997 if (intel_private
.base
.needs_dmar
) {
998 intel_gtt_unmap_memory(mem
->sg_list
, mem
->num_sg
);
1006 static struct agp_memory
*intel_fake_agp_alloc_by_type(size_t pg_count
,
1009 struct agp_memory
*new;
1011 if (type
== AGP_DCACHE_MEMORY
&& INTEL_GTT_GEN
== 1) {
1012 if (pg_count
!= intel_private
.num_dcache_entries
)
1015 new = agp_create_memory(1);
1019 new->type
= AGP_DCACHE_MEMORY
;
1020 new->page_count
= pg_count
;
1021 new->num_scratch_pages
= 0;
1022 agp_free_page_array(new);
1025 if (type
== AGP_PHYS_MEMORY
)
1026 return alloc_agpphysmem_i8xx(pg_count
, type
);
1027 /* always return NULL for other allocation types for now */
1031 static int intel_alloc_chipset_flush_resource(void)
1034 ret
= pci_bus_alloc_resource(intel_private
.bridge_dev
->bus
, &intel_private
.ifp_resource
, PAGE_SIZE
,
1035 PAGE_SIZE
, PCIBIOS_MIN_MEM
, 0,
1036 pcibios_align_resource
, intel_private
.bridge_dev
);
1041 static void intel_i915_setup_chipset_flush(void)
1046 pci_read_config_dword(intel_private
.bridge_dev
, I915_IFPADDR
, &temp
);
1047 if (!(temp
& 0x1)) {
1048 intel_alloc_chipset_flush_resource();
1049 intel_private
.resource_valid
= 1;
1050 pci_write_config_dword(intel_private
.bridge_dev
, I915_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
1054 intel_private
.resource_valid
= 1;
1055 intel_private
.ifp_resource
.start
= temp
;
1056 intel_private
.ifp_resource
.end
= temp
+ PAGE_SIZE
;
1057 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
1058 /* some BIOSes reserve this area in a pnp some don't */
1060 intel_private
.resource_valid
= 0;
1064 static void intel_i965_g33_setup_chipset_flush(void)
1066 u32 temp_hi
, temp_lo
;
1069 pci_read_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
+ 4, &temp_hi
);
1070 pci_read_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
, &temp_lo
);
1072 if (!(temp_lo
& 0x1)) {
1074 intel_alloc_chipset_flush_resource();
1076 intel_private
.resource_valid
= 1;
1077 pci_write_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
+ 4,
1078 upper_32_bits(intel_private
.ifp_resource
.start
));
1079 pci_write_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
1084 l64
= ((u64
)temp_hi
<< 32) | temp_lo
;
1086 intel_private
.resource_valid
= 1;
1087 intel_private
.ifp_resource
.start
= l64
;
1088 intel_private
.ifp_resource
.end
= l64
+ PAGE_SIZE
;
1089 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
1090 /* some BIOSes reserve this area in a pnp some don't */
1092 intel_private
.resource_valid
= 0;
1096 static void intel_i9xx_setup_flush(void)
1098 /* return if already configured */
1099 if (intel_private
.ifp_resource
.start
)
1102 if (INTEL_GTT_GEN
== 6)
1105 /* setup a resource for this object */
1106 intel_private
.ifp_resource
.name
= "Intel Flush Page";
1107 intel_private
.ifp_resource
.flags
= IORESOURCE_MEM
;
1109 /* Setup chipset flush for 915 */
1110 if (IS_G33
|| INTEL_GTT_GEN
>= 4) {
1111 intel_i965_g33_setup_chipset_flush();
1113 intel_i915_setup_chipset_flush();
1116 if (intel_private
.ifp_resource
.start
)
1117 intel_private
.i9xx_flush_page
= ioremap_nocache(intel_private
.ifp_resource
.start
, PAGE_SIZE
);
1118 if (!intel_private
.i9xx_flush_page
)
1119 dev_err(&intel_private
.pcidev
->dev
,
1120 "can't ioremap flush page - no chipset flushing\n");
1123 static void i9xx_cleanup(void)
1125 if (intel_private
.i9xx_flush_page
)
1126 iounmap(intel_private
.i9xx_flush_page
);
1127 if (intel_private
.resource_valid
)
1128 release_resource(&intel_private
.ifp_resource
);
1129 intel_private
.ifp_resource
.start
= 0;
1130 intel_private
.resource_valid
= 0;
1133 static void i9xx_chipset_flush(void)
1135 if (intel_private
.i9xx_flush_page
)
1136 writel(1, intel_private
.i9xx_flush_page
);
1139 static void i965_write_entry(dma_addr_t addr
,
1145 pte_flags
= I810_PTE_VALID
;
1146 if (flags
== AGP_USER_CACHED_MEMORY
)
1147 pte_flags
|= I830_PTE_SYSTEM_CACHED
;
1149 /* Shift high bits down */
1150 addr
|= (addr
>> 28) & 0xf0;
1151 writel(addr
| pte_flags
, intel_private
.gtt
+ entry
);
1154 static bool gen6_check_flags(unsigned int flags
)
1159 static void gen6_write_entry(dma_addr_t addr
, unsigned int entry
,
1162 unsigned int type_mask
= flags
& ~AGP_USER_CACHED_MEMORY_GFDT
;
1163 unsigned int gfdt
= flags
& AGP_USER_CACHED_MEMORY_GFDT
;
1166 if (type_mask
== AGP_USER_MEMORY
)
1167 pte_flags
= GEN6_PTE_UNCACHED
| I810_PTE_VALID
;
1168 else if (type_mask
== AGP_USER_CACHED_MEMORY_LLC_MLC
) {
1169 pte_flags
= GEN6_PTE_LLC_MLC
| I810_PTE_VALID
;
1171 pte_flags
|= GEN6_PTE_GFDT
;
1172 } else { /* set 'normal'/'cached' to LLC by default */
1173 pte_flags
= GEN6_PTE_LLC
| I810_PTE_VALID
;
1175 pte_flags
|= GEN6_PTE_GFDT
;
1178 /* gen6 has bit11-4 for physical addr bit39-32 */
1179 addr
|= (addr
>> 28) & 0xff0;
1180 writel(addr
| pte_flags
, intel_private
.gtt
+ entry
);
1183 static void valleyview_write_entry(dma_addr_t addr
, unsigned int entry
,
1186 unsigned int type_mask
= flags
& ~AGP_USER_CACHED_MEMORY_GFDT
;
1187 unsigned int gfdt
= flags
& AGP_USER_CACHED_MEMORY_GFDT
;
1190 if (type_mask
== AGP_USER_MEMORY
)
1191 pte_flags
= GEN6_PTE_UNCACHED
| I810_PTE_VALID
;
1193 pte_flags
= GEN6_PTE_LLC
| I810_PTE_VALID
;
1195 pte_flags
|= GEN6_PTE_GFDT
;
1198 /* gen6 has bit11-4 for physical addr bit39-32 */
1199 addr
|= (addr
>> 28) & 0xff0;
1200 writel(addr
| pte_flags
, intel_private
.gtt
+ entry
);
1202 writel(1, intel_private
.registers
+ GFX_FLSH_CNTL_VLV
);
1205 static void gen6_cleanup(void)
1209 /* Certain Gen5 chipsets require require idling the GPU before
1210 * unmapping anything from the GTT when VT-d is enabled.
1212 static inline int needs_idle_maps(void)
1214 #ifdef CONFIG_INTEL_IOMMU
1215 const unsigned short gpu_devid
= intel_private
.pcidev
->device
;
1217 /* Query intel_iommu to see if we need the workaround. Presumably that
1220 if ((gpu_devid
== PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB
||
1221 gpu_devid
== PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG
) &&
1222 intel_iommu_gfx_mapped
)
1228 static int i9xx_setup(void)
1233 pci_read_config_dword(intel_private
.pcidev
, I915_MMADDR
, ®_addr
);
1235 reg_addr
&= 0xfff80000;
1237 if (INTEL_GTT_GEN
>= 7)
1240 intel_private
.registers
= ioremap(reg_addr
, size
);
1241 if (!intel_private
.registers
)
1244 if (INTEL_GTT_GEN
== 3) {
1247 pci_read_config_dword(intel_private
.pcidev
,
1248 I915_PTEADDR
, >t_addr
);
1249 intel_private
.gtt_bus_addr
= gtt_addr
;
1253 switch (INTEL_GTT_GEN
) {
1261 gtt_offset
= KB(512);
1264 intel_private
.gtt_bus_addr
= reg_addr
+ gtt_offset
;
1267 if (needs_idle_maps())
1268 intel_private
.base
.do_idle_maps
= 1;
1270 intel_i9xx_setup_flush();
1275 static const struct agp_bridge_driver intel_fake_agp_driver
= {
1276 .owner
= THIS_MODULE
,
1277 .size_type
= FIXED_APER_SIZE
,
1278 .aperture_sizes
= intel_fake_agp_sizes
,
1279 .num_aperture_sizes
= ARRAY_SIZE(intel_fake_agp_sizes
),
1280 .configure
= intel_fake_agp_configure
,
1281 .fetch_size
= intel_fake_agp_fetch_size
,
1282 .cleanup
= intel_gtt_cleanup
,
1283 .agp_enable
= intel_fake_agp_enable
,
1284 .cache_flush
= global_cache_flush
,
1285 .create_gatt_table
= intel_fake_agp_create_gatt_table
,
1286 .free_gatt_table
= intel_fake_agp_free_gatt_table
,
1287 .insert_memory
= intel_fake_agp_insert_entries
,
1288 .remove_memory
= intel_fake_agp_remove_entries
,
1289 .alloc_by_type
= intel_fake_agp_alloc_by_type
,
1290 .free_by_type
= intel_i810_free_by_type
,
1291 .agp_alloc_page
= agp_generic_alloc_page
,
1292 .agp_alloc_pages
= agp_generic_alloc_pages
,
1293 .agp_destroy_page
= agp_generic_destroy_page
,
1294 .agp_destroy_pages
= agp_generic_destroy_pages
,
1297 static const struct intel_gtt_driver i81x_gtt_driver
= {
1299 .has_pgtbl_enable
= 1,
1300 .dma_mask_size
= 32,
1301 .setup
= i810_setup
,
1302 .cleanup
= i810_cleanup
,
1303 .check_flags
= i830_check_flags
,
1304 .write_entry
= i810_write_entry
,
1306 static const struct intel_gtt_driver i8xx_gtt_driver
= {
1308 .has_pgtbl_enable
= 1,
1309 .setup
= i830_setup
,
1310 .cleanup
= i830_cleanup
,
1311 .write_entry
= i830_write_entry
,
1312 .dma_mask_size
= 32,
1313 .check_flags
= i830_check_flags
,
1314 .chipset_flush
= i830_chipset_flush
,
1316 static const struct intel_gtt_driver i915_gtt_driver
= {
1318 .has_pgtbl_enable
= 1,
1319 .setup
= i9xx_setup
,
1320 .cleanup
= i9xx_cleanup
,
1321 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1322 .write_entry
= i830_write_entry
,
1323 .dma_mask_size
= 32,
1324 .check_flags
= i830_check_flags
,
1325 .chipset_flush
= i9xx_chipset_flush
,
1327 static const struct intel_gtt_driver g33_gtt_driver
= {
1330 .setup
= i9xx_setup
,
1331 .cleanup
= i9xx_cleanup
,
1332 .write_entry
= i965_write_entry
,
1333 .dma_mask_size
= 36,
1334 .check_flags
= i830_check_flags
,
1335 .chipset_flush
= i9xx_chipset_flush
,
1337 static const struct intel_gtt_driver pineview_gtt_driver
= {
1339 .is_pineview
= 1, .is_g33
= 1,
1340 .setup
= i9xx_setup
,
1341 .cleanup
= i9xx_cleanup
,
1342 .write_entry
= i965_write_entry
,
1343 .dma_mask_size
= 36,
1344 .check_flags
= i830_check_flags
,
1345 .chipset_flush
= i9xx_chipset_flush
,
1347 static const struct intel_gtt_driver i965_gtt_driver
= {
1349 .has_pgtbl_enable
= 1,
1350 .setup
= i9xx_setup
,
1351 .cleanup
= i9xx_cleanup
,
1352 .write_entry
= i965_write_entry
,
1353 .dma_mask_size
= 36,
1354 .check_flags
= i830_check_flags
,
1355 .chipset_flush
= i9xx_chipset_flush
,
1357 static const struct intel_gtt_driver g4x_gtt_driver
= {
1359 .setup
= i9xx_setup
,
1360 .cleanup
= i9xx_cleanup
,
1361 .write_entry
= i965_write_entry
,
1362 .dma_mask_size
= 36,
1363 .check_flags
= i830_check_flags
,
1364 .chipset_flush
= i9xx_chipset_flush
,
1366 static const struct intel_gtt_driver ironlake_gtt_driver
= {
1369 .setup
= i9xx_setup
,
1370 .cleanup
= i9xx_cleanup
,
1371 .write_entry
= i965_write_entry
,
1372 .dma_mask_size
= 36,
1373 .check_flags
= i830_check_flags
,
1374 .chipset_flush
= i9xx_chipset_flush
,
1376 static const struct intel_gtt_driver sandybridge_gtt_driver
= {
1378 .setup
= i9xx_setup
,
1379 .cleanup
= gen6_cleanup
,
1380 .write_entry
= gen6_write_entry
,
1381 .dma_mask_size
= 40,
1382 .check_flags
= gen6_check_flags
,
1383 .chipset_flush
= i9xx_chipset_flush
,
1385 static const struct intel_gtt_driver valleyview_gtt_driver
= {
1387 .setup
= i9xx_setup
,
1388 .cleanup
= gen6_cleanup
,
1389 .write_entry
= valleyview_write_entry
,
1390 .dma_mask_size
= 40,
1391 .check_flags
= gen6_check_flags
,
1394 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1395 * driver and gmch_driver must be non-null, and find_gmch will determine
1396 * which one should be used if a gmch_chip_id is present.
1398 static const struct intel_gtt_driver_description
{
1399 unsigned int gmch_chip_id
;
1401 const struct intel_gtt_driver
*gtt_driver
;
1402 } intel_gtt_chipsets
[] = {
1403 { PCI_DEVICE_ID_INTEL_82810_IG1
, "i810",
1405 { PCI_DEVICE_ID_INTEL_82810_IG3
, "i810",
1407 { PCI_DEVICE_ID_INTEL_82810E_IG
, "i810",
1409 { PCI_DEVICE_ID_INTEL_82815_CGC
, "i815",
1411 { PCI_DEVICE_ID_INTEL_82830_CGC
, "830M",
1413 { PCI_DEVICE_ID_INTEL_82845G_IG
, "845G",
1415 { PCI_DEVICE_ID_INTEL_82854_IG
, "854",
1417 { PCI_DEVICE_ID_INTEL_82855GM_IG
, "855GM",
1419 { PCI_DEVICE_ID_INTEL_82865_IG
, "865",
1421 { PCI_DEVICE_ID_INTEL_E7221_IG
, "E7221 (i915)",
1423 { PCI_DEVICE_ID_INTEL_82915G_IG
, "915G",
1425 { PCI_DEVICE_ID_INTEL_82915GM_IG
, "915GM",
1427 { PCI_DEVICE_ID_INTEL_82945G_IG
, "945G",
1429 { PCI_DEVICE_ID_INTEL_82945GM_IG
, "945GM",
1431 { PCI_DEVICE_ID_INTEL_82945GME_IG
, "945GME",
1433 { PCI_DEVICE_ID_INTEL_82946GZ_IG
, "946GZ",
1435 { PCI_DEVICE_ID_INTEL_82G35_IG
, "G35",
1437 { PCI_DEVICE_ID_INTEL_82965Q_IG
, "965Q",
1439 { PCI_DEVICE_ID_INTEL_82965G_IG
, "965G",
1441 { PCI_DEVICE_ID_INTEL_82965GM_IG
, "965GM",
1443 { PCI_DEVICE_ID_INTEL_82965GME_IG
, "965GME/GLE",
1445 { PCI_DEVICE_ID_INTEL_G33_IG
, "G33",
1447 { PCI_DEVICE_ID_INTEL_Q35_IG
, "Q35",
1449 { PCI_DEVICE_ID_INTEL_Q33_IG
, "Q33",
1451 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG
, "GMA3150",
1452 &pineview_gtt_driver
},
1453 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG
, "GMA3150",
1454 &pineview_gtt_driver
},
1455 { PCI_DEVICE_ID_INTEL_GM45_IG
, "GM45",
1457 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG
, "Eaglelake",
1459 { PCI_DEVICE_ID_INTEL_Q45_IG
, "Q45/Q43",
1461 { PCI_DEVICE_ID_INTEL_G45_IG
, "G45/G43",
1463 { PCI_DEVICE_ID_INTEL_B43_IG
, "B43",
1465 { PCI_DEVICE_ID_INTEL_B43_1_IG
, "B43",
1467 { PCI_DEVICE_ID_INTEL_G41_IG
, "G41",
1469 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG
,
1470 "HD Graphics", &ironlake_gtt_driver
},
1471 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG
,
1472 "HD Graphics", &ironlake_gtt_driver
},
1473 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG
,
1474 "Sandybridge", &sandybridge_gtt_driver
},
1475 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG
,
1476 "Sandybridge", &sandybridge_gtt_driver
},
1477 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG
,
1478 "Sandybridge", &sandybridge_gtt_driver
},
1479 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG
,
1480 "Sandybridge", &sandybridge_gtt_driver
},
1481 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG
,
1482 "Sandybridge", &sandybridge_gtt_driver
},
1483 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG
,
1484 "Sandybridge", &sandybridge_gtt_driver
},
1485 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG
,
1486 "Sandybridge", &sandybridge_gtt_driver
},
1487 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG
,
1488 "Ivybridge", &sandybridge_gtt_driver
},
1489 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG
,
1490 "Ivybridge", &sandybridge_gtt_driver
},
1491 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG
,
1492 "Ivybridge", &sandybridge_gtt_driver
},
1493 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG
,
1494 "Ivybridge", &sandybridge_gtt_driver
},
1495 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG
,
1496 "Ivybridge", &sandybridge_gtt_driver
},
1497 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG
,
1498 "Ivybridge", &sandybridge_gtt_driver
},
1499 { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG
,
1500 "ValleyView", &valleyview_gtt_driver
},
1501 { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG
,
1502 "Haswell", &sandybridge_gtt_driver
},
1503 { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG
,
1504 "Haswell", &sandybridge_gtt_driver
},
1505 { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG
,
1506 "Haswell", &sandybridge_gtt_driver
},
1507 { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG
,
1508 "Haswell", &sandybridge_gtt_driver
},
1509 { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG
,
1510 "Haswell", &sandybridge_gtt_driver
},
1511 { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG
,
1512 "Haswell", &sandybridge_gtt_driver
},
1513 { PCI_DEVICE_ID_INTEL_HASWELL_SDV
,
1514 "Haswell", &sandybridge_gtt_driver
},
1518 static int find_gmch(u16 device
)
1520 struct pci_dev
*gmch_device
;
1522 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
, device
, NULL
);
1523 if (gmch_device
&& PCI_FUNC(gmch_device
->devfn
) != 0) {
1524 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
,
1525 device
, gmch_device
);
1531 intel_private
.pcidev
= gmch_device
;
1535 int intel_gmch_probe(struct pci_dev
*bridge_pdev
, struct pci_dev
*gpu_pdev
,
1536 struct agp_bridge_data
*bridge
)
1541 * Can be called from the fake agp driver but also directly from
1542 * drm/i915.ko. Hence we need to check whether everything is set up
1545 if (intel_private
.driver
) {
1546 intel_private
.refcount
++;
1550 for (i
= 0; intel_gtt_chipsets
[i
].name
!= NULL
; i
++) {
1552 if (gpu_pdev
->device
==
1553 intel_gtt_chipsets
[i
].gmch_chip_id
) {
1554 intel_private
.pcidev
= pci_dev_get(gpu_pdev
);
1555 intel_private
.driver
=
1556 intel_gtt_chipsets
[i
].gtt_driver
;
1560 } else if (find_gmch(intel_gtt_chipsets
[i
].gmch_chip_id
)) {
1561 intel_private
.driver
=
1562 intel_gtt_chipsets
[i
].gtt_driver
;
1567 if (!intel_private
.driver
)
1570 intel_private
.refcount
++;
1573 bridge
->driver
= &intel_fake_agp_driver
;
1574 bridge
->dev_private_data
= &intel_private
;
1575 bridge
->dev
= bridge_pdev
;
1578 intel_private
.bridge_dev
= pci_dev_get(bridge_pdev
);
1580 dev_info(&bridge_pdev
->dev
, "Intel %s Chipset\n", intel_gtt_chipsets
[i
].name
);
1582 mask
= intel_private
.driver
->dma_mask_size
;
1583 if (pci_set_dma_mask(intel_private
.pcidev
, DMA_BIT_MASK(mask
)))
1584 dev_err(&intel_private
.pcidev
->dev
,
1585 "set gfx device dma mask %d-bit failed!\n", mask
);
1587 pci_set_consistent_dma_mask(intel_private
.pcidev
,
1588 DMA_BIT_MASK(mask
));
1590 if (intel_gtt_init() != 0) {
1591 intel_gmch_remove();
1598 EXPORT_SYMBOL(intel_gmch_probe
);
1600 const struct intel_gtt
*intel_gtt_get(void)
1602 return &intel_private
.base
;
1604 EXPORT_SYMBOL(intel_gtt_get
);
1606 void intel_gtt_chipset_flush(void)
1608 if (intel_private
.driver
->chipset_flush
)
1609 intel_private
.driver
->chipset_flush();
1611 EXPORT_SYMBOL(intel_gtt_chipset_flush
);
1613 void intel_gmch_remove(void)
1615 if (--intel_private
.refcount
)
1618 if (intel_private
.pcidev
)
1619 pci_dev_put(intel_private
.pcidev
);
1620 if (intel_private
.bridge_dev
)
1621 pci_dev_put(intel_private
.bridge_dev
);
1622 intel_private
.driver
= NULL
;
1624 EXPORT_SYMBOL(intel_gmch_remove
);
1626 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1627 MODULE_LICENSE("GPL and additional rights");