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block: move down direct IO plugging
[linux/fpc-iii.git] / drivers / mfd / omap-usb-host.c
blob41088ecbb2a92e3c6350038ad61f77ceb500e8ce
1 /**
2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/types.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spinlock.h>
28 #include <linux/gpio.h>
29 #include <plat/cpu.h>
30 #include <plat/usb.h>
31 #include <linux/pm_runtime.h>
32
33 #define USBHS_DRIVER_NAME "usbhs_omap"
34 #define OMAP_EHCI_DEVICE "ehci-omap"
35 #define OMAP_OHCI_DEVICE "ohci-omap3"
36
37 /* OMAP USBHOST Register addresses */
38
39 /* TLL Register Set */
40 #define OMAP_USBTLL_REVISION (0x00)
41 #define OMAP_USBTLL_SYSCONFIG (0x10)
42 #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
43 #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
44 #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
45 #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
46 #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
47
48 #define OMAP_USBTLL_SYSSTATUS (0x14)
49 #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
50
51 #define OMAP_USBTLL_IRQSTATUS (0x18)
52 #define OMAP_USBTLL_IRQENABLE (0x1C)
53
54 #define OMAP_TLL_SHARED_CONF (0x30)
55 #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
56 #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
57 #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
58 #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
59 #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
60
61 #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
62 #define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
63 #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
64 #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
65 #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
66 #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
67 #define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
68 #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
69
70 #define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0
71 #define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1
72 #define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2
73 #define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3
74 #define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4
75 #define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5
76 #define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6
77 #define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7
78 #define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA
79 #define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB
80
81 #define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
82 #define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
83 #define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
84 #define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
85 #define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
86 #define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
87 #define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
88 #define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
89 #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
90
91 #define OMAP_TLL_CHANNEL_COUNT 3
92 #define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0)
93 #define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1)
94 #define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2)
95
96 /* UHH Register Set */
97 #define OMAP_UHH_REVISION (0x00)
98 #define OMAP_UHH_SYSCONFIG (0x10)
99 #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
100 #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
101 #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
102 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
103 #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
104 #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
105
106 #define OMAP_UHH_SYSSTATUS (0x14)
107 #define OMAP_UHH_HOSTCONFIG (0x40)
108 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
109 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
110 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
111 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
112 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
113 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
114 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
115 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
116 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
117 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
118 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
119 #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
120
121 /* OMAP4-specific defines */
122 #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
123 #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
124 #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
125 #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
126 #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
127
128 #define OMAP4_P1_MODE_CLEAR (3 << 16)
129 #define OMAP4_P1_MODE_TLL (1 << 16)
130 #define OMAP4_P1_MODE_HSIC (3 << 16)
131 #define OMAP4_P2_MODE_CLEAR (3 << 18)
132 #define OMAP4_P2_MODE_TLL (1 << 18)
133 #define OMAP4_P2_MODE_HSIC (3 << 18)
134
135 #define OMAP_REV2_TLL_CHANNEL_COUNT 2
136
137 #define OMAP_UHH_DEBUG_CSR (0x44)
138
139 /* Values of UHH_REVISION - Note: these are not given in the TRM */
140 #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
141 #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
142
143 #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
144 #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
145
146 #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
147 #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
148 #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
149
150
151 struct usbhs_hcd_omap {
152 struct clk *xclk60mhsp1_ck;
153 struct clk *xclk60mhsp2_ck;
154 struct clk *utmi_p1_fck;
155 struct clk *usbhost_p1_fck;
156 struct clk *usbtll_p1_fck;
157 struct clk *utmi_p2_fck;
158 struct clk *usbhost_p2_fck;
159 struct clk *usbtll_p2_fck;
160 struct clk *init_60m_fclk;
161 struct clk *ehci_logic_fck;
162
163 void __iomem *uhh_base;
164 void __iomem *tll_base;
165
166 struct usbhs_omap_platform_data platdata;
167
168 u32 usbhs_rev;
169 spinlock_t lock;
170 };
171 /*-------------------------------------------------------------------------*/
172
173 const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
174 static u64 usbhs_dmamask = DMA_BIT_MASK(32);
175
176 /*-------------------------------------------------------------------------*/
177
178 static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
179 {
180 __raw_writel(val, base + reg);
181 }
182
183 static inline u32 usbhs_read(void __iomem *base, u32 reg)
184 {
185 return __raw_readl(base + reg);
186 }
187
188 static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
189 {
190 __raw_writeb(val, base + reg);
191 }
192
193 static inline u8 usbhs_readb(void __iomem *base, u8 reg)
194 {
195 return __raw_readb(base + reg);
196 }
197
198 /*-------------------------------------------------------------------------*/
199
200 static struct platform_device *omap_usbhs_alloc_child(const char *name,
201 struct resource *res, int num_resources, void *pdata,
202 size_t pdata_size, struct device *dev)
203 {
204 struct platform_device *child;
205 int ret;
206
207 child = platform_device_alloc(name, 0);
208
209 if (!child) {
210 dev_err(dev, "platform_device_alloc %s failed\n", name);
211 goto err_end;
212 }
213
214 ret = platform_device_add_resources(child, res, num_resources);
215 if (ret) {
216 dev_err(dev, "platform_device_add_resources failed\n");
217 goto err_alloc;
218 }
219
220 ret = platform_device_add_data(child, pdata, pdata_size);
221 if (ret) {
222 dev_err(dev, "platform_device_add_data failed\n");
223 goto err_alloc;
224 }
225
226 child->dev.dma_mask = &usbhs_dmamask;
227 dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
228 child->dev.parent = dev;
229
230 ret = platform_device_add(child);
231 if (ret) {
232 dev_err(dev, "platform_device_add failed\n");
233 goto err_alloc;
234 }
235
236 return child;
237
238 err_alloc:
239 platform_device_put(child);
240
241 err_end:
242 return NULL;
243 }
244
245 static int omap_usbhs_alloc_children(struct platform_device *pdev)
246 {
247 struct device *dev = &pdev->dev;
248 struct usbhs_hcd_omap *omap;
249 struct ehci_hcd_omap_platform_data *ehci_data;
250 struct ohci_hcd_omap_platform_data *ohci_data;
251 struct platform_device *ehci;
252 struct platform_device *ohci;
253 struct resource *res;
254 struct resource resources[2];
255 int ret;
256
257 omap = platform_get_drvdata(pdev);
258 ehci_data = omap->platdata.ehci_data;
259 ohci_data = omap->platdata.ohci_data;
260
261 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
262 if (!res) {
263 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
264 ret = -ENODEV;
265 goto err_end;
266 }
267 resources[0] = *res;
268
269 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
270 if (!res) {
271 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
272 ret = -ENODEV;
273 goto err_end;
274 }
275 resources[1] = *res;
276
277 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data,
278 sizeof(*ehci_data), dev);
279
280 if (!ehci) {
281 dev_err(dev, "omap_usbhs_alloc_child failed\n");
282 ret = -ENOMEM;
283 goto err_end;
284 }
285
286 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
287 if (!res) {
288 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
289 ret = -ENODEV;
290 goto err_ehci;
291 }
292 resources[0] = *res;
293
294 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
295 if (!res) {
296 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
297 ret = -ENODEV;
298 goto err_ehci;
299 }
300 resources[1] = *res;
301
302 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data,
303 sizeof(*ohci_data), dev);
304 if (!ohci) {
305 dev_err(dev, "omap_usbhs_alloc_child failed\n");
306 ret = -ENOMEM;
307 goto err_ehci;
308 }
309
310 return 0;
311
312 err_ehci:
313 platform_device_unregister(ehci);
314
315 err_end:
316 return ret;
317 }
318
319 static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
320 {
321 switch (pmode) {
322 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
323 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
324 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
325 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
326 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
327 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
328 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
329 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
330 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
331 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
332 return true;
333
334 default:
335 return false;
336 }
337 }
338
339 /*
340 * convert the port-mode enum to a value we can use in the FSLSMODE
341 * field of USBTLL_CHANNEL_CONF
342 */
343 static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
344 {
345 switch (mode) {
346 case OMAP_USBHS_PORT_MODE_UNUSED:
347 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
348 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
349
350 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
351 return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
352
353 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
354 return OMAP_TLL_FSLSMODE_3PIN_PHY;
355
356 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
357 return OMAP_TLL_FSLSMODE_4PIN_PHY;
358
359 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
360 return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
361
362 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
363 return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
364
365 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
366 return OMAP_TLL_FSLSMODE_3PIN_TLL;
367
368 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
369 return OMAP_TLL_FSLSMODE_4PIN_TLL;
370
371 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
372 return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
373
374 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
375 return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
376 default:
377 pr_warning("Invalid port mode, using default\n");
378 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
379 }
380 }
381
382 static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count)
383 {
384 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
385 struct usbhs_omap_platform_data *pdata = dev->platform_data;
386 unsigned reg;
387 int i;
388
389 /* Program Common TLL register */
390 reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF);
391 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
392 | OMAP_TLL_SHARED_CONF_USB_DIVRATION);
393 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
394 reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
395
396 usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
397
398 /* Enable channels now */
399 for (i = 0; i < tll_channel_count; i++) {
400 reg = usbhs_read(omap->tll_base,
401 OMAP_TLL_CHANNEL_CONF(i));
402
403 if (is_ohci_port(pdata->port_mode[i])) {
404 reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
405 << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
406 reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
407 } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) {
408
409 /* Disable AutoIdle, BitStuffing and use SDR Mode */
410 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
411 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
412 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
413
414 } else
415 continue;
416
417 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
418 usbhs_write(omap->tll_base,
419 OMAP_TLL_CHANNEL_CONF(i), reg);
420
421 usbhs_writeb(omap->tll_base,
422 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
423 }
424 }
425
426 static int usbhs_runtime_resume(struct device *dev)
427 {
428 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
429 struct usbhs_omap_platform_data *pdata = &omap->platdata;
430 unsigned long flags;
431
432 dev_dbg(dev, "usbhs_runtime_resume\n");
433
434 if (!pdata) {
435 dev_dbg(dev, "missing platform_data\n");
436 return -ENODEV;
437 }
438
439 spin_lock_irqsave(&omap->lock, flags);
440
441 if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
442 clk_enable(omap->ehci_logic_fck);
443
444 if (is_ehci_tll_mode(pdata->port_mode[0])) {
445 clk_enable(omap->usbhost_p1_fck);
446 clk_enable(omap->usbtll_p1_fck);
447 }
448 if (is_ehci_tll_mode(pdata->port_mode[1])) {
449 clk_enable(omap->usbhost_p2_fck);
450 clk_enable(omap->usbtll_p2_fck);
451 }
452 clk_enable(omap->utmi_p1_fck);
453 clk_enable(omap->utmi_p2_fck);
454
455 spin_unlock_irqrestore(&omap->lock, flags);
456
457 return 0;
458 }
459
460 static int usbhs_runtime_suspend(struct device *dev)
461 {
462 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
463 struct usbhs_omap_platform_data *pdata = &omap->platdata;
464 unsigned long flags;
465
466 dev_dbg(dev, "usbhs_runtime_suspend\n");
467
468 if (!pdata) {
469 dev_dbg(dev, "missing platform_data\n");
470 return -ENODEV;
471 }
472
473 spin_lock_irqsave(&omap->lock, flags);
474
475 if (is_ehci_tll_mode(pdata->port_mode[0])) {
476 clk_disable(omap->usbhost_p1_fck);
477 clk_disable(omap->usbtll_p1_fck);
478 }
479 if (is_ehci_tll_mode(pdata->port_mode[1])) {
480 clk_disable(omap->usbhost_p2_fck);
481 clk_disable(omap->usbtll_p2_fck);
482 }
483 clk_disable(omap->utmi_p2_fck);
484 clk_disable(omap->utmi_p1_fck);
485
486 if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
487 clk_disable(omap->ehci_logic_fck);
488
489 spin_unlock_irqrestore(&omap->lock, flags);
490
491 return 0;
492 }
493
494 static void omap_usbhs_init(struct device *dev)
495 {
496 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
497 struct usbhs_omap_platform_data *pdata = &omap->platdata;
498 unsigned long flags;
499 unsigned reg;
500
501 dev_dbg(dev, "starting TI HSUSB Controller\n");
502
503 pm_runtime_get_sync(dev);
504
505 if (pdata->ehci_data->phy_reset) {
506 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
507 gpio_request_one(pdata->ehci_data->reset_gpio_port[0],
508 GPIOF_OUT_INIT_LOW, "USB1 PHY reset");
509
510 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
511 gpio_request_one(pdata->ehci_data->reset_gpio_port[1],
512 GPIOF_OUT_INIT_LOW, "USB2 PHY reset");
513
514 /* Hold the PHY in RESET for enough time till DIR is high */
515 udelay(10);
516 }
517
518 spin_lock_irqsave(&omap->lock, flags);
519 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
520 dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
521
522 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
523 /* setup ULPI bypass and burst configurations */
524 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
525 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
526 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
527 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
528 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
529
530 if (is_omap_usbhs_rev1(omap)) {
531 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
532 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
533 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
534 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
535 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
536 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
537
538 /* Bypass the TLL module for PHY mode operation */
539 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
540 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
541 if (is_ehci_phy_mode(pdata->port_mode[0]) ||
542 is_ehci_phy_mode(pdata->port_mode[1]) ||
543 is_ehci_phy_mode(pdata->port_mode[2]))
544 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
545 else
546 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
547 } else {
548 dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
549 if (is_ehci_phy_mode(pdata->port_mode[0]))
550 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
551 else
552 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
553 if (is_ehci_phy_mode(pdata->port_mode[1]))
554 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
555 else
556 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
557 if (is_ehci_phy_mode(pdata->port_mode[2]))
558 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
559 else
560 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
561 }
562 } else if (is_omap_usbhs_rev2(omap)) {
563 /* Clear port mode fields for PHY mode*/
564 reg &= ~OMAP4_P1_MODE_CLEAR;
565 reg &= ~OMAP4_P2_MODE_CLEAR;
566
567 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
568 (is_ohci_port(pdata->port_mode[0])))
569 reg |= OMAP4_P1_MODE_TLL;
570 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
571 reg |= OMAP4_P1_MODE_HSIC;
572
573 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
574 (is_ohci_port(pdata->port_mode[1])))
575 reg |= OMAP4_P2_MODE_TLL;
576 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
577 reg |= OMAP4_P2_MODE_HSIC;
578 }
579
580 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
581 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
582
583 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
584 is_ehci_tll_mode(pdata->port_mode[1]) ||
585 is_ehci_tll_mode(pdata->port_mode[2]) ||
586 (is_ohci_port(pdata->port_mode[0])) ||
587 (is_ohci_port(pdata->port_mode[1])) ||
588 (is_ohci_port(pdata->port_mode[2]))) {
589
590 /* Enable UTMI mode for required TLL channels */
591 if (is_omap_usbhs_rev2(omap))
592 usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT);
593 else
594 usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT);
595 }
596
597 spin_unlock_irqrestore(&omap->lock, flags);
598
599 if (pdata->ehci_data->phy_reset) {
600 /* Hold the PHY in RESET for enough time till
601 * PHY is settled and ready
602 */
603 udelay(10);
604
605 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
606 gpio_set_value_cansleep
607 (pdata->ehci_data->reset_gpio_port[0], 1);
608
609 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
610 gpio_set_value_cansleep
611 (pdata->ehci_data->reset_gpio_port[1], 1);
612 }
613
614 pm_runtime_put_sync(dev);
615 }
616
617 static void omap_usbhs_deinit(struct device *dev)
618 {
619 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
620 struct usbhs_omap_platform_data *pdata = &omap->platdata;
621
622 if (pdata->ehci_data->phy_reset) {
623 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
624 gpio_free(pdata->ehci_data->reset_gpio_port[0]);
625
626 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
627 gpio_free(pdata->ehci_data->reset_gpio_port[1]);
628 }
629 }
630
631
632 /**
633 * usbhs_omap_probe - initialize TI-based HCDs
634 *
635 * Allocates basic resources for this USB host controller.
636 */
637 static int __devinit usbhs_omap_probe(struct platform_device *pdev)
638 {
639 struct device *dev = &pdev->dev;
640 struct usbhs_omap_platform_data *pdata = dev->platform_data;
641 struct usbhs_hcd_omap *omap;
642 struct resource *res;
643 int ret = 0;
644 int i;
645
646 if (!pdata) {
647 dev_err(dev, "Missing platform data\n");
648 ret = -ENOMEM;
649 goto end_probe;
650 }
651
652 omap = kzalloc(sizeof(*omap), GFP_KERNEL);
653 if (!omap) {
654 dev_err(dev, "Memory allocation failed\n");
655 ret = -ENOMEM;
656 goto end_probe;
657 }
658
659 spin_lock_init(&omap->lock);
660
661 for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
662 omap->platdata.port_mode[i] = pdata->port_mode[i];
663
664 omap->platdata.ehci_data = pdata->ehci_data;
665 omap->platdata.ohci_data = pdata->ohci_data;
666
667 pm_runtime_enable(dev);
668
669
670 for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
671 if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
672 is_ehci_hsic_mode(i)) {
673 omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
674 if (IS_ERR(omap->ehci_logic_fck)) {
675 ret = PTR_ERR(omap->ehci_logic_fck);
676 dev_warn(dev, "ehci_logic_fck failed:%d\n",
677 ret);
678 }
679 break;
680 }
681
682 omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
683 if (IS_ERR(omap->utmi_p1_fck)) {
684 ret = PTR_ERR(omap->utmi_p1_fck);
685 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
686 goto err_end;
687 }
688
689 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
690 if (IS_ERR(omap->xclk60mhsp1_ck)) {
691 ret = PTR_ERR(omap->xclk60mhsp1_ck);
692 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
693 goto err_utmi_p1_fck;
694 }
695
696 omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
697 if (IS_ERR(omap->utmi_p2_fck)) {
698 ret = PTR_ERR(omap->utmi_p2_fck);
699 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
700 goto err_xclk60mhsp1_ck;
701 }
702
703 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
704 if (IS_ERR(omap->xclk60mhsp2_ck)) {
705 ret = PTR_ERR(omap->xclk60mhsp2_ck);
706 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
707 goto err_utmi_p2_fck;
708 }
709
710 omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
711 if (IS_ERR(omap->usbhost_p1_fck)) {
712 ret = PTR_ERR(omap->usbhost_p1_fck);
713 dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
714 goto err_xclk60mhsp2_ck;
715 }
716
717 omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
718 if (IS_ERR(omap->usbtll_p1_fck)) {
719 ret = PTR_ERR(omap->usbtll_p1_fck);
720 dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
721 goto err_usbhost_p1_fck;
722 }
723
724 omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
725 if (IS_ERR(omap->usbhost_p2_fck)) {
726 ret = PTR_ERR(omap->usbhost_p2_fck);
727 dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
728 goto err_usbtll_p1_fck;
729 }
730
731 omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
732 if (IS_ERR(omap->usbtll_p2_fck)) {
733 ret = PTR_ERR(omap->usbtll_p2_fck);
734 dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
735 goto err_usbhost_p2_fck;
736 }
737
738 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
739 if (IS_ERR(omap->init_60m_fclk)) {
740 ret = PTR_ERR(omap->init_60m_fclk);
741 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
742 goto err_usbtll_p2_fck;
743 }
744
745 if (is_ehci_phy_mode(pdata->port_mode[0])) {
746 /* for OMAP3 , the clk set paretn fails */
747 ret = clk_set_parent(omap->utmi_p1_fck,
748 omap->xclk60mhsp1_ck);
749 if (ret != 0)
750 dev_err(dev, "xclk60mhsp1_ck set parent"
751 "failed error:%d\n", ret);
752 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
753 ret = clk_set_parent(omap->utmi_p1_fck,
754 omap->init_60m_fclk);
755 if (ret != 0)
756 dev_err(dev, "init_60m_fclk set parent"
757 "failed error:%d\n", ret);
758 }
759
760 if (is_ehci_phy_mode(pdata->port_mode[1])) {
761 ret = clk_set_parent(omap->utmi_p2_fck,
762 omap->xclk60mhsp2_ck);
763 if (ret != 0)
764 dev_err(dev, "xclk60mhsp2_ck set parent"
765 "failed error:%d\n", ret);
766 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
767 ret = clk_set_parent(omap->utmi_p2_fck,
768 omap->init_60m_fclk);
769 if (ret != 0)
770 dev_err(dev, "init_60m_fclk set parent"
771 "failed error:%d\n", ret);
772 }
773
774 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
775 if (!res) {
776 dev_err(dev, "UHH EHCI get resource failed\n");
777 ret = -ENODEV;
778 goto err_init_60m_fclk;
779 }
780
781 omap->uhh_base = ioremap(res->start, resource_size(res));
782 if (!omap->uhh_base) {
783 dev_err(dev, "UHH ioremap failed\n");
784 ret = -ENOMEM;
785 goto err_init_60m_fclk;
786 }
787
788 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
789 if (!res) {
790 dev_err(dev, "UHH EHCI get resource failed\n");
791 ret = -ENODEV;
792 goto err_tll;
793 }
794
795 omap->tll_base = ioremap(res->start, resource_size(res));
796 if (!omap->tll_base) {
797 dev_err(dev, "TLL ioremap failed\n");
798 ret = -ENOMEM;
799 goto err_tll;
800 }
801
802 platform_set_drvdata(pdev, omap);
803
804 omap_usbhs_init(dev);
805 ret = omap_usbhs_alloc_children(pdev);
806 if (ret) {
807 dev_err(dev, "omap_usbhs_alloc_children failed\n");
808 goto err_alloc;
809 }
810
811 goto end_probe;
812
813 err_alloc:
814 omap_usbhs_deinit(&pdev->dev);
815 iounmap(omap->tll_base);
816
817 err_tll:
818 iounmap(omap->uhh_base);
819
820 err_init_60m_fclk:
821 clk_put(omap->init_60m_fclk);
822
823 err_usbtll_p2_fck:
824 clk_put(omap->usbtll_p2_fck);
825
826 err_usbhost_p2_fck:
827 clk_put(omap->usbhost_p2_fck);
828
829 err_usbtll_p1_fck:
830 clk_put(omap->usbtll_p1_fck);
831
832 err_usbhost_p1_fck:
833 clk_put(omap->usbhost_p1_fck);
834
835 err_xclk60mhsp2_ck:
836 clk_put(omap->xclk60mhsp2_ck);
837
838 err_utmi_p2_fck:
839 clk_put(omap->utmi_p2_fck);
840
841 err_xclk60mhsp1_ck:
842 clk_put(omap->xclk60mhsp1_ck);
843
844 err_utmi_p1_fck:
845 clk_put(omap->utmi_p1_fck);
846
847 err_end:
848 clk_put(omap->ehci_logic_fck);
849 pm_runtime_disable(dev);
850 kfree(omap);
851
852 end_probe:
853 return ret;
854 }
855
856 /**
857 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
858 * @pdev: USB Host Controller being removed
859 *
860 * Reverses the effect of usbhs_omap_probe().
861 */
862 static int __devexit usbhs_omap_remove(struct platform_device *pdev)
863 {
864 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
865
866 omap_usbhs_deinit(&pdev->dev);
867 iounmap(omap->tll_base);
868 iounmap(omap->uhh_base);
869 clk_put(omap->init_60m_fclk);
870 clk_put(omap->usbtll_p2_fck);
871 clk_put(omap->usbhost_p2_fck);
872 clk_put(omap->usbtll_p1_fck);
873 clk_put(omap->usbhost_p1_fck);
874 clk_put(omap->xclk60mhsp2_ck);
875 clk_put(omap->utmi_p2_fck);
876 clk_put(omap->xclk60mhsp1_ck);
877 clk_put(omap->utmi_p1_fck);
878 clk_put(omap->ehci_logic_fck);
879 pm_runtime_disable(&pdev->dev);
880 kfree(omap);
881
882 return 0;
883 }
884
885 static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
886 .runtime_suspend = usbhs_runtime_suspend,
887 .runtime_resume = usbhs_runtime_resume,
888 };
889
890 static struct platform_driver usbhs_omap_driver = {
891 .driver = {
892 .name = (char *)usbhs_driver_name,
893 .owner = THIS_MODULE,
894 .pm = &usbhsomap_dev_pm_ops,
895 },
896 .remove = __exit_p(usbhs_omap_remove),
897 };
898
899 MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
900 MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
901 MODULE_LICENSE("GPL v2");
902 MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
903
904 static int __init omap_usbhs_drvinit(void)
905 {
906 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
907 }
908
909 /*
910 * init before ehci and ohci drivers;
911 * The usbhs core driver should be initialized much before
912 * the omap ehci and ohci probe functions are called.
913 */
914 fs_initcall(omap_usbhs_drvinit);
915
916 static void __exit omap_usbhs_drvexit(void)
917 {
918 platform_driver_unregister(&usbhs_omap_driver);
919 }
920 module_exit(omap_usbhs_drvexit);
Linux with added FPC-III support