| blob | af68ef7b0caadee75e8d8fc9bffee1153ed355b9 |
1 /*
2 * Copyright 2012 DENX Software Engineering GmbH
3 * Heiko Schocher <hs@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10 #include "skeleton.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
13 / {
14 arm {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges;
18 intc: interrupt-controller@fffee000 {
19 compatible = "ti,cp-intc";
20 interrupt-controller;
21 #interrupt-cells = <1>;
22 ti,intc-size = <101>;
23 reg = <0xfffee000 0x2000>;
24 };
25 };
26 soc@1c00000 {
27 compatible = "simple-bus";
28 model = "da850";
29 #address-cells = <1>;
30 #size-cells = <1>;
31 ranges = <0x0 0x01c00000 0x400000>;
32 interrupt-parent = <&intc>;
34 pmx_core: pinmux@14120 {
35 compatible = "pinctrl-single";
36 reg = <0x14120 0x50>;
37 #address-cells = <1>;
38 #size-cells = <0>;
39 #pinctrl-cells = <2>;
40 pinctrl-single,bit-per-mux;
41 pinctrl-single,register-width = <32>;
42 pinctrl-single,function-mask = <0xf>;
43 status = "disabled";
45 serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
46 pinctrl-single,bits = <
47 /* UART0_RTS UART0_CTS */
48 0x0c 0x22000000 0xff000000
49 >;
50 };
51 serial0_rxtx_pins: pinmux_serial0_rxtx_pins {
52 pinctrl-single,bits = <
53 /* UART0_TXD UART0_RXD */
54 0x0c 0x00220000 0x00ff0000
55 >;
56 };
57 serial1_rtscts_pins: pinmux_serial1_rtscts_pins {
58 pinctrl-single,bits = <
59 /* UART1_CTS UART1_RTS */
60 0x00 0x00440000 0x00ff0000
61 >;
62 };
63 serial1_rxtx_pins: pinmux_serial1_rxtx_pins {
64 pinctrl-single,bits = <
65 /* UART1_TXD UART1_RXD */
66 0x10 0x22000000 0xff000000
67 >;
68 };
69 serial2_rtscts_pins: pinmux_serial2_rtscts_pins {
70 pinctrl-single,bits = <
71 /* UART2_CTS UART2_RTS */
72 0x00 0x44000000 0xff000000
73 >;
74 };
75 serial2_rxtx_pins: pinmux_serial2_rxtx_pins {
76 pinctrl-single,bits = <
77 /* UART2_TXD UART2_RXD */
78 0x10 0x00220000 0x00ff0000
79 >;
80 };
81 i2c0_pins: pinmux_i2c0_pins {
82 pinctrl-single,bits = <
83 /* I2C0_SDA,I2C0_SCL */
84 0x10 0x00002200 0x0000ff00
85 >;
86 };
87 i2c1_pins: pinmux_i2c1_pins {
88 pinctrl-single,bits = <
89 /* I2C1_SDA, I2C1_SCL */
90 0x10 0x00440000 0x00ff0000
91 >;
92 };
93 mmc0_pins: pinmux_mmc_pins {
94 pinctrl-single,bits = <
95 /* MMCSD0_DAT[3] MMCSD0_DAT[2]
96 * MMCSD0_DAT[1] MMCSD0_DAT[0]
97 * MMCSD0_CMD MMCSD0_CLK
98 */
99 0x28 0x00222222 0x00ffffff
100 >;
101 };
102 ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
103 pinctrl-single,bits = <
104 /* EPWM0A */
105 0xc 0x00000002 0x0000000f
106 >;
107 };
108 ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
109 pinctrl-single,bits = <
110 /* EPWM0B */
111 0xc 0x00000020 0x000000f0
112 >;
113 };
114 ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
115 pinctrl-single,bits = <
116 /* EPWM1A */
117 0x14 0x00000002 0x0000000f
118 >;
119 };
120 ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
121 pinctrl-single,bits = <
122 /* EPWM1B */
123 0x14 0x00000020 0x000000f0
124 >;
125 };
126 ecap0_pins: pinmux_ecap0_pins {
127 pinctrl-single,bits = <
128 /* ECAP0_APWM0 */
129 0x8 0x20000000 0xf0000000
130 >;
131 };
132 ecap1_pins: pinmux_ecap1_pins {
133 pinctrl-single,bits = <
134 /* ECAP1_APWM1 */
135 0x4 0x40000000 0xf0000000
136 >;
137 };
138 ecap2_pins: pinmux_ecap2_pins {
139 pinctrl-single,bits = <
140 /* ECAP2_APWM2 */
141 0x4 0x00000004 0x0000000f
142 >;
143 };
144 spi0_pins: pinmux_spi0_pins {
145 pinctrl-single,bits = <
146 /* SIMO, SOMI, CLK */
147 0xc 0x00001101 0x0000ff0f
148 >;
149 };
150 spi0_cs0_pin: pinmux_spi0_cs0 {
151 pinctrl-single,bits = <
152 /* CS0 */
153 0x10 0x00000010 0x000000f0
154 >;
155 };
156 spi0_cs3_pin: pinmux_spi0_cs3_pin {
157 pinctrl-single,bits = <
158 /* CS3 */
159 0xc 0x01000000 0x0f000000
160 >;
161 };
162 spi1_pins: pinmux_spi1_pins {
163 pinctrl-single,bits = <
164 /* SIMO, SOMI, CLK */
165 0x14 0x00110100 0x00ff0f00
166 >;
167 };
168 spi1_cs0_pin: pinmux_spi1_cs0 {
169 pinctrl-single,bits = <
170 /* CS0 */
171 0x14 0x00000010 0x000000f0
172 >;
173 };
174 mdio_pins: pinmux_mdio_pins {
175 pinctrl-single,bits = <
176 /* MDIO_CLK, MDIO_D */
177 0x10 0x00000088 0x000000ff
178 >;
179 };
180 mii_pins: pinmux_mii_pins {
181 pinctrl-single,bits = <
182 /*
183 * MII_TXEN, MII_TXCLK, MII_COL
184 * MII_TXD_3, MII_TXD_2, MII_TXD_1
185 * MII_TXD_0
186 */
187 0x8 0x88888880 0xfffffff0
188 /*
189 * MII_RXER, MII_CRS, MII_RXCLK
190 * MII_RXDV, MII_RXD_3, MII_RXD_2
191 * MII_RXD_1, MII_RXD_0
192 */
193 0xc 0x88888888 0xffffffff
194 >;
195 };
196 lcd_pins: pinmux_lcd_pins {
197 pinctrl-single,bits = <
198 /*
199 * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
200 * LCD_D[6], LCD_D[7]
201 */
202 0x40 0x22222200 0xffffff00
203 /*
204 * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
205 * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
206 */
207 0x44 0x22222222 0xffffffff
208 /* LCD_D[8], LCD_D[9] */
209 0x48 0x00000022 0x000000ff
211 /* LCD_PCLK */
212 0x48 0x02000000 0x0f000000
213 /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
214 0x4c 0x02000022 0x0f0000ff
215 >;
216 };
217 vpif_capture_pins: vpif_capture_pins {
218 pinctrl-single,bits = <
219 /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */
220 0x38 0x11111111 0xffffffff
221 /* VP_DIN[10..15,0..1] */
222 0x3c 0x11111111 0xffffffff
223 /* VP_DIN[8..9] */
224 0x40 0x00000011 0x000000ff
225 >;
226 };
227 vpif_display_pins: vpif_display_pins {
228 pinctrl-single,bits = <
229 /* VP_DOUT[2..7] */
230 0x40 0x11111100 0xffffff00
231 /* VP_DOUT[10..15,0..1] */
232 0x44 0x11111111 0xffffffff
233 /* VP_DOUT[8..9] */
234 0x48 0x00000011 0x000000ff
235 /*
236 * VP_CLKOUT3, VP_CLKIN3,
237 * VP_CLKOUT2, VP_CLKIN2
238 */
239 0x4c 0x00111100 0x00ffff00
240 >;
241 };
242 };
243 prictrl: priority-controller@14110 {
244 compatible = "ti,da850-mstpri";
245 reg = <0x14110 0x0c>;
246 status = "disabled";
247 };
248 cfgchip: chip-controller@1417c {
249 compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
250 reg = <0x1417c 0x14>;
252 usb_phy: usb-phy {
253 compatible = "ti,da830-usb-phy";
254 #phy-cells = <1>;
255 status = "disabled";
256 };
257 };
258 edma0: edma@0 {
259 compatible = "ti,edma3-tpcc";
260 /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
261 reg = <0x0 0x8000>;
262 reg-names = "edma3_cc";
263 interrupts = <11 12>;
264 interrupt-names = "edma3_ccint", "edma3_ccerrint";
265 #dma-cells = <2>;
267 ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
268 };
269 edma0_tptc0: tptc@8000 {
270 compatible = "ti,edma3-tptc";
271 reg = <0x8000 0x400>;
272 interrupts = <13>;
273 interrupt-names = "edm3_tcerrint";
274 };
275 edma0_tptc1: tptc@8400 {
276 compatible = "ti,edma3-tptc";
277 reg = <0x8400 0x400>;
278 interrupts = <32>;
279 interrupt-names = "edm3_tcerrint";
280 };
281 edma1: edma@230000 {
282 compatible = "ti,edma3-tpcc";
283 /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
284 reg = <0x230000 0x8000>;
285 reg-names = "edma3_cc";
286 interrupts = <93 94>;
287 interrupt-names = "edma3_ccint", "edma3_ccerrint";
288 #dma-cells = <2>;
290 ti,tptcs = <&edma1_tptc0 7>;
291 };
292 edma1_tptc0: tptc@238000 {
293 compatible = "ti,edma3-tptc";
294 reg = <0x238000 0x400>;
295 interrupts = <95>;
296 interrupt-names = "edm3_tcerrint";
297 };
298 serial0: serial@42000 {
299 compatible = "ti,da830-uart", "ns16550a";
300 reg = <0x42000 0x100>;
301 reg-io-width = <4>;
302 reg-shift = <2>;
303 interrupts = <25>;
304 status = "disabled";
305 };
306 serial1: serial@10c000 {
307 compatible = "ti,da830-uart", "ns16550a";
308 reg = <0x10c000 0x100>;
309 reg-io-width = <4>;
310 reg-shift = <2>;
311 interrupts = <53>;
312 status = "disabled";
313 };
314 serial2: serial@10d000 {
315 compatible = "ti,da830-uart", "ns16550a";
316 reg = <0x10d000 0x100>;
317 reg-io-width = <4>;
318 reg-shift = <2>;
319 interrupts = <61>;
320 status = "disabled";
321 };
322 rtc0: rtc@23000 {
323 compatible = "ti,da830-rtc";
324 reg = <0x23000 0x1000>;
325 interrupts = <19
326 19>;
327 status = "disabled";
328 };
329 i2c0: i2c@22000 {
330 compatible = "ti,davinci-i2c";
331 reg = <0x22000 0x1000>;
332 interrupts = <15>;
333 #address-cells = <1>;
334 #size-cells = <0>;
335 status = "disabled";
336 };
337 i2c1: i2c@228000 {
338 compatible = "ti,davinci-i2c";
339 reg = <0x228000 0x1000>;
340 interrupts = <51>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 status = "disabled";
344 };
345 wdt: wdt@21000 {
346 compatible = "ti,davinci-wdt";
347 reg = <0x21000 0x1000>;
348 status = "disabled";
349 };
350 mmc0: mmc@40000 {
351 compatible = "ti,da830-mmc";
352 reg = <0x40000 0x1000>;
353 cap-sd-highspeed;
354 cap-mmc-highspeed;
355 interrupts = <16>;
356 dmas = <&edma0 16 0>, <&edma0 17 0>;
357 dma-names = "rx", "tx";
358 status = "disabled";
359 };
360 vpif: video@217000 {
361 compatible = "ti,da850-vpif";
362 reg = <0x217000 0x1000>;
363 interrupts = <92>;
364 status = "disabled";
366 /* VPIF capture port */
367 port@0 {
368 #address-cells = <1>;
369 #size-cells = <0>;
370 };
372 /* VPIF display port */
373 port@1 {
374 #address-cells = <1>;
375 #size-cells = <0>;
376 };
377 };
378 mmc1: mmc@21b000 {
379 compatible = "ti,da830-mmc";
380 reg = <0x21b000 0x1000>;
381 cap-sd-highspeed;
382 cap-mmc-highspeed;
383 interrupts = <72>;
384 dmas = <&edma1 28 0>, <&edma1 29 0>;
385 dma-names = "rx", "tx";
386 status = "disabled";
387 };
388 ehrpwm0: pwm@300000 {
389 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
390 "ti,am33xx-ehrpwm";
391 #pwm-cells = <3>;
392 reg = <0x300000 0x2000>;
393 status = "disabled";
394 };
395 ehrpwm1: pwm@302000 {
396 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
397 "ti,am33xx-ehrpwm";
398 #pwm-cells = <3>;
399 reg = <0x302000 0x2000>;
400 status = "disabled";
401 };
402 ecap0: ecap@306000 {
403 compatible = "ti,da850-ecap", "ti,am3352-ecap",
404 "ti,am33xx-ecap";
405 #pwm-cells = <3>;
406 reg = <0x306000 0x80>;
407 status = "disabled";
408 };
409 ecap1: ecap@307000 {
410 compatible = "ti,da850-ecap", "ti,am3352-ecap",
411 "ti,am33xx-ecap";
412 #pwm-cells = <3>;
413 reg = <0x307000 0x80>;
414 status = "disabled";
415 };
416 ecap2: ecap@308000 {
417 compatible = "ti,da850-ecap", "ti,am3352-ecap",
418 "ti,am33xx-ecap";
419 #pwm-cells = <3>;
420 reg = <0x308000 0x80>;
421 status = "disabled";
422 };
423 spi0: spi@41000 {
424 #address-cells = <1>;
425 #size-cells = <0>;
426 compatible = "ti,da830-spi";
427 reg = <0x41000 0x1000>;
428 num-cs = <6>;
429 ti,davinci-spi-intr-line = <1>;
430 interrupts = <20>;
431 dmas = <&edma0 14 0>, <&edma0 15 0>;
432 dma-names = "rx", "tx";
433 status = "disabled";
434 };
435 spi1: spi@30e000 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 compatible = "ti,da830-spi";
439 reg = <0x30e000 0x1000>;
440 num-cs = <4>;
441 ti,davinci-spi-intr-line = <1>;
442 interrupts = <56>;
443 dmas = <&edma0 18 0>, <&edma0 19 0>;
444 dma-names = "rx", "tx";
445 status = "disabled";
446 };
447 usb0: usb@200000 {
448 compatible = "ti,da830-musb";
449 reg = <0x200000 0x1000>;
450 ranges;
451 interrupts = <58>;
452 interrupt-names = "mc";
453 dr_mode = "otg";
454 phys = <&usb_phy 0>;
455 phy-names = "usb-phy";
456 status = "disabled";
458 #address-cells = <1>;
459 #size-cells = <1>;
461 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
462 &cppi41dma 2 0 &cppi41dma 3 0
463 &cppi41dma 0 1 &cppi41dma 1 1
464 &cppi41dma 2 1 &cppi41dma 3 1>;
465 dma-names =
466 "rx1", "rx2", "rx3", "rx4",
467 "tx1", "tx2", "tx3", "tx4";
469 cppi41dma: dma-controller@201000 {
470 compatible = "ti,da830-cppi41";
471 reg = <0x201000 0x1000
472 0x202000 0x1000
473 0x204000 0x4000>;
474 reg-names = "controller",
475 "scheduler", "queuemgr";
476 interrupts = <58>;
477 #dma-cells = <2>;
478 #dma-channels = <4>;
479 status = "okay";
480 };
481 };
482 sata: sata@218000 {
483 compatible = "ti,da850-ahci";
484 reg = <0x218000 0x2000>, <0x22c018 0x4>;
485 interrupts = <67>;
486 status = "disabled";
487 };
488 mdio: mdio@224000 {
489 compatible = "ti,davinci_mdio";
490 #address-cells = <1>;
491 #size-cells = <0>;
492 reg = <0x224000 0x1000>;
493 status = "disabled";
494 };
495 eth0: ethernet@220000 {
496 compatible = "ti,davinci-dm6467-emac";
497 reg = <0x220000 0x4000>;
498 ti,davinci-ctrl-reg-offset = <0x3000>;
499 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
500 ti,davinci-ctrl-ram-offset = <0>;
501 ti,davinci-ctrl-ram-size = <0x2000>;
502 local-mac-address = [ 00 00 00 00 00 00 ];
503 interrupts = <33
504 34
505 35
506 36
507 >;
508 status = "disabled";
509 };
510 usb1: usb@225000 {
511 compatible = "ti,da830-ohci";
512 reg = <0x225000 0x1000>;
513 interrupts = <59>;
514 phys = <&usb_phy 1>;
515 phy-names = "usb-phy";
516 status = "disabled";
517 };
518 gpio: gpio@226000 {
519 compatible = "ti,dm6441-gpio";
520 gpio-controller;
521 #gpio-cells = <2>;
522 reg = <0x226000 0x1000>;
523 interrupts = <42 IRQ_TYPE_EDGE_BOTH
524 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
525 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
526 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
527 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
528 ti,ngpio = <144>;
529 ti,davinci-gpio-unbanked = <0>;
530 status = "disabled";
531 interrupt-controller;
532 #interrupt-cells = <2>;
533 };
534 pinconf: pin-controller@22c00c {
535 compatible = "ti,da850-pupd";
536 reg = <0x22c00c 0x8>;
537 status = "disabled";
538 };
540 mcasp0: mcasp@100000 {
541 compatible = "ti,da830-mcasp-audio";
542 reg = <0x100000 0x2000>,
543 <0x102000 0x400000>;
544 reg-names = "mpu", "dat";
545 interrupts = <54>;
546 interrupt-names = "common";
547 status = "disabled";
548 dmas = <&edma0 1 1>,
549 <&edma0 0 1>;
550 dma-names = "tx", "rx";
551 };
553 lcdc: display@213000 {
554 compatible = "ti,da850-tilcdc";
555 reg = <0x213000 0x1000>;
556 interrupts = <52>;
557 max-pixelclock = <37500>;
558 status = "disabled";
559 };
560 };
561 aemif: aemif@68000000 {
562 compatible = "ti,da850-aemif";
563 #address-cells = <2>;
564 #size-cells = <1>;
566 reg = <0x68000000 0x00008000>;
567 ranges = <0 0 0x60000000 0x08000000
568 1 0 0x68000000 0x00008000>;
569 status = "disabled";
570 };
571 memctrl: memory-controller@b0000000 {
572 compatible = "ti,da850-ddr-controller";
573 reg = <0xb0000000 0xe8>;
574 status = "disabled";
575 };
576 };