| blob | 768fb075b1fd1b520b17f908e7797267200a1bde |
1 /*
2 * Samsung's Exynos4210 SoC device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
11 * bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
22 #include "exynos4.dtsi"
23 #include "exynos4210-pinctrl.dtsi"
24 #include "exynos4-cpu-thermal.dtsi"
26 / {
27 compatible = "samsung,exynos4210", "samsung,exynos4";
29 aliases {
30 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
32 pinctrl2 = &pinctrl_2;
33 };
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
39 cpu0: cpu@900 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a9";
42 reg = <0x900>;
43 clocks = <&clock CLK_ARM_CLK>;
44 clock-names = "cpu";
45 clock-latency = <160000>;
47 operating-points = <
48 1200000 1250000
49 1000000 1150000
50 800000 1075000
51 500000 975000
52 400000 975000
53 200000 950000
54 >;
55 cooling-min-level = <4>;
56 cooling-max-level = <2>;
57 #cooling-cells = <2>; /* min followed by max */
58 };
60 cpu@901 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a9";
63 reg = <0x901>;
64 };
65 };
67 sysram: sysram@02020000 {
68 compatible = "mmio-sram";
69 reg = <0x02020000 0x20000>;
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges = <0 0x02020000 0x20000>;
74 smp-sysram@0 {
75 compatible = "samsung,exynos4210-sysram";
76 reg = <0x0 0x1000>;
77 };
79 smp-sysram@1f000 {
80 compatible = "samsung,exynos4210-sysram-ns";
81 reg = <0x1f000 0x1000>;
82 };
83 };
85 pd_lcd1: lcd1-power-domain@10023CA0 {
86 compatible = "samsung,exynos4210-pd";
87 reg = <0x10023CA0 0x20>;
88 #power-domain-cells = <0>;
89 label = "LCD1";
90 };
92 l2c: l2-cache-controller@10502000 {
93 compatible = "arm,pl310-cache";
94 reg = <0x10502000 0x1000>;
95 cache-unified;
96 cache-level = <2>;
97 arm,tag-latency = <2 2 1>;
98 arm,data-latency = <2 2 1>;
99 };
101 mct: mct@10050000 {
102 compatible = "samsung,exynos4210-mct";
103 reg = <0x10050000 0x800>;
104 interrupt-parent = <&mct_map>;
105 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
106 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
107 clock-names = "fin_pll", "mct";
109 mct_map: mct-map {
110 #interrupt-cells = <1>;
111 #address-cells = <0>;
112 #size-cells = <0>;
113 interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
114 <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
115 <2 &combiner 12 6>,
116 <3 &combiner 12 7>,
117 <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
118 <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
119 };
120 };
122 watchdog: watchdog@10060000 {
123 compatible = "samsung,s3c6410-wdt";
124 reg = <0x10060000 0x100>;
125 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&clock CLK_WDT>;
127 clock-names = "watchdog";
128 };
130 clock: clock-controller@10030000 {
131 compatible = "samsung,exynos4210-clock";
132 reg = <0x10030000 0x20000>;
133 #clock-cells = <1>;
134 };
136 pinctrl_0: pinctrl@11400000 {
137 compatible = "samsung,exynos4210-pinctrl";
138 reg = <0x11400000 0x1000>;
139 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
140 };
142 pinctrl_1: pinctrl@11000000 {
143 compatible = "samsung,exynos4210-pinctrl";
144 reg = <0x11000000 0x1000>;
145 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
147 wakup_eint: wakeup-interrupt-controller {
148 compatible = "samsung,exynos4210-wakeup-eint";
149 interrupt-parent = <&gic>;
150 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
151 };
152 };
154 pinctrl_2: pinctrl@03860000 {
155 compatible = "samsung,exynos4210-pinctrl";
156 reg = <0x03860000 0x1000>;
157 };
159 tmu: tmu@100C0000 {
160 compatible = "samsung,exynos4210-tmu";
161 interrupt-parent = <&combiner>;
162 reg = <0x100C0000 0x100>;
163 interrupts = <2 4>;
164 clocks = <&clock CLK_TMU_APBIF>;
165 clock-names = "tmu_apbif";
166 samsung,tmu_gain = <15>;
167 samsung,tmu_reference_voltage = <7>;
168 status = "disabled";
169 };
171 thermal-zones {
172 cpu_thermal: cpu-thermal {
173 polling-delay-passive = <0>;
174 polling-delay = <0>;
175 thermal-sensors = <&tmu 0>;
177 trips {
178 cpu_alert0: cpu-alert-0 {
179 temperature = <85000>; /* millicelsius */
180 };
181 cpu_alert1: cpu-alert-1 {
182 temperature = <100000>; /* millicelsius */
183 };
184 cpu_alert2: cpu-alert-2 {
185 temperature = <110000>; /* millicelsius */
186 };
187 };
188 };
189 };
191 g2d: g2d@12800000 {
192 compatible = "samsung,s5pv210-g2d";
193 reg = <0x12800000 0x1000>;
194 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
196 clock-names = "sclk_fimg2d", "fimg2d";
197 power-domains = <&pd_lcd0>;
198 iommus = <&sysmmu_g2d>;
199 };
201 camera {
202 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
203 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
204 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
206 fimc_0: fimc@11800000 {
207 samsung,pix-limits = <4224 8192 1920 4224>;
208 samsung,mainscaler-ext;
209 samsung,cam-if;
210 };
212 fimc_1: fimc@11810000 {
213 samsung,pix-limits = <4224 8192 1920 4224>;
214 samsung,mainscaler-ext;
215 samsung,cam-if;
216 };
218 fimc_2: fimc@11820000 {
219 samsung,pix-limits = <4224 8192 1920 4224>;
220 samsung,mainscaler-ext;
221 samsung,lcd-wb;
222 };
224 fimc_3: fimc@11830000 {
225 samsung,pix-limits = <1920 8192 1366 1920>;
226 samsung,rotators = <0>;
227 samsung,mainscaler-ext;
228 samsung,lcd-wb;
229 };
230 };
232 mixer: mixer@12C10000 {
233 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
234 "sclk_mixer";
235 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
236 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
237 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
238 };
240 ppmu_lcd1: ppmu_lcd1@12240000 {
241 compatible = "samsung,exynos-ppmu";
242 reg = <0x12240000 0x2000>;
243 clocks = <&clock CLK_PPMULCD1>;
244 clock-names = "ppmu";
245 status = "disabled";
246 };
248 sysmmu_g2d: sysmmu@12A20000 {
249 compatible = "samsung,exynos-sysmmu";
250 reg = <0x12A20000 0x1000>;
251 interrupt-parent = <&combiner>;
252 interrupts = <4 7>;
253 clock-names = "sysmmu", "master";
254 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
255 power-domains = <&pd_lcd0>;
256 #iommu-cells = <0>;
257 };
259 sysmmu_fimd1: sysmmu@12220000 {
260 compatible = "samsung,exynos-sysmmu";
261 interrupt-parent = <&combiner>;
262 reg = <0x12220000 0x1000>;
263 interrupts = <5 3>;
264 clock-names = "sysmmu", "master";
265 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
266 power-domains = <&pd_lcd1>;
267 #iommu-cells = <0>;
268 };
270 bus_dmc: bus_dmc {
271 compatible = "samsung,exynos-bus";
272 clocks = <&clock CLK_DIV_DMC>;
273 clock-names = "bus";
274 operating-points-v2 = <&bus_dmc_opp_table>;
275 status = "disabled";
276 };
278 bus_acp: bus_acp {
279 compatible = "samsung,exynos-bus";
280 clocks = <&clock CLK_DIV_ACP>;
281 clock-names = "bus";
282 operating-points-v2 = <&bus_acp_opp_table>;
283 status = "disabled";
284 };
286 bus_peri: bus_peri {
287 compatible = "samsung,exynos-bus";
288 clocks = <&clock CLK_ACLK100>;
289 clock-names = "bus";
290 operating-points-v2 = <&bus_peri_opp_table>;
291 status = "disabled";
292 };
294 bus_fsys: bus_fsys {
295 compatible = "samsung,exynos-bus";
296 clocks = <&clock CLK_ACLK133>;
297 clock-names = "bus";
298 operating-points-v2 = <&bus_fsys_opp_table>;
299 status = "disabled";
300 };
302 bus_display: bus_display {
303 compatible = "samsung,exynos-bus";
304 clocks = <&clock CLK_ACLK160>;
305 clock-names = "bus";
306 operating-points-v2 = <&bus_display_opp_table>;
307 status = "disabled";
308 };
310 bus_lcd0: bus_lcd0 {
311 compatible = "samsung,exynos-bus";
312 clocks = <&clock CLK_ACLK200>;
313 clock-names = "bus";
314 operating-points-v2 = <&bus_leftbus_opp_table>;
315 status = "disabled";
316 };
318 bus_leftbus: bus_leftbus {
319 compatible = "samsung,exynos-bus";
320 clocks = <&clock CLK_DIV_GDL>;
321 clock-names = "bus";
322 operating-points-v2 = <&bus_leftbus_opp_table>;
323 status = "disabled";
324 };
326 bus_rightbus: bus_rightbus {
327 compatible = "samsung,exynos-bus";
328 clocks = <&clock CLK_DIV_GDR>;
329 clock-names = "bus";
330 operating-points-v2 = <&bus_leftbus_opp_table>;
331 status = "disabled";
332 };
334 bus_mfc: bus_mfc {
335 compatible = "samsung,exynos-bus";
336 clocks = <&clock CLK_SCLK_MFC>;
337 clock-names = "bus";
338 operating-points-v2 = <&bus_leftbus_opp_table>;
339 status = "disabled";
340 };
342 bus_dmc_opp_table: opp_table1 {
343 compatible = "operating-points-v2";
344 opp-shared;
346 opp-134000000 {
347 opp-hz = /bits/ 64 <134000000>;
348 opp-microvolt = <1025000>;
349 };
350 opp-267000000 {
351 opp-hz = /bits/ 64 <267000000>;
352 opp-microvolt = <1050000>;
353 };
354 opp-400000000 {
355 opp-hz = /bits/ 64 <400000000>;
356 opp-microvolt = <1150000>;
357 };
358 };
360 bus_acp_opp_table: opp_table2 {
361 compatible = "operating-points-v2";
362 opp-shared;
364 opp-134000000 {
365 opp-hz = /bits/ 64 <134000000>;
366 };
367 opp-160000000 {
368 opp-hz = /bits/ 64 <160000000>;
369 };
370 opp-200000000 {
371 opp-hz = /bits/ 64 <200000000>;
372 };
373 };
375 bus_peri_opp_table: opp_table3 {
376 compatible = "operating-points-v2";
377 opp-shared;
379 opp-5000000 {
380 opp-hz = /bits/ 64 <5000000>;
381 };
382 opp-100000000 {
383 opp-hz = /bits/ 64 <100000000>;
384 };
385 };
387 bus_fsys_opp_table: opp_table4 {
388 compatible = "operating-points-v2";
389 opp-shared;
391 opp-10000000 {
392 opp-hz = /bits/ 64 <10000000>;
393 };
394 opp-134000000 {
395 opp-hz = /bits/ 64 <134000000>;
396 };
397 };
399 bus_display_opp_table: opp_table5 {
400 compatible = "operating-points-v2";
401 opp-shared;
403 opp-100000000 {
404 opp-hz = /bits/ 64 <100000000>;
405 };
406 opp-134000000 {
407 opp-hz = /bits/ 64 <134000000>;
408 };
409 opp-160000000 {
410 opp-hz = /bits/ 64 <160000000>;
411 };
412 };
414 bus_leftbus_opp_table: opp_table6 {
415 compatible = "operating-points-v2";
416 opp-shared;
418 opp-100000000 {
419 opp-hz = /bits/ 64 <100000000>;
420 };
421 opp-160000000 {
422 opp-hz = /bits/ 64 <160000000>;
423 };
424 opp-200000000 {
425 opp-hz = /bits/ 64 <200000000>;
426 };
427 };
428 };
430 &gic {
431 cpu-offset = <0x8000>;
432 };
434 &combiner {
435 samsung,combiner-nr = <16>;
436 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
452 };
454 &mdma1 {
455 power-domains = <&pd_lcd0>;
456 };
458 &pmu_system_controller {
459 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
460 "clkout4", "clkout8", "clkout9";
461 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
462 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
463 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
464 #clock-cells = <1>;
465 };
467 &rotator {
468 power-domains = <&pd_lcd0>;
469 };
471 &sysmmu_rotator {
472 power-domains = <&pd_lcd0>;
473 };