| blob | c68e8d430234c3824198d46b336f0d689cf38611 |
1 /*
2 * Device Tree file for Cortina systems Gemini SoC
3 */
5 /include/ "skeleton.dtsi"
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/cortina,gemini-clock.h>
9 #include <dt-bindings/reset/cortina,gemini-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
12 / {
13 soc {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges;
17 compatible = "simple-bus";
18 interrupt-parent = <&intcon>;
20 flash@30000000 {
21 compatible = "cortina,gemini-flash", "cfi-flash";
22 syscon = <&syscon>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&pflash_default_pins>;
25 bank-width = <2>;
26 #address-cells = <1>;
27 #size-cells = <1>;
28 status = "disabled";
29 };
31 syscon: syscon@40000000 {
32 compatible = "cortina,gemini-syscon",
33 "syscon", "simple-mfd";
34 reg = <0x40000000 0x1000>;
35 #clock-cells = <1>;
36 #reset-cells = <1>;
38 syscon-reboot {
39 compatible = "syscon-reboot";
40 regmap = <&syscon>;
41 /* GLOBAL_RESET register */
42 offset = <0x0c>;
43 /* RESET_GLOBAL | RESET_CPU1 */
44 mask = <0xC0000000>;
45 };
47 pinctrl {
48 compatible = "cortina,gemini-pinctrl";
49 regmap = <&syscon>;
50 /* Hog the DRAM pins */
51 pinctrl-names = "default";
52 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
53 <&vcontrol_default_pins>;
55 dram_default_pins: pinctrl-dram {
56 mux {
57 function = "dram";
58 groups = "dramgrp";
59 };
60 };
61 rtc_default_pins: pinctrl-rtc {
62 mux {
63 function = "rtc";
64 groups = "rtcgrp";
65 };
66 };
67 power_default_pins: pinctrl-power {
68 mux {
69 function = "power";
70 groups = "powergrp";
71 };
72 };
73 cir_default_pins: pinctrl-cir {
74 mux {
75 function = "cir";
76 groups = "cirgrp";
77 };
78 };
79 system_default_pins: pinctrl-system {
80 mux {
81 function = "system";
82 groups = "systemgrp";
83 };
84 };
85 vcontrol_default_pins: pinctrl-vcontrol {
86 mux {
87 function = "vcontrol";
88 groups = "vcontrolgrp";
89 };
90 };
91 ice_default_pins: pinctrl-ice {
92 mux {
93 function = "ice";
94 groups = "icegrp";
95 };
96 };
97 uart_default_pins: pinctrl-uart {
98 mux {
99 function = "uart";
100 groups = "uartrxtxgrp";
101 };
102 };
103 pflash_default_pins: pinctrl-pflash {
104 mux {
105 function = "pflash";
106 groups = "pflashgrp";
107 };
108 };
109 usb_default_pins: pinctrl-usb {
110 mux {
111 function = "usb";
112 groups = "usbgrp";
113 };
114 };
115 gmii_default_pins: pinctrl-gmii {
116 mux {
117 function = "gmii";
118 groups = "gmiigrp";
119 };
120 };
121 pci_default_pins: pinctrl-pci {
122 mux {
123 function = "pci";
124 groups = "pcigrp";
125 };
126 };
127 sata_default_pins: pinctrl-sata {
128 mux {
129 function = "sata";
130 groups = "satagrp";
131 };
132 };
133 /* Activate both groups of pins for this state */
134 sata_and_ide_pins: pinctrl-sata-ide {
135 mux0 {
136 function = "sata";
137 groups = "satagrp";
138 };
139 mux1 {
140 function = "ide";
141 groups = "idegrp";
142 };
143 };
144 };
145 };
147 watchdog@41000000 {
148 compatible = "cortina,gemini-watchdog";
149 reg = <0x41000000 0x1000>;
150 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
151 resets = <&syscon GEMINI_RESET_WDOG>;
152 clocks = <&syscon GEMINI_CLK_APB>;
153 };
155 uart0: serial@42000000 {
156 compatible = "ns16550a";
157 reg = <0x42000000 0x100>;
158 resets = <&syscon GEMINI_RESET_UART>;
159 clocks = <&syscon GEMINI_CLK_UART>;
160 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&uart_default_pins>;
163 reg-shift = <2>;
164 };
166 timer@43000000 {
167 compatible = "faraday,fttmr010";
168 reg = <0x43000000 0x1000>;
169 interrupt-parent = <&intcon>;
170 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
171 <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
172 <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
173 resets = <&syscon GEMINI_RESET_TIMER>;
174 /* APB clock or RTC clock */
175 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
176 clock-names = "PCLK", "EXTCLK";
177 syscon = <&syscon>;
178 };
180 rtc@45000000 {
181 compatible = "cortina,gemini-rtc";
182 reg = <0x45000000 0x100>;
183 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
184 resets = <&syscon GEMINI_RESET_RTC>;
185 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
186 clock-names = "PCLK", "EXTCLK";
187 pinctrl-names = "default";
188 pinctrl-0 = <&rtc_default_pins>;
189 };
191 sata: sata@46000000 {
192 compatible = "cortina,gemini-sata-bridge";
193 reg = <0x46000000 0x100>;
194 resets = <&syscon GEMINI_RESET_SATA0>,
195 <&syscon GEMINI_RESET_SATA1>;
196 reset-names = "sata0", "sata1";
197 clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
198 <&syscon GEMINI_CLK_GATE_SATA1>;
199 clock-names = "SATA0_PCLK", "SATA1_PCLK";
200 /*
201 * This defines the special "ide" state that needs
202 * to be explicitly enabled to enable the IDE pins,
203 * as these pins are normally used for other things.
204 */
205 pinctrl-names = "default", "ide";
206 pinctrl-0 = <&sata_default_pins>;
207 pinctrl-1 = <&sata_and_ide_pins>;
208 syscon = <&syscon>;
209 status = "disabled";
210 };
212 intcon: interrupt-controller@48000000 {
213 compatible = "faraday,ftintc010";
214 reg = <0x48000000 0x1000>;
215 resets = <&syscon GEMINI_RESET_INTCON0>;
216 interrupt-controller;
217 #interrupt-cells = <2>;
218 };
220 power-controller@4b000000 {
221 compatible = "cortina,gemini-power-controller";
222 reg = <0x4b000000 0x100>;
223 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&power_default_pins>;
226 };
228 gpio0: gpio@4d000000 {
229 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
230 reg = <0x4d000000 0x100>;
231 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
232 resets = <&syscon GEMINI_RESET_GPIO0>;
233 clocks = <&syscon GEMINI_CLK_APB>;
234 gpio-controller;
235 #gpio-cells = <2>;
236 interrupt-controller;
237 #interrupt-cells = <2>;
238 };
240 gpio1: gpio@4e000000 {
241 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
242 reg = <0x4e000000 0x100>;
243 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
244 resets = <&syscon GEMINI_RESET_GPIO1>;
245 clocks = <&syscon GEMINI_CLK_APB>;
246 gpio-controller;
247 #gpio-cells = <2>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
250 };
252 gpio2: gpio@4f000000 {
253 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
254 reg = <0x4f000000 0x100>;
255 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
256 resets = <&syscon GEMINI_RESET_GPIO2>;
257 clocks = <&syscon GEMINI_CLK_APB>;
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-controller;
261 #interrupt-cells = <2>;
262 };
264 pci@50000000 {
265 compatible = "cortina,gemini-pci", "faraday,ftpci100";
266 /*
267 * The first 256 bytes in the IO range is actually used
268 * to configure the host bridge.
269 */
270 reg = <0x50000000 0x100>;
271 resets = <&syscon GEMINI_RESET_PCI>;
272 clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
273 clock-names = "PCLK", "PCICLK";
274 pinctrl-names = "default";
275 pinctrl-0 = <&pci_default_pins>;
276 #address-cells = <3>;
277 #size-cells = <2>;
278 #interrupt-cells = <1>;
279 status = "disabled";
281 bus-range = <0x00 0xff>;
282 /* PCI ranges mappings */
283 ranges =
284 /* 1MiB I/O space 0x50000000-0x500fffff */
285 <0x01000000 0 0 0x50000000 0 0x00100000>,
286 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
287 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
289 /* DMA ranges */
290 dma-ranges =
291 /* 128MiB at 0x00000000-0x07ffffff */
292 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
293 /* 64MiB at 0x00000000-0x03ffffff */
294 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
295 /* 64MiB at 0x00000000-0x03ffffff */
296 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
298 /*
299 * This PCI host bridge variant has a cascaded interrupt
300 * controller embedded in the host bridge.
301 */
302 pci_intc: interrupt-controller {
303 interrupt-parent = <&intcon>;
304 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-controller;
306 #address-cells = <0>;
307 #interrupt-cells = <1>;
308 };
309 };
311 ata@63000000 {
312 compatible = "cortina,gemini-pata", "faraday,ftide010";
313 reg = <0x63000000 0x1000>;
314 interrupts = <4 IRQ_TYPE_EDGE_RISING>;
315 resets = <&syscon GEMINI_RESET_IDE>;
316 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
317 clock-names = "PCLK";
318 sata = <&sata>;
319 status = "disabled";
320 };
322 ata@63400000 {
323 compatible = "cortina,gemini-pata", "faraday,ftide010";
324 reg = <0x63400000 0x1000>;
325 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
326 resets = <&syscon GEMINI_RESET_IDE>;
327 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
328 clock-names = "PCLK";
329 sata = <&sata>;
330 status = "disabled";
331 };
333 dma-controller@67000000 {
334 compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
335 /* Faraday Technology FTDMAC020 variant */
336 arm,primecell-periphid = <0x0003b080>;
337 reg = <0x67000000 0x1000>;
338 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
339 resets = <&syscon GEMINI_RESET_DMAC>;
340 clocks = <&syscon GEMINI_CLK_AHB>;
341 clock-names = "apb_pclk";
342 /* Bus interface AHB1 (AHB0) is totally tilted */
343 lli-bus-interface-ahb2;
344 mem-bus-interface-ahb2;
345 memcpy-burst-size = <256>;
346 memcpy-bus-width = <32>;
347 #dma-cells = <2>;
348 };
349 };
350 };