| blob | 3747d80104f4530226638a9051e18ba14f457701 |
1 /*
2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
14 #include "imx50-pinfunc.h"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/imx5-clock.h>
18 / {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 /*
22 * The decompressor and also some bootloaders rely on a
23 * pre-existing /chosen node to be available to insert the
24 * command line and merge other ATAGS info.
25 * Also for U-Boot there must be a pre-existing /memory node.
26 */
27 chosen {};
28 memory { device_type = "memory"; reg = <0 0>; };
30 aliases {
31 ethernet0 = &fec;
32 gpio0 = &gpio1;
33 gpio1 = &gpio2;
34 gpio2 = &gpio3;
35 gpio3 = &gpio4;
36 gpio4 = &gpio5;
37 gpio5 = &gpio6;
38 serial0 = &uart1;
39 serial1 = &uart2;
40 serial2 = &uart3;
41 serial3 = &uart4;
42 serial4 = &uart5;
43 };
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a8";
51 reg = <0x0>;
52 };
53 };
55 tzic: tz-interrupt-controller@0fffc000 {
56 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
57 interrupt-controller;
58 #interrupt-cells = <1>;
59 reg = <0x0fffc000 0x4000>;
60 };
62 clocks {
63 #address-cells = <1>;
64 #size-cells = <0>;
66 ckil {
67 compatible = "fsl,imx-ckil", "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <32768>;
70 };
72 ckih1 {
73 compatible = "fsl,imx-ckih1", "fixed-clock";
74 #clock-cells = <0>;
75 clock-frequency = <22579200>;
76 };
78 ckih2 {
79 compatible = "fsl,imx-ckih2", "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <0>;
82 };
84 osc {
85 compatible = "fsl,imx-osc", "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <24000000>;
88 };
89 };
91 soc {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "simple-bus";
95 interrupt-parent = <&tzic>;
96 ranges;
98 aips@50000000 { /* AIPS1 */
99 compatible = "fsl,aips-bus", "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 reg = <0x50000000 0x10000000>;
103 ranges;
105 spba@50000000 {
106 compatible = "fsl,spba-bus", "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 reg = <0x50000000 0x40000>;
110 ranges;
112 esdhc1: esdhc@50004000 {
113 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
114 reg = <0x50004000 0x4000>;
115 interrupts = <1>;
116 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
117 <&clks IMX5_CLK_DUMMY>,
118 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
119 clock-names = "ipg", "ahb", "per";
120 bus-width = <4>;
121 status = "disabled";
122 };
124 esdhc2: esdhc@50008000 {
125 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
126 reg = <0x50008000 0x4000>;
127 interrupts = <2>;
128 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
129 <&clks IMX5_CLK_DUMMY>,
130 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
131 clock-names = "ipg", "ahb", "per";
132 bus-width = <4>;
133 status = "disabled";
134 };
136 uart3: serial@5000c000 {
137 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
138 reg = <0x5000c000 0x4000>;
139 interrupts = <33>;
140 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
141 <&clks IMX5_CLK_UART3_PER_GATE>;
142 clock-names = "ipg", "per";
143 status = "disabled";
144 };
146 ecspi1: ecspi@50010000 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
150 reg = <0x50010000 0x4000>;
151 interrupts = <36>;
152 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
153 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
154 clock-names = "ipg", "per";
155 status = "disabled";
156 };
158 ssi2: ssi@50014000 {
159 #sound-dai-cells = <0>;
160 compatible = "fsl,imx50-ssi",
161 "fsl,imx51-ssi",
162 "fsl,imx21-ssi";
163 reg = <0x50014000 0x4000>;
164 interrupts = <30>;
165 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
166 dmas = <&sdma 24 1 0>,
167 <&sdma 25 1 0>;
168 dma-names = "rx", "tx";
169 fsl,fifo-depth = <15>;
170 status = "disabled";
171 };
173 esdhc3: esdhc@50020000 {
174 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
175 reg = <0x50020000 0x4000>;
176 interrupts = <3>;
177 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
178 <&clks IMX5_CLK_DUMMY>,
179 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
180 clock-names = "ipg", "ahb", "per";
181 bus-width = <4>;
182 status = "disabled";
183 };
185 esdhc4: esdhc@50024000 {
186 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
187 reg = <0x50024000 0x4000>;
188 interrupts = <4>;
189 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
190 <&clks IMX5_CLK_DUMMY>,
191 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
192 clock-names = "ipg", "ahb", "per";
193 bus-width = <4>;
194 status = "disabled";
195 };
196 };
198 usbotg: usb@53f80000 {
199 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
200 reg = <0x53f80000 0x0200>;
201 interrupts = <18>;
202 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
203 status = "disabled";
204 };
206 usbh1: usb@53f80200 {
207 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
208 reg = <0x53f80200 0x0200>;
209 interrupts = <14>;
210 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
211 dr_mode = "host";
212 status = "disabled";
213 };
215 usbh2: usb@53f80400 {
216 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
217 reg = <0x53f80400 0x0200>;
218 interrupts = <16>;
219 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
220 dr_mode = "host";
221 status = "disabled";
222 };
224 usbh3: usb@53f80600 {
225 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
226 reg = <0x53f80600 0x0200>;
227 interrupts = <17>;
228 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
229 dr_mode = "host";
230 status = "disabled";
231 };
233 gpio1: gpio@53f84000 {
234 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
235 reg = <0x53f84000 0x4000>;
236 interrupts = <50 51>;
237 gpio-controller;
238 #gpio-cells = <2>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
241 gpio-ranges = <&iomuxc 0 151 28>;
242 };
244 gpio2: gpio@53f88000 {
245 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
246 reg = <0x53f88000 0x4000>;
247 interrupts = <52 53>;
248 gpio-controller;
249 #gpio-cells = <2>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
253 <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
254 <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
255 <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
256 };
258 gpio3: gpio@53f8c000 {
259 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
260 reg = <0x53f8c000 0x4000>;
261 interrupts = <54 55>;
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
266 gpio-ranges = <&iomuxc 0 108 32>;
267 };
269 gpio4: gpio@53f90000 {
270 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
271 reg = <0x53f90000 0x4000>;
272 interrupts = <56 57>;
273 gpio-controller;
274 #gpio-cells = <2>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
278 <&iomuxc 20 140 11>;
279 };
281 wdog1: wdog@53f98000 {
282 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
283 reg = <0x53f98000 0x4000>;
284 interrupts = <58>;
285 clocks = <&clks IMX5_CLK_DUMMY>;
286 };
288 gpt: timer@53fa0000 {
289 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
290 reg = <0x53fa0000 0x4000>;
291 interrupts = <39>;
292 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
293 <&clks IMX5_CLK_GPT_HF_GATE>;
294 clock-names = "ipg", "per";
295 };
297 iomuxc: iomuxc@53fa8000 {
298 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
299 reg = <0x53fa8000 0x4000>;
300 };
302 gpr: iomuxc-gpr@53fa8000 {
303 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
304 reg = <0x53fa8000 0xc>;
305 };
307 pwm1: pwm@53fb4000 {
308 #pwm-cells = <2>;
309 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
310 reg = <0x53fb4000 0x4000>;
311 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
312 <&clks IMX5_CLK_PWM1_HF_GATE>;
313 clock-names = "ipg", "per";
314 interrupts = <61>;
315 };
317 pwm2: pwm@53fb8000 {
318 #pwm-cells = <2>;
319 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
320 reg = <0x53fb8000 0x4000>;
321 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
322 <&clks IMX5_CLK_PWM2_HF_GATE>;
323 clock-names = "ipg", "per";
324 interrupts = <94>;
325 };
327 uart1: serial@53fbc000 {
328 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
329 reg = <0x53fbc000 0x4000>;
330 interrupts = <31>;
331 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
332 <&clks IMX5_CLK_UART1_PER_GATE>;
333 clock-names = "ipg", "per";
334 status = "disabled";
335 };
337 uart2: serial@53fc0000 {
338 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
339 reg = <0x53fc0000 0x4000>;
340 interrupts = <32>;
341 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
342 <&clks IMX5_CLK_UART2_PER_GATE>;
343 clock-names = "ipg", "per";
344 status = "disabled";
345 };
347 src: src@53fd0000 {
348 compatible = "fsl,imx50-src", "fsl,imx51-src";
349 reg = <0x53fd0000 0x4000>;
350 #reset-cells = <1>;
351 };
353 clks: ccm@53fd4000{
354 compatible = "fsl,imx50-ccm";
355 reg = <0x53fd4000 0x4000>;
356 interrupts = <0 71 0x04 0 72 0x04>;
357 #clock-cells = <1>;
358 };
360 gpio5: gpio@53fdc000 {
361 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
362 reg = <0x53fdc000 0x4000>;
363 interrupts = <103 104>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
369 };
371 gpio6: gpio@53fe0000 {
372 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
373 reg = <0x53fe0000 0x4000>;
374 interrupts = <105 106>;
375 gpio-controller;
376 #gpio-cells = <2>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
380 };
382 i2c3: i2c@53fec000 {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
386 reg = <0x53fec000 0x4000>;
387 interrupts = <64>;
388 clocks = <&clks IMX5_CLK_I2C3_GATE>;
389 status = "disabled";
390 };
392 uart4: serial@53ff0000 {
393 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
394 reg = <0x53ff0000 0x4000>;
395 interrupts = <13>;
396 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
397 <&clks IMX5_CLK_UART4_PER_GATE>;
398 clock-names = "ipg", "per";
399 status = "disabled";
400 };
401 };
403 aips@60000000 { /* AIPS2 */
404 compatible = "fsl,aips-bus", "simple-bus";
405 #address-cells = <1>;
406 #size-cells = <1>;
407 reg = <0x60000000 0x10000000>;
408 ranges;
410 uart5: serial@63f90000 {
411 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
412 reg = <0x63f90000 0x4000>;
413 interrupts = <86>;
414 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
415 <&clks IMX5_CLK_UART5_PER_GATE>;
416 clock-names = "ipg", "per";
417 status = "disabled";
418 };
420 owire: owire@63fa4000 {
421 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
422 reg = <0x63fa4000 0x4000>;
423 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
424 status = "disabled";
425 };
427 ecspi2: ecspi@63fac000 {
428 #address-cells = <1>;
429 #size-cells = <0>;
430 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
431 reg = <0x63fac000 0x4000>;
432 interrupts = <37>;
433 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
434 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
435 clock-names = "ipg", "per";
436 status = "disabled";
437 };
439 sdma: sdma@63fb0000 {
440 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
441 reg = <0x63fb0000 0x4000>;
442 interrupts = <6>;
443 clocks = <&clks IMX5_CLK_SDMA_GATE>,
444 <&clks IMX5_CLK_SDMA_GATE>;
445 clock-names = "ipg", "ahb";
446 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
447 };
449 cspi: cspi@63fc0000 {
450 #address-cells = <1>;
451 #size-cells = <0>;
452 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
453 reg = <0x63fc0000 0x4000>;
454 interrupts = <38>;
455 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
456 <&clks IMX5_CLK_CSPI_IPG_GATE>;
457 clock-names = "ipg", "per";
458 status = "disabled";
459 };
461 i2c2: i2c@63fc4000 {
462 #address-cells = <1>;
463 #size-cells = <0>;
464 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
465 reg = <0x63fc4000 0x4000>;
466 interrupts = <63>;
467 clocks = <&clks IMX5_CLK_I2C2_GATE>;
468 status = "disabled";
469 };
471 i2c1: i2c@63fc8000 {
472 #address-cells = <1>;
473 #size-cells = <0>;
474 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
475 reg = <0x63fc8000 0x4000>;
476 interrupts = <62>;
477 clocks = <&clks IMX5_CLK_I2C1_GATE>;
478 status = "disabled";
479 };
481 ssi1: ssi@63fcc000 {
482 #sound-dai-cells = <0>;
483 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
484 "fsl,imx21-ssi";
485 reg = <0x63fcc000 0x4000>;
486 interrupts = <29>;
487 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
488 dmas = <&sdma 28 0 0>,
489 <&sdma 29 0 0>;
490 dma-names = "rx", "tx";
491 fsl,fifo-depth = <15>;
492 status = "disabled";
493 };
495 audmux: audmux@63fd0000 {
496 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
497 reg = <0x63fd0000 0x4000>;
498 status = "disabled";
499 };
501 fec: ethernet@63fec000 {
502 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
503 reg = <0x63fec000 0x4000>;
504 interrupts = <87>;
505 clocks = <&clks IMX5_CLK_FEC_GATE>,
506 <&clks IMX5_CLK_FEC_GATE>,
507 <&clks IMX5_CLK_FEC_GATE>;
508 clock-names = "ipg", "ahb", "ptp";
509 status = "disabled";
510 };
511 };
512 };
513 };