| blob | 6a7594e5d183f92c5ed7df23466d2e4bc3e508f2 |
1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
13 #include <dt-bindings/gpio/gpio.h>
15 / {
16 memory {
17 reg = <0x10000000 0x80000000>;
18 };
20 leds {
21 compatible = "gpio-leds";
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_gpio_leds>;
25 user {
26 label = "debug";
27 gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
28 };
29 };
31 clocks {
32 codec_osc: anaclk2 {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <24576000>;
36 };
37 };
39 regulators {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <0>;
44 reg_audio: regulator@0 {
45 compatible = "regulator-fixed";
46 reg = <0>;
47 regulator-name = "cs42888_supply";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 regulator-always-on;
51 };
53 reg_usb_h1_vbus: regulator@1 {
54 compatible = "regulator-fixed";
55 reg = <1>;
56 regulator-name = "usb_h1_vbus";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
59 gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
60 enable-active-high;
61 };
63 reg_usb_otg_vbus: regulator@2 {
64 compatible = "regulator-fixed";
65 reg = <2>;
66 regulator-name = "usb_otg_vbus";
67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>;
69 gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
70 enable-active-high;
71 };
72 };
74 sound-cs42888 {
75 compatible = "fsl,imx6-sabreauto-cs42888",
76 "fsl,imx-audio-cs42888";
77 model = "imx-cs42888";
78 audio-cpu = <&esai>;
79 audio-asrc = <&asrc>;
80 audio-codec = <&codec>;
81 audio-routing =
82 "Line Out Jack", "AOUT1L",
83 "Line Out Jack", "AOUT1R",
84 "Line Out Jack", "AOUT2L",
85 "Line Out Jack", "AOUT2R",
86 "Line Out Jack", "AOUT3L",
87 "Line Out Jack", "AOUT3R",
88 "Line Out Jack", "AOUT4L",
89 "Line Out Jack", "AOUT4R",
90 "AIN1L", "Line In Jack",
91 "AIN1R", "Line In Jack",
92 "AIN2L", "Line In Jack",
93 "AIN2R", "Line In Jack";
94 };
96 sound-spdif {
97 compatible = "fsl,imx-audio-spdif",
98 "fsl,imx-sabreauto-spdif";
99 model = "imx-spdif";
100 spdif-controller = <&spdif>;
101 spdif-in;
102 };
104 backlight {
105 compatible = "pwm-backlight";
106 pwms = <&pwm3 0 5000000>;
107 brightness-levels = <0 4 8 16 32 64 128 255>;
108 default-brightness-level = <7>;
109 status = "okay";
110 };
112 i2cmux {
113 compatible = "i2c-mux-gpio";
114 #address-cells = <1>;
115 #size-cells = <0>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c3mux>;
118 mux-gpios = <&gpio5 4 0>;
119 i2c-parent = <&i2c3>;
120 idle-state = <0>;
122 i2c@1 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 reg = <1>;
127 adv7180: camera@21 {
128 compatible = "adi,adv7180";
129 reg = <0x21>;
130 powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
131 interrupt-parent = <&gpio1>;
132 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
134 port {
135 adv7180_to_ipu1_csi0_mux: endpoint {
136 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
137 bus-width = <8>;
138 };
139 };
140 };
142 max7310_a: gpio@30 {
143 compatible = "maxim,max7310";
144 reg = <0x30>;
145 gpio-controller;
146 #gpio-cells = <2>;
147 };
149 max7310_b: gpio@32 {
150 compatible = "maxim,max7310";
151 reg = <0x32>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_max7310>;
156 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
157 };
159 max7310_c: gpio@34 {
160 compatible = "maxim,max7310";
161 reg = <0x34>;
162 gpio-controller;
163 #gpio-cells = <2>;
164 };
165 };
166 };
167 };
169 &ipu1_csi0_from_ipu1_csi0_mux {
170 bus-width = <8>;
171 };
173 &ipu1_csi0_mux_from_parallel_sensor {
174 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
175 bus-width = <8>;
176 };
178 &ipu1_csi0 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_ipu1_csi0>;
181 };
183 &clks {
184 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
185 <&clks IMX6QDL_PLL4_BYPASS>,
186 <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
187 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
188 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
189 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
190 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
191 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
192 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
193 assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
194 };
196 &ecspi1 {
197 cs-gpios = <&gpio3 19 0>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
200 status = "disabled"; /* pin conflict with WEIM NOR */
202 flash: m25p80@0 {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "st,m25p32", "jedec,spi-nor";
206 spi-max-frequency = <20000000>;
207 reg = <0>;
208 };
209 };
211 &esai {
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_esai>;
214 assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
215 <&clks IMX6QDL_CLK_ESAI_EXTAL>;
216 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
217 assigned-clock-rates = <0>, <24576000>;
218 status = "okay";
219 };
221 &fec {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_enet>;
224 phy-mode = "rgmii";
225 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
226 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
227 fsl,err006687-workaround-present;
228 status = "okay";
229 };
231 &gpmi {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_gpmi_nand>;
234 status = "okay";
235 };
237 &hdmi {
238 status = "okay";
239 };
241 &i2c2 {
242 clock-frequency = <100000>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_i2c2>;
245 status = "okay";
247 pmic: pfuze100@08 {
248 compatible = "fsl,pfuze100";
249 reg = <0x08>;
251 regulators {
252 sw1a_reg: sw1ab {
253 regulator-min-microvolt = <300000>;
254 regulator-max-microvolt = <1875000>;
255 regulator-boot-on;
256 regulator-always-on;
257 regulator-ramp-delay = <6250>;
258 };
260 sw1c_reg: sw1c {
261 regulator-min-microvolt = <300000>;
262 regulator-max-microvolt = <1875000>;
263 regulator-boot-on;
264 regulator-always-on;
265 regulator-ramp-delay = <6250>;
266 };
268 sw2_reg: sw2 {
269 regulator-min-microvolt = <800000>;
270 regulator-max-microvolt = <3300000>;
271 regulator-boot-on;
272 regulator-always-on;
273 };
275 sw3a_reg: sw3a {
276 regulator-min-microvolt = <400000>;
277 regulator-max-microvolt = <1975000>;
278 regulator-boot-on;
279 regulator-always-on;
280 };
282 sw3b_reg: sw3b {
283 regulator-min-microvolt = <400000>;
284 regulator-max-microvolt = <1975000>;
285 regulator-boot-on;
286 regulator-always-on;
287 };
289 sw4_reg: sw4 {
290 regulator-min-microvolt = <800000>;
291 regulator-max-microvolt = <3300000>;
292 };
294 swbst_reg: swbst {
295 regulator-min-microvolt = <5000000>;
296 regulator-max-microvolt = <5150000>;
297 };
299 snvs_reg: vsnvs {
300 regulator-min-microvolt = <1000000>;
301 regulator-max-microvolt = <3000000>;
302 regulator-boot-on;
303 regulator-always-on;
304 };
306 vref_reg: vrefddr {
307 regulator-boot-on;
308 regulator-always-on;
309 };
311 vgen1_reg: vgen1 {
312 regulator-min-microvolt = <800000>;
313 regulator-max-microvolt = <1550000>;
314 };
316 vgen2_reg: vgen2 {
317 regulator-min-microvolt = <800000>;
318 regulator-max-microvolt = <1550000>;
319 };
321 vgen3_reg: vgen3 {
322 regulator-min-microvolt = <1800000>;
323 regulator-max-microvolt = <3300000>;
324 };
326 vgen4_reg: vgen4 {
327 regulator-min-microvolt = <1800000>;
328 regulator-max-microvolt = <3300000>;
329 regulator-always-on;
330 };
332 vgen5_reg: vgen5 {
333 regulator-min-microvolt = <1800000>;
334 regulator-max-microvolt = <3300000>;
335 regulator-always-on;
336 };
338 vgen6_reg: vgen6 {
339 regulator-min-microvolt = <1800000>;
340 regulator-max-microvolt = <3300000>;
341 regulator-always-on;
342 };
343 };
344 };
346 codec: cs42888@48 {
347 compatible = "cirrus,cs42888";
348 reg = <0x48>;
349 clocks = <&codec_osc>;
350 clock-names = "mclk";
351 VA-supply = <®_audio>;
352 VD-supply = <®_audio>;
353 VLS-supply = <®_audio>;
354 VLC-supply = <®_audio>;
355 };
357 };
359 &i2c3 {
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_i2c3>;
362 status = "okay";
363 };
365 &iomuxc {
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_hog>;
369 imx6qdl-sabreauto {
370 pinctrl_hog: hoggrp {
371 fsl,pins = <
372 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
373 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
374 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
375 >;
376 };
378 pinctrl_ecspi1: ecspi1grp {
379 fsl,pins = <
380 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
381 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
382 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
383 >;
384 };
386 pinctrl_ecspi1_cs: ecspi1cs {
387 fsl,pins = <
388 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
389 >;
390 };
392 pinctrl_enet: enetgrp {
393 fsl,pins = <
394 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
395 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
396 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
397 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
398 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
399 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
400 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
401 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
402 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
403 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
404 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
405 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
406 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
407 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
408 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
409 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
410 >;
411 };
413 pinctrl_esai: esaigrp {
414 fsl,pins = <
415 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
416 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
417 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
418 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
419 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
420 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
421 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
422 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
423 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
424 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
425 >;
426 };
428 pinctrl_gpio_leds: gpioledsgrp {
429 fsl,pins = <
430 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
431 >;
432 };
434 pinctrl_gpmi_nand: gpminandgrp {
435 fsl,pins = <
436 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
437 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
438 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
439 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
440 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
441 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
442 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
443 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
444 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
445 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
446 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
447 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
448 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
449 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
450 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
451 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
452 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
453 >;
454 };
456 pinctrl_i2c2: i2c2grp {
457 fsl,pins = <
458 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
459 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
460 >;
461 };
463 pinctrl_i2c3: i2c3grp {
464 fsl,pins = <
465 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
466 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
467 >;
468 };
470 pinctrl_i2c3mux: i2c3muxgrp {
471 fsl,pins = <
472 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
473 >;
474 };
476 pinctrl_ipu1_csi0: ipu1csi0grp {
477 fsl,pins = <
478 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
479 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
480 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
481 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
482 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
483 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
484 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
485 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
486 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
487 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
488 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
489 >;
490 };
492 pinctrl_max7310: max7310grp {
493 fsl,pins = <
494 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
495 >;
496 };
498 pinctrl_pwm3: pwm1grp {
499 fsl,pins = <
500 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
501 >;
502 };
504 pinctrl_gpt_input_capture0: gptinputcapture0grp {
505 fsl,pins = <
506 MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
507 >;
508 };
510 pinctrl_gpt_input_capture1: gptinputcapture1grp {
511 fsl,pins = <
512 MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
513 >;
514 };
516 pinctrl_spdif: spdifgrp {
517 fsl,pins = <
518 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
519 >;
520 };
522 pinctrl_uart4: uart4grp {
523 fsl,pins = <
524 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
525 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
526 >;
527 };
529 pinctrl_usbotg: usbotggrp {
530 fsl,pins = <
531 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
532 >;
533 };
535 pinctrl_usdhc3: usdhc3grp {
536 fsl,pins = <
537 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
538 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
539 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
540 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
541 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
542 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
543 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
544 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
545 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
546 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
547 >;
548 };
550 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
551 fsl,pins = <
552 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
553 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
554 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
555 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
556 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
557 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
558 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
559 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
560 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
561 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
562 >;
563 };
565 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
566 fsl,pins = <
567 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
568 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
569 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
570 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
571 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
572 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
573 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
574 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
575 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
576 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
577 >;
578 };
580 pinctrl_weim_cs0: weimcs0grp {
581 fsl,pins = <
582 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
583 >;
584 };
586 pinctrl_weim_nor: weimnorgrp {
587 fsl,pins = <
588 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
589 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
590 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
591 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
592 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
593 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
594 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
595 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
596 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
597 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
598 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
599 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
600 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
601 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
602 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
603 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
604 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
605 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
606 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
607 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
608 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
609 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
610 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
611 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
612 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
613 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
614 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
615 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
616 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
617 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
618 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
619 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
620 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
621 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
622 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
623 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
624 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
625 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
626 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
627 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
628 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
629 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
630 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
631 >;
632 };
633 };
634 };
636 &ldb {
637 status = "okay";
639 lvds-channel@0 {
640 fsl,data-mapping = "spwg";
641 fsl,data-width = <18>;
642 status = "okay";
644 display-timings {
645 native-mode = <&timing0>;
646 timing0: hsd100pxn1 {
647 clock-frequency = <65000000>;
648 hactive = <1024>;
649 vactive = <768>;
650 hback-porch = <220>;
651 hfront-porch = <40>;
652 vback-porch = <21>;
653 vfront-porch = <7>;
654 hsync-len = <60>;
655 vsync-len = <10>;
656 };
657 };
658 };
659 };
661 &pwm3 {
662 pinctrl-names = "default";
663 pinctrl-0 = <&pinctrl_pwm3>;
664 status = "okay";
665 };
667 &spdif {
668 pinctrl-names = "default";
669 pinctrl-0 = <&pinctrl_spdif>;
670 status = "okay";
671 };
673 &uart4 {
674 pinctrl-names = "default";
675 pinctrl-0 = <&pinctrl_uart4>;
676 status = "okay";
677 };
679 &usbh1 {
680 vbus-supply = <®_usb_h1_vbus>;
681 status = "okay";
682 };
684 &usbotg {
685 vbus-supply = <®_usb_otg_vbus>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_usbotg>;
688 status = "okay";
689 };
691 &usdhc3 {
692 pinctrl-names = "default", "state_100mhz", "state_200mhz";
693 pinctrl-0 = <&pinctrl_usdhc3>;
694 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
695 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
696 cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
697 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
698 status = "okay";
699 };
701 &weim {
702 pinctrl-names = "default";
703 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
704 ranges = <0 0 0x08000000 0x08000000>;
705 status = "disabled"; /* pin conflict with SPI NOR */
707 nor@0,0 {
708 compatible = "cfi-flash";
709 reg = <0 0 0x02000000>;
710 #address-cells = <1>;
711 #size-cells = <1>;
712 bank-width = <2>;
713 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
714 0x0000c000 0x1404a38e 0x00000000>;
715 };
716 };