4 compatible = "marvell,kirkwood-pcie";
11 bus-range = <0x00 0xff>;
14 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
15 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
16 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
20 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
21 reg = <0x0800 0 0 0 0>;
24 #interrupt-cells = <1>;
25 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
26 0x81000000 0 0 0x81000000 0x1 0 1 0>;
27 bus-range = <0x00 0xff>;
28 interrupt-map-mask = <0 0 0 0>;
29 interrupt-map = <0 0 0 0 &intc 9>;
30 marvell,pcie-port = <0>;
31 marvell,pcie-lane = <0>;
32 clocks = <&gate_clk 2>;
39 pinctrl: pin-controller@10000 {
40 compatible = "marvell,88f6192-pinctrl";
42 pmx_sata0: pmx-sata0 {
43 marvell,pins = "mpp5", "mpp21", "mpp23";
44 marvell,function = "sata0";
46 pmx_sata1: pmx-sata1 {
47 marvell,pins = "mpp4", "mpp20", "mpp22";
48 marvell,function = "sata1";
51 marvell,pins = "mpp12", "mpp13", "mpp14",
52 "mpp15", "mpp16", "mpp17";
53 marvell,function = "sdio";
58 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
61 clocks = <&gate_clk 7>;
65 compatible = "marvell,orion-sata";
66 reg = <0x80000 0x5000>;
68 clocks = <&gate_clk 14>, <&gate_clk 15>;
69 clock-names = "0", "1";
70 phys = <&sata_phy0>, <&sata_phy1>;
71 phy-names = "port0", "port1";
76 compatible = "marvell,orion-sdio";
77 reg = <0x90000 0x200>;
79 clocks = <&gate_clk 4>;