arch/arm/boot/dts/omap44xx-clocks.dtsi

   1 /*
   2  * Device Tree Source for OMAP4 clock data
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 &cm1_clocks {
  11         extalt_clkin_ck: extalt_clkin_ck {
  12                 #clock-cells = <0>;
  13                 compatible = "fixed-clock";
  14                 clock-frequency = <59000000>;
  15         };
  16
  17         pad_clks_src_ck: pad_clks_src_ck {
  18                 #clock-cells = <0>;
  19                 compatible = "fixed-clock";
  20                 clock-frequency = <12000000>;
  21         };
  22
  23         pad_clks_ck: pad_clks_ck@108 {
  24                 #clock-cells = <0>;
  25                 compatible = "ti,gate-clock";
  26                 clocks = <&pad_clks_src_ck>;
  27                 ti,bit-shift = <8>;
  28                 reg = <0x0108>;
  29         };
  30
  31         pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
  32                 #clock-cells = <0>;
  33                 compatible = "fixed-clock";
  34                 clock-frequency = <12000000>;
  35         };
  36
  37         secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  38                 #clock-cells = <0>;
  39                 compatible = "fixed-clock";
  40                 clock-frequency = <32768>;
  41         };
  42
  43         slimbus_src_clk: slimbus_src_clk {
  44                 #clock-cells = <0>;
  45                 compatible = "fixed-clock";
  46                 clock-frequency = <12000000>;
  47         };
  48
  49         slimbus_clk: slimbus_clk@108 {
  50                 #clock-cells = <0>;
  51                 compatible = "ti,gate-clock";
  52                 clocks = <&slimbus_src_clk>;
  53                 ti,bit-shift = <10>;
  54                 reg = <0x0108>;
  55         };
  56
  57         sys_32k_ck: sys_32k_ck {
  58                 #clock-cells = <0>;
  59                 compatible = "fixed-clock";
  60                 clock-frequency = <32768>;
  61         };
  62
  63         virt_12000000_ck: virt_12000000_ck {
  64                 #clock-cells = <0>;
  65                 compatible = "fixed-clock";
  66                 clock-frequency = <12000000>;
  67         };
  68
  69         virt_13000000_ck: virt_13000000_ck {
  70                 #clock-cells = <0>;
  71                 compatible = "fixed-clock";
  72                 clock-frequency = <13000000>;
  73         };
  74
  75         virt_16800000_ck: virt_16800000_ck {
  76                 #clock-cells = <0>;
  77                 compatible = "fixed-clock";
  78                 clock-frequency = <16800000>;
  79         };
  80
  81         virt_19200000_ck: virt_19200000_ck {
  82                 #clock-cells = <0>;
  83                 compatible = "fixed-clock";
  84                 clock-frequency = <19200000>;
  85         };
  86
  87         virt_26000000_ck: virt_26000000_ck {
  88                 #clock-cells = <0>;
  89                 compatible = "fixed-clock";
  90                 clock-frequency = <26000000>;
  91         };
  92
  93         virt_27000000_ck: virt_27000000_ck {
  94                 #clock-cells = <0>;
  95                 compatible = "fixed-clock";
  96                 clock-frequency = <27000000>;
  97         };
  98
  99         virt_38400000_ck: virt_38400000_ck {
 100                 #clock-cells = <0>;
 101                 compatible = "fixed-clock";
 102                 clock-frequency = <38400000>;
 103         };
 104
 105         tie_low_clock_ck: tie_low_clock_ck {
 106                 #clock-cells = <0>;
 107                 compatible = "fixed-clock";
 108                 clock-frequency = <0>;
 109         };
 110
 111         utmi_phy_clkout_ck: utmi_phy_clkout_ck {
 112                 #clock-cells = <0>;
 113                 compatible = "fixed-clock";
 114                 clock-frequency = <60000000>;
 115         };
 116
 117         xclk60mhsp1_ck: xclk60mhsp1_ck {
 118                 #clock-cells = <0>;
 119                 compatible = "fixed-clock";
 120                 clock-frequency = <60000000>;
 121         };
 122
 123         xclk60mhsp2_ck: xclk60mhsp2_ck {
 124                 #clock-cells = <0>;
 125                 compatible = "fixed-clock";
 126                 clock-frequency = <60000000>;
 127         };
 128
 129         xclk60motg_ck: xclk60motg_ck {
 130                 #clock-cells = <0>;
 131                 compatible = "fixed-clock";
 132                 clock-frequency = <60000000>;
 133         };
 134
 135         dpll_abe_ck: dpll_abe_ck@1e0 {
 136                 #clock-cells = <0>;
 137                 compatible = "ti,omap4-dpll-m4xen-clock";
 138                 clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
 139                 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 140         };
 141
 142         dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
 143                 #clock-cells = <0>;
 144                 compatible = "ti,omap4-dpll-x2-clock";
 145                 clocks = <&dpll_abe_ck>;
 146                 reg = <0x01f0>;
 147         };
 148
 149         dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 150                 #clock-cells = <0>;
 151                 compatible = "ti,divider-clock";
 152                 clocks = <&dpll_abe_x2_ck>;
 153                 ti,max-div = <31>;
 154                 ti,autoidle-shift = <8>;
 155                 reg = <0x01f0>;
 156                 ti,index-starts-at-one;
 157                 ti,invert-autoidle-bit;
 158         };
 159
 160         abe_24m_fclk: abe_24m_fclk {
 161                 #clock-cells = <0>;
 162                 compatible = "fixed-factor-clock";
 163                 clocks = <&dpll_abe_m2x2_ck>;
 164                 clock-mult = <1>;
 165                 clock-div = <8>;
 166         };
 167
 168         abe_clk: abe_clk@108 {
 169                 #clock-cells = <0>;
 170                 compatible = "ti,divider-clock";
 171                 clocks = <&dpll_abe_m2x2_ck>;
 172                 ti,max-div = <4>;
 173                 reg = <0x0108>;
 174                 ti,index-power-of-two;
 175         };
 176
 177         aess_fclk: aess_fclk@528 {
 178                 #clock-cells = <0>;
 179                 compatible = "ti,divider-clock";
 180                 clocks = <&abe_clk>;
 181                 ti,bit-shift = <24>;
 182                 ti,max-div = <2>;
 183                 reg = <0x0528>;
 184         };
 185
 186         dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 187                 #clock-cells = <0>;
 188                 compatible = "ti,divider-clock";
 189                 clocks = <&dpll_abe_x2_ck>;
 190                 ti,max-div = <31>;
 191                 ti,autoidle-shift = <8>;
 192                 reg = <0x01f4>;
 193                 ti,index-starts-at-one;
 194                 ti,invert-autoidle-bit;
 195         };
 196
 197         core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
 198                 #clock-cells = <0>;
 199                 compatible = "ti,mux-clock";
 200                 clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
 201                 ti,bit-shift = <23>;
 202                 reg = <0x012c>;
 203         };
 204
 205         dpll_core_ck: dpll_core_ck@120 {
 206                 #clock-cells = <0>;
 207                 compatible = "ti,omap4-dpll-core-clock";
 208                 clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
 209                 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 210         };
 211
 212         dpll_core_x2_ck: dpll_core_x2_ck {
 213                 #clock-cells = <0>;
 214                 compatible = "ti,omap4-dpll-x2-clock";
 215                 clocks = <&dpll_core_ck>;
 216         };
 217
 218         dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
 219                 #clock-cells = <0>;
 220                 compatible = "ti,divider-clock";
 221                 clocks = <&dpll_core_x2_ck>;
 222                 ti,max-div = <31>;
 223                 ti,autoidle-shift = <8>;
 224                 reg = <0x0140>;
 225                 ti,index-starts-at-one;
 226                 ti,invert-autoidle-bit;
 227         };
 228
 229         dpll_core_m2_ck: dpll_core_m2_ck@130 {
 230                 #clock-cells = <0>;
 231                 compatible = "ti,divider-clock";
 232                 clocks = <&dpll_core_ck>;
 233                 ti,max-div = <31>;
 234                 ti,autoidle-shift = <8>;
 235                 reg = <0x0130>;
 236                 ti,index-starts-at-one;
 237                 ti,invert-autoidle-bit;
 238         };
 239
 240         ddrphy_ck: ddrphy_ck {
 241                 #clock-cells = <0>;
 242                 compatible = "fixed-factor-clock";
 243                 clocks = <&dpll_core_m2_ck>;
 244                 clock-mult = <1>;
 245                 clock-div = <2>;
 246         };
 247
 248         dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
 249                 #clock-cells = <0>;
 250                 compatible = "ti,divider-clock";
 251                 clocks = <&dpll_core_x2_ck>;
 252                 ti,max-div = <31>;
 253                 ti,autoidle-shift = <8>;
 254                 reg = <0x013c>;
 255                 ti,index-starts-at-one;
 256                 ti,invert-autoidle-bit;
 257         };
 258
 259         div_core_ck: div_core_ck@100 {
 260                 #clock-cells = <0>;
 261                 compatible = "ti,divider-clock";
 262                 clocks = <&dpll_core_m5x2_ck>;
 263                 reg = <0x0100>;
 264                 ti,max-div = <2>;
 265         };
 266
 267         div_iva_hs_clk: div_iva_hs_clk@1dc {
 268                 #clock-cells = <0>;
 269                 compatible = "ti,divider-clock";
 270                 clocks = <&dpll_core_m5x2_ck>;
 271                 ti,max-div = <4>;
 272                 reg = <0x01dc>;
 273                 ti,index-power-of-two;
 274         };
 275
 276         div_mpu_hs_clk: div_mpu_hs_clk@19c {
 277                 #clock-cells = <0>;
 278                 compatible = "ti,divider-clock";
 279                 clocks = <&dpll_core_m5x2_ck>;
 280                 ti,max-div = <4>;
 281                 reg = <0x019c>;
 282                 ti,index-power-of-two;
 283         };
 284
 285         dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
 286                 #clock-cells = <0>;
 287                 compatible = "ti,divider-clock";
 288                 clocks = <&dpll_core_x2_ck>;
 289                 ti,max-div = <31>;
 290                 ti,autoidle-shift = <8>;
 291                 reg = <0x0138>;
 292                 ti,index-starts-at-one;
 293                 ti,invert-autoidle-bit;
 294         };
 295
 296         dll_clk_div_ck: dll_clk_div_ck {
 297                 #clock-cells = <0>;
 298                 compatible = "fixed-factor-clock";
 299                 clocks = <&dpll_core_m4x2_ck>;
 300                 clock-mult = <1>;
 301                 clock-div = <2>;
 302         };
 303
 304         dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
 305                 #clock-cells = <0>;
 306                 compatible = "ti,divider-clock";
 307                 clocks = <&dpll_abe_ck>;
 308                 ti,max-div = <31>;
 309                 reg = <0x01f0>;
 310                 ti,index-starts-at-one;
 311         };
 312
 313         dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
 314                 #clock-cells = <0>;
 315                 compatible = "ti,composite-no-wait-gate-clock";
 316                 clocks = <&dpll_core_x2_ck>;
 317                 ti,bit-shift = <8>;
 318                 reg = <0x0134>;
 319         };
 320
 321         dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
 322                 #clock-cells = <0>;
 323                 compatible = "ti,composite-divider-clock";
 324                 clocks = <&dpll_core_x2_ck>;
 325                 ti,max-div = <31>;
 326                 reg = <0x0134>;
 327                 ti,index-starts-at-one;
 328         };
 329
 330         dpll_core_m3x2_ck: dpll_core_m3x2_ck {
 331                 #clock-cells = <0>;
 332                 compatible = "ti,composite-clock";
 333                 clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
 334         };
 335
 336         dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
 337                 #clock-cells = <0>;
 338                 compatible = "ti,divider-clock";
 339                 clocks = <&dpll_core_x2_ck>;
 340                 ti,max-div = <31>;
 341                 ti,autoidle-shift = <8>;
 342                 reg = <0x0144>;
 343                 ti,index-starts-at-one;
 344                 ti,invert-autoidle-bit;
 345         };
 346
 347         iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
 348                 #clock-cells = <0>;
 349                 compatible = "ti,mux-clock";
 350                 clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
 351                 ti,bit-shift = <23>;
 352                 reg = <0x01ac>;
 353         };
 354
 355         dpll_iva_ck: dpll_iva_ck@1a0 {
 356                 #clock-cells = <0>;
 357                 compatible = "ti,omap4-dpll-clock";
 358                 clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
 359                 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 360                 assigned-clocks = <&dpll_iva_ck>;
 361                 assigned-clock-rates = <931200000>;
 362         };
 363
 364         dpll_iva_x2_ck: dpll_iva_x2_ck {
 365                 #clock-cells = <0>;
 366                 compatible = "ti,omap4-dpll-x2-clock";
 367                 clocks = <&dpll_iva_ck>;
 368         };
 369
 370         dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
 371                 #clock-cells = <0>;
 372                 compatible = "ti,divider-clock";
 373                 clocks = <&dpll_iva_x2_ck>;
 374                 ti,max-div = <31>;
 375                 ti,autoidle-shift = <8>;
 376                 reg = <0x01b8>;
 377                 ti,index-starts-at-one;
 378                 ti,invert-autoidle-bit;
 379                 assigned-clocks = <&dpll_iva_m4x2_ck>;
 380                 assigned-clock-rates = <465600000>;
 381         };
 382
 383         dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
 384                 #clock-cells = <0>;
 385                 compatible = "ti,divider-clock";
 386                 clocks = <&dpll_iva_x2_ck>;
 387                 ti,max-div = <31>;
 388                 ti,autoidle-shift = <8>;
 389                 reg = <0x01bc>;
 390                 ti,index-starts-at-one;
 391                 ti,invert-autoidle-bit;
 392                 assigned-clocks = <&dpll_iva_m5x2_ck>;
 393                 assigned-clock-rates = <266100000>;
 394         };
 395
 396         dpll_mpu_ck: dpll_mpu_ck@160 {
 397                 #clock-cells = <0>;
 398                 compatible = "ti,omap4-dpll-clock";
 399                 clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
 400                 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 401         };
 402
 403         dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 404                 #clock-cells = <0>;
 405                 compatible = "ti,divider-clock";
 406                 clocks = <&dpll_mpu_ck>;
 407                 ti,max-div = <31>;
 408                 ti,autoidle-shift = <8>;
 409                 reg = <0x0170>;
 410                 ti,index-starts-at-one;
 411                 ti,invert-autoidle-bit;
 412         };
 413
 414         per_hs_clk_div_ck: per_hs_clk_div_ck {
 415                 #clock-cells = <0>;
 416                 compatible = "fixed-factor-clock";
 417                 clocks = <&dpll_abe_m3x2_ck>;
 418                 clock-mult = <1>;
 419                 clock-div = <2>;
 420         };
 421
 422         usb_hs_clk_div_ck: usb_hs_clk_div_ck {
 423                 #clock-cells = <0>;
 424                 compatible = "fixed-factor-clock";
 425                 clocks = <&dpll_abe_m3x2_ck>;
 426                 clock-mult = <1>;
 427                 clock-div = <3>;
 428         };
 429
 430         l3_div_ck: l3_div_ck@100 {
 431                 #clock-cells = <0>;
 432                 compatible = "ti,divider-clock";
 433                 clocks = <&div_core_ck>;
 434                 ti,bit-shift = <4>;
 435                 ti,max-div = <2>;
 436                 reg = <0x0100>;
 437         };
 438
 439         l4_div_ck: l4_div_ck@100 {
 440                 #clock-cells = <0>;
 441                 compatible = "ti,divider-clock";
 442                 clocks = <&l3_div_ck>;
 443                 ti,bit-shift = <8>;
 444                 ti,max-div = <2>;
 445                 reg = <0x0100>;
 446         };
 447
 448         lp_clk_div_ck: lp_clk_div_ck {
 449                 #clock-cells = <0>;
 450                 compatible = "fixed-factor-clock";
 451                 clocks = <&dpll_abe_m2x2_ck>;
 452                 clock-mult = <1>;
 453                 clock-div = <16>;
 454         };
 455
 456         mpu_periphclk: mpu_periphclk {
 457                 #clock-cells = <0>;
 458                 compatible = "fixed-factor-clock";
 459                 clocks = <&dpll_mpu_ck>;
 460                 clock-mult = <1>;
 461                 clock-div = <2>;
 462         };
 463
 464         ocp_abe_iclk: ocp_abe_iclk@528 {
 465                 #clock-cells = <0>;
 466                 compatible = "ti,divider-clock";
 467                 clocks = <&aess_fclk>;
 468                 ti,bit-shift = <24>;
 469                 reg = <0x0528>;
 470                 ti,dividers = <2>, <1>;
 471         };
 472
 473         per_abe_24m_fclk: per_abe_24m_fclk {
 474                 #clock-cells = <0>;
 475                 compatible = "fixed-factor-clock";
 476                 clocks = <&dpll_abe_m2_ck>;
 477                 clock-mult = <1>;
 478                 clock-div = <4>;
 479         };
 480
 481         dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
 482                 #clock-cells = <0>;
 483                 compatible = "ti,mux-clock";
 484                 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
 485                 ti,bit-shift = <25>;
 486                 reg = <0x0538>;
 487         };
 488
 489         func_dmic_abe_gfclk: func_dmic_abe_gfclk@538 {
 490                 #clock-cells = <0>;
 491                 compatible = "ti,mux-clock";
 492                 clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
 493                 ti,bit-shift = <24>;
 494                 reg = <0x0538>;
 495         };
 496
 497         mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
 498                 #clock-cells = <0>;
 499                 compatible = "ti,mux-clock";
 500                 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
 501                 ti,bit-shift = <25>;
 502                 reg = <0x0540>;
 503         };
 504
 505         func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@540 {
 506                 #clock-cells = <0>;
 507                 compatible = "ti,mux-clock";
 508                 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
 509                 ti,bit-shift = <24>;
 510                 reg = <0x0540>;
 511         };
 512
 513         mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
 514                 #clock-cells = <0>;
 515                 compatible = "ti,mux-clock";
 516                 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
 517                 ti,bit-shift = <25>;
 518                 reg = <0x0548>;
 519         };
 520
 521         func_mcbsp1_gfclk: func_mcbsp1_gfclk@548 {
 522                 #clock-cells = <0>;
 523                 compatible = "ti,mux-clock";
 524                 clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
 525                 ti,bit-shift = <24>;
 526                 reg = <0x0548>;
 527         };
 528
 529         mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
 530                 #clock-cells = <0>;
 531                 compatible = "ti,mux-clock";
 532                 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
 533                 ti,bit-shift = <25>;
 534                 reg = <0x0550>;
 535         };
 536
 537         func_mcbsp2_gfclk: func_mcbsp2_gfclk@550 {
 538                 #clock-cells = <0>;
 539                 compatible = "ti,mux-clock";
 540                 clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
 541                 ti,bit-shift = <24>;
 542                 reg = <0x0550>;
 543         };
 544
 545         mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
 546                 #clock-cells = <0>;
 547                 compatible = "ti,mux-clock";
 548                 clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
 549                 ti,bit-shift = <25>;
 550                 reg = <0x0558>;
 551         };
 552
 553         func_mcbsp3_gfclk: func_mcbsp3_gfclk@558 {
 554                 #clock-cells = <0>;
 555                 compatible = "ti,mux-clock";
 556                 clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
 557                 ti,bit-shift = <24>;
 558                 reg = <0x0558>;
 559         };
 560
 561         slimbus1_fclk_1: slimbus1_fclk_1@560 {
 562                 #clock-cells = <0>;
 563                 compatible = "ti,gate-clock";
 564                 clocks = <&func_24m_clk>;
 565                 ti,bit-shift = <9>;
 566                 reg = <0x0560>;
 567         };
 568
 569         slimbus1_fclk_0: slimbus1_fclk_0@560 {
 570                 #clock-cells = <0>;
 571                 compatible = "ti,gate-clock";
 572                 clocks = <&abe_24m_fclk>;
 573                 ti,bit-shift = <8>;
 574                 reg = <0x0560>;
 575         };
 576
 577         slimbus1_fclk_2: slimbus1_fclk_2@560 {
 578                 #clock-cells = <0>;
 579                 compatible = "ti,gate-clock";
 580                 clocks = <&pad_clks_ck>;
 581                 ti,bit-shift = <10>;
 582                 reg = <0x0560>;
 583         };
 584
 585         slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
 586                 #clock-cells = <0>;
 587                 compatible = "ti,gate-clock";
 588                 clocks = <&slimbus_clk>;
 589                 ti,bit-shift = <11>;
 590                 reg = <0x0560>;
 591         };
 592
 593         timer5_sync_mux: timer5_sync_mux@568 {
 594                 #clock-cells = <0>;
 595                 compatible = "ti,mux-clock";
 596                 clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
 597                 ti,bit-shift = <24>;
 598                 reg = <0x0568>;
 599         };
 600
 601         timer6_sync_mux: timer6_sync_mux@570 {
 602                 #clock-cells = <0>;
 603                 compatible = "ti,mux-clock";
 604                 clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
 605                 ti,bit-shift = <24>;
 606                 reg = <0x0570>;
 607         };
 608
 609         timer7_sync_mux: timer7_sync_mux@578 {
 610                 #clock-cells = <0>;
 611                 compatible = "ti,mux-clock";
 612                 clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
 613                 ti,bit-shift = <24>;
 614                 reg = <0x0578>;
 615         };
 616
 617         timer8_sync_mux: timer8_sync_mux@580 {
 618                 #clock-cells = <0>;
 619                 compatible = "ti,mux-clock";
 620                 clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
 621                 ti,bit-shift = <24>;
 622                 reg = <0x0580>;
 623         };
 624
 625         dummy_ck: dummy_ck {
 626                 #clock-cells = <0>;
 627                 compatible = "fixed-clock";
 628                 clock-frequency = <0>;
 629         };
 630 };
 631 &prm_clocks {
 632         sys_clkin_ck: sys_clkin_ck@110 {
 633                 #clock-cells = <0>;
 634                 compatible = "ti,mux-clock";
 635                 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
 636                 reg = <0x0110>;
 637                 ti,index-starts-at-one;
 638         };
 639
 640         abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
 641                 #clock-cells = <0>;
 642                 compatible = "ti,mux-clock";
 643                 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
 644                 ti,bit-shift = <24>;
 645                 reg = <0x0108>;
 646         };
 647
 648         abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
 649                 #clock-cells = <0>;
 650                 compatible = "ti,mux-clock";
 651                 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
 652                 reg = <0x010c>;
 653         };
 654
 655         dbgclk_mux_ck: dbgclk_mux_ck {
 656                 #clock-cells = <0>;
 657                 compatible = "fixed-factor-clock";
 658                 clocks = <&sys_clkin_ck>;
 659                 clock-mult = <1>;
 660                 clock-div = <1>;
 661         };
 662
 663         l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
 664                 #clock-cells = <0>;
 665                 compatible = "ti,mux-clock";
 666                 clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
 667                 reg = <0x0108>;
 668         };
 669
 670         syc_clk_div_ck: syc_clk_div_ck@100 {
 671                 #clock-cells = <0>;
 672                 compatible = "ti,divider-clock";
 673                 clocks = <&sys_clkin_ck>;
 674                 reg = <0x0100>;
 675                 ti,max-div = <2>;
 676         };
 677
 678         gpio1_dbclk: gpio1_dbclk@1838 {
 679                 #clock-cells = <0>;
 680                 compatible = "ti,gate-clock";
 681                 clocks = <&sys_32k_ck>;
 682                 ti,bit-shift = <8>;
 683                 reg = <0x1838>;
 684         };
 685
 686         dmt1_clk_mux: dmt1_clk_mux@1840 {
 687                 #clock-cells = <0>;
 688                 compatible = "ti,mux-clock";
 689                 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
 690                 ti,bit-shift = <24>;
 691                 reg = <0x1840>;
 692         };
 693
 694         usim_ck: usim_ck@1858 {
 695                 #clock-cells = <0>;
 696                 compatible = "ti,divider-clock";
 697                 clocks = <&dpll_per_m4x2_ck>;
 698                 ti,bit-shift = <24>;
 699                 reg = <0x1858>;
 700                 ti,dividers = <14>, <18>;
 701         };
 702
 703         usim_fclk: usim_fclk@1858 {
 704                 #clock-cells = <0>;
 705                 compatible = "ti,gate-clock";
 706                 clocks = <&usim_ck>;
 707                 ti,bit-shift = <8>;
 708                 reg = <0x1858>;
 709         };
 710
 711         pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@1a20 {
 712                 #clock-cells = <0>;
 713                 compatible = "ti,mux-clock";
 714                 clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
 715                 ti,bit-shift = <20>;
 716                 reg = <0x1a20>;
 717         };
 718
 719         pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@1a20 {
 720                 #clock-cells = <0>;
 721                 compatible = "ti,mux-clock";
 722                 clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
 723                 ti,bit-shift = <22>;
 724                 reg = <0x1a20>;
 725         };
 726
 727         stm_clk_div_ck: stm_clk_div_ck@1a20 {
 728                 #clock-cells = <0>;
 729                 compatible = "ti,divider-clock";
 730                 clocks = <&pmd_stm_clock_mux_ck>;
 731                 ti,bit-shift = <27>;
 732                 ti,max-div = <64>;
 733                 reg = <0x1a20>;
 734                 ti,index-power-of-two;
 735         };
 736
 737         trace_clk_div_div_ck: trace_clk_div_div_ck@1a20 {
 738                 #clock-cells = <0>;
 739                 compatible = "ti,divider-clock";
 740                 clocks = <&pmd_trace_clk_mux_ck>;
 741                 ti,bit-shift = <24>;
 742                 reg = <0x1a20>;
 743                 ti,dividers = <0>, <1>, <2>, <0>, <4>;
 744         };
 745
 746         trace_clk_div_ck: trace_clk_div_ck {
 747                 #clock-cells = <0>;
 748                 compatible = "ti,clkdm-gate-clock";
 749                 clocks = <&trace_clk_div_div_ck>;
 750         };
 751 };
 752
 753 &prm_clockdomains {
 754         emu_sys_clkdm: emu_sys_clkdm {
 755                 compatible = "ti,clockdomain";
 756                 clocks = <&trace_clk_div_ck>;
 757         };
 758 };
 759
 760 &cm2_clocks {
 761         per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
 762                 #clock-cells = <0>;
 763                 compatible = "ti,mux-clock";
 764                 clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
 765                 ti,bit-shift = <23>;
 766                 reg = <0x014c>;
 767         };
 768
 769         dpll_per_ck: dpll_per_ck@140 {
 770                 #clock-cells = <0>;
 771                 compatible = "ti,omap4-dpll-clock";
 772                 clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
 773                 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
 774         };
 775
 776         dpll_per_m2_ck: dpll_per_m2_ck@150 {
 777                 #clock-cells = <0>;
 778                 compatible = "ti,divider-clock";
 779                 clocks = <&dpll_per_ck>;
 780                 ti,max-div = <31>;
 781                 reg = <0x0150>;
 782                 ti,index-starts-at-one;
 783         };
 784
 785         dpll_per_x2_ck: dpll_per_x2_ck@150 {
 786                 #clock-cells = <0>;
 787                 compatible = "ti,omap4-dpll-x2-clock";
 788                 clocks = <&dpll_per_ck>;
 789                 reg = <0x0150>;
 790         };
 791
 792         dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
 793                 #clock-cells = <0>;
 794                 compatible = "ti,divider-clock";
 795                 clocks = <&dpll_per_x2_ck>;
 796                 ti,max-div = <31>;
 797                 ti,autoidle-shift = <8>;
 798                 reg = <0x0150>;
 799                 ti,index-starts-at-one;
 800                 ti,invert-autoidle-bit;
 801         };
 802
 803         dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
 804                 #clock-cells = <0>;
 805                 compatible = "ti,composite-no-wait-gate-clock";
 806                 clocks = <&dpll_per_x2_ck>;
 807                 ti,bit-shift = <8>;
 808                 reg = <0x0154>;
 809         };
 810
 811         dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
 812                 #clock-cells = <0>;
 813                 compatible = "ti,composite-divider-clock";
 814                 clocks = <&dpll_per_x2_ck>;
 815                 ti,max-div = <31>;
 816                 reg = <0x0154>;
 817                 ti,index-starts-at-one;
 818         };
 819
 820         dpll_per_m3x2_ck: dpll_per_m3x2_ck {
 821                 #clock-cells = <0>;
 822                 compatible = "ti,composite-clock";
 823                 clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
 824         };
 825
 826         dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
 827                 #clock-cells = <0>;
 828                 compatible = "ti,divider-clock";
 829                 clocks = <&dpll_per_x2_ck>;
 830                 ti,max-div = <31>;
 831                 ti,autoidle-shift = <8>;
 832                 reg = <0x0158>;
 833                 ti,index-starts-at-one;
 834                 ti,invert-autoidle-bit;
 835         };
 836
 837         dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
 838                 #clock-cells = <0>;
 839                 compatible = "ti,divider-clock";
 840                 clocks = <&dpll_per_x2_ck>;
 841                 ti,max-div = <31>;
 842                 ti,autoidle-shift = <8>;
 843                 reg = <0x015c>;
 844                 ti,index-starts-at-one;
 845                 ti,invert-autoidle-bit;
 846         };
 847
 848         dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
 849                 #clock-cells = <0>;
 850                 compatible = "ti,divider-clock";
 851                 clocks = <&dpll_per_x2_ck>;
 852                 ti,max-div = <31>;
 853                 ti,autoidle-shift = <8>;
 854                 reg = <0x0160>;
 855                 ti,index-starts-at-one;
 856                 ti,invert-autoidle-bit;
 857         };
 858
 859         dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
 860                 #clock-cells = <0>;
 861                 compatible = "ti,divider-clock";
 862                 clocks = <&dpll_per_x2_ck>;
 863                 ti,max-div = <31>;
 864                 ti,autoidle-shift = <8>;
 865                 reg = <0x0164>;
 866                 ti,index-starts-at-one;
 867                 ti,invert-autoidle-bit;
 868         };
 869
 870         dpll_usb_ck: dpll_usb_ck@180 {
 871                 #clock-cells = <0>;
 872                 compatible = "ti,omap4-dpll-j-type-clock";
 873                 clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
 874                 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
 875         };
 876
 877         dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
 878                 #clock-cells = <0>;
 879                 compatible = "ti,fixed-factor-clock";
 880                 clocks = <&dpll_usb_ck>;
 881                 ti,clock-div = <1>;
 882                 ti,autoidle-shift = <8>;
 883                 reg = <0x01b4>;
 884                 ti,clock-mult = <1>;
 885                 ti,invert-autoidle-bit;
 886         };
 887
 888         dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
 889                 #clock-cells = <0>;
 890                 compatible = "ti,divider-clock";
 891                 clocks = <&dpll_usb_ck>;
 892                 ti,max-div = <127>;
 893                 ti,autoidle-shift = <8>;
 894                 reg = <0x0190>;
 895                 ti,index-starts-at-one;
 896                 ti,invert-autoidle-bit;
 897         };
 898
 899         ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
 900                 #clock-cells = <0>;
 901                 compatible = "ti,mux-clock";
 902                 clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
 903                 reg = <0x0100>;
 904         };
 905
 906         func_12m_fclk: func_12m_fclk {
 907                 #clock-cells = <0>;
 908                 compatible = "fixed-factor-clock";
 909                 clocks = <&dpll_per_m2x2_ck>;
 910                 clock-mult = <1>;
 911                 clock-div = <16>;
 912         };
 913
 914         func_24m_clk: func_24m_clk {
 915                 #clock-cells = <0>;
 916                 compatible = "fixed-factor-clock";
 917                 clocks = <&dpll_per_m2_ck>;
 918                 clock-mult = <1>;
 919                 clock-div = <4>;
 920         };
 921
 922         func_24mc_fclk: func_24mc_fclk {
 923                 #clock-cells = <0>;
 924                 compatible = "fixed-factor-clock";
 925                 clocks = <&dpll_per_m2x2_ck>;
 926                 clock-mult = <1>;
 927                 clock-div = <8>;
 928         };
 929
 930         func_48m_fclk: func_48m_fclk@108 {
 931                 #clock-cells = <0>;
 932                 compatible = "ti,divider-clock";
 933                 clocks = <&dpll_per_m2x2_ck>;
 934                 reg = <0x0108>;
 935                 ti,dividers = <4>, <8>;
 936         };
 937
 938         func_48mc_fclk: func_48mc_fclk {
 939                 #clock-cells = <0>;
 940                 compatible = "fixed-factor-clock";
 941                 clocks = <&dpll_per_m2x2_ck>;
 942                 clock-mult = <1>;
 943                 clock-div = <4>;
 944         };
 945
 946         func_64m_fclk: func_64m_fclk@108 {
 947                 #clock-cells = <0>;
 948                 compatible = "ti,divider-clock";
 949                 clocks = <&dpll_per_m4x2_ck>;
 950                 reg = <0x0108>;
 951                 ti,dividers = <2>, <4>;
 952         };
 953
 954         func_96m_fclk: func_96m_fclk@108 {
 955                 #clock-cells = <0>;
 956                 compatible = "ti,divider-clock";
 957                 clocks = <&dpll_per_m2x2_ck>;
 958                 reg = <0x0108>;
 959                 ti,dividers = <2>, <4>;
 960         };
 961
 962         init_60m_fclk: init_60m_fclk@104 {
 963                 #clock-cells = <0>;
 964                 compatible = "ti,divider-clock";
 965                 clocks = <&dpll_usb_m2_ck>;
 966                 reg = <0x0104>;
 967                 ti,dividers = <1>, <8>;
 968         };
 969
 970         per_abe_nc_fclk: per_abe_nc_fclk@108 {
 971                 #clock-cells = <0>;
 972                 compatible = "ti,divider-clock";
 973                 clocks = <&dpll_abe_m2_ck>;
 974                 reg = <0x0108>;
 975                 ti,max-div = <2>;
 976         };
 977
 978         dss_sys_clk: dss_sys_clk@1120 {
 979                 #clock-cells = <0>;
 980                 compatible = "ti,gate-clock";
 981                 clocks = <&syc_clk_div_ck>;
 982                 ti,bit-shift = <10>;
 983                 reg = <0x1120>;
 984         };
 985
 986         dss_tv_clk: dss_tv_clk@1120 {
 987                 #clock-cells = <0>;
 988                 compatible = "ti,gate-clock";
 989                 clocks = <&extalt_clkin_ck>;
 990                 ti,bit-shift = <11>;
 991                 reg = <0x1120>;
 992         };
 993
 994         dss_dss_clk: dss_dss_clk@1120 {
 995                 #clock-cells = <0>;
 996                 compatible = "ti,gate-clock";
 997                 clocks = <&dpll_per_m5x2_ck>;
 998                 ti,bit-shift = <8>;
 999                 reg = <0x1120>;
1000                 ti,set-rate-parent;
1001         };
1002
1003         dss_48mhz_clk: dss_48mhz_clk@1120 {
1004                 #clock-cells = <0>;
1005                 compatible = "ti,gate-clock";
1006                 clocks = <&func_48mc_fclk>;
1007                 ti,bit-shift = <9>;
1008                 reg = <0x1120>;
1009         };
1010
1011         fdif_fck: fdif_fck@1028 {
1012                 #clock-cells = <0>;
1013                 compatible = "ti,divider-clock";
1014                 clocks = <&dpll_per_m4x2_ck>;
1015                 ti,bit-shift = <24>;
1016                 ti,max-div = <4>;
1017                 reg = <0x1028>;
1018                 ti,index-power-of-two;
1019         };
1020
1021         gpio2_dbclk: gpio2_dbclk@1460 {
1022                 #clock-cells = <0>;
1023                 compatible = "ti,gate-clock";
1024                 clocks = <&sys_32k_ck>;
1025                 ti,bit-shift = <8>;
1026                 reg = <0x1460>;
1027         };
1028
1029         gpio3_dbclk: gpio3_dbclk@1468 {
1030                 #clock-cells = <0>;
1031                 compatible = "ti,gate-clock";
1032                 clocks = <&sys_32k_ck>;
1033                 ti,bit-shift = <8>;
1034                 reg = <0x1468>;
1035         };
1036
1037         gpio4_dbclk: gpio4_dbclk@1470 {
1038                 #clock-cells = <0>;
1039                 compatible = "ti,gate-clock";
1040                 clocks = <&sys_32k_ck>;
1041                 ti,bit-shift = <8>;
1042                 reg = <0x1470>;
1043         };
1044
1045         gpio5_dbclk: gpio5_dbclk@1478 {
1046                 #clock-cells = <0>;
1047                 compatible = "ti,gate-clock";
1048                 clocks = <&sys_32k_ck>;
1049                 ti,bit-shift = <8>;
1050                 reg = <0x1478>;
1051         };
1052
1053         gpio6_dbclk: gpio6_dbclk@1480 {
1054                 #clock-cells = <0>;
1055                 compatible = "ti,gate-clock";
1056                 clocks = <&sys_32k_ck>;
1057                 ti,bit-shift = <8>;
1058                 reg = <0x1480>;
1059         };
1060
1061         sgx_clk_mux: sgx_clk_mux@1220 {
1062                 #clock-cells = <0>;
1063                 compatible = "ti,mux-clock";
1064                 clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
1065                 ti,bit-shift = <24>;
1066                 reg = <0x1220>;
1067         };
1068
1069         hsi_fck: hsi_fck@1338 {
1070                 #clock-cells = <0>;
1071                 compatible = "ti,divider-clock";
1072                 clocks = <&dpll_per_m2x2_ck>;
1073                 ti,bit-shift = <24>;
1074                 ti,max-div = <4>;
1075                 reg = <0x1338>;
1076                 ti,index-power-of-two;
1077         };
1078
1079         iss_ctrlclk: iss_ctrlclk@1020 {
1080                 #clock-cells = <0>;
1081                 compatible = "ti,gate-clock";
1082                 clocks = <&func_96m_fclk>;
1083                 ti,bit-shift = <8>;
1084                 reg = <0x1020>;
1085         };
1086
1087         mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@14e0 {
1088                 #clock-cells = <0>;
1089                 compatible = "ti,mux-clock";
1090                 clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
1091                 ti,bit-shift = <25>;
1092                 reg = <0x14e0>;
1093         };
1094
1095         per_mcbsp4_gfclk: per_mcbsp4_gfclk@14e0 {
1096                 #clock-cells = <0>;
1097                 compatible = "ti,mux-clock";
1098                 clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
1099                 ti,bit-shift = <24>;
1100                 reg = <0x14e0>;
1101         };
1102
1103         hsmmc1_fclk: hsmmc1_fclk@1328 {
1104                 #clock-cells = <0>;
1105                 compatible = "ti,mux-clock";
1106                 clocks = <&func_64m_fclk>, <&func_96m_fclk>;
1107                 ti,bit-shift = <24>;
1108                 reg = <0x1328>;
1109         };
1110
1111         hsmmc2_fclk: hsmmc2_fclk@1330 {
1112                 #clock-cells = <0>;
1113                 compatible = "ti,mux-clock";
1114                 clocks = <&func_64m_fclk>, <&func_96m_fclk>;
1115                 ti,bit-shift = <24>;
1116                 reg = <0x1330>;
1117         };
1118
1119         ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@13e0 {
1120                 #clock-cells = <0>;
1121                 compatible = "ti,gate-clock";
1122                 clocks = <&func_48m_fclk>;
1123                 ti,bit-shift = <8>;
1124                 reg = <0x13e0>;
1125         };
1126
1127         sha2md5_fck: sha2md5_fck@15c8 {
1128                 #clock-cells = <0>;
1129                 compatible = "ti,gate-clock";
1130                 clocks = <&l3_div_ck>;
1131                 ti,bit-shift = <1>;
1132                 reg = <0x15c8>;
1133         };
1134
1135         slimbus2_fclk_1: slimbus2_fclk_1@1538 {
1136                 #clock-cells = <0>;
1137                 compatible = "ti,gate-clock";
1138                 clocks = <&per_abe_24m_fclk>;
1139                 ti,bit-shift = <9>;
1140                 reg = <0x1538>;
1141         };
1142
1143         slimbus2_fclk_0: slimbus2_fclk_0@1538 {
1144                 #clock-cells = <0>;
1145                 compatible = "ti,gate-clock";
1146                 clocks = <&func_24mc_fclk>;
1147                 ti,bit-shift = <8>;
1148                 reg = <0x1538>;
1149         };
1150
1151         slimbus2_slimbus_clk: slimbus2_slimbus_clk@1538 {
1152                 #clock-cells = <0>;
1153                 compatible = "ti,gate-clock";
1154                 clocks = <&pad_slimbus_core_clks_ck>;
1155                 ti,bit-shift = <10>;
1156                 reg = <0x1538>;
1157         };
1158
1159         smartreflex_core_fck: smartreflex_core_fck@638 {
1160                 #clock-cells = <0>;
1161                 compatible = "ti,gate-clock";
1162                 clocks = <&l4_wkup_clk_mux_ck>;
1163                 ti,bit-shift = <1>;
1164                 reg = <0x0638>;
1165         };
1166
1167         smartreflex_iva_fck: smartreflex_iva_fck@630 {
1168                 #clock-cells = <0>;
1169                 compatible = "ti,gate-clock";
1170                 clocks = <&l4_wkup_clk_mux_ck>;
1171                 ti,bit-shift = <1>;
1172                 reg = <0x0630>;
1173         };
1174
1175         smartreflex_mpu_fck: smartreflex_mpu_fck@628 {
1176                 #clock-cells = <0>;
1177                 compatible = "ti,gate-clock";
1178                 clocks = <&l4_wkup_clk_mux_ck>;
1179                 ti,bit-shift = <1>;
1180                 reg = <0x0628>;
1181         };
1182
1183         cm2_dm10_mux: cm2_dm10_mux@1428 {
1184                 #clock-cells = <0>;
1185                 compatible = "ti,mux-clock";
1186                 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
1187                 ti,bit-shift = <24>;
1188                 reg = <0x1428>;
1189         };
1190
1191         cm2_dm11_mux: cm2_dm11_mux@1430 {
1192                 #clock-cells = <0>;
1193                 compatible = "ti,mux-clock";
1194                 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
1195                 ti,bit-shift = <24>;
1196                 reg = <0x1430>;
1197         };
1198
1199         cm2_dm2_mux: cm2_dm2_mux@1438 {
1200                 #clock-cells = <0>;
1201                 compatible = "ti,mux-clock";
1202                 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
1203                 ti,bit-shift = <24>;
1204                 reg = <0x1438>;
1205         };
1206
1207         cm2_dm3_mux: cm2_dm3_mux@1440 {
1208                 #clock-cells = <0>;
1209                 compatible = "ti,mux-clock";
1210                 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
1211                 ti,bit-shift = <24>;
1212                 reg = <0x1440>;
1213         };
1214
1215         cm2_dm4_mux: cm2_dm4_mux@1448 {
1216                 #clock-cells = <0>;
1217                 compatible = "ti,mux-clock";
1218                 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
1219                 ti,bit-shift = <24>;
1220                 reg = <0x1448>;
1221         };
1222
1223         cm2_dm9_mux: cm2_dm9_mux@1450 {
1224                 #clock-cells = <0>;
1225                 compatible = "ti,mux-clock";
1226                 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
1227                 ti,bit-shift = <24>;
1228                 reg = <0x1450>;
1229         };
1230
1231         usb_host_fs_fck: usb_host_fs_fck@13d0 {
1232                 #clock-cells = <0>;
1233                 compatible = "ti,gate-clock";
1234                 clocks = <&func_48mc_fclk>;
1235                 ti,bit-shift = <1>;
1236                 reg = <0x13d0>;
1237         };
1238
1239         utmi_p1_gfclk: utmi_p1_gfclk@1358 {
1240                 #clock-cells = <0>;
1241                 compatible = "ti,mux-clock";
1242                 clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
1243                 ti,bit-shift = <24>;
1244                 reg = <0x1358>;
1245         };
1246
1247         usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1358 {
1248                 #clock-cells = <0>;
1249                 compatible = "ti,gate-clock";
1250                 clocks = <&utmi_p1_gfclk>;
1251                 ti,bit-shift = <8>;
1252                 reg = <0x1358>;
1253         };
1254
1255         utmi_p2_gfclk: utmi_p2_gfclk@1358 {
1256                 #clock-cells = <0>;
1257                 compatible = "ti,mux-clock";
1258                 clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
1259                 ti,bit-shift = <25>;
1260                 reg = <0x1358>;
1261         };
1262
1263         usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1358 {
1264                 #clock-cells = <0>;
1265                 compatible = "ti,gate-clock";
1266                 clocks = <&utmi_p2_gfclk>;
1267                 ti,bit-shift = <9>;
1268                 reg = <0x1358>;
1269         };
1270
1271         usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1358 {
1272                 #clock-cells = <0>;
1273                 compatible = "ti,gate-clock";
1274                 clocks = <&init_60m_fclk>;
1275                 ti,bit-shift = <10>;
1276                 reg = <0x1358>;
1277         };
1278
1279         usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1358 {
1280                 #clock-cells = <0>;
1281                 compatible = "ti,gate-clock";
1282                 clocks = <&dpll_usb_m2_ck>;
1283                 ti,bit-shift = <13>;
1284                 reg = <0x1358>;
1285         };
1286
1287         usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1358 {
1288                 #clock-cells = <0>;
1289                 compatible = "ti,gate-clock";
1290                 clocks = <&init_60m_fclk>;
1291                 ti,bit-shift = <11>;
1292                 reg = <0x1358>;
1293         };
1294
1295         usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1358 {
1296                 #clock-cells = <0>;
1297                 compatible = "ti,gate-clock";
1298                 clocks = <&init_60m_fclk>;
1299                 ti,bit-shift = <12>;
1300                 reg = <0x1358>;
1301         };
1302
1303         usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1358 {
1304                 #clock-cells = <0>;
1305                 compatible = "ti,gate-clock";
1306                 clocks = <&dpll_usb_m2_ck>;
1307                 ti,bit-shift = <14>;
1308                 reg = <0x1358>;
1309         };
1310
1311         usb_host_hs_func48mclk: usb_host_hs_func48mclk@1358 {
1312                 #clock-cells = <0>;
1313                 compatible = "ti,gate-clock";
1314                 clocks = <&func_48mc_fclk>;
1315                 ti,bit-shift = <15>;
1316                 reg = <0x1358>;
1317         };
1318
1319         usb_host_hs_fck: usb_host_hs_fck@1358 {
1320                 #clock-cells = <0>;
1321                 compatible = "ti,gate-clock";
1322                 clocks = <&init_60m_fclk>;
1323                 ti,bit-shift = <1>;
1324                 reg = <0x1358>;
1325         };
1326
1327         otg_60m_gfclk: otg_60m_gfclk@1360 {
1328                 #clock-cells = <0>;
1329                 compatible = "ti,mux-clock";
1330                 clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
1331                 ti,bit-shift = <24>;
1332                 reg = <0x1360>;
1333         };
1334
1335         usb_otg_hs_xclk: usb_otg_hs_xclk@1360 {
1336                 #clock-cells = <0>;
1337                 compatible = "ti,gate-clock";
1338                 clocks = <&otg_60m_gfclk>;
1339                 ti,bit-shift = <8>;
1340                 reg = <0x1360>;
1341         };
1342
1343         usb_otg_hs_ick: usb_otg_hs_ick@1360 {
1344                 #clock-cells = <0>;
1345                 compatible = "ti,gate-clock";
1346                 clocks = <&l3_div_ck>;
1347                 ti,bit-shift = <0>;
1348                 reg = <0x1360>;
1349         };
1350
1351         usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
1352                 #clock-cells = <0>;
1353                 compatible = "ti,gate-clock";
1354                 clocks = <&sys_32k_ck>;
1355                 ti,bit-shift = <8>;
1356                 reg = <0x0640>;
1357         };
1358
1359         usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1368 {
1360                 #clock-cells = <0>;
1361                 compatible = "ti,gate-clock";
1362                 clocks = <&init_60m_fclk>;
1363                 ti,bit-shift = <10>;
1364                 reg = <0x1368>;
1365         };
1366
1367         usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1368 {
1368                 #clock-cells = <0>;
1369                 compatible = "ti,gate-clock";
1370                 clocks = <&init_60m_fclk>;
1371                 ti,bit-shift = <8>;
1372                 reg = <0x1368>;
1373         };
1374
1375         usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1368 {
1376                 #clock-cells = <0>;
1377                 compatible = "ti,gate-clock";
1378                 clocks = <&init_60m_fclk>;
1379                 ti,bit-shift = <9>;
1380                 reg = <0x1368>;
1381         };
1382
1383         usb_tll_hs_ick: usb_tll_hs_ick@1368 {
1384                 #clock-cells = <0>;
1385                 compatible = "ti,gate-clock";
1386                 clocks = <&l4_div_ck>;
1387                 ti,bit-shift = <0>;
1388                 reg = <0x1368>;
1389         };
1390 };
1391
1392 &cm2_clockdomains {
1393         l3_init_clkdm: l3_init_clkdm {
1394                 compatible = "ti,clockdomain";
1395                 clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>;
1396         };
1397 };
1398
1399 &scrm_clocks {
1400         auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
1401                 #clock-cells = <0>;
1402                 compatible = "ti,composite-no-wait-gate-clock";
1403                 clocks = <&dpll_core_m3x2_ck>;
1404                 ti,bit-shift = <8>;
1405                 reg = <0x0310>;
1406         };
1407
1408         auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
1409                 #clock-cells = <0>;
1410                 compatible = "ti,composite-mux-clock";
1411                 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1412                 ti,bit-shift = <1>;
1413                 reg = <0x0310>;
1414         };
1415
1416         auxclk0_src_ck: auxclk0_src_ck {
1417                 #clock-cells = <0>;
1418                 compatible = "ti,composite-clock";
1419                 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
1420         };
1421
1422         auxclk0_ck: auxclk0_ck@310 {
1423                 #clock-cells = <0>;
1424                 compatible = "ti,divider-clock";
1425                 clocks = <&auxclk0_src_ck>;
1426                 ti,bit-shift = <16>;
1427                 ti,max-div = <16>;
1428                 reg = <0x0310>;
1429         };
1430
1431         auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
1432                 #clock-cells = <0>;
1433                 compatible = "ti,composite-no-wait-gate-clock";
1434                 clocks = <&dpll_core_m3x2_ck>;
1435                 ti,bit-shift = <8>;
1436                 reg = <0x0314>;
1437         };
1438
1439         auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
1440                 #clock-cells = <0>;
1441                 compatible = "ti,composite-mux-clock";
1442                 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1443                 ti,bit-shift = <1>;
1444                 reg = <0x0314>;
1445         };
1446
1447         auxclk1_src_ck: auxclk1_src_ck {
1448                 #clock-cells = <0>;
1449                 compatible = "ti,composite-clock";
1450                 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
1451         };
1452
1453         auxclk1_ck: auxclk1_ck@314 {
1454                 #clock-cells = <0>;
1455                 compatible = "ti,divider-clock";
1456                 clocks = <&auxclk1_src_ck>;
1457                 ti,bit-shift = <16>;
1458                 ti,max-div = <16>;
1459                 reg = <0x0314>;
1460         };
1461
1462         auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
1463                 #clock-cells = <0>;
1464                 compatible = "ti,composite-no-wait-gate-clock";
1465                 clocks = <&dpll_core_m3x2_ck>;
1466                 ti,bit-shift = <8>;
1467                 reg = <0x0318>;
1468         };
1469
1470         auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
1471                 #clock-cells = <0>;
1472                 compatible = "ti,composite-mux-clock";
1473                 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1474                 ti,bit-shift = <1>;
1475                 reg = <0x0318>;
1476         };
1477
1478         auxclk2_src_ck: auxclk2_src_ck {
1479                 #clock-cells = <0>;
1480                 compatible = "ti,composite-clock";
1481                 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
1482         };
1483
1484         auxclk2_ck: auxclk2_ck@318 {
1485                 #clock-cells = <0>;
1486                 compatible = "ti,divider-clock";
1487                 clocks = <&auxclk2_src_ck>;
1488                 ti,bit-shift = <16>;
1489                 ti,max-div = <16>;
1490                 reg = <0x0318>;
1491         };
1492
1493         auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
1494                 #clock-cells = <0>;
1495                 compatible = "ti,composite-no-wait-gate-clock";
1496                 clocks = <&dpll_core_m3x2_ck>;
1497                 ti,bit-shift = <8>;
1498                 reg = <0x031c>;
1499         };
1500
1501         auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
1502                 #clock-cells = <0>;
1503                 compatible = "ti,composite-mux-clock";
1504                 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1505                 ti,bit-shift = <1>;
1506                 reg = <0x031c>;
1507         };
1508
1509         auxclk3_src_ck: auxclk3_src_ck {
1510                 #clock-cells = <0>;
1511                 compatible = "ti,composite-clock";
1512                 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
1513         };
1514
1515         auxclk3_ck: auxclk3_ck@31c {
1516                 #clock-cells = <0>;
1517                 compatible = "ti,divider-clock";
1518                 clocks = <&auxclk3_src_ck>;
1519                 ti,bit-shift = <16>;
1520                 ti,max-div = <16>;
1521                 reg = <0x031c>;
1522         };
1523
1524         auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
1525                 #clock-cells = <0>;
1526                 compatible = "ti,composite-no-wait-gate-clock";
1527                 clocks = <&dpll_core_m3x2_ck>;
1528                 ti,bit-shift = <8>;
1529                 reg = <0x0320>;
1530         };
1531
1532         auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
1533                 #clock-cells = <0>;
1534                 compatible = "ti,composite-mux-clock";
1535                 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1536                 ti,bit-shift = <1>;
1537                 reg = <0x0320>;
1538         };
1539
1540         auxclk4_src_ck: auxclk4_src_ck {
1541                 #clock-cells = <0>;
1542                 compatible = "ti,composite-clock";
1543                 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
1544         };
1545
1546         auxclk4_ck: auxclk4_ck@320 {
1547                 #clock-cells = <0>;
1548                 compatible = "ti,divider-clock";
1549                 clocks = <&auxclk4_src_ck>;
1550                 ti,bit-shift = <16>;
1551                 ti,max-div = <16>;
1552                 reg = <0x0320>;
1553         };
1554
1555         auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
1556                 #clock-cells = <0>;
1557                 compatible = "ti,composite-no-wait-gate-clock";
1558                 clocks = <&dpll_core_m3x2_ck>;
1559                 ti,bit-shift = <8>;
1560                 reg = <0x0324>;
1561         };
1562
1563         auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
1564                 #clock-cells = <0>;
1565                 compatible = "ti,composite-mux-clock";
1566                 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1567                 ti,bit-shift = <1>;
1568                 reg = <0x0324>;
1569         };
1570
1571         auxclk5_src_ck: auxclk5_src_ck {
1572                 #clock-cells = <0>;
1573                 compatible = "ti,composite-clock";
1574                 clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
1575         };
1576
1577         auxclk5_ck: auxclk5_ck@324 {
1578                 #clock-cells = <0>;
1579                 compatible = "ti,divider-clock";
1580                 clocks = <&auxclk5_src_ck>;
1581                 ti,bit-shift = <16>;
1582                 ti,max-div = <16>;
1583                 reg = <0x0324>;
1584         };
1585
1586         auxclkreq0_ck: auxclkreq0_ck@210 {
1587                 #clock-cells = <0>;
1588                 compatible = "ti,mux-clock";
1589                 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1590                 ti,bit-shift = <2>;
1591                 reg = <0x0210>;
1592         };
1593
1594         auxclkreq1_ck: auxclkreq1_ck@214 {
1595                 #clock-cells = <0>;
1596                 compatible = "ti,mux-clock";
1597                 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1598                 ti,bit-shift = <2>;
1599                 reg = <0x0214>;
1600         };
1601
1602         auxclkreq2_ck: auxclkreq2_ck@218 {
1603                 #clock-cells = <0>;
1604                 compatible = "ti,mux-clock";
1605                 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1606                 ti,bit-shift = <2>;
1607                 reg = <0x0218>;
1608         };
1609
1610         auxclkreq3_ck: auxclkreq3_ck@21c {
1611                 #clock-cells = <0>;
1612                 compatible = "ti,mux-clock";
1613                 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1614                 ti,bit-shift = <2>;
1615                 reg = <0x021c>;
1616         };
1617
1618         auxclkreq4_ck: auxclkreq4_ck@220 {
1619                 #clock-cells = <0>;
1620                 compatible = "ti,mux-clock";
1621                 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1622                 ti,bit-shift = <2>;
1623                 reg = <0x0220>;
1624         };
1625
1626         auxclkreq5_ck: auxclkreq5_ck@224 {
1627                 #clock-cells = <0>;
1628                 compatible = "ti,mux-clock";
1629                 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1630                 ti,bit-shift = <2>;
1631                 reg = <0x0224>;
1632         };
1633 };