arch/arm/boot/dts/omap54xx-clocks.dtsi

   1 /*
   2  * Device Tree Source for OMAP5 clock data
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 &cm_core_aon_clocks {
  11         pad_clks_src_ck: pad_clks_src_ck {
  12                 #clock-cells = <0>;
  13                 compatible = "fixed-clock";
  14                 clock-frequency = <12000000>;
  15         };
  16
  17         pad_clks_ck: pad_clks_ck@108 {
  18                 #clock-cells = <0>;
  19                 compatible = "ti,gate-clock";
  20                 clocks = <&pad_clks_src_ck>;
  21                 ti,bit-shift = <8>;
  22                 reg = <0x0108>;
  23         };
  24
  25         secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  26                 #clock-cells = <0>;
  27                 compatible = "fixed-clock";
  28                 clock-frequency = <32768>;
  29         };
  30
  31         slimbus_src_clk: slimbus_src_clk {
  32                 #clock-cells = <0>;
  33                 compatible = "fixed-clock";
  34                 clock-frequency = <12000000>;
  35         };
  36
  37         slimbus_clk: slimbus_clk@108 {
  38                 #clock-cells = <0>;
  39                 compatible = "ti,gate-clock";
  40                 clocks = <&slimbus_src_clk>;
  41                 ti,bit-shift = <10>;
  42                 reg = <0x0108>;
  43         };
  44
  45         sys_32k_ck: sys_32k_ck {
  46                 #clock-cells = <0>;
  47                 compatible = "fixed-clock";
  48                 clock-frequency = <32768>;
  49         };
  50
  51         virt_12000000_ck: virt_12000000_ck {
  52                 #clock-cells = <0>;
  53                 compatible = "fixed-clock";
  54                 clock-frequency = <12000000>;
  55         };
  56
  57         virt_13000000_ck: virt_13000000_ck {
  58                 #clock-cells = <0>;
  59                 compatible = "fixed-clock";
  60                 clock-frequency = <13000000>;
  61         };
  62
  63         virt_16800000_ck: virt_16800000_ck {
  64                 #clock-cells = <0>;
  65                 compatible = "fixed-clock";
  66                 clock-frequency = <16800000>;
  67         };
  68
  69         virt_19200000_ck: virt_19200000_ck {
  70                 #clock-cells = <0>;
  71                 compatible = "fixed-clock";
  72                 clock-frequency = <19200000>;
  73         };
  74
  75         virt_26000000_ck: virt_26000000_ck {
  76                 #clock-cells = <0>;
  77                 compatible = "fixed-clock";
  78                 clock-frequency = <26000000>;
  79         };
  80
  81         virt_27000000_ck: virt_27000000_ck {
  82                 #clock-cells = <0>;
  83                 compatible = "fixed-clock";
  84                 clock-frequency = <27000000>;
  85         };
  86
  87         virt_38400000_ck: virt_38400000_ck {
  88                 #clock-cells = <0>;
  89                 compatible = "fixed-clock";
  90                 clock-frequency = <38400000>;
  91         };
  92
  93         xclk60mhsp1_ck: xclk60mhsp1_ck {
  94                 #clock-cells = <0>;
  95                 compatible = "fixed-clock";
  96                 clock-frequency = <60000000>;
  97         };
  98
  99         xclk60mhsp2_ck: xclk60mhsp2_ck {
 100                 #clock-cells = <0>;
 101                 compatible = "fixed-clock";
 102                 clock-frequency = <60000000>;
 103         };
 104
 105         dpll_abe_ck: dpll_abe_ck@1e0 {
 106                 #clock-cells = <0>;
 107                 compatible = "ti,omap4-dpll-m4xen-clock";
 108                 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
 109                 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 110         };
 111
 112         dpll_abe_x2_ck: dpll_abe_x2_ck {
 113                 #clock-cells = <0>;
 114                 compatible = "ti,omap4-dpll-x2-clock";
 115                 clocks = <&dpll_abe_ck>;
 116         };
 117
 118         dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 119                 #clock-cells = <0>;
 120                 compatible = "ti,divider-clock";
 121                 clocks = <&dpll_abe_x2_ck>;
 122                 ti,max-div = <31>;
 123                 reg = <0x01f0>;
 124                 ti,index-starts-at-one;
 125         };
 126
 127         abe_24m_fclk: abe_24m_fclk {
 128                 #clock-cells = <0>;
 129                 compatible = "fixed-factor-clock";
 130                 clocks = <&dpll_abe_m2x2_ck>;
 131                 clock-mult = <1>;
 132                 clock-div = <8>;
 133         };
 134
 135         abe_clk: abe_clk@108 {
 136                 #clock-cells = <0>;
 137                 compatible = "ti,divider-clock";
 138                 clocks = <&dpll_abe_m2x2_ck>;
 139                 ti,max-div = <4>;
 140                 reg = <0x0108>;
 141                 ti,index-power-of-two;
 142         };
 143
 144         abe_iclk: abe_iclk@528 {
 145                 #clock-cells = <0>;
 146                 compatible = "ti,divider-clock";
 147                 clocks = <&aess_fclk>;
 148                 ti,bit-shift = <24>;
 149                 reg = <0x0528>;
 150                 ti,dividers = <2>, <1>;
 151         };
 152
 153         abe_lp_clk_div: abe_lp_clk_div {
 154                 #clock-cells = <0>;
 155                 compatible = "fixed-factor-clock";
 156                 clocks = <&dpll_abe_m2x2_ck>;
 157                 clock-mult = <1>;
 158                 clock-div = <16>;
 159         };
 160
 161         dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 162                 #clock-cells = <0>;
 163                 compatible = "ti,divider-clock";
 164                 clocks = <&dpll_abe_x2_ck>;
 165                 ti,max-div = <31>;
 166                 reg = <0x01f4>;
 167                 ti,index-starts-at-one;
 168         };
 169
 170         dpll_core_byp_mux: dpll_core_byp_mux@12c {
 171                 #clock-cells = <0>;
 172                 compatible = "ti,mux-clock";
 173                 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
 174                 ti,bit-shift = <23>;
 175                 reg = <0x012c>;
 176         };
 177
 178         dpll_core_ck: dpll_core_ck@120 {
 179                 #clock-cells = <0>;
 180                 compatible = "ti,omap4-dpll-core-clock";
 181                 clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
 182                 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 183         };
 184
 185         dpll_core_x2_ck: dpll_core_x2_ck {
 186                 #clock-cells = <0>;
 187                 compatible = "ti,omap4-dpll-x2-clock";
 188                 clocks = <&dpll_core_ck>;
 189         };
 190
 191         dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
 192                 #clock-cells = <0>;
 193                 compatible = "ti,divider-clock";
 194                 clocks = <&dpll_core_x2_ck>;
 195                 ti,max-div = <63>;
 196                 reg = <0x0150>;
 197                 ti,index-starts-at-one;
 198         };
 199
 200         c2c_fclk: c2c_fclk {
 201                 #clock-cells = <0>;
 202                 compatible = "fixed-factor-clock";
 203                 clocks = <&dpll_core_h21x2_ck>;
 204                 clock-mult = <1>;
 205                 clock-div = <1>;
 206         };
 207
 208         c2c_iclk: c2c_iclk {
 209                 #clock-cells = <0>;
 210                 compatible = "fixed-factor-clock";
 211                 clocks = <&c2c_fclk>;
 212                 clock-mult = <1>;
 213                 clock-div = <2>;
 214         };
 215
 216         dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
 217                 #clock-cells = <0>;
 218                 compatible = "ti,divider-clock";
 219                 clocks = <&dpll_core_x2_ck>;
 220                 ti,max-div = <63>;
 221                 reg = <0x0138>;
 222                 ti,index-starts-at-one;
 223         };
 224
 225         dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
 226                 #clock-cells = <0>;
 227                 compatible = "ti,divider-clock";
 228                 clocks = <&dpll_core_x2_ck>;
 229                 ti,max-div = <63>;
 230                 reg = <0x013c>;
 231                 ti,index-starts-at-one;
 232         };
 233
 234         dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
 235                 #clock-cells = <0>;
 236                 compatible = "ti,divider-clock";
 237                 clocks = <&dpll_core_x2_ck>;
 238                 ti,max-div = <63>;
 239                 reg = <0x0140>;
 240                 ti,index-starts-at-one;
 241         };
 242
 243         dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
 244                 #clock-cells = <0>;
 245                 compatible = "ti,divider-clock";
 246                 clocks = <&dpll_core_x2_ck>;
 247                 ti,max-div = <63>;
 248                 reg = <0x0144>;
 249                 ti,index-starts-at-one;
 250         };
 251
 252         dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
 253                 #clock-cells = <0>;
 254                 compatible = "ti,divider-clock";
 255                 clocks = <&dpll_core_x2_ck>;
 256                 ti,max-div = <63>;
 257                 reg = <0x0154>;
 258                 ti,index-starts-at-one;
 259         };
 260
 261         dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
 262                 #clock-cells = <0>;
 263                 compatible = "ti,divider-clock";
 264                 clocks = <&dpll_core_x2_ck>;
 265                 ti,max-div = <63>;
 266                 reg = <0x0158>;
 267                 ti,index-starts-at-one;
 268         };
 269
 270         dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
 271                 #clock-cells = <0>;
 272                 compatible = "ti,divider-clock";
 273                 clocks = <&dpll_core_x2_ck>;
 274                 ti,max-div = <63>;
 275                 reg = <0x015c>;
 276                 ti,index-starts-at-one;
 277         };
 278
 279         dpll_core_m2_ck: dpll_core_m2_ck@130 {
 280                 #clock-cells = <0>;
 281                 compatible = "ti,divider-clock";
 282                 clocks = <&dpll_core_ck>;
 283                 ti,max-div = <31>;
 284                 reg = <0x0130>;
 285                 ti,index-starts-at-one;
 286         };
 287
 288         dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
 289                 #clock-cells = <0>;
 290                 compatible = "ti,divider-clock";
 291                 clocks = <&dpll_core_x2_ck>;
 292                 ti,max-div = <31>;
 293                 reg = <0x0134>;
 294                 ti,index-starts-at-one;
 295         };
 296
 297         iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
 298                 #clock-cells = <0>;
 299                 compatible = "fixed-factor-clock";
 300                 clocks = <&dpll_core_h12x2_ck>;
 301                 clock-mult = <1>;
 302                 clock-div = <1>;
 303         };
 304
 305         dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
 306                 #clock-cells = <0>;
 307                 compatible = "ti,mux-clock";
 308                 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
 309                 ti,bit-shift = <23>;
 310                 reg = <0x01ac>;
 311         };
 312
 313         dpll_iva_ck: dpll_iva_ck@1a0 {
 314                 #clock-cells = <0>;
 315                 compatible = "ti,omap4-dpll-clock";
 316                 clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
 317                 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 318                 assigned-clocks = <&dpll_iva_ck>;
 319                 assigned-clock-rates = <1165000000>;
 320         };
 321
 322         dpll_iva_x2_ck: dpll_iva_x2_ck {
 323                 #clock-cells = <0>;
 324                 compatible = "ti,omap4-dpll-x2-clock";
 325                 clocks = <&dpll_iva_ck>;
 326         };
 327
 328         dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
 329                 #clock-cells = <0>;
 330                 compatible = "ti,divider-clock";
 331                 clocks = <&dpll_iva_x2_ck>;
 332                 ti,max-div = <63>;
 333                 reg = <0x01b8>;
 334                 ti,index-starts-at-one;
 335                 assigned-clocks = <&dpll_iva_h11x2_ck>;
 336                 assigned-clock-rates = <465920000>;
 337         };
 338
 339         dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
 340                 #clock-cells = <0>;
 341                 compatible = "ti,divider-clock";
 342                 clocks = <&dpll_iva_x2_ck>;
 343                 ti,max-div = <63>;
 344                 reg = <0x01bc>;
 345                 ti,index-starts-at-one;
 346                 assigned-clocks = <&dpll_iva_h12x2_ck>;
 347                 assigned-clock-rates = <388300000>;
 348         };
 349
 350         mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
 351                 #clock-cells = <0>;
 352                 compatible = "fixed-factor-clock";
 353                 clocks = <&dpll_core_h12x2_ck>;
 354                 clock-mult = <1>;
 355                 clock-div = <1>;
 356         };
 357
 358         dpll_mpu_ck: dpll_mpu_ck@160 {
 359                 #clock-cells = <0>;
 360                 compatible = "ti,omap5-mpu-dpll-clock";
 361                 clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
 362                 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 363         };
 364
 365         dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 366                 #clock-cells = <0>;
 367                 compatible = "ti,divider-clock";
 368                 clocks = <&dpll_mpu_ck>;
 369                 ti,max-div = <31>;
 370                 reg = <0x0170>;
 371                 ti,index-starts-at-one;
 372         };
 373
 374         per_dpll_hs_clk_div: per_dpll_hs_clk_div {
 375                 #clock-cells = <0>;
 376                 compatible = "fixed-factor-clock";
 377                 clocks = <&dpll_abe_m3x2_ck>;
 378                 clock-mult = <1>;
 379                 clock-div = <2>;
 380         };
 381
 382         usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
 383                 #clock-cells = <0>;
 384                 compatible = "fixed-factor-clock";
 385                 clocks = <&dpll_abe_m3x2_ck>;
 386                 clock-mult = <1>;
 387                 clock-div = <3>;
 388         };
 389
 390         l3_iclk_div: l3_iclk_div@100 {
 391                 #clock-cells = <0>;
 392                 compatible = "ti,divider-clock";
 393                 ti,max-div = <2>;
 394                 ti,bit-shift = <4>;
 395                 reg = <0x100>;
 396                 clocks = <&dpll_core_h12x2_ck>;
 397                 ti,index-power-of-two;
 398         };
 399
 400         gpu_l3_iclk: gpu_l3_iclk {
 401                 #clock-cells = <0>;
 402                 compatible = "fixed-factor-clock";
 403                 clocks = <&l3_iclk_div>;
 404                 clock-mult = <1>;
 405                 clock-div = <1>;
 406         };
 407
 408         l4_root_clk_div: l4_root_clk_div@100 {
 409                 #clock-cells = <0>;
 410                 compatible = "ti,divider-clock";
 411                 ti,max-div = <2>;
 412                 ti,bit-shift = <8>;
 413                 reg = <0x100>;
 414                 clocks = <&l3_iclk_div>;
 415                 ti,index-power-of-two;
 416         };
 417
 418         slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
 419                 #clock-cells = <0>;
 420                 compatible = "ti,gate-clock";
 421                 clocks = <&slimbus_clk>;
 422                 ti,bit-shift = <11>;
 423                 reg = <0x0560>;
 424         };
 425
 426         aess_fclk: aess_fclk@528 {
 427                 #clock-cells = <0>;
 428                 compatible = "ti,divider-clock";
 429                 clocks = <&abe_clk>;
 430                 ti,bit-shift = <24>;
 431                 ti,max-div = <2>;
 432                 reg = <0x0528>;
 433         };
 434
 435         dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
 436                 #clock-cells = <0>;
 437                 compatible = "ti,mux-clock";
 438                 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
 439                 ti,bit-shift = <26>;
 440                 reg = <0x0538>;
 441         };
 442
 443         dmic_gfclk: dmic_gfclk@538 {
 444                 #clock-cells = <0>;
 445                 compatible = "ti,mux-clock";
 446                 clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
 447                 ti,bit-shift = <24>;
 448                 reg = <0x0538>;
 449         };
 450
 451         mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
 452                 #clock-cells = <0>;
 453                 compatible = "ti,mux-clock";
 454                 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
 455                 ti,bit-shift = <26>;
 456                 reg = <0x0540>;
 457         };
 458
 459         mcasp_gfclk: mcasp_gfclk@540 {
 460                 #clock-cells = <0>;
 461                 compatible = "ti,mux-clock";
 462                 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
 463                 ti,bit-shift = <24>;
 464                 reg = <0x0540>;
 465         };
 466
 467         mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
 468                 #clock-cells = <0>;
 469                 compatible = "ti,mux-clock";
 470                 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
 471                 ti,bit-shift = <26>;
 472                 reg = <0x0548>;
 473         };
 474
 475         mcbsp1_gfclk: mcbsp1_gfclk@548 {
 476                 #clock-cells = <0>;
 477                 compatible = "ti,mux-clock";
 478                 clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
 479                 ti,bit-shift = <24>;
 480                 reg = <0x0548>;
 481         };
 482
 483         mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
 484                 #clock-cells = <0>;
 485                 compatible = "ti,mux-clock";
 486                 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
 487                 ti,bit-shift = <26>;
 488                 reg = <0x0550>;
 489         };
 490
 491         mcbsp2_gfclk: mcbsp2_gfclk@550 {
 492                 #clock-cells = <0>;
 493                 compatible = "ti,mux-clock";
 494                 clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
 495                 ti,bit-shift = <24>;
 496                 reg = <0x0550>;
 497         };
 498
 499         mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
 500                 #clock-cells = <0>;
 501                 compatible = "ti,mux-clock";
 502                 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
 503                 ti,bit-shift = <26>;
 504                 reg = <0x0558>;
 505         };
 506
 507         mcbsp3_gfclk: mcbsp3_gfclk@558 {
 508                 #clock-cells = <0>;
 509                 compatible = "ti,mux-clock";
 510                 clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
 511                 ti,bit-shift = <24>;
 512                 reg = <0x0558>;
 513         };
 514
 515         timer5_gfclk_mux: timer5_gfclk_mux@568 {
 516                 #clock-cells = <0>;
 517                 compatible = "ti,mux-clock";
 518                 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
 519                 ti,bit-shift = <24>;
 520                 reg = <0x0568>;
 521         };
 522
 523         timer6_gfclk_mux: timer6_gfclk_mux@570 {
 524                 #clock-cells = <0>;
 525                 compatible = "ti,mux-clock";
 526                 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
 527                 ti,bit-shift = <24>;
 528                 reg = <0x0570>;
 529         };
 530
 531         timer7_gfclk_mux: timer7_gfclk_mux@578 {
 532                 #clock-cells = <0>;
 533                 compatible = "ti,mux-clock";
 534                 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
 535                 ti,bit-shift = <24>;
 536                 reg = <0x0578>;
 537         };
 538
 539         timer8_gfclk_mux: timer8_gfclk_mux@580 {
 540                 #clock-cells = <0>;
 541                 compatible = "ti,mux-clock";
 542                 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
 543                 ti,bit-shift = <24>;
 544                 reg = <0x0580>;
 545         };
 546
 547         dummy_ck: dummy_ck {
 548                 #clock-cells = <0>;
 549                 compatible = "fixed-clock";
 550                 clock-frequency = <0>;
 551         };
 552 };
 553 &prm_clocks {
 554         sys_clkin: sys_clkin@110 {
 555                 #clock-cells = <0>;
 556                 compatible = "ti,mux-clock";
 557                 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
 558                 reg = <0x0110>;
 559                 ti,index-starts-at-one;
 560         };
 561
 562         abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
 563                 #clock-cells = <0>;
 564                 compatible = "ti,mux-clock";
 565                 clocks = <&sys_clkin>, <&sys_32k_ck>;
 566                 reg = <0x0108>;
 567         };
 568
 569         abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
 570                 #clock-cells = <0>;
 571                 compatible = "ti,mux-clock";
 572                 clocks = <&sys_clkin>, <&sys_32k_ck>;
 573                 reg = <0x010c>;
 574         };
 575
 576         custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
 577                 #clock-cells = <0>;
 578                 compatible = "fixed-factor-clock";
 579                 clocks = <&sys_clkin>;
 580                 clock-mult = <1>;
 581                 clock-div = <2>;
 582         };
 583
 584         dss_syc_gfclk_div: dss_syc_gfclk_div {
 585                 #clock-cells = <0>;
 586                 compatible = "fixed-factor-clock";
 587                 clocks = <&sys_clkin>;
 588                 clock-mult = <1>;
 589                 clock-div = <1>;
 590         };
 591
 592         wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
 593                 #clock-cells = <0>;
 594                 compatible = "ti,mux-clock";
 595                 clocks = <&sys_clkin>, <&abe_lp_clk_div>;
 596                 reg = <0x0108>;
 597         };
 598
 599         l3instr_ts_gclk_div: l3instr_ts_gclk_div {
 600                 #clock-cells = <0>;
 601                 compatible = "fixed-factor-clock";
 602                 clocks = <&wkupaon_iclk_mux>;
 603                 clock-mult = <1>;
 604                 clock-div = <1>;
 605         };
 606
 607         gpio1_dbclk: gpio1_dbclk@1938 {
 608                 #clock-cells = <0>;
 609                 compatible = "ti,gate-clock";
 610                 clocks = <&sys_32k_ck>;
 611                 ti,bit-shift = <8>;
 612                 reg = <0x1938>;
 613         };
 614
 615         timer1_gfclk_mux: timer1_gfclk_mux@1940 {
 616                 #clock-cells = <0>;
 617                 compatible = "ti,mux-clock";
 618                 clocks = <&sys_clkin>, <&sys_32k_ck>;
 619                 ti,bit-shift = <24>;
 620                 reg = <0x1940>;
 621         };
 622 };
 623 &cm_core_clocks {
 624
 625         dpll_per_byp_mux: dpll_per_byp_mux@14c {
 626                 #clock-cells = <0>;
 627                 compatible = "ti,mux-clock";
 628                 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
 629                 ti,bit-shift = <23>;
 630                 reg = <0x014c>;
 631         };
 632
 633         dpll_per_ck: dpll_per_ck@140 {
 634                 #clock-cells = <0>;
 635                 compatible = "ti,omap4-dpll-clock";
 636                 clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
 637                 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
 638         };
 639
 640         dpll_per_x2_ck: dpll_per_x2_ck {
 641                 #clock-cells = <0>;
 642                 compatible = "ti,omap4-dpll-x2-clock";
 643                 clocks = <&dpll_per_ck>;
 644         };
 645
 646         dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
 647                 #clock-cells = <0>;
 648                 compatible = "ti,divider-clock";
 649                 clocks = <&dpll_per_x2_ck>;
 650                 ti,max-div = <63>;
 651                 reg = <0x0158>;
 652                 ti,index-starts-at-one;
 653         };
 654
 655         dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
 656                 #clock-cells = <0>;
 657                 compatible = "ti,divider-clock";
 658                 clocks = <&dpll_per_x2_ck>;
 659                 ti,max-div = <63>;
 660                 reg = <0x015c>;
 661                 ti,index-starts-at-one;
 662         };
 663
 664         dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
 665                 #clock-cells = <0>;
 666                 compatible = "ti,divider-clock";
 667                 clocks = <&dpll_per_x2_ck>;
 668                 ti,max-div = <63>;
 669                 reg = <0x0164>;
 670                 ti,index-starts-at-one;
 671         };
 672
 673         dpll_per_m2_ck: dpll_per_m2_ck@150 {
 674                 #clock-cells = <0>;
 675                 compatible = "ti,divider-clock";
 676                 clocks = <&dpll_per_ck>;
 677                 ti,max-div = <31>;
 678                 reg = <0x0150>;
 679                 ti,index-starts-at-one;
 680         };
 681
 682         dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
 683                 #clock-cells = <0>;
 684                 compatible = "ti,divider-clock";
 685                 clocks = <&dpll_per_x2_ck>;
 686                 ti,max-div = <31>;
 687                 reg = <0x0150>;
 688                 ti,index-starts-at-one;
 689         };
 690
 691         dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
 692                 #clock-cells = <0>;
 693                 compatible = "ti,divider-clock";
 694                 clocks = <&dpll_per_x2_ck>;
 695                 ti,max-div = <31>;
 696                 reg = <0x0154>;
 697                 ti,index-starts-at-one;
 698         };
 699
 700         dpll_unipro1_ck: dpll_unipro1_ck@200 {
 701                 #clock-cells = <0>;
 702                 compatible = "ti,omap4-dpll-clock";
 703                 clocks = <&sys_clkin>, <&sys_clkin>;
 704                 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
 705         };
 706
 707         dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
 708                 #clock-cells = <0>;
 709                 compatible = "fixed-factor-clock";
 710                 clocks = <&dpll_unipro1_ck>;
 711                 clock-mult = <1>;
 712                 clock-div = <1>;
 713         };
 714
 715         dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
 716                 #clock-cells = <0>;
 717                 compatible = "ti,divider-clock";
 718                 clocks = <&dpll_unipro1_ck>;
 719                 ti,max-div = <127>;
 720                 reg = <0x0210>;
 721                 ti,index-starts-at-one;
 722         };
 723
 724         dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
 725                 #clock-cells = <0>;
 726                 compatible = "ti,omap4-dpll-clock";
 727                 clocks = <&sys_clkin>, <&sys_clkin>;
 728                 reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
 729         };
 730
 731         dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
 732                 #clock-cells = <0>;
 733                 compatible = "fixed-factor-clock";
 734                 clocks = <&dpll_unipro2_ck>;
 735                 clock-mult = <1>;
 736                 clock-div = <1>;
 737         };
 738
 739         dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
 740                 #clock-cells = <0>;
 741                 compatible = "ti,divider-clock";
 742                 clocks = <&dpll_unipro2_ck>;
 743                 ti,max-div = <127>;
 744                 reg = <0x01d0>;
 745                 ti,index-starts-at-one;
 746         };
 747
 748         dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
 749                 #clock-cells = <0>;
 750                 compatible = "ti,mux-clock";
 751                 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
 752                 ti,bit-shift = <23>;
 753                 reg = <0x018c>;
 754         };
 755
 756         dpll_usb_ck: dpll_usb_ck@180 {
 757                 #clock-cells = <0>;
 758                 compatible = "ti,omap4-dpll-j-type-clock";
 759                 clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
 760                 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
 761         };
 762
 763         dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
 764                 #clock-cells = <0>;
 765                 compatible = "fixed-factor-clock";
 766                 clocks = <&dpll_usb_ck>;
 767                 clock-mult = <1>;
 768                 clock-div = <1>;
 769         };
 770
 771         dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
 772                 #clock-cells = <0>;
 773                 compatible = "ti,divider-clock";
 774                 clocks = <&dpll_usb_ck>;
 775                 ti,max-div = <127>;
 776                 reg = <0x0190>;
 777                 ti,index-starts-at-one;
 778         };
 779
 780         func_128m_clk: func_128m_clk {
 781                 #clock-cells = <0>;
 782                 compatible = "fixed-factor-clock";
 783                 clocks = <&dpll_per_h11x2_ck>;
 784                 clock-mult = <1>;
 785                 clock-div = <2>;
 786         };
 787
 788         func_12m_fclk: func_12m_fclk {
 789                 #clock-cells = <0>;
 790                 compatible = "fixed-factor-clock";
 791                 clocks = <&dpll_per_m2x2_ck>;
 792                 clock-mult = <1>;
 793                 clock-div = <16>;
 794         };
 795
 796         func_24m_clk: func_24m_clk {
 797                 #clock-cells = <0>;
 798                 compatible = "fixed-factor-clock";
 799                 clocks = <&dpll_per_m2_ck>;
 800                 clock-mult = <1>;
 801                 clock-div = <4>;
 802         };
 803
 804         func_48m_fclk: func_48m_fclk {
 805                 #clock-cells = <0>;
 806                 compatible = "fixed-factor-clock";
 807                 clocks = <&dpll_per_m2x2_ck>;
 808                 clock-mult = <1>;
 809                 clock-div = <4>;
 810         };
 811
 812         func_96m_fclk: func_96m_fclk {
 813                 #clock-cells = <0>;
 814                 compatible = "fixed-factor-clock";
 815                 clocks = <&dpll_per_m2x2_ck>;
 816                 clock-mult = <1>;
 817                 clock-div = <2>;
 818         };
 819
 820         l3init_60m_fclk: l3init_60m_fclk@104 {
 821                 #clock-cells = <0>;
 822                 compatible = "ti,divider-clock";
 823                 clocks = <&dpll_usb_m2_ck>;
 824                 reg = <0x0104>;
 825                 ti,dividers = <1>, <8>;
 826         };
 827
 828         dss_32khz_clk: dss_32khz_clk@1420 {
 829                 #clock-cells = <0>;
 830                 compatible = "ti,gate-clock";
 831                 clocks = <&sys_32k_ck>;
 832                 ti,bit-shift = <11>;
 833                 reg = <0x1420>;
 834         };
 835
 836         dss_48mhz_clk: dss_48mhz_clk@1420 {
 837                 #clock-cells = <0>;
 838                 compatible = "ti,gate-clock";
 839                 clocks = <&func_48m_fclk>;
 840                 ti,bit-shift = <9>;
 841                 reg = <0x1420>;
 842         };
 843
 844         dss_dss_clk: dss_dss_clk@1420 {
 845                 #clock-cells = <0>;
 846                 compatible = "ti,gate-clock";
 847                 clocks = <&dpll_per_h12x2_ck>;
 848                 ti,bit-shift = <8>;
 849                 reg = <0x1420>;
 850                 ti,set-rate-parent;
 851         };
 852
 853         dss_sys_clk: dss_sys_clk@1420 {
 854                 #clock-cells = <0>;
 855                 compatible = "ti,gate-clock";
 856                 clocks = <&dss_syc_gfclk_div>;
 857                 ti,bit-shift = <10>;
 858                 reg = <0x1420>;
 859         };
 860
 861         gpio2_dbclk: gpio2_dbclk@1060 {
 862                 #clock-cells = <0>;
 863                 compatible = "ti,gate-clock";
 864                 clocks = <&sys_32k_ck>;
 865                 ti,bit-shift = <8>;
 866                 reg = <0x1060>;
 867         };
 868
 869         gpio3_dbclk: gpio3_dbclk@1068 {
 870                 #clock-cells = <0>;
 871                 compatible = "ti,gate-clock";
 872                 clocks = <&sys_32k_ck>;
 873                 ti,bit-shift = <8>;
 874                 reg = <0x1068>;
 875         };
 876
 877         gpio4_dbclk: gpio4_dbclk@1070 {
 878                 #clock-cells = <0>;
 879                 compatible = "ti,gate-clock";
 880                 clocks = <&sys_32k_ck>;
 881                 ti,bit-shift = <8>;
 882                 reg = <0x1070>;
 883         };
 884
 885         gpio5_dbclk: gpio5_dbclk@1078 {
 886                 #clock-cells = <0>;
 887                 compatible = "ti,gate-clock";
 888                 clocks = <&sys_32k_ck>;
 889                 ti,bit-shift = <8>;
 890                 reg = <0x1078>;
 891         };
 892
 893         gpio6_dbclk: gpio6_dbclk@1080 {
 894                 #clock-cells = <0>;
 895                 compatible = "ti,gate-clock";
 896                 clocks = <&sys_32k_ck>;
 897                 ti,bit-shift = <8>;
 898                 reg = <0x1080>;
 899         };
 900
 901         gpio7_dbclk: gpio7_dbclk@1110 {
 902                 #clock-cells = <0>;
 903                 compatible = "ti,gate-clock";
 904                 clocks = <&sys_32k_ck>;
 905                 ti,bit-shift = <8>;
 906                 reg = <0x1110>;
 907         };
 908
 909         gpio8_dbclk: gpio8_dbclk@1118 {
 910                 #clock-cells = <0>;
 911                 compatible = "ti,gate-clock";
 912                 clocks = <&sys_32k_ck>;
 913                 ti,bit-shift = <8>;
 914                 reg = <0x1118>;
 915         };
 916
 917         iss_ctrlclk: iss_ctrlclk@1320 {
 918                 #clock-cells = <0>;
 919                 compatible = "ti,gate-clock";
 920                 clocks = <&func_96m_fclk>;
 921                 ti,bit-shift = <8>;
 922                 reg = <0x1320>;
 923         };
 924
 925         lli_txphy_clk: lli_txphy_clk@f20 {
 926                 #clock-cells = <0>;
 927                 compatible = "ti,gate-clock";
 928                 clocks = <&dpll_unipro1_clkdcoldo>;
 929                 ti,bit-shift = <8>;
 930                 reg = <0x0f20>;
 931         };
 932
 933         lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
 934                 #clock-cells = <0>;
 935                 compatible = "ti,gate-clock";
 936                 clocks = <&dpll_unipro1_m2_ck>;
 937                 ti,bit-shift = <9>;
 938                 reg = <0x0f20>;
 939         };
 940
 941         mmc1_32khz_clk: mmc1_32khz_clk@1628 {
 942                 #clock-cells = <0>;
 943                 compatible = "ti,gate-clock";
 944                 clocks = <&sys_32k_ck>;
 945                 ti,bit-shift = <8>;
 946                 reg = <0x1628>;
 947         };
 948
 949         sata_ref_clk: sata_ref_clk@1688 {
 950                 #clock-cells = <0>;
 951                 compatible = "ti,gate-clock";
 952                 clocks = <&sys_clkin>;
 953                 ti,bit-shift = <8>;
 954                 reg = <0x1688>;
 955         };
 956
 957         usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1658 {
 958                 #clock-cells = <0>;
 959                 compatible = "ti,gate-clock";
 960                 clocks = <&dpll_usb_m2_ck>;
 961                 ti,bit-shift = <13>;
 962                 reg = <0x1658>;
 963         };
 964
 965         usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1658 {
 966                 #clock-cells = <0>;
 967                 compatible = "ti,gate-clock";
 968                 clocks = <&dpll_usb_m2_ck>;
 969                 ti,bit-shift = <14>;
 970                 reg = <0x1658>;
 971         };
 972
 973         usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@1658 {
 974                 #clock-cells = <0>;
 975                 compatible = "ti,gate-clock";
 976                 clocks = <&dpll_usb_m2_ck>;
 977                 ti,bit-shift = <7>;
 978                 reg = <0x1658>;
 979         };
 980
 981         usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1658 {
 982                 #clock-cells = <0>;
 983                 compatible = "ti,gate-clock";
 984                 clocks = <&l3init_60m_fclk>;
 985                 ti,bit-shift = <11>;
 986                 reg = <0x1658>;
 987         };
 988
 989         usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1658 {
 990                 #clock-cells = <0>;
 991                 compatible = "ti,gate-clock";
 992                 clocks = <&l3init_60m_fclk>;
 993                 ti,bit-shift = <12>;
 994                 reg = <0x1658>;
 995         };
 996
 997         usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@1658 {
 998                 #clock-cells = <0>;
 999                 compatible = "ti,gate-clock";
1000                 clocks = <&l3init_60m_fclk>;
1001                 ti,bit-shift = <6>;
1002                 reg = <0x1658>;
1003         };
1004
1005         utmi_p1_gfclk: utmi_p1_gfclk@1658 {
1006                 #clock-cells = <0>;
1007                 compatible = "ti,mux-clock";
1008                 clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
1009                 ti,bit-shift = <24>;
1010                 reg = <0x1658>;
1011         };
1012
1013         usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1658 {
1014                 #clock-cells = <0>;
1015                 compatible = "ti,gate-clock";
1016                 clocks = <&utmi_p1_gfclk>;
1017                 ti,bit-shift = <8>;
1018                 reg = <0x1658>;
1019         };
1020
1021         utmi_p2_gfclk: utmi_p2_gfclk@1658 {
1022                 #clock-cells = <0>;
1023                 compatible = "ti,mux-clock";
1024                 clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
1025                 ti,bit-shift = <25>;
1026                 reg = <0x1658>;
1027         };
1028
1029         usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1658 {
1030                 #clock-cells = <0>;
1031                 compatible = "ti,gate-clock";
1032                 clocks = <&utmi_p2_gfclk>;
1033                 ti,bit-shift = <9>;
1034                 reg = <0x1658>;
1035         };
1036
1037         usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1658 {
1038                 #clock-cells = <0>;
1039                 compatible = "ti,gate-clock";
1040                 clocks = <&l3init_60m_fclk>;
1041                 ti,bit-shift = <10>;
1042                 reg = <0x1658>;
1043         };
1044
1045         usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@16f0 {
1046                 #clock-cells = <0>;
1047                 compatible = "ti,gate-clock";
1048                 clocks = <&dpll_usb_clkdcoldo>;
1049                 ti,bit-shift = <8>;
1050                 reg = <0x16f0>;
1051         };
1052
1053         usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
1054                 #clock-cells = <0>;
1055                 compatible = "ti,gate-clock";
1056                 clocks = <&sys_32k_ck>;
1057                 ti,bit-shift = <8>;
1058                 reg = <0x0640>;
1059         };
1060
1061         usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1668 {
1062                 #clock-cells = <0>;
1063                 compatible = "ti,gate-clock";
1064                 clocks = <&l3init_60m_fclk>;
1065                 ti,bit-shift = <8>;
1066                 reg = <0x1668>;
1067         };
1068
1069         usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1668 {
1070                 #clock-cells = <0>;
1071                 compatible = "ti,gate-clock";
1072                 clocks = <&l3init_60m_fclk>;
1073                 ti,bit-shift = <9>;
1074                 reg = <0x1668>;
1075         };
1076
1077         usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1668 {
1078                 #clock-cells = <0>;
1079                 compatible = "ti,gate-clock";
1080                 clocks = <&l3init_60m_fclk>;
1081                 ti,bit-shift = <10>;
1082                 reg = <0x1668>;
1083         };
1084
1085         fdif_fclk: fdif_fclk@1328 {
1086                 #clock-cells = <0>;
1087                 compatible = "ti,divider-clock";
1088                 clocks = <&dpll_per_h11x2_ck>;
1089                 ti,bit-shift = <24>;
1090                 ti,max-div = <2>;
1091                 reg = <0x1328>;
1092         };
1093
1094         gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
1095                 #clock-cells = <0>;
1096                 compatible = "ti,mux-clock";
1097                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
1098                 ti,bit-shift = <24>;
1099                 reg = <0x1520>;
1100         };
1101
1102         gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
1103                 #clock-cells = <0>;
1104                 compatible = "ti,mux-clock";
1105                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
1106                 ti,bit-shift = <25>;
1107                 reg = <0x1520>;
1108         };
1109
1110         hsi_fclk: hsi_fclk@1638 {
1111                 #clock-cells = <0>;
1112                 compatible = "ti,divider-clock";
1113                 clocks = <&dpll_per_m2x2_ck>;
1114                 ti,bit-shift = <24>;
1115                 ti,max-div = <2>;
1116                 reg = <0x1638>;
1117         };
1118
1119         mmc1_fclk_mux: mmc1_fclk_mux@1628 {
1120                 #clock-cells = <0>;
1121                 compatible = "ti,mux-clock";
1122                 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1123                 ti,bit-shift = <24>;
1124                 reg = <0x1628>;
1125         };
1126
1127         mmc1_fclk: mmc1_fclk@1628 {
1128                 #clock-cells = <0>;
1129                 compatible = "ti,divider-clock";
1130                 clocks = <&mmc1_fclk_mux>;
1131                 ti,bit-shift = <25>;
1132                 ti,max-div = <2>;
1133                 reg = <0x1628>;
1134         };
1135
1136         mmc2_fclk_mux: mmc2_fclk_mux@1630 {
1137                 #clock-cells = <0>;
1138                 compatible = "ti,mux-clock";
1139                 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1140                 ti,bit-shift = <24>;
1141                 reg = <0x1630>;
1142         };
1143
1144         mmc2_fclk: mmc2_fclk@1630 {
1145                 #clock-cells = <0>;
1146                 compatible = "ti,divider-clock";
1147                 clocks = <&mmc2_fclk_mux>;
1148                 ti,bit-shift = <25>;
1149                 ti,max-div = <2>;
1150                 reg = <0x1630>;
1151         };
1152
1153         timer10_gfclk_mux: timer10_gfclk_mux@1028 {
1154                 #clock-cells = <0>;
1155                 compatible = "ti,mux-clock";
1156                 clocks = <&sys_clkin>, <&sys_32k_ck>;
1157                 ti,bit-shift = <24>;
1158                 reg = <0x1028>;
1159         };
1160
1161         timer11_gfclk_mux: timer11_gfclk_mux@1030 {
1162                 #clock-cells = <0>;
1163                 compatible = "ti,mux-clock";
1164                 clocks = <&sys_clkin>, <&sys_32k_ck>;
1165                 ti,bit-shift = <24>;
1166                 reg = <0x1030>;
1167         };
1168
1169         timer2_gfclk_mux: timer2_gfclk_mux@1038 {
1170                 #clock-cells = <0>;
1171                 compatible = "ti,mux-clock";
1172                 clocks = <&sys_clkin>, <&sys_32k_ck>;
1173                 ti,bit-shift = <24>;
1174                 reg = <0x1038>;
1175         };
1176
1177         timer3_gfclk_mux: timer3_gfclk_mux@1040 {
1178                 #clock-cells = <0>;
1179                 compatible = "ti,mux-clock";
1180                 clocks = <&sys_clkin>, <&sys_32k_ck>;
1181                 ti,bit-shift = <24>;
1182                 reg = <0x1040>;
1183         };
1184
1185         timer4_gfclk_mux: timer4_gfclk_mux@1048 {
1186                 #clock-cells = <0>;
1187                 compatible = "ti,mux-clock";
1188                 clocks = <&sys_clkin>, <&sys_32k_ck>;
1189                 ti,bit-shift = <24>;
1190                 reg = <0x1048>;
1191         };
1192
1193         timer9_gfclk_mux: timer9_gfclk_mux@1050 {
1194                 #clock-cells = <0>;
1195                 compatible = "ti,mux-clock";
1196                 clocks = <&sys_clkin>, <&sys_32k_ck>;
1197                 ti,bit-shift = <24>;
1198                 reg = <0x1050>;
1199         };
1200 };
1201
1202 &cm_core_clockdomains {
1203         l3init_clkdm: l3init_clkdm {
1204                 compatible = "ti,clockdomain";
1205                 clocks = <&dpll_usb_ck>;
1206         };
1207 };
1208
1209 &scrm_clocks {
1210         auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
1211                 #clock-cells = <0>;
1212                 compatible = "ti,composite-no-wait-gate-clock";
1213                 clocks = <&dpll_core_m3x2_ck>;
1214                 ti,bit-shift = <8>;
1215                 reg = <0x0310>;
1216         };
1217
1218         auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
1219                 #clock-cells = <0>;
1220                 compatible = "ti,composite-mux-clock";
1221                 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1222                 ti,bit-shift = <1>;
1223                 reg = <0x0310>;
1224         };
1225
1226         auxclk0_src_ck: auxclk0_src_ck {
1227                 #clock-cells = <0>;
1228                 compatible = "ti,composite-clock";
1229                 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
1230         };
1231
1232         auxclk0_ck: auxclk0_ck@310 {
1233                 #clock-cells = <0>;
1234                 compatible = "ti,divider-clock";
1235                 clocks = <&auxclk0_src_ck>;
1236                 ti,bit-shift = <16>;
1237                 ti,max-div = <16>;
1238                 reg = <0x0310>;
1239         };
1240
1241         auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
1242                 #clock-cells = <0>;
1243                 compatible = "ti,composite-no-wait-gate-clock";
1244                 clocks = <&dpll_core_m3x2_ck>;
1245                 ti,bit-shift = <8>;
1246                 reg = <0x0314>;
1247         };
1248
1249         auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
1250                 #clock-cells = <0>;
1251                 compatible = "ti,composite-mux-clock";
1252                 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1253                 ti,bit-shift = <1>;
1254                 reg = <0x0314>;
1255         };
1256
1257         auxclk1_src_ck: auxclk1_src_ck {
1258                 #clock-cells = <0>;
1259                 compatible = "ti,composite-clock";
1260                 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
1261         };
1262
1263         auxclk1_ck: auxclk1_ck@314 {
1264                 #clock-cells = <0>;
1265                 compatible = "ti,divider-clock";
1266                 clocks = <&auxclk1_src_ck>;
1267                 ti,bit-shift = <16>;
1268                 ti,max-div = <16>;
1269                 reg = <0x0314>;
1270         };
1271
1272         auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
1273                 #clock-cells = <0>;
1274                 compatible = "ti,composite-no-wait-gate-clock";
1275                 clocks = <&dpll_core_m3x2_ck>;
1276                 ti,bit-shift = <8>;
1277                 reg = <0x0318>;
1278         };
1279
1280         auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
1281                 #clock-cells = <0>;
1282                 compatible = "ti,composite-mux-clock";
1283                 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1284                 ti,bit-shift = <1>;
1285                 reg = <0x0318>;
1286         };
1287
1288         auxclk2_src_ck: auxclk2_src_ck {
1289                 #clock-cells = <0>;
1290                 compatible = "ti,composite-clock";
1291                 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
1292         };
1293
1294         auxclk2_ck: auxclk2_ck@318 {
1295                 #clock-cells = <0>;
1296                 compatible = "ti,divider-clock";
1297                 clocks = <&auxclk2_src_ck>;
1298                 ti,bit-shift = <16>;
1299                 ti,max-div = <16>;
1300                 reg = <0x0318>;
1301         };
1302
1303         auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
1304                 #clock-cells = <0>;
1305                 compatible = "ti,composite-no-wait-gate-clock";
1306                 clocks = <&dpll_core_m3x2_ck>;
1307                 ti,bit-shift = <8>;
1308                 reg = <0x031c>;
1309         };
1310
1311         auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
1312                 #clock-cells = <0>;
1313                 compatible = "ti,composite-mux-clock";
1314                 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1315                 ti,bit-shift = <1>;
1316                 reg = <0x031c>;
1317         };
1318
1319         auxclk3_src_ck: auxclk3_src_ck {
1320                 #clock-cells = <0>;
1321                 compatible = "ti,composite-clock";
1322                 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
1323         };
1324
1325         auxclk3_ck: auxclk3_ck@31c {
1326                 #clock-cells = <0>;
1327                 compatible = "ti,divider-clock";
1328                 clocks = <&auxclk3_src_ck>;
1329                 ti,bit-shift = <16>;
1330                 ti,max-div = <16>;
1331                 reg = <0x031c>;
1332         };
1333
1334         auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
1335                 #clock-cells = <0>;
1336                 compatible = "ti,composite-no-wait-gate-clock";
1337                 clocks = <&dpll_core_m3x2_ck>;
1338                 ti,bit-shift = <8>;
1339                 reg = <0x0320>;
1340         };
1341
1342         auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
1343                 #clock-cells = <0>;
1344                 compatible = "ti,composite-mux-clock";
1345                 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1346                 ti,bit-shift = <1>;
1347                 reg = <0x0320>;
1348         };
1349
1350         auxclk4_src_ck: auxclk4_src_ck {
1351                 #clock-cells = <0>;
1352                 compatible = "ti,composite-clock";
1353                 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
1354         };
1355
1356         auxclk4_ck: auxclk4_ck@320 {
1357                 #clock-cells = <0>;
1358                 compatible = "ti,divider-clock";
1359                 clocks = <&auxclk4_src_ck>;
1360                 ti,bit-shift = <16>;
1361                 ti,max-div = <16>;
1362                 reg = <0x0320>;
1363         };
1364
1365         auxclkreq0_ck: auxclkreq0_ck@210 {
1366                 #clock-cells = <0>;
1367                 compatible = "ti,mux-clock";
1368                 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1369                 ti,bit-shift = <2>;
1370                 reg = <0x0210>;
1371         };
1372
1373         auxclkreq1_ck: auxclkreq1_ck@214 {
1374                 #clock-cells = <0>;
1375                 compatible = "ti,mux-clock";
1376                 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1377                 ti,bit-shift = <2>;
1378                 reg = <0x0214>;
1379         };
1380
1381         auxclkreq2_ck: auxclkreq2_ck@218 {
1382                 #clock-cells = <0>;
1383                 compatible = "ti,mux-clock";
1384                 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1385                 ti,bit-shift = <2>;
1386                 reg = <0x0218>;
1387         };
1388
1389         auxclkreq3_ck: auxclkreq3_ck@21c {
1390                 #clock-cells = <0>;
1391                 compatible = "ti,mux-clock";
1392                 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1393                 ti,bit-shift = <2>;
1394                 reg = <0x021c>;
1395         };
1396 };