| blob | 4916c65e0ace7ca0b9ec68cddaca34b55c39d932 |
1 /*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3036-cru.h>
46 #include <dt-bindings/soc/rockchip,boot-mode.h>
48 / {
49 #address-cells = <1>;
50 #size-cells = <1>;
52 compatible = "rockchip,rk3036";
54 interrupt-parent = <&gic>;
56 aliases {
57 i2c0 = &i2c0;
58 i2c1 = &i2c1;
59 i2c2 = &i2c2;
60 mshc0 = &emmc;
61 mshc1 = &sdmmc;
62 mshc2 = &sdio;
63 serial0 = &uart0;
64 serial1 = &uart1;
65 serial2 = &uart2;
66 spi = &spi;
67 };
69 cpus {
70 #address-cells = <1>;
71 #size-cells = <0>;
72 enable-method = "rockchip,rk3036-smp";
74 cpu0: cpu@f00 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a7";
77 reg = <0xf00>;
78 resets = <&cru SRST_CORE0>;
79 operating-points = <
80 /* KHz uV */
81 816000 1000000
82 >;
83 clock-latency = <40000>;
84 clocks = <&cru ARMCLK>;
85 };
87 cpu1: cpu@f01 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a7";
90 reg = <0xf01>;
91 resets = <&cru SRST_CORE1>;
92 };
93 };
95 amba {
96 compatible = "simple-bus";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges;
101 pdma: pdma@20078000 {
102 compatible = "arm,pl330", "arm,primecell";
103 reg = <0x20078000 0x4000>;
104 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
106 #dma-cells = <1>;
107 arm,pl330-broken-no-flushp;
108 clocks = <&cru ACLK_DMAC2>;
109 clock-names = "apb_pclk";
110 };
111 };
113 arm-pmu {
114 compatible = "arm,cortex-a7-pmu";
115 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
117 interrupt-affinity = <&cpu0>, <&cpu1>;
118 };
120 display-subsystem {
121 compatible = "rockchip,display-subsystem";
122 ports = <&vop_out>;
123 };
125 timer {
126 compatible = "arm,armv7-timer";
127 arm,cpu-registers-not-fw-configured;
128 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
129 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
130 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
131 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
132 clock-frequency = <24000000>;
133 };
135 xin24m: oscillator {
136 compatible = "fixed-clock";
137 clock-frequency = <24000000>;
138 clock-output-names = "xin24m";
139 #clock-cells = <0>;
140 };
142 bus_intmem@10080000 {
143 compatible = "mmio-sram";
144 reg = <0x10080000 0x2000>;
145 #address-cells = <1>;
146 #size-cells = <1>;
147 ranges = <0 0x10080000 0x2000>;
149 smp-sram@0 {
150 compatible = "rockchip,rk3066-smp-sram";
151 reg = <0x00 0x10>;
152 };
153 };
155 vop: vop@10118000 {
156 compatible = "rockchip,rk3036-vop";
157 reg = <0x10118000 0x19c>;
158 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
160 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
161 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
162 reset-names = "axi", "ahb", "dclk";
163 iommus = <&vop_mmu>;
164 status = "disabled";
166 vop_out: port {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 vop_out_hdmi: endpoint@0 {
170 reg = <0>;
171 remote-endpoint = <&hdmi_in_vop>;
172 };
173 };
174 };
176 vop_mmu: iommu@10118300 {
177 compatible = "rockchip,iommu";
178 reg = <0x10118300 0x100>;
179 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-names = "vop_mmu";
181 #iommu-cells = <0>;
182 status = "disabled";
183 };
185 gic: interrupt-controller@10139000 {
186 compatible = "arm,gic-400";
187 interrupt-controller;
188 #interrupt-cells = <3>;
189 #address-cells = <0>;
191 reg = <0x10139000 0x1000>,
192 <0x1013a000 0x2000>,
193 <0x1013c000 0x2000>,
194 <0x1013e000 0x2000>;
195 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
196 };
198 usb_otg: usb@10180000 {
199 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
200 "snps,dwc2";
201 reg = <0x10180000 0x40000>;
202 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&cru HCLK_OTG0>;
204 clock-names = "otg";
205 dr_mode = "otg";
206 g-np-tx-fifo-size = <16>;
207 g-rx-fifo-size = <275>;
208 g-tx-fifo-size = <256 128 128 64 64 32>;
209 status = "disabled";
210 };
212 usb_host: usb@101c0000 {
213 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
214 "snps,dwc2";
215 reg = <0x101c0000 0x40000>;
216 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cru HCLK_OTG1>;
218 clock-names = "otg";
219 dr_mode = "host";
220 status = "disabled";
221 };
223 emac: ethernet@10200000 {
224 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
225 reg = <0x10200000 0x4000>;
226 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
227 #address-cells = <1>;
228 #size-cells = <0>;
229 rockchip,grf = <&grf>;
230 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
231 clock-names = "hclk", "macref", "macclk";
232 /*
233 * Fix the emac parent clock is DPLL instead of APLL.
234 * since that will cause some unstable things if the cpufreq
235 * is working. (e.g: the accurate 50MHz what mac_ref need)
236 */
237 assigned-clocks = <&cru SCLK_MACPLL>;
238 assigned-clock-parents = <&cru PLL_DPLL>;
239 max-speed = <100>;
240 phy-mode = "rmii";
241 status = "disabled";
242 };
244 sdmmc: dwmmc@10214000 {
245 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
246 reg = <0x10214000 0x4000>;
247 clock-frequency = <37500000>;
248 max-frequency = <37500000>;
249 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
250 clock-names = "biu", "ciu";
251 fifo-depth = <0x100>;
252 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
253 resets = <&cru SRST_MMC0>;
254 reset-names = "reset";
255 status = "disabled";
256 };
258 sdio: dwmmc@10218000 {
259 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
260 reg = <0x10218000 0x4000>;
261 max-frequency = <37500000>;
262 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
263 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
264 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
265 fifo-depth = <0x100>;
266 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
267 resets = <&cru SRST_SDIO>;
268 reset-names = "reset";
269 status = "disabled";
270 };
272 emmc: dwmmc@1021c000 {
273 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
274 reg = <0x1021c000 0x4000>;
275 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
276 bus-width = <8>;
277 cap-mmc-highspeed;
278 clock-frequency = <37500000>;
279 max-frequency = <37500000>;
280 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
281 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
282 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
283 default-sample-phase = <158>;
284 disable-wp;
285 dmas = <&pdma 12>;
286 dma-names = "rx-tx";
287 fifo-depth = <0x100>;
288 mmc-ddr-1_8v;
289 non-removable;
290 pinctrl-names = "default";
291 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
292 resets = <&cru SRST_EMMC>;
293 reset-names = "reset";
294 status = "disabled";
295 };
297 i2s: i2s@10220000 {
298 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
299 reg = <0x10220000 0x4000>;
300 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 clock-names = "i2s_clk", "i2s_hclk";
304 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
305 dmas = <&pdma 0>, <&pdma 1>;
306 dma-names = "tx", "rx";
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2s_bus>;
309 status = "disabled";
310 };
312 cru: clock-controller@20000000 {
313 compatible = "rockchip,rk3036-cru";
314 reg = <0x20000000 0x1000>;
315 rockchip,grf = <&grf>;
316 #clock-cells = <1>;
317 #reset-cells = <1>;
318 assigned-clocks = <&cru PLL_GPLL>;
319 assigned-clock-rates = <594000000>;
320 };
322 grf: syscon@20008000 {
323 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
324 reg = <0x20008000 0x1000>;
326 reboot-mode {
327 compatible = "syscon-reboot-mode";
328 offset = <0x1d8>;
329 mode-normal = <BOOT_NORMAL>;
330 mode-recovery = <BOOT_RECOVERY>;
331 mode-bootloader = <BOOT_FASTBOOT>;
332 mode-loader = <BOOT_BL_DOWNLOAD>;
333 };
334 };
336 acodec: acodec-ana@20030000 {
337 compatible = "rk3036-codec";
338 reg = <0x20030000 0x4000>;
339 rockchip,grf = <&grf>;
340 clock-names = "acodec_pclk";
341 clocks = <&cru PCLK_ACODEC>;
342 status = "disabled";
343 };
345 hdmi: hdmi@20034000 {
346 compatible = "rockchip,rk3036-inno-hdmi";
347 reg = <0x20034000 0x4000>;
348 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&cru PCLK_HDMI>;
350 clock-names = "pclk";
351 rockchip,grf = <&grf>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&hdmi_ctl>;
354 status = "disabled";
356 hdmi_in: port {
357 #address-cells = <1>;
358 #size-cells = <0>;
359 hdmi_in_vop: endpoint@0 {
360 reg = <0>;
361 remote-endpoint = <&vop_out_hdmi>;
362 };
363 };
364 };
366 timer: timer@20044000 {
367 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
368 reg = <0x20044000 0x20>;
369 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&xin24m>, <&cru PCLK_TIMER>;
371 clock-names = "timer", "pclk";
372 };
374 pwm0: pwm@20050000 {
375 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
376 reg = <0x20050000 0x10>;
377 #pwm-cells = <3>;
378 clocks = <&cru PCLK_PWM>;
379 clock-names = "pwm";
380 pinctrl-names = "default";
381 pinctrl-0 = <&pwm0_pin>;
382 status = "disabled";
383 };
385 pwm1: pwm@20050010 {
386 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
387 reg = <0x20050010 0x10>;
388 #pwm-cells = <3>;
389 clocks = <&cru PCLK_PWM>;
390 clock-names = "pwm";
391 pinctrl-names = "default";
392 pinctrl-0 = <&pwm1_pin>;
393 status = "disabled";
394 };
396 pwm2: pwm@20050020 {
397 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
398 reg = <0x20050020 0x10>;
399 #pwm-cells = <3>;
400 clocks = <&cru PCLK_PWM>;
401 clock-names = "pwm";
402 pinctrl-names = "default";
403 pinctrl-0 = <&pwm2_pin>;
404 status = "disabled";
405 };
407 pwm3: pwm@20050030 {
408 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
409 reg = <0x20050030 0x10>;
410 #pwm-cells = <2>;
411 clocks = <&cru PCLK_PWM>;
412 clock-names = "pwm";
413 pinctrl-names = "default";
414 pinctrl-0 = <&pwm3_pin>;
415 status = "disabled";
416 };
418 i2c1: i2c@20056000 {
419 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
420 reg = <0x20056000 0x1000>;
421 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
422 #address-cells = <1>;
423 #size-cells = <0>;
424 clock-names = "i2c";
425 clocks = <&cru PCLK_I2C1>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&i2c1_xfer>;
428 status = "disabled";
429 };
431 i2c2: i2c@2005a000 {
432 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
433 reg = <0x2005a000 0x1000>;
434 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
435 #address-cells = <1>;
436 #size-cells = <0>;
437 clock-names = "i2c";
438 clocks = <&cru PCLK_I2C2>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&i2c2_xfer>;
441 status = "disabled";
442 };
444 uart0: serial@20060000 {
445 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
446 reg = <0x20060000 0x100>;
447 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
448 reg-shift = <2>;
449 reg-io-width = <4>;
450 clock-frequency = <24000000>;
451 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
452 clock-names = "baudclk", "apb_pclk";
453 pinctrl-names = "default";
454 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
455 status = "disabled";
456 };
458 uart1: serial@20064000 {
459 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
460 reg = <0x20064000 0x100>;
461 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
462 reg-shift = <2>;
463 reg-io-width = <4>;
464 clock-frequency = <24000000>;
465 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
466 clock-names = "baudclk", "apb_pclk";
467 pinctrl-names = "default";
468 pinctrl-0 = <&uart1_xfer>;
469 status = "disabled";
470 };
472 uart2: serial@20068000 {
473 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
474 reg = <0x20068000 0x100>;
475 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
476 reg-shift = <2>;
477 reg-io-width = <4>;
478 clock-frequency = <24000000>;
479 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
480 clock-names = "baudclk", "apb_pclk";
481 pinctrl-names = "default";
482 pinctrl-0 = <&uart2_xfer>;
483 status = "disabled";
484 };
486 i2c0: i2c@20072000 {
487 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
488 reg = <0x20072000 0x1000>;
489 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 clock-names = "i2c";
493 clocks = <&cru PCLK_I2C0>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2c0_xfer>;
496 status = "disabled";
497 };
499 spi: spi@20074000 {
500 compatible = "rockchip,rockchip-spi";
501 reg = <0x20074000 0x1000>;
502 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
503 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
504 clock-names = "apb-pclk","spi_pclk";
505 dmas = <&pdma 8>, <&pdma 9>;
506 dma-names = "tx", "rx";
507 pinctrl-names = "default";
508 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 status = "disabled";
512 };
514 pinctrl: pinctrl {
515 compatible = "rockchip,rk3036-pinctrl";
516 rockchip,grf = <&grf>;
517 #address-cells = <1>;
518 #size-cells = <1>;
519 ranges;
521 gpio0: gpio0@2007c000 {
522 compatible = "rockchip,gpio-bank";
523 reg = <0x2007c000 0x100>;
524 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cru PCLK_GPIO0>;
527 gpio-controller;
528 #gpio-cells = <2>;
530 interrupt-controller;
531 #interrupt-cells = <2>;
532 };
534 gpio1: gpio1@20080000 {
535 compatible = "rockchip,gpio-bank";
536 reg = <0x20080000 0x100>;
537 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&cru PCLK_GPIO1>;
540 gpio-controller;
541 #gpio-cells = <2>;
543 interrupt-controller;
544 #interrupt-cells = <2>;
545 };
547 gpio2: gpio2@20084000 {
548 compatible = "rockchip,gpio-bank";
549 reg = <0x20084000 0x100>;
550 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&cru PCLK_GPIO2>;
553 gpio-controller;
554 #gpio-cells = <2>;
556 interrupt-controller;
557 #interrupt-cells = <2>;
558 };
560 pcfg_pull_default: pcfg_pull_default {
561 bias-pull-pin-default;
562 };
564 pcfg_pull_none: pcfg-pull-none {
565 bias-disable;
566 };
568 pwm0 {
569 pwm0_pin: pwm0-pin {
570 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
571 };
572 };
574 pwm1 {
575 pwm1_pin: pwm1-pin {
576 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
577 };
578 };
580 pwm2 {
581 pwm2_pin: pwm2-pin {
582 rockchip,pins = <0 1 2 &pcfg_pull_none>;
583 };
584 };
586 pwm3 {
587 pwm3_pin: pwm3-pin {
588 rockchip,pins = <0 27 1 &pcfg_pull_none>;
589 };
590 };
592 sdmmc {
593 sdmmc_clk: sdmmc-clk {
594 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
595 };
597 sdmmc_cmd: sdmmc-cmd {
598 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
599 };
601 sdmmc_cd: sdmmc-cd {
602 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
603 };
605 sdmmc_bus1: sdmmc-bus1 {
606 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
607 };
609 sdmmc_bus4: sdmmc-bus4 {
610 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
611 <1 19 RK_FUNC_1 &pcfg_pull_default>,
612 <1 20 RK_FUNC_1 &pcfg_pull_default>,
613 <1 21 RK_FUNC_1 &pcfg_pull_default>;
614 };
615 };
617 sdio {
618 sdio_bus1: sdio-bus1 {
619 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
620 };
622 sdio_bus4: sdio-bus4 {
623 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
624 <0 12 RK_FUNC_1 &pcfg_pull_default>,
625 <0 13 RK_FUNC_1 &pcfg_pull_default>,
626 <0 14 RK_FUNC_1 &pcfg_pull_default>;
627 };
629 sdio_cmd: sdio-cmd {
630 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
631 };
633 sdio_clk: sdio-clk {
634 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
635 };
636 };
638 emmc {
639 /*
640 * We run eMMC at max speed; bump up drive strength.
641 * We also have external pulls, so disable the internal ones.
642 */
643 emmc_clk: emmc-clk {
644 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
645 };
647 emmc_cmd: emmc-cmd {
648 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
649 };
651 emmc_bus8: emmc-bus8 {
652 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
653 <1 25 RK_FUNC_2 &pcfg_pull_default>,
654 <1 26 RK_FUNC_2 &pcfg_pull_default>,
655 <1 27 RK_FUNC_2 &pcfg_pull_default>,
656 <1 28 RK_FUNC_2 &pcfg_pull_default>,
657 <1 29 RK_FUNC_2 &pcfg_pull_default>,
658 <1 30 RK_FUNC_2 &pcfg_pull_default>,
659 <1 31 RK_FUNC_2 &pcfg_pull_default>;
660 };
661 };
663 emac {
664 emac_xfer: emac-xfer {
665 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
666 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
667 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
668 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
669 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
670 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
671 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
672 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
673 };
675 emac_mdio: emac-mdio {
676 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
677 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
678 };
679 };
681 i2c0 {
682 i2c0_xfer: i2c0-xfer {
683 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
684 <0 1 RK_FUNC_1 &pcfg_pull_none>;
685 };
686 };
688 i2c1 {
689 i2c1_xfer: i2c1-xfer {
690 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
691 <0 3 RK_FUNC_1 &pcfg_pull_none>;
692 };
693 };
695 i2c2 {
696 i2c2_xfer: i2c2-xfer {
697 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
698 <2 21 RK_FUNC_1 &pcfg_pull_none>;
699 };
700 };
702 i2s {
703 i2s_bus: i2s-bus {
704 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
705 <1 1 RK_FUNC_1 &pcfg_pull_default>,
706 <1 2 RK_FUNC_1 &pcfg_pull_default>,
707 <1 3 RK_FUNC_1 &pcfg_pull_default>,
708 <1 4 RK_FUNC_1 &pcfg_pull_default>,
709 <1 5 RK_FUNC_1 &pcfg_pull_default>;
710 };
711 };
713 hdmi {
714 hdmi_ctl: hdmi-ctl {
715 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
716 <1 9 RK_FUNC_1 &pcfg_pull_none>,
717 <1 10 RK_FUNC_1 &pcfg_pull_none>,
718 <1 11 RK_FUNC_1 &pcfg_pull_none>;
719 };
720 };
722 uart0 {
723 uart0_xfer: uart0-xfer {
724 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
725 <0 17 RK_FUNC_1 &pcfg_pull_none>;
726 };
728 uart0_cts: uart0-cts {
729 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
730 };
732 uart0_rts: uart0-rts {
733 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
734 };
735 };
737 uart1 {
738 uart1_xfer: uart1-xfer {
739 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
740 <2 23 RK_FUNC_1 &pcfg_pull_none>;
741 };
742 /* no rts / cts for uart1 */
743 };
745 uart2 {
746 uart2_xfer: uart2-xfer {
747 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
748 <1 19 RK_FUNC_2 &pcfg_pull_none>;
749 };
750 /* no rts / cts for uart2 */
751 };
753 spi {
754 spi_txd:spi-txd {
755 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
756 };
758 spi_rxd:spi-rxd {
759 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
760 };
762 spi_clk:spi-clk {
763 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
764 };
766 spi_cs0:spi-cs0 {
767 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
769 };
771 spi_cs1:spi-cs1 {
772 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
774 };
775 };
776 };
777 };