arch/arm/boot/dts/rk3288-veyron.dtsi

   1 /*
   2  * Google Veyron (and derivatives) board device tree source
   3  *
   4  * Copyright 2015 Google, Inc
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *  Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/clock/rockchip,rk808.h>
  46 #include <dt-bindings/input/input.h>
  47 #include "rk3288.dtsi"
  48
  49 / {
  50         memory@0 {
  51                 device_type = "memory";
  52                 reg = <0x0 0x0 0x0 0x80000000>;
  53         };
  54
  55         gpio_keys: gpio-keys {
  56                 compatible = "gpio-keys";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 pinctrl-names = "default";
  61                 pinctrl-0 = <&pwr_key_l>;
  62                 power {
  63                         label = "Power";
  64                         gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
  65                         linux,code = <KEY_POWER>;
  66                         debounce-interval = <100>;
  67                         wakeup-source;
  68                 };
  69         };
  70
  71         gpio-restart {
  72                 compatible = "gpio-restart";
  73                 gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&ap_warm_reset_h>;
  76                 priority = <200>;
  77         };
  78
  79         emmc_pwrseq: emmc-pwrseq {
  80                 compatible = "mmc-pwrseq-emmc";
  81                 pinctrl-0 = <&emmc_reset>;
  82                 pinctrl-names = "default";
  83                 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
  84         };
  85
  86         sdio_pwrseq: sdio-pwrseq {
  87                 compatible = "mmc-pwrseq-simple";
  88                 clocks = <&rk808 RK808_CLKOUT1>;
  89                 clock-names = "ext_clock";
  90                 pinctrl-names = "default";
  91                 pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
  92
  93                 /*
  94                  * On the module itself this is one of these (depending
  95                  * on the actual card populated):
  96                  * - SDIO_RESET_L_WL_REG_ON
  97                  * - PDN (power down when low)
  98                  */
  99                 reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
 100         };
 101
 102         vcc_5v: vcc-5v {
 103                 compatible = "regulator-fixed";
 104                 regulator-name = "vcc_5v";
 105                 regulator-always-on;
 106                 regulator-boot-on;
 107                 regulator-min-microvolt = <5000000>;
 108                 regulator-max-microvolt = <5000000>;
 109         };
 110
 111         vcc33_sys: vcc33-sys {
 112                 compatible = "regulator-fixed";
 113                 regulator-name = "vcc33_sys";
 114                 regulator-always-on;
 115                 regulator-boot-on;
 116                 regulator-min-microvolt = <3300000>;
 117                 regulator-max-microvolt = <3300000>;
 118         };
 119
 120         vcc50_hdmi: vcc50-hdmi {
 121                 compatible = "regulator-fixed";
 122                 regulator-name = "vcc50_hdmi";
 123                 regulator-always-on;
 124                 regulator-boot-on;
 125                 vin-supply = <&vcc_5v>;
 126         };
 127 };
 128
 129 &cpu0 {
 130         cpu0-supply = <&vdd_cpu>;
 131         operating-points = <
 132                 /* KHz    uV */
 133                 1800000 1400000
 134                 1704000 1350000
 135                 1608000 1300000
 136                 1512000 1250000
 137                 1416000 1200000
 138                 1200000 1100000
 139                 1008000 1050000
 140                  816000 1000000
 141                  696000  950000
 142                  600000  900000
 143                  408000  900000
 144                  216000  900000
 145                  126000  900000
 146         >;
 147 };
 148
 149 &emmc {
 150         status = "okay";
 151
 152         bus-width = <8>;
 153         cap-mmc-highspeed;
 154         rockchip,default-sample-phase = <158>;
 155         disable-wp;
 156         mmc-hs200-1_8v;
 157         mmc-pwrseq = <&emmc_pwrseq>;
 158         non-removable;
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 161 };
 162
 163 &gpu {
 164         mali-supply = <&vdd_gpu>;
 165         status = "okay";
 166 };
 167
 168 &hdmi {
 169         ddc-i2c-bus = <&i2c5>;
 170         status = "okay";
 171 };
 172
 173 &i2c0 {
 174         status = "okay";
 175
 176         clock-frequency = <400000>;
 177         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 178         i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
 179
 180         rk808: pmic@1b {
 181                 compatible = "rockchip,rk808";
 182                 reg = <0x1b>;
 183                 clock-output-names = "xin32k", "wifibt_32kin";
 184                 interrupt-parent = <&gpio0>;
 185                 interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
 186                 pinctrl-names = "default";
 187                 pinctrl-0 = <&pmic_int_l>;
 188                 rockchip,system-power-controller;
 189                 wakeup-source;
 190                 #clock-cells = <1>;
 191
 192                 vcc1-supply = <&vcc33_sys>;
 193                 vcc2-supply = <&vcc33_sys>;
 194                 vcc3-supply = <&vcc33_sys>;
 195                 vcc4-supply = <&vcc33_sys>;
 196                 vcc6-supply = <&vcc_5v>;
 197                 vcc7-supply = <&vcc33_sys>;
 198                 vcc8-supply = <&vcc33_sys>;
 199                 vcc12-supply = <&vcc_18>;
 200                 vddio-supply = <&vcc33_io>;
 201
 202                 regulators {
 203                         vdd_cpu: DCDC_REG1 {
 204                                 regulator-name = "vdd_arm";
 205                                 regulator-always-on;
 206                                 regulator-boot-on;
 207                                 regulator-min-microvolt = <750000>;
 208                                 regulator-max-microvolt = <1450000>;
 209                                 regulator-ramp-delay = <6001>;
 210                                 regulator-state-mem {
 211                                         regulator-off-in-suspend;
 212                                 };
 213                         };
 214
 215                         vdd_gpu: DCDC_REG2 {
 216                                 regulator-name = "vdd_gpu";
 217                                 regulator-always-on;
 218                                 regulator-boot-on;
 219                                 regulator-min-microvolt = <800000>;
 220                                 regulator-max-microvolt = <1250000>;
 221                                 regulator-ramp-delay = <6001>;
 222                                 regulator-state-mem {
 223                                         regulator-on-in-suspend;
 224                                         regulator-suspend-microvolt = <1000000>;
 225                                 };
 226                         };
 227
 228                         vcc135_ddr: DCDC_REG3 {
 229                                 regulator-name = "vcc135_ddr";
 230                                 regulator-always-on;
 231                                 regulator-boot-on;
 232                                 regulator-state-mem {
 233                                         regulator-on-in-suspend;
 234                                 };
 235                         };
 236
 237                         /*
 238                          * vcc_18 has several aliases.  (vcc18_flashio and
 239                          * vcc18_wl).  We'll add those aliases here just to
 240                          * make it easier to follow the schematic.  The signals
 241                          * are actually hooked together and only separated for
 242                          * power measurement purposes).
 243                          */
 244                         vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
 245                                 regulator-name = "vcc_18";
 246                                 regulator-always-on;
 247                                 regulator-boot-on;
 248                                 regulator-min-microvolt = <1800000>;
 249                                 regulator-max-microvolt = <1800000>;
 250                                 regulator-state-mem {
 251                                         regulator-on-in-suspend;
 252                                         regulator-suspend-microvolt = <1800000>;
 253                                 };
 254                         };
 255
 256                         /*
 257                          * Note that both vcc33_io and vcc33_pmuio are always
 258                          * powered together. To simplify the logic in the dts
 259                          * we just refer to vcc33_io every time something is
 260                          * powered from vcc33_pmuio. In fact, on later boards
 261                          * (such as danger) they're the same net.
 262                          */
 263                         vcc33_io: LDO_REG1 {
 264                                 regulator-name = "vcc33_io";
 265                                 regulator-always-on;
 266                                 regulator-boot-on;
 267                                 regulator-min-microvolt = <3300000>;
 268                                 regulator-max-microvolt = <3300000>;
 269                                 regulator-state-mem {
 270                                         regulator-on-in-suspend;
 271                                         regulator-suspend-microvolt = <3300000>;
 272                                 };
 273                         };
 274
 275                         vdd_10: LDO_REG3 {
 276                                 regulator-name = "vdd_10";
 277                                 regulator-always-on;
 278                                 regulator-boot-on;
 279                                 regulator-min-microvolt = <1000000>;
 280                                 regulator-max-microvolt = <1000000>;
 281                                 regulator-state-mem {
 282                                         regulator-on-in-suspend;
 283                                         regulator-suspend-microvolt = <1000000>;
 284                                 };
 285                         };
 286
 287                         vdd10_lcd_pwren_h: LDO_REG7 {
 288                                 regulator-name = "vdd10_lcd_pwren_h";
 289                                 regulator-always-on;
 290                                 regulator-boot-on;
 291                                 regulator-min-microvolt = <2500000>;
 292                                 regulator-max-microvolt = <2500000>;
 293                                 regulator-state-mem {
 294                                         regulator-off-in-suspend;
 295                                 };
 296                         };
 297
 298                         vcc33_lcd: SWITCH_REG1 {
 299                                 regulator-name = "vcc33_lcd";
 300                                 regulator-always-on;
 301                                 regulator-boot-on;
 302                                 regulator-state-mem {
 303                                         regulator-off-in-suspend;
 304                                 };
 305                         };
 306                 };
 307         };
 308 };
 309
 310 &i2c1 {
 311         status = "okay";
 312
 313         clock-frequency = <400000>;
 314         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 315         i2c-scl-rising-time-ns = <100>;         /* 40ns measured */
 316
 317         tpm: tpm@20 {
 318                 compatible = "infineon,slb9645tt";
 319                 reg = <0x20>;
 320                 powered-while-suspended;
 321         };
 322 };
 323
 324 &i2c2 {
 325         status = "okay";
 326
 327         /* 100kHz since 4.7k resistors don't rise fast enough */
 328         clock-frequency = <100000>;
 329         i2c-scl-falling-time-ns = <50>;         /* 10ns measured */
 330         i2c-scl-rising-time-ns = <800>;         /* 600ns measured */
 331 };
 332
 333 &i2c4 {
 334         status = "okay";
 335
 336         clock-frequency = <400000>;
 337         i2c-scl-falling-time-ns = <50>;         /* 11ns measured */
 338         i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
 339 };
 340
 341 &i2c5 {
 342         status = "okay";
 343
 344         clock-frequency = <100000>;
 345         i2c-scl-falling-time-ns = <300>;
 346         i2c-scl-rising-time-ns = <1000>;
 347 };
 348
 349 &io_domains {
 350         status = "okay";
 351
 352         bb-supply = <&vcc33_io>;
 353         dvp-supply = <&vcc_18>;
 354         flash0-supply = <&vcc18_flashio>;
 355         gpio1830-supply = <&vcc33_io>;
 356         gpio30-supply = <&vcc33_io>;
 357         lcdc-supply = <&vcc33_lcd>;
 358         wifi-supply = <&vcc18_wl>;
 359 };
 360
 361 &pwm1 {
 362         status = "okay";
 363 };
 364
 365 &sdio0 {
 366         status = "okay";
 367
 368         bus-width = <4>;
 369         cap-sd-highspeed;
 370         cap-sdio-irq;
 371         keep-power-in-suspend;
 372         mmc-pwrseq = <&sdio_pwrseq>;
 373         non-removable;
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
 376         sd-uhs-sdr12;
 377         sd-uhs-sdr25;
 378         sd-uhs-sdr50;
 379         sd-uhs-sdr104;
 380         vmmc-supply = <&vcc33_sys>;
 381         vqmmc-supply = <&vcc18_wl>;
 382 };
 383
 384 &spi2 {
 385         status = "okay";
 386
 387         rx-sample-delay-ns = <12>;
 388
 389         flash@0 {
 390                 compatible = "jedec,spi-nor";
 391                 spi-max-frequency = <50000000>;
 392                 reg = <0>;
 393         };
 394 };
 395
 396 &tsadc {
 397         status = "okay";
 398
 399         rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 400         rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 401 };
 402
 403 &uart0 {
 404         status = "okay";
 405
 406         /* We need to go faster than 24MHz, so adjust clock parents / rates */
 407         assigned-clocks = <&cru SCLK_UART0>;
 408         assigned-clock-rates = <48000000>;
 409
 410         /* Pins don't include flow control by default; add that in */
 411         pinctrl-names = "default";
 412         pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 413 };
 414
 415 &uart1 {
 416         status = "okay";
 417 };
 418
 419 &uart2 {
 420         status = "okay";
 421 };
 422
 423 &usbphy {
 424         status = "okay";
 425 };
 426
 427 &usb_host0_ehci {
 428         status = "okay";
 429
 430         needs-reset-on-resume;
 431 };
 432
 433 &usb_host1 {
 434         status = "okay";
 435 };
 436
 437 &usb_otg {
 438         status = "okay";
 439
 440         assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
 441         assigned-clock-parents = <&usbphy0>;
 442         dr_mode = "host";
 443 };
 444
 445 &vopb {
 446         status = "okay";
 447 };
 448
 449 &vopb_mmu {
 450         status = "okay";
 451 };
 452
 453 &wdt {
 454         status = "okay";
 455 };
 456
 457 &pinctrl {
 458         pinctrl-names = "default", "sleep";
 459         pinctrl-0 = <
 460                 /* Common for sleep and wake, but no owners */
 461                 &global_pwroff
 462         >;
 463         pinctrl-1 = <
 464                 /* Common for sleep and wake, but no owners */
 465                 &global_pwroff
 466         >;
 467
 468         pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 469                 bias-disable;
 470                 drive-strength = <8>;
 471         };
 472
 473         pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 474                 bias-pull-up;
 475                 drive-strength = <8>;
 476         };
 477
 478         pcfg_output_high: pcfg-output-high {
 479                 output-high;
 480         };
 481
 482         pcfg_output_low: pcfg-output-low {
 483                 output-low;
 484         };
 485
 486         buttons {
 487                 pwr_key_l: pwr-key-l {
 488                         rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
 489                 };
 490         };
 491
 492         emmc {
 493                 emmc_reset: emmc-reset {
 494                         rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
 495                 };
 496
 497                 /*
 498                  * We run eMMC at max speed; bump up drive strength.
 499                  * We also have external pulls, so disable the internal ones.
 500                  */
 501                 emmc_clk: emmc-clk {
 502                         rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 503                 };
 504
 505                 emmc_cmd: emmc-cmd {
 506                         rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 507                 };
 508
 509                 emmc_bus8: emmc-bus8 {
 510                         rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 511                                         <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 512                                         <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 513                                         <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 514                                         <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 515                                         <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 516                                         <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 517                                         <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 518                 };
 519         };
 520
 521         pmic {
 522                 pmic_int_l: pmic-int-l {
 523                         rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
 524                 };
 525         };
 526
 527         reboot {
 528                 ap_warm_reset_h: ap-warm-reset-h {
 529                         rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
 530                 };
 531         };
 532
 533         recovery-switch {
 534                 rec_mode_l: rec-mode-l {
 535                         rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
 536                 };
 537         };
 538
 539         sdio0 {
 540                 wifi_enable_h: wifienable-h {
 541                         rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
 542                 };
 543
 544                 /* NOTE: mislabelled on schematic; should be bt_enable_h */
 545                 bt_enable_l: bt-enable-l {
 546                         rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
 547                 };
 548
 549                 /*
 550                  * We run sdio0 at max speed; bump up drive strength.
 551                  * We also have external pulls, so disable the internal ones.
 552                  */
 553                 sdio0_bus4: sdio0-bus4 {
 554                         rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 555                                         <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 556                                         <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 557                                         <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 558                 };
 559
 560                 sdio0_cmd: sdio0-cmd {
 561                         rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 562                 };
 563
 564                 sdio0_clk: sdio0-clk {
 565                         rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 566                 };
 567         };
 568
 569         tpm {
 570                 tpm_int_h: tpm-int-h {
 571                         rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
 572                 };
 573         };
 574
 575         write-protect {
 576                 fw_wp_ap: fw-wp-ap {
 577                         rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
 578                 };
 579         };
 580 };