| blob | 356ed1e624525224c8e797da0990f83a75823008 |
1 /*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/power/rk3288-power.h>
47 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/power/rk3288-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
51 / {
52 #address-cells = <2>;
53 #size-cells = <2>;
55 compatible = "rockchip,rk3288";
57 interrupt-parent = <&gic>;
59 aliases {
60 ethernet0 = &gmac;
61 i2c0 = &i2c0;
62 i2c1 = &i2c1;
63 i2c2 = &i2c2;
64 i2c3 = &i2c3;
65 i2c4 = &i2c4;
66 i2c5 = &i2c5;
67 mshc0 = &emmc;
68 mshc1 = &sdmmc;
69 mshc2 = &sdio0;
70 mshc3 = &sdio1;
71 serial0 = &uart0;
72 serial1 = &uart1;
73 serial2 = &uart2;
74 serial3 = &uart3;
75 serial4 = &uart4;
76 spi0 = &spi0;
77 spi1 = &spi1;
78 spi2 = &spi2;
79 };
81 arm-pmu {
82 compatible = "arm,cortex-a12-pmu";
83 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
87 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88 };
90 cpus {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 enable-method = "rockchip,rk3066-smp";
94 rockchip,pmu = <&pmu>;
96 cpu0: cpu@500 {
97 device_type = "cpu";
98 compatible = "arm,cortex-a12";
99 reg = <0x500>;
100 resets = <&cru SRST_CORE0>;
101 operating-points = <
102 /* KHz uV */
103 1608000 1350000
104 1512000 1300000
105 1416000 1200000
106 1200000 1100000
107 1008000 1050000
108 816000 1000000
109 696000 950000
110 600000 900000
111 408000 900000
112 312000 900000
113 216000 900000
114 126000 900000
115 >;
116 #cooling-cells = <2>; /* min followed by max */
117 clock-latency = <40000>;
118 clocks = <&cru ARMCLK>;
119 };
120 cpu1: cpu@501 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a12";
123 reg = <0x501>;
124 resets = <&cru SRST_CORE1>;
125 };
126 cpu2: cpu@502 {
127 device_type = "cpu";
128 compatible = "arm,cortex-a12";
129 reg = <0x502>;
130 resets = <&cru SRST_CORE2>;
131 };
132 cpu3: cpu@503 {
133 device_type = "cpu";
134 compatible = "arm,cortex-a12";
135 reg = <0x503>;
136 resets = <&cru SRST_CORE3>;
137 };
138 };
140 amba {
141 compatible = "simple-bus";
142 #address-cells = <2>;
143 #size-cells = <2>;
144 ranges;
146 dmac_peri: dma-controller@ff250000 {
147 compatible = "arm,pl330", "arm,primecell";
148 reg = <0x0 0xff250000 0x0 0x4000>;
149 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
151 #dma-cells = <1>;
152 arm,pl330-broken-no-flushp;
153 clocks = <&cru ACLK_DMAC2>;
154 clock-names = "apb_pclk";
155 };
157 dmac_bus_ns: dma-controller@ff600000 {
158 compatible = "arm,pl330", "arm,primecell";
159 reg = <0x0 0xff600000 0x0 0x4000>;
160 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
162 #dma-cells = <1>;
163 arm,pl330-broken-no-flushp;
164 clocks = <&cru ACLK_DMAC1>;
165 clock-names = "apb_pclk";
166 status = "disabled";
167 };
169 dmac_bus_s: dma-controller@ffb20000 {
170 compatible = "arm,pl330", "arm,primecell";
171 reg = <0x0 0xffb20000 0x0 0x4000>;
172 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
174 #dma-cells = <1>;
175 arm,pl330-broken-no-flushp;
176 clocks = <&cru ACLK_DMAC1>;
177 clock-names = "apb_pclk";
178 };
179 };
181 reserved-memory {
182 #address-cells = <2>;
183 #size-cells = <2>;
184 ranges;
186 /*
187 * The rk3288 cannot use the memory area above 0xfe000000
188 * for dma operations for some reason. While there is
189 * probably a better solution available somewhere, we
190 * haven't found it yet and while devices with 2GB of ram
191 * are not affected, this issue prevents 4GB from booting.
192 * So to make these devices at least bootable, block
193 * this area for the time being until the real solution
194 * is found.
195 */
196 dma-unusable@fe000000 {
197 reg = <0x0 0xfe000000 0x0 0x1000000>;
198 };
199 };
201 xin24m: oscillator {
202 compatible = "fixed-clock";
203 clock-frequency = <24000000>;
204 clock-output-names = "xin24m";
205 #clock-cells = <0>;
206 };
208 timer {
209 compatible = "arm,armv7-timer";
210 arm,cpu-registers-not-fw-configured;
211 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
212 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
213 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
214 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
215 clock-frequency = <24000000>;
216 };
218 timer: timer@ff810000 {
219 compatible = "rockchip,rk3288-timer";
220 reg = <0x0 0xff810000 0x0 0x20>;
221 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&xin24m>, <&cru PCLK_TIMER>;
223 clock-names = "timer", "pclk";
224 };
226 display-subsystem {
227 compatible = "rockchip,display-subsystem";
228 ports = <&vopl_out>, <&vopb_out>;
229 };
231 sdmmc: dwmmc@ff0c0000 {
232 compatible = "rockchip,rk3288-dw-mshc";
233 max-frequency = <150000000>;
234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
235 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
237 fifo-depth = <0x100>;
238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
239 reg = <0x0 0xff0c0000 0x0 0x4000>;
240 resets = <&cru SRST_MMC0>;
241 reset-names = "reset";
242 status = "disabled";
243 };
245 sdio0: dwmmc@ff0d0000 {
246 compatible = "rockchip,rk3288-dw-mshc";
247 max-frequency = <150000000>;
248 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
249 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
250 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
251 fifo-depth = <0x100>;
252 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
253 reg = <0x0 0xff0d0000 0x0 0x4000>;
254 resets = <&cru SRST_SDIO0>;
255 reset-names = "reset";
256 status = "disabled";
257 };
259 sdio1: dwmmc@ff0e0000 {
260 compatible = "rockchip,rk3288-dw-mshc";
261 max-frequency = <150000000>;
262 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
263 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
264 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
265 fifo-depth = <0x100>;
266 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
267 reg = <0x0 0xff0e0000 0x0 0x4000>;
268 resets = <&cru SRST_SDIO1>;
269 reset-names = "reset";
270 status = "disabled";
271 };
273 emmc: dwmmc@ff0f0000 {
274 compatible = "rockchip,rk3288-dw-mshc";
275 max-frequency = <150000000>;
276 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
277 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
278 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
279 fifo-depth = <0x100>;
280 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
281 reg = <0x0 0xff0f0000 0x0 0x4000>;
282 resets = <&cru SRST_EMMC>;
283 reset-names = "reset";
284 status = "disabled";
285 };
287 saradc: saradc@ff100000 {
288 compatible = "rockchip,saradc";
289 reg = <0x0 0xff100000 0x0 0x100>;
290 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
291 #io-channel-cells = <1>;
292 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
293 clock-names = "saradc", "apb_pclk";
294 resets = <&cru SRST_SARADC>;
295 reset-names = "saradc-apb";
296 status = "disabled";
297 };
299 spi0: spi@ff110000 {
300 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
301 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
302 clock-names = "spiclk", "apb_pclk";
303 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
304 dma-names = "tx", "rx";
305 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
308 reg = <0x0 0xff110000 0x0 0x1000>;
309 #address-cells = <1>;
310 #size-cells = <0>;
311 status = "disabled";
312 };
314 spi1: spi@ff120000 {
315 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
316 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
317 clock-names = "spiclk", "apb_pclk";
318 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
319 dma-names = "tx", "rx";
320 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
323 reg = <0x0 0xff120000 0x0 0x1000>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 status = "disabled";
327 };
329 spi2: spi@ff130000 {
330 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
331 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
332 clock-names = "spiclk", "apb_pclk";
333 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
334 dma-names = "tx", "rx";
335 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
338 reg = <0x0 0xff130000 0x0 0x1000>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 status = "disabled";
342 };
344 i2c1: i2c@ff140000 {
345 compatible = "rockchip,rk3288-i2c";
346 reg = <0x0 0xff140000 0x0 0x1000>;
347 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 clock-names = "i2c";
351 clocks = <&cru PCLK_I2C1>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2c1_xfer>;
354 status = "disabled";
355 };
357 i2c3: i2c@ff150000 {
358 compatible = "rockchip,rk3288-i2c";
359 reg = <0x0 0xff150000 0x0 0x1000>;
360 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363 clock-names = "i2c";
364 clocks = <&cru PCLK_I2C3>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&i2c3_xfer>;
367 status = "disabled";
368 };
370 i2c4: i2c@ff160000 {
371 compatible = "rockchip,rk3288-i2c";
372 reg = <0x0 0xff160000 0x0 0x1000>;
373 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
374 #address-cells = <1>;
375 #size-cells = <0>;
376 clock-names = "i2c";
377 clocks = <&cru PCLK_I2C4>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&i2c4_xfer>;
380 status = "disabled";
381 };
383 i2c5: i2c@ff170000 {
384 compatible = "rockchip,rk3288-i2c";
385 reg = <0x0 0xff170000 0x0 0x1000>;
386 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 clock-names = "i2c";
390 clocks = <&cru PCLK_I2C5>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&i2c5_xfer>;
393 status = "disabled";
394 };
396 uart0: serial@ff180000 {
397 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
398 reg = <0x0 0xff180000 0x0 0x100>;
399 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
400 reg-shift = <2>;
401 reg-io-width = <4>;
402 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
403 clock-names = "baudclk", "apb_pclk";
404 pinctrl-names = "default";
405 pinctrl-0 = <&uart0_xfer>;
406 status = "disabled";
407 };
409 uart1: serial@ff190000 {
410 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
411 reg = <0x0 0xff190000 0x0 0x100>;
412 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
413 reg-shift = <2>;
414 reg-io-width = <4>;
415 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
416 clock-names = "baudclk", "apb_pclk";
417 pinctrl-names = "default";
418 pinctrl-0 = <&uart1_xfer>;
419 status = "disabled";
420 };
422 uart2: serial@ff690000 {
423 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
424 reg = <0x0 0xff690000 0x0 0x100>;
425 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
426 reg-shift = <2>;
427 reg-io-width = <4>;
428 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
429 clock-names = "baudclk", "apb_pclk";
430 pinctrl-names = "default";
431 pinctrl-0 = <&uart2_xfer>;
432 status = "disabled";
433 };
435 uart3: serial@ff1b0000 {
436 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
437 reg = <0x0 0xff1b0000 0x0 0x100>;
438 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
439 reg-shift = <2>;
440 reg-io-width = <4>;
441 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
442 clock-names = "baudclk", "apb_pclk";
443 pinctrl-names = "default";
444 pinctrl-0 = <&uart3_xfer>;
445 status = "disabled";
446 };
448 uart4: serial@ff1c0000 {
449 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
450 reg = <0x0 0xff1c0000 0x0 0x100>;
451 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
452 reg-shift = <2>;
453 reg-io-width = <4>;
454 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
455 clock-names = "baudclk", "apb_pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&uart4_xfer>;
458 status = "disabled";
459 };
461 thermal-zones {
462 reserve_thermal: reserve_thermal {
463 polling-delay-passive = <1000>; /* milliseconds */
464 polling-delay = <5000>; /* milliseconds */
466 thermal-sensors = <&tsadc 0>;
467 };
469 cpu_thermal: cpu_thermal {
470 polling-delay-passive = <100>; /* milliseconds */
471 polling-delay = <5000>; /* milliseconds */
473 thermal-sensors = <&tsadc 1>;
475 trips {
476 cpu_alert0: cpu_alert0 {
477 temperature = <70000>; /* millicelsius */
478 hysteresis = <2000>; /* millicelsius */
479 type = "passive";
480 };
481 cpu_alert1: cpu_alert1 {
482 temperature = <75000>; /* millicelsius */
483 hysteresis = <2000>; /* millicelsius */
484 type = "passive";
485 };
486 cpu_crit: cpu_crit {
487 temperature = <90000>; /* millicelsius */
488 hysteresis = <2000>; /* millicelsius */
489 type = "critical";
490 };
491 };
493 cooling-maps {
494 map0 {
495 trip = <&cpu_alert0>;
496 cooling-device =
497 <&cpu0 THERMAL_NO_LIMIT 6>;
498 };
499 map1 {
500 trip = <&cpu_alert1>;
501 cooling-device =
502 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
503 };
504 };
505 };
507 gpu_thermal: gpu_thermal {
508 polling-delay-passive = <100>; /* milliseconds */
509 polling-delay = <5000>; /* milliseconds */
511 thermal-sensors = <&tsadc 2>;
513 trips {
514 gpu_alert0: gpu_alert0 {
515 temperature = <70000>; /* millicelsius */
516 hysteresis = <2000>; /* millicelsius */
517 type = "passive";
518 };
519 gpu_crit: gpu_crit {
520 temperature = <90000>; /* millicelsius */
521 hysteresis = <2000>; /* millicelsius */
522 type = "critical";
523 };
524 };
526 cooling-maps {
527 map0 {
528 trip = <&gpu_alert0>;
529 cooling-device =
530 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
531 };
532 };
533 };
534 };
536 tsadc: tsadc@ff280000 {
537 compatible = "rockchip,rk3288-tsadc";
538 reg = <0x0 0xff280000 0x0 0x100>;
539 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
541 clock-names = "tsadc", "apb_pclk";
542 resets = <&cru SRST_TSADC>;
543 reset-names = "tsadc-apb";
544 pinctrl-names = "init", "default", "sleep";
545 pinctrl-0 = <&otp_gpio>;
546 pinctrl-1 = <&otp_out>;
547 pinctrl-2 = <&otp_gpio>;
548 #thermal-sensor-cells = <1>;
549 rockchip,hw-tshut-temp = <95000>;
550 status = "disabled";
551 };
553 gmac: ethernet@ff290000 {
554 compatible = "rockchip,rk3288-gmac";
555 reg = <0x0 0xff290000 0x0 0x10000>;
556 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
558 interrupt-names = "macirq", "eth_wake_irq";
559 rockchip,grf = <&grf>;
560 clocks = <&cru SCLK_MAC>,
561 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
562 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
563 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
564 clock-names = "stmmaceth",
565 "mac_clk_rx", "mac_clk_tx",
566 "clk_mac_ref", "clk_mac_refout",
567 "aclk_mac", "pclk_mac";
568 resets = <&cru SRST_MAC>;
569 reset-names = "stmmaceth";
570 status = "disabled";
571 };
573 usb_host0_ehci: usb@ff500000 {
574 compatible = "generic-ehci";
575 reg = <0x0 0xff500000 0x0 0x100>;
576 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&cru HCLK_USBHOST0>;
578 clock-names = "usbhost";
579 phys = <&usbphy1>;
580 phy-names = "usb";
581 status = "disabled";
582 };
584 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
586 usb_host1: usb@ff540000 {
587 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
588 "snps,dwc2";
589 reg = <0x0 0xff540000 0x0 0x40000>;
590 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&cru HCLK_USBHOST1>;
592 clock-names = "otg";
593 dr_mode = "host";
594 phys = <&usbphy2>;
595 phy-names = "usb2-phy";
596 status = "disabled";
597 };
599 usb_otg: usb@ff580000 {
600 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
601 "snps,dwc2";
602 reg = <0x0 0xff580000 0x0 0x40000>;
603 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cru HCLK_OTG0>;
605 clock-names = "otg";
606 dr_mode = "otg";
607 g-np-tx-fifo-size = <16>;
608 g-rx-fifo-size = <275>;
609 g-tx-fifo-size = <256 128 128 64 64 32>;
610 phys = <&usbphy0>;
611 phy-names = "usb2-phy";
612 status = "disabled";
613 };
615 usb_hsic: usb@ff5c0000 {
616 compatible = "generic-ehci";
617 reg = <0x0 0xff5c0000 0x0 0x100>;
618 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cru HCLK_HSIC>;
620 clock-names = "usbhost";
621 status = "disabled";
622 };
624 i2c0: i2c@ff650000 {
625 compatible = "rockchip,rk3288-i2c";
626 reg = <0x0 0xff650000 0x0 0x1000>;
627 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
628 #address-cells = <1>;
629 #size-cells = <0>;
630 clock-names = "i2c";
631 clocks = <&cru PCLK_I2C0>;
632 pinctrl-names = "default";
633 pinctrl-0 = <&i2c0_xfer>;
634 status = "disabled";
635 };
637 i2c2: i2c@ff660000 {
638 compatible = "rockchip,rk3288-i2c";
639 reg = <0x0 0xff660000 0x0 0x1000>;
640 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
641 #address-cells = <1>;
642 #size-cells = <0>;
643 clock-names = "i2c";
644 clocks = <&cru PCLK_I2C2>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&i2c2_xfer>;
647 status = "disabled";
648 };
650 pwm0: pwm@ff680000 {
651 compatible = "rockchip,rk3288-pwm";
652 reg = <0x0 0xff680000 0x0 0x10>;
653 #pwm-cells = <3>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&pwm0_pin>;
656 clocks = <&cru PCLK_PWM>;
657 clock-names = "pwm";
658 status = "disabled";
659 };
661 pwm1: pwm@ff680010 {
662 compatible = "rockchip,rk3288-pwm";
663 reg = <0x0 0xff680010 0x0 0x10>;
664 #pwm-cells = <3>;
665 pinctrl-names = "default";
666 pinctrl-0 = <&pwm1_pin>;
667 clocks = <&cru PCLK_PWM>;
668 clock-names = "pwm";
669 status = "disabled";
670 };
672 pwm2: pwm@ff680020 {
673 compatible = "rockchip,rk3288-pwm";
674 reg = <0x0 0xff680020 0x0 0x10>;
675 #pwm-cells = <3>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&pwm2_pin>;
678 clocks = <&cru PCLK_PWM>;
679 clock-names = "pwm";
680 status = "disabled";
681 };
683 pwm3: pwm@ff680030 {
684 compatible = "rockchip,rk3288-pwm";
685 reg = <0x0 0xff680030 0x0 0x10>;
686 #pwm-cells = <2>;
687 pinctrl-names = "default";
688 pinctrl-0 = <&pwm3_pin>;
689 clocks = <&cru PCLK_PWM>;
690 clock-names = "pwm";
691 status = "disabled";
692 };
694 bus_intmem@ff700000 {
695 compatible = "mmio-sram";
696 reg = <0x0 0xff700000 0x0 0x18000>;
697 #address-cells = <1>;
698 #size-cells = <1>;
699 ranges = <0 0x0 0xff700000 0x18000>;
700 smp-sram@0 {
701 compatible = "rockchip,rk3066-smp-sram";
702 reg = <0x00 0x10>;
703 };
704 };
706 sram@ff720000 {
707 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
708 reg = <0x0 0xff720000 0x0 0x1000>;
709 };
711 pmu: power-management@ff730000 {
712 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
713 reg = <0x0 0xff730000 0x0 0x100>;
715 power: power-controller {
716 compatible = "rockchip,rk3288-power-controller";
717 #power-domain-cells = <1>;
718 #address-cells = <1>;
719 #size-cells = <0>;
721 assigned-clocks = <&cru SCLK_EDP_24M>;
722 assigned-clock-parents = <&xin24m>;
724 /*
725 * Note: Although SCLK_* are the working clocks
726 * of device without including on the NOC, needed for
727 * synchronous reset.
728 *
729 * The clocks on the which NOC:
730 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
731 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
732 * ACLK_RGA is on ACLK_RGA_NIU.
733 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
734 *
735 * Which clock are device clocks:
736 * clocks devices
737 * *_IEP IEP:Image Enhancement Processor
738 * *_ISP ISP:Image Signal Processing
739 * *_VIP VIP:Video Input Processor
740 * *_VOP* VOP:Visual Output Processor
741 * *_RGA RGA
742 * *_EDP* EDP
743 * *_LVDS_* LVDS
744 * *_HDMI HDMI
745 * *_MIPI_* MIPI
746 */
747 pd_vio@RK3288_PD_VIO {
748 reg = <RK3288_PD_VIO>;
749 clocks = <&cru ACLK_IEP>,
750 <&cru ACLK_ISP>,
751 <&cru ACLK_RGA>,
752 <&cru ACLK_VIP>,
753 <&cru ACLK_VOP0>,
754 <&cru ACLK_VOP1>,
755 <&cru DCLK_VOP0>,
756 <&cru DCLK_VOP1>,
757 <&cru HCLK_IEP>,
758 <&cru HCLK_ISP>,
759 <&cru HCLK_RGA>,
760 <&cru HCLK_VIP>,
761 <&cru HCLK_VOP0>,
762 <&cru HCLK_VOP1>,
763 <&cru PCLK_EDP_CTRL>,
764 <&cru PCLK_HDMI_CTRL>,
765 <&cru PCLK_LVDS_PHY>,
766 <&cru PCLK_MIPI_CSI>,
767 <&cru PCLK_MIPI_DSI0>,
768 <&cru PCLK_MIPI_DSI1>,
769 <&cru SCLK_EDP_24M>,
770 <&cru SCLK_EDP>,
771 <&cru SCLK_ISP_JPE>,
772 <&cru SCLK_ISP>,
773 <&cru SCLK_RGA>;
774 pm_qos = <&qos_vio0_iep>,
775 <&qos_vio1_vop>,
776 <&qos_vio1_isp_w0>,
777 <&qos_vio1_isp_w1>,
778 <&qos_vio0_vop>,
779 <&qos_vio0_vip>,
780 <&qos_vio2_rga_r>,
781 <&qos_vio2_rga_w>,
782 <&qos_vio1_isp_r>;
783 };
785 /*
786 * Note: The following 3 are HEVC(H.265) clocks,
787 * and on the ACLK_HEVC_NIU (NOC).
788 */
789 pd_hevc@RK3288_PD_HEVC {
790 reg = <RK3288_PD_HEVC>;
791 clocks = <&cru ACLK_HEVC>,
792 <&cru SCLK_HEVC_CABAC>,
793 <&cru SCLK_HEVC_CORE>;
794 pm_qos = <&qos_hevc_r>,
795 <&qos_hevc_w>;
796 };
798 /*
799 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
800 * (video endecoder & decoder) clocks that on the
801 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
802 */
803 pd_video@RK3288_PD_VIDEO {
804 reg = <RK3288_PD_VIDEO>;
805 clocks = <&cru ACLK_VCODEC>,
806 <&cru HCLK_VCODEC>;
807 pm_qos = <&qos_video>;
808 };
810 /*
811 * Note: ACLK_GPU is the GPU clock,
812 * and on the ACLK_GPU_NIU (NOC).
813 */
814 pd_gpu@RK3288_PD_GPU {
815 reg = <RK3288_PD_GPU>;
816 clocks = <&cru ACLK_GPU>;
817 pm_qos = <&qos_gpu_r>,
818 <&qos_gpu_w>;
819 };
820 };
822 reboot-mode {
823 compatible = "syscon-reboot-mode";
824 offset = <0x94>;
825 mode-normal = <BOOT_NORMAL>;
826 mode-recovery = <BOOT_RECOVERY>;
827 mode-bootloader = <BOOT_FASTBOOT>;
828 mode-loader = <BOOT_BL_DOWNLOAD>;
829 };
830 };
832 sgrf: syscon@ff740000 {
833 compatible = "rockchip,rk3288-sgrf", "syscon";
834 reg = <0x0 0xff740000 0x0 0x1000>;
835 };
837 cru: clock-controller@ff760000 {
838 compatible = "rockchip,rk3288-cru";
839 reg = <0x0 0xff760000 0x0 0x1000>;
840 rockchip,grf = <&grf>;
841 #clock-cells = <1>;
842 #reset-cells = <1>;
843 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
844 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
845 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
846 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
847 <&cru PCLK_PERI>;
848 assigned-clock-rates = <594000000>, <400000000>,
849 <500000000>, <300000000>,
850 <150000000>, <75000000>,
851 <300000000>, <150000000>,
852 <75000000>;
853 };
855 grf: syscon@ff770000 {
856 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
857 reg = <0x0 0xff770000 0x0 0x1000>;
859 edp_phy: edp-phy {
860 compatible = "rockchip,rk3288-dp-phy";
861 clocks = <&cru SCLK_EDP_24M>;
862 clock-names = "24m";
863 #phy-cells = <0>;
864 status = "disabled";
865 };
867 io_domains: io-domains {
868 compatible = "rockchip,rk3288-io-voltage-domain";
869 status = "disabled";
870 };
872 usbphy: usbphy {
873 compatible = "rockchip,rk3288-usb-phy";
874 #address-cells = <1>;
875 #size-cells = <0>;
876 status = "disabled";
878 usbphy0: usb-phy@320 {
879 #phy-cells = <0>;
880 reg = <0x320>;
881 clocks = <&cru SCLK_OTGPHY0>;
882 clock-names = "phyclk";
883 #clock-cells = <0>;
884 };
886 usbphy1: usb-phy@334 {
887 #phy-cells = <0>;
888 reg = <0x334>;
889 clocks = <&cru SCLK_OTGPHY1>;
890 clock-names = "phyclk";
891 #clock-cells = <0>;
892 };
894 usbphy2: usb-phy@348 {
895 #phy-cells = <0>;
896 reg = <0x348>;
897 clocks = <&cru SCLK_OTGPHY2>;
898 clock-names = "phyclk";
899 #clock-cells = <0>;
900 };
901 };
902 };
904 wdt: watchdog@ff800000 {
905 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
906 reg = <0x0 0xff800000 0x0 0x100>;
907 clocks = <&cru PCLK_WDT>;
908 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
909 status = "disabled";
910 };
912 spdif: sound@ff88b0000 {
913 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
914 reg = <0x0 0xff8b0000 0x0 0x10000>;
915 #sound-dai-cells = <0>;
916 clock-names = "hclk", "mclk";
917 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
918 dmas = <&dmac_bus_s 3>;
919 dma-names = "tx";
920 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&spdif_tx>;
923 rockchip,grf = <&grf>;
924 status = "disabled";
925 };
927 i2s: i2s@ff890000 {
928 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
929 reg = <0x0 0xff890000 0x0 0x10000>;
930 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
931 #address-cells = <1>;
932 #size-cells = <0>;
933 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
934 dma-names = "tx", "rx";
935 clock-names = "i2s_hclk", "i2s_clk";
936 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
937 pinctrl-names = "default";
938 pinctrl-0 = <&i2s0_bus>;
939 rockchip,playback-channels = <8>;
940 rockchip,capture-channels = <2>;
941 status = "disabled";
942 };
944 crypto: cypto-controller@ff8a0000 {
945 compatible = "rockchip,rk3288-crypto";
946 reg = <0x0 0xff8a0000 0x0 0x4000>;
947 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
949 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
950 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
951 resets = <&cru SRST_CRYPTO>;
952 reset-names = "crypto-rst";
953 status = "okay";
954 };
956 iep_mmu: iommu@ff900800 {
957 compatible = "rockchip,iommu";
958 reg = <0x0 0xff900800 0x0 0x40>;
959 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
960 interrupt-names = "iep_mmu";
961 #iommu-cells = <0>;
962 status = "disabled";
963 };
965 isp_mmu: iommu@ff914000 {
966 compatible = "rockchip,iommu";
967 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
968 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
969 interrupt-names = "isp_mmu";
970 #iommu-cells = <0>;
971 rockchip,disable-mmu-reset;
972 status = "disabled";
973 };
975 vopb: vop@ff930000 {
976 compatible = "rockchip,rk3288-vop";
977 reg = <0x0 0xff930000 0x0 0x19c>;
978 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
980 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
981 power-domains = <&power RK3288_PD_VIO>;
982 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
983 reset-names = "axi", "ahb", "dclk";
984 iommus = <&vopb_mmu>;
985 status = "disabled";
987 vopb_out: port {
988 #address-cells = <1>;
989 #size-cells = <0>;
991 vopb_out_hdmi: endpoint@0 {
992 reg = <0>;
993 remote-endpoint = <&hdmi_in_vopb>;
994 };
996 vopb_out_edp: endpoint@1 {
997 reg = <1>;
998 remote-endpoint = <&edp_in_vopb>;
999 };
1001 vopb_out_mipi: endpoint@2 {
1002 reg = <2>;
1003 remote-endpoint = <&mipi_in_vopb>;
1004 };
1005 };
1006 };
1008 vopb_mmu: iommu@ff930300 {
1009 compatible = "rockchip,iommu";
1010 reg = <0x0 0xff930300 0x0 0x100>;
1011 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1012 interrupt-names = "vopb_mmu";
1013 power-domains = <&power RK3288_PD_VIO>;
1014 #iommu-cells = <0>;
1015 status = "disabled";
1016 };
1018 vopl: vop@ff940000 {
1019 compatible = "rockchip,rk3288-vop";
1020 reg = <0x0 0xff940000 0x0 0x19c>;
1021 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1022 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1023 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1024 power-domains = <&power RK3288_PD_VIO>;
1025 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1026 reset-names = "axi", "ahb", "dclk";
1027 iommus = <&vopl_mmu>;
1028 status = "disabled";
1030 vopl_out: port {
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1034 vopl_out_hdmi: endpoint@0 {
1035 reg = <0>;
1036 remote-endpoint = <&hdmi_in_vopl>;
1037 };
1039 vopl_out_edp: endpoint@1 {
1040 reg = <1>;
1041 remote-endpoint = <&edp_in_vopl>;
1042 };
1044 vopl_out_mipi: endpoint@2 {
1045 reg = <2>;
1046 remote-endpoint = <&mipi_in_vopl>;
1047 };
1048 };
1049 };
1051 vopl_mmu: iommu@ff940300 {
1052 compatible = "rockchip,iommu";
1053 reg = <0x0 0xff940300 0x0 0x100>;
1054 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1055 interrupt-names = "vopl_mmu";
1056 power-domains = <&power RK3288_PD_VIO>;
1057 #iommu-cells = <0>;
1058 status = "disabled";
1059 };
1061 mipi_dsi: mipi@ff960000 {
1062 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1063 reg = <0x0 0xff960000 0x0 0x4000>;
1064 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1066 clock-names = "ref", "pclk";
1067 power-domains = <&power RK3288_PD_VIO>;
1068 rockchip,grf = <&grf>;
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1071 status = "disabled";
1073 ports {
1074 mipi_in: port {
1075 #address-cells = <1>;
1076 #size-cells = <0>;
1077 mipi_in_vopb: endpoint@0 {
1078 reg = <0>;
1079 remote-endpoint = <&vopb_out_mipi>;
1080 };
1081 mipi_in_vopl: endpoint@1 {
1082 reg = <1>;
1083 remote-endpoint = <&vopl_out_mipi>;
1084 };
1085 };
1086 };
1087 };
1089 edp: dp@ff970000 {
1090 compatible = "rockchip,rk3288-dp";
1091 reg = <0x0 0xff970000 0x0 0x4000>;
1092 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1094 clock-names = "dp", "pclk";
1095 phys = <&edp_phy>;
1096 phy-names = "dp";
1097 resets = <&cru SRST_EDP>;
1098 reset-names = "dp";
1099 rockchip,grf = <&grf>;
1100 status = "disabled";
1102 ports {
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1105 edp_in: port@0 {
1106 reg = <0>;
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1109 edp_in_vopb: endpoint@0 {
1110 reg = <0>;
1111 remote-endpoint = <&vopb_out_edp>;
1112 };
1113 edp_in_vopl: endpoint@1 {
1114 reg = <1>;
1115 remote-endpoint = <&vopl_out_edp>;
1116 };
1117 };
1118 };
1119 };
1121 hdmi: hdmi@ff980000 {
1122 compatible = "rockchip,rk3288-dw-hdmi";
1123 reg = <0x0 0xff980000 0x0 0x20000>;
1124 reg-io-width = <4>;
1125 rockchip,grf = <&grf>;
1126 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1127 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1128 clock-names = "iahb", "isfr";
1129 power-domains = <&power RK3288_PD_VIO>;
1130 status = "disabled";
1132 ports {
1133 hdmi_in: port {
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1136 hdmi_in_vopb: endpoint@0 {
1137 reg = <0>;
1138 remote-endpoint = <&vopb_out_hdmi>;
1139 };
1140 hdmi_in_vopl: endpoint@1 {
1141 reg = <1>;
1142 remote-endpoint = <&vopl_out_hdmi>;
1143 };
1144 };
1145 };
1146 };
1148 vpu_mmu: iommu@ff9a0800 {
1149 compatible = "rockchip,iommu";
1150 reg = <0x0 0xff9a0800 0x0 0x100>;
1151 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1152 interrupt-names = "vpu_mmu";
1153 #iommu-cells = <0>;
1154 status = "disabled";
1155 };
1157 hevc_mmu: iommu@ff9c0440 {
1158 compatible = "rockchip,iommu";
1159 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1160 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1161 interrupt-names = "hevc_mmu";
1162 #iommu-cells = <0>;
1163 status = "disabled";
1164 };
1166 gpu: gpu@ffa30000 {
1167 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1168 reg = <0x0 0xffa30000 0x0 0x10000>;
1169 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1172 interrupt-names = "job", "mmu", "gpu";
1173 clocks = <&cru ACLK_GPU>;
1174 operating-points-v2 = <&gpu_opp_table>;
1175 power-domains = <&power RK3288_PD_GPU>;
1176 status = "disabled";
1177 };
1179 gpu_opp_table: gpu-opp-table {
1180 compatible = "operating-points-v2";
1182 opp@100000000 {
1183 opp-hz = /bits/ 64 <100000000>;
1184 opp-microvolt = <950000>;
1185 };
1186 opp@200000000 {
1187 opp-hz = /bits/ 64 <200000000>;
1188 opp-microvolt = <950000>;
1189 };
1190 opp@300000000 {
1191 opp-hz = /bits/ 64 <300000000>;
1192 opp-microvolt = <1000000>;
1193 };
1194 opp@400000000 {
1195 opp-hz = /bits/ 64 <400000000>;
1196 opp-microvolt = <1100000>;
1197 };
1198 opp@500000000 {
1199 opp-hz = /bits/ 64 <500000000>;
1200 opp-microvolt = <1200000>;
1201 };
1202 opp@600000000 {
1203 opp-hz = /bits/ 64 <600000000>;
1204 opp-microvolt = <1250000>;
1205 };
1206 };
1208 qos_gpu_r: qos@ffaa0000 {
1209 compatible = "syscon";
1210 reg = <0x0 0xffaa0000 0x0 0x20>;
1211 };
1213 qos_gpu_w: qos@ffaa0080 {
1214 compatible = "syscon";
1215 reg = <0x0 0xffaa0080 0x0 0x20>;
1216 };
1218 qos_vio1_vop: qos@ffad0000 {
1219 compatible = "syscon";
1220 reg = <0x0 0xffad0000 0x0 0x20>;
1221 };
1223 qos_vio1_isp_w0: qos@ffad0100 {
1224 compatible = "syscon";
1225 reg = <0x0 0xffad0100 0x0 0x20>;
1226 };
1228 qos_vio1_isp_w1: qos@ffad0180 {
1229 compatible = "syscon";
1230 reg = <0x0 0xffad0180 0x0 0x20>;
1231 };
1233 qos_vio0_vop: qos@ffad0400 {
1234 compatible = "syscon";
1235 reg = <0x0 0xffad0400 0x0 0x20>;
1236 };
1238 qos_vio0_vip: qos@ffad0480 {
1239 compatible = "syscon";
1240 reg = <0x0 0xffad0480 0x0 0x20>;
1241 };
1243 qos_vio0_iep: qos@ffad0500 {
1244 compatible = "syscon";
1245 reg = <0x0 0xffad0500 0x0 0x20>;
1246 };
1248 qos_vio2_rga_r: qos@ffad0800 {
1249 compatible = "syscon";
1250 reg = <0x0 0xffad0800 0x0 0x20>;
1251 };
1253 qos_vio2_rga_w: qos@ffad0880 {
1254 compatible = "syscon";
1255 reg = <0x0 0xffad0880 0x0 0x20>;
1256 };
1258 qos_vio1_isp_r: qos@ffad0900 {
1259 compatible = "syscon";
1260 reg = <0x0 0xffad0900 0x0 0x20>;
1261 };
1263 qos_video: qos@ffae0000 {
1264 compatible = "syscon";
1265 reg = <0x0 0xffae0000 0x0 0x20>;
1266 };
1268 qos_hevc_r: qos@ffaf0000 {
1269 compatible = "syscon";
1270 reg = <0x0 0xffaf0000 0x0 0x20>;
1271 };
1273 qos_hevc_w: qos@ffaf0080 {
1274 compatible = "syscon";
1275 reg = <0x0 0xffaf0080 0x0 0x20>;
1276 };
1278 gic: interrupt-controller@ffc01000 {
1279 compatible = "arm,gic-400";
1280 interrupt-controller;
1281 #interrupt-cells = <3>;
1282 #address-cells = <0>;
1284 reg = <0x0 0xffc01000 0x0 0x1000>,
1285 <0x0 0xffc02000 0x0 0x2000>,
1286 <0x0 0xffc04000 0x0 0x2000>,
1287 <0x0 0xffc06000 0x0 0x2000>;
1288 interrupts = <GIC_PPI 9 0xf04>;
1289 };
1291 efuse: efuse@ffb40000 {
1292 compatible = "rockchip,rk3288-efuse";
1293 reg = <0x0 0xffb40000 0x0 0x20>;
1294 #address-cells = <1>;
1295 #size-cells = <1>;
1296 clocks = <&cru PCLK_EFUSE256>;
1297 clock-names = "pclk_efuse";
1299 cpu_leakage: cpu_leakage@17 {
1300 reg = <0x17 0x1>;
1301 };
1302 };
1304 pinctrl: pinctrl {
1305 compatible = "rockchip,rk3288-pinctrl";
1306 rockchip,grf = <&grf>;
1307 rockchip,pmu = <&pmu>;
1308 #address-cells = <2>;
1309 #size-cells = <2>;
1310 ranges;
1312 gpio0: gpio0@ff750000 {
1313 compatible = "rockchip,gpio-bank";
1314 reg = <0x0 0xff750000 0x0 0x100>;
1315 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1316 clocks = <&cru PCLK_GPIO0>;
1318 gpio-controller;
1319 #gpio-cells = <2>;
1321 interrupt-controller;
1322 #interrupt-cells = <2>;
1323 };
1325 gpio1: gpio1@ff780000 {
1326 compatible = "rockchip,gpio-bank";
1327 reg = <0x0 0xff780000 0x0 0x100>;
1328 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1329 clocks = <&cru PCLK_GPIO1>;
1331 gpio-controller;
1332 #gpio-cells = <2>;
1334 interrupt-controller;
1335 #interrupt-cells = <2>;
1336 };
1338 gpio2: gpio2@ff790000 {
1339 compatible = "rockchip,gpio-bank";
1340 reg = <0x0 0xff790000 0x0 0x100>;
1341 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1342 clocks = <&cru PCLK_GPIO2>;
1344 gpio-controller;
1345 #gpio-cells = <2>;
1347 interrupt-controller;
1348 #interrupt-cells = <2>;
1349 };
1351 gpio3: gpio3@ff7a0000 {
1352 compatible = "rockchip,gpio-bank";
1353 reg = <0x0 0xff7a0000 0x0 0x100>;
1354 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1355 clocks = <&cru PCLK_GPIO3>;
1357 gpio-controller;
1358 #gpio-cells = <2>;
1360 interrupt-controller;
1361 #interrupt-cells = <2>;
1362 };
1364 gpio4: gpio4@ff7b0000 {
1365 compatible = "rockchip,gpio-bank";
1366 reg = <0x0 0xff7b0000 0x0 0x100>;
1367 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1368 clocks = <&cru PCLK_GPIO4>;
1370 gpio-controller;
1371 #gpio-cells = <2>;
1373 interrupt-controller;
1374 #interrupt-cells = <2>;
1375 };
1377 gpio5: gpio5@ff7c0000 {
1378 compatible = "rockchip,gpio-bank";
1379 reg = <0x0 0xff7c0000 0x0 0x100>;
1380 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1381 clocks = <&cru PCLK_GPIO5>;
1383 gpio-controller;
1384 #gpio-cells = <2>;
1386 interrupt-controller;
1387 #interrupt-cells = <2>;
1388 };
1390 gpio6: gpio6@ff7d0000 {
1391 compatible = "rockchip,gpio-bank";
1392 reg = <0x0 0xff7d0000 0x0 0x100>;
1393 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1394 clocks = <&cru PCLK_GPIO6>;
1396 gpio-controller;
1397 #gpio-cells = <2>;
1399 interrupt-controller;
1400 #interrupt-cells = <2>;
1401 };
1403 gpio7: gpio7@ff7e0000 {
1404 compatible = "rockchip,gpio-bank";
1405 reg = <0x0 0xff7e0000 0x0 0x100>;
1406 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1407 clocks = <&cru PCLK_GPIO7>;
1409 gpio-controller;
1410 #gpio-cells = <2>;
1412 interrupt-controller;
1413 #interrupt-cells = <2>;
1414 };
1416 gpio8: gpio8@ff7f0000 {
1417 compatible = "rockchip,gpio-bank";
1418 reg = <0x0 0xff7f0000 0x0 0x100>;
1419 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1420 clocks = <&cru PCLK_GPIO8>;
1422 gpio-controller;
1423 #gpio-cells = <2>;
1425 interrupt-controller;
1426 #interrupt-cells = <2>;
1427 };
1429 hdmi {
1430 hdmi_ddc: hdmi-ddc {
1431 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1432 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1433 };
1434 };
1436 pcfg_pull_up: pcfg-pull-up {
1437 bias-pull-up;
1438 };
1440 pcfg_pull_down: pcfg-pull-down {
1441 bias-pull-down;
1442 };
1444 pcfg_pull_none: pcfg-pull-none {
1445 bias-disable;
1446 };
1448 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1449 bias-disable;
1450 drive-strength = <12>;
1451 };
1453 sleep {
1454 global_pwroff: global-pwroff {
1455 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1456 };
1458 ddrio_pwroff: ddrio-pwroff {
1459 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1460 };
1462 ddr0_retention: ddr0-retention {
1463 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1464 };
1466 ddr1_retention: ddr1-retention {
1467 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1468 };
1469 };
1471 edp {
1472 edp_hpd: edp-hpd {
1473 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1474 };
1475 };
1477 i2c0 {
1478 i2c0_xfer: i2c0-xfer {
1479 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1480 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1481 };
1482 };
1484 i2c1 {
1485 i2c1_xfer: i2c1-xfer {
1486 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1487 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1488 };
1489 };
1491 i2c2 {
1492 i2c2_xfer: i2c2-xfer {
1493 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1494 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1495 };
1496 };
1498 i2c3 {
1499 i2c3_xfer: i2c3-xfer {
1500 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1501 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1502 };
1503 };
1505 i2c4 {
1506 i2c4_xfer: i2c4-xfer {
1507 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1508 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1509 };
1510 };
1512 i2c5 {
1513 i2c5_xfer: i2c5-xfer {
1514 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1515 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1516 };
1517 };
1519 i2s0 {
1520 i2s0_bus: i2s0-bus {
1521 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1522 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1523 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1524 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1525 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1526 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1527 };
1528 };
1530 sdmmc {
1531 sdmmc_clk: sdmmc-clk {
1532 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1533 };
1535 sdmmc_cmd: sdmmc-cmd {
1536 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1537 };
1539 sdmmc_cd: sdmmc-cd {
1540 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1541 };
1543 sdmmc_bus1: sdmmc-bus1 {
1544 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1545 };
1547 sdmmc_bus4: sdmmc-bus4 {
1548 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1549 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1550 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1551 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1552 };
1553 };
1555 sdio0 {
1556 sdio0_bus1: sdio0-bus1 {
1557 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1558 };
1560 sdio0_bus4: sdio0-bus4 {
1561 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1562 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1563 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1564 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1565 };
1567 sdio0_cmd: sdio0-cmd {
1568 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1569 };
1571 sdio0_clk: sdio0-clk {
1572 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1573 };
1575 sdio0_cd: sdio0-cd {
1576 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1577 };
1579 sdio0_wp: sdio0-wp {
1580 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1581 };
1583 sdio0_pwr: sdio0-pwr {
1584 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1585 };
1587 sdio0_bkpwr: sdio0-bkpwr {
1588 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1589 };
1591 sdio0_int: sdio0-int {
1592 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1593 };
1594 };
1596 sdio1 {
1597 sdio1_bus1: sdio1-bus1 {
1598 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1599 };
1601 sdio1_bus4: sdio1-bus4 {
1602 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1603 <3 25 4 &pcfg_pull_up>,
1604 <3 26 4 &pcfg_pull_up>,
1605 <3 27 4 &pcfg_pull_up>;
1606 };
1608 sdio1_cd: sdio1-cd {
1609 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1610 };
1612 sdio1_wp: sdio1-wp {
1613 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1614 };
1616 sdio1_bkpwr: sdio1-bkpwr {
1617 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1618 };
1620 sdio1_int: sdio1-int {
1621 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1622 };
1624 sdio1_cmd: sdio1-cmd {
1625 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1626 };
1628 sdio1_clk: sdio1-clk {
1629 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1630 };
1632 sdio1_pwr: sdio1-pwr {
1633 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1634 };
1635 };
1637 emmc {
1638 emmc_clk: emmc-clk {
1639 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1640 };
1642 emmc_cmd: emmc-cmd {
1643 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1644 };
1646 emmc_pwr: emmc-pwr {
1647 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1648 };
1650 emmc_bus1: emmc-bus1 {
1651 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1652 };
1654 emmc_bus4: emmc-bus4 {
1655 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1656 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1657 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1658 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1659 };
1661 emmc_bus8: emmc-bus8 {
1662 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1663 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1664 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1665 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1666 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1667 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1668 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1669 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1670 };
1671 };
1673 spi0 {
1674 spi0_clk: spi0-clk {
1675 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1676 };
1677 spi0_cs0: spi0-cs0 {
1678 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1679 };
1680 spi0_tx: spi0-tx {
1681 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1682 };
1683 spi0_rx: spi0-rx {
1684 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1685 };
1686 spi0_cs1: spi0-cs1 {
1687 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1688 };
1689 };
1690 spi1 {
1691 spi1_clk: spi1-clk {
1692 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1693 };
1694 spi1_cs0: spi1-cs0 {
1695 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1696 };
1697 spi1_rx: spi1-rx {
1698 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1699 };
1700 spi1_tx: spi1-tx {
1701 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1702 };
1703 };
1705 spi2 {
1706 spi2_cs1: spi2-cs1 {
1707 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1708 };
1709 spi2_clk: spi2-clk {
1710 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1711 };
1712 spi2_cs0: spi2-cs0 {
1713 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1714 };
1715 spi2_rx: spi2-rx {
1716 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1717 };
1718 spi2_tx: spi2-tx {
1719 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1720 };
1721 };
1723 uart0 {
1724 uart0_xfer: uart0-xfer {
1725 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1726 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1727 };
1729 uart0_cts: uart0-cts {
1730 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1731 };
1733 uart0_rts: uart0-rts {
1734 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1735 };
1736 };
1738 uart1 {
1739 uart1_xfer: uart1-xfer {
1740 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1741 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1742 };
1744 uart1_cts: uart1-cts {
1745 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1746 };
1748 uart1_rts: uart1-rts {
1749 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1750 };
1751 };
1753 uart2 {
1754 uart2_xfer: uart2-xfer {
1755 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1756 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1757 };
1758 /* no rts / cts for uart2 */
1759 };
1761 uart3 {
1762 uart3_xfer: uart3-xfer {
1763 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1764 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1765 };
1767 uart3_cts: uart3-cts {
1768 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1769 };
1771 uart3_rts: uart3-rts {
1772 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1773 };
1774 };
1776 uart4 {
1777 uart4_xfer: uart4-xfer {
1778 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1779 <5 13 3 &pcfg_pull_none>;
1780 };
1782 uart4_cts: uart4-cts {
1783 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1784 };
1786 uart4_rts: uart4-rts {
1787 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1788 };
1789 };
1791 tsadc {
1792 otp_gpio: otp-gpio {
1793 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1794 };
1796 otp_out: otp-out {
1797 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1798 };
1799 };
1801 pwm0 {
1802 pwm0_pin: pwm0-pin {
1803 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1804 };
1805 };
1807 pwm1 {
1808 pwm1_pin: pwm1-pin {
1809 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1810 };
1811 };
1813 pwm2 {
1814 pwm2_pin: pwm2-pin {
1815 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1816 };
1817 };
1819 pwm3 {
1820 pwm3_pin: pwm3-pin {
1821 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1822 };
1823 };
1825 gmac {
1826 rgmii_pins: rgmii-pins {
1827 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1828 <3 31 3 &pcfg_pull_none>,
1829 <3 26 3 &pcfg_pull_none>,
1830 <3 27 3 &pcfg_pull_none>,
1831 <3 28 3 &pcfg_pull_none_12ma>,
1832 <3 29 3 &pcfg_pull_none_12ma>,
1833 <3 24 3 &pcfg_pull_none_12ma>,
1834 <3 25 3 &pcfg_pull_none_12ma>,
1835 <4 0 3 &pcfg_pull_none>,
1836 <4 5 3 &pcfg_pull_none>,
1837 <4 6 3 &pcfg_pull_none>,
1838 <4 9 3 &pcfg_pull_none_12ma>,
1839 <4 4 3 &pcfg_pull_none_12ma>,
1840 <4 1 3 &pcfg_pull_none>,
1841 <4 3 3 &pcfg_pull_none>;
1842 };
1844 rmii_pins: rmii-pins {
1845 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1846 <3 31 3 &pcfg_pull_none>,
1847 <3 28 3 &pcfg_pull_none>,
1848 <3 29 3 &pcfg_pull_none>,
1849 <4 0 3 &pcfg_pull_none>,
1850 <4 5 3 &pcfg_pull_none>,
1851 <4 4 3 &pcfg_pull_none>,
1852 <4 1 3 &pcfg_pull_none>,
1853 <4 2 3 &pcfg_pull_none>,
1854 <4 3 3 &pcfg_pull_none>;
1855 };
1856 };
1858 spdif {
1859 spdif_tx: spdif-tx {
1860 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1861 };
1862 };
1863 };
1864 };