| blob | b147cb0dc14b26ce92db7ea70bba2a8f77bd0d38 |
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
51 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53 / {
54 interrupt-parent = <&gic>;
56 aliases {
57 ethernet0 = &gmac;
58 };
60 chosen {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
65 simplefb_hdmi: framebuffer@0 {
66 compatible = "allwinner,simple-framebuffer",
67 "simple-framebuffer";
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
73 status = "disabled";
74 };
76 simplefb_lcd: framebuffer@1 {
77 compatible = "allwinner,simple-framebuffer",
78 "simple-framebuffer";
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
83 status = "disabled";
84 };
85 };
87 timer {
88 compatible = "arm,armv7-timer";
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
93 clock-frequency = <24000000>;
94 arm,cpu-registers-not-fw-configured;
95 };
97 cpus {
98 enable-method = "allwinner,sun6i-a31";
99 #address-cells = <1>;
100 #size-cells = <0>;
102 cpu0: cpu@0 {
103 compatible = "arm,cortex-a7";
104 device_type = "cpu";
105 reg = <0>;
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
108 operating-points = <
109 /* kHz uV */
110 1008000 1200000
111 864000 1200000
112 720000 1100000
113 480000 1000000
114 >;
115 #cooling-cells = <2>;
116 cooling-min-level = <0>;
117 cooling-max-level = <3>;
118 };
120 cpu@1 {
121 compatible = "arm,cortex-a7";
122 device_type = "cpu";
123 reg = <1>;
124 };
126 cpu@2 {
127 compatible = "arm,cortex-a7";
128 device_type = "cpu";
129 reg = <2>;
130 };
132 cpu@3 {
133 compatible = "arm,cortex-a7";
134 device_type = "cpu";
135 reg = <3>;
136 };
137 };
139 thermal-zones {
140 cpu_thermal {
141 /* milliseconds */
142 polling-delay-passive = <250>;
143 polling-delay = <1000>;
144 thermal-sensors = <&rtp>;
146 cooling-maps {
147 map0 {
148 trip = <&cpu_alert0>;
149 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
150 };
151 };
153 trips {
154 cpu_alert0: cpu_alert0 {
155 /* milliCelsius */
156 temperature = <70000>;
157 hysteresis = <2000>;
158 type = "passive";
159 };
161 cpu_crit: cpu_crit {
162 /* milliCelsius */
163 temperature = <100000>;
164 hysteresis = <2000>;
165 type = "critical";
166 };
167 };
168 };
169 };
171 memory {
172 reg = <0x40000000 0x80000000>;
173 };
175 pmu {
176 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
177 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
181 };
183 clocks {
184 #address-cells = <1>;
185 #size-cells = <1>;
186 ranges;
188 osc24M: osc24M {
189 #clock-cells = <0>;
190 compatible = "fixed-clock";
191 clock-frequency = <24000000>;
192 };
194 osc32k: clk@0 {
195 #clock-cells = <0>;
196 compatible = "fixed-clock";
197 clock-frequency = <32768>;
198 clock-output-names = "osc32k";
199 };
201 /*
202 * The following two are dummy clocks, placeholders
203 * used in the gmac_tx clock. The gmac driver will
204 * choose one parent depending on the PHY interface
205 * mode, using clk_set_rate auto-reparenting.
206 *
207 * The actual TX clock rate is not controlled by the
208 * gmac_tx clock.
209 */
210 mii_phy_tx_clk: clk@1 {
211 #clock-cells = <0>;
212 compatible = "fixed-clock";
213 clock-frequency = <25000000>;
214 clock-output-names = "mii_phy_tx";
215 };
217 gmac_int_tx_clk: clk@2 {
218 #clock-cells = <0>;
219 compatible = "fixed-clock";
220 clock-frequency = <125000000>;
221 clock-output-names = "gmac_int_tx";
222 };
224 gmac_tx_clk: clk@01c200d0 {
225 #clock-cells = <0>;
226 compatible = "allwinner,sun7i-a20-gmac-clk";
227 reg = <0x01c200d0 0x4>;
228 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
229 clock-output-names = "gmac_tx";
230 };
231 };
233 de: display-engine {
234 compatible = "allwinner,sun6i-a31-display-engine";
235 allwinner,pipelines = <&fe0>, <&fe1>;
236 status = "disabled";
237 };
239 soc@01c00000 {
240 compatible = "simple-bus";
241 #address-cells = <1>;
242 #size-cells = <1>;
243 ranges;
245 dma: dma-controller@01c02000 {
246 compatible = "allwinner,sun6i-a31-dma";
247 reg = <0x01c02000 0x1000>;
248 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&ccu CLK_AHB1_DMA>;
250 resets = <&ccu RST_AHB1_DMA>;
251 #dma-cells = <1>;
252 };
254 tcon0: lcd-controller@01c0c000 {
255 compatible = "allwinner,sun6i-a31-tcon";
256 reg = <0x01c0c000 0x1000>;
257 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
258 resets = <&ccu RST_AHB1_LCD0>;
259 reset-names = "lcd";
260 clocks = <&ccu CLK_AHB1_LCD0>,
261 <&ccu CLK_LCD0_CH0>,
262 <&ccu CLK_LCD0_CH1>;
263 clock-names = "ahb",
264 "tcon-ch0",
265 "tcon-ch1";
266 clock-output-names = "tcon0-pixel-clock";
268 ports {
269 #address-cells = <1>;
270 #size-cells = <0>;
272 tcon0_in: port@0 {
273 #address-cells = <1>;
274 #size-cells = <0>;
275 reg = <0>;
277 tcon0_in_drc0: endpoint@0 {
278 reg = <0>;
279 remote-endpoint = <&drc0_out_tcon0>;
280 };
281 };
283 tcon0_out: port@1 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 reg = <1>;
287 };
288 };
289 };
291 tcon1: lcd-controller@01c0d000 {
292 compatible = "allwinner,sun6i-a31-tcon";
293 reg = <0x01c0d000 0x1000>;
294 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
295 resets = <&ccu RST_AHB1_LCD1>;
296 reset-names = "lcd";
297 clocks = <&ccu CLK_AHB1_LCD1>,
298 <&ccu CLK_LCD1_CH0>,
299 <&ccu CLK_LCD1_CH1>;
300 clock-names = "ahb",
301 "tcon-ch0",
302 "tcon-ch1";
303 clock-output-names = "tcon1-pixel-clock";
305 ports {
306 #address-cells = <1>;
307 #size-cells = <0>;
309 tcon1_in: port@0 {
310 #address-cells = <1>;
311 #size-cells = <0>;
312 reg = <0>;
314 tcon1_in_drc1: endpoint@0 {
315 reg = <0>;
316 remote-endpoint = <&drc1_out_tcon1>;
317 };
318 };
320 tcon1_out: port@1 {
321 #address-cells = <1>;
322 #size-cells = <0>;
323 reg = <1>;
324 };
325 };
326 };
328 mmc0: mmc@01c0f000 {
329 compatible = "allwinner,sun7i-a20-mmc";
330 reg = <0x01c0f000 0x1000>;
331 clocks = <&ccu CLK_AHB1_MMC0>,
332 <&ccu CLK_MMC0>,
333 <&ccu CLK_MMC0_OUTPUT>,
334 <&ccu CLK_MMC0_SAMPLE>;
335 clock-names = "ahb",
336 "mmc",
337 "output",
338 "sample";
339 resets = <&ccu RST_AHB1_MMC0>;
340 reset-names = "ahb";
341 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
342 status = "disabled";
343 #address-cells = <1>;
344 #size-cells = <0>;
345 };
347 mmc1: mmc@01c10000 {
348 compatible = "allwinner,sun7i-a20-mmc";
349 reg = <0x01c10000 0x1000>;
350 clocks = <&ccu CLK_AHB1_MMC1>,
351 <&ccu CLK_MMC1>,
352 <&ccu CLK_MMC1_OUTPUT>,
353 <&ccu CLK_MMC1_SAMPLE>;
354 clock-names = "ahb",
355 "mmc",
356 "output",
357 "sample";
358 resets = <&ccu RST_AHB1_MMC1>;
359 reset-names = "ahb";
360 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
361 status = "disabled";
362 #address-cells = <1>;
363 #size-cells = <0>;
364 };
366 mmc2: mmc@01c11000 {
367 compatible = "allwinner,sun7i-a20-mmc";
368 reg = <0x01c11000 0x1000>;
369 clocks = <&ccu CLK_AHB1_MMC2>,
370 <&ccu CLK_MMC2>,
371 <&ccu CLK_MMC2_OUTPUT>,
372 <&ccu CLK_MMC2_SAMPLE>;
373 clock-names = "ahb",
374 "mmc",
375 "output",
376 "sample";
377 resets = <&ccu RST_AHB1_MMC2>;
378 reset-names = "ahb";
379 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
380 status = "disabled";
381 #address-cells = <1>;
382 #size-cells = <0>;
383 };
385 mmc3: mmc@01c12000 {
386 compatible = "allwinner,sun7i-a20-mmc";
387 reg = <0x01c12000 0x1000>;
388 clocks = <&ccu CLK_AHB1_MMC3>,
389 <&ccu CLK_MMC3>,
390 <&ccu CLK_MMC3_OUTPUT>,
391 <&ccu CLK_MMC3_SAMPLE>;
392 clock-names = "ahb",
393 "mmc",
394 "output",
395 "sample";
396 resets = <&ccu RST_AHB1_MMC3>;
397 reset-names = "ahb";
398 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
399 status = "disabled";
400 #address-cells = <1>;
401 #size-cells = <0>;
402 };
404 usb_otg: usb@01c19000 {
405 compatible = "allwinner,sun6i-a31-musb";
406 reg = <0x01c19000 0x0400>;
407 clocks = <&ccu CLK_AHB1_OTG>;
408 resets = <&ccu RST_AHB1_OTG>;
409 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
410 interrupt-names = "mc";
411 phys = <&usbphy 0>;
412 phy-names = "usb";
413 extcon = <&usbphy 0>;
414 status = "disabled";
415 };
417 usbphy: phy@01c19400 {
418 compatible = "allwinner,sun6i-a31-usb-phy";
419 reg = <0x01c19400 0x10>,
420 <0x01c1a800 0x4>,
421 <0x01c1b800 0x4>;
422 reg-names = "phy_ctrl",
423 "pmu1",
424 "pmu2";
425 clocks = <&ccu CLK_USB_PHY0>,
426 <&ccu CLK_USB_PHY1>,
427 <&ccu CLK_USB_PHY2>;
428 clock-names = "usb0_phy",
429 "usb1_phy",
430 "usb2_phy";
431 resets = <&ccu RST_USB_PHY0>,
432 <&ccu RST_USB_PHY1>,
433 <&ccu RST_USB_PHY2>;
434 reset-names = "usb0_reset",
435 "usb1_reset",
436 "usb2_reset";
437 status = "disabled";
438 #phy-cells = <1>;
439 };
441 ehci0: usb@01c1a000 {
442 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
443 reg = <0x01c1a000 0x100>;
444 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&ccu CLK_AHB1_EHCI0>;
446 resets = <&ccu RST_AHB1_EHCI0>;
447 phys = <&usbphy 1>;
448 phy-names = "usb";
449 status = "disabled";
450 };
452 ohci0: usb@01c1a400 {
453 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
454 reg = <0x01c1a400 0x100>;
455 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
457 resets = <&ccu RST_AHB1_OHCI0>;
458 phys = <&usbphy 1>;
459 phy-names = "usb";
460 status = "disabled";
461 };
463 ehci1: usb@01c1b000 {
464 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
465 reg = <0x01c1b000 0x100>;
466 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&ccu CLK_AHB1_EHCI1>;
468 resets = <&ccu RST_AHB1_EHCI1>;
469 phys = <&usbphy 2>;
470 phy-names = "usb";
471 status = "disabled";
472 };
474 ohci1: usb@01c1b400 {
475 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
476 reg = <0x01c1b400 0x100>;
477 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
479 resets = <&ccu RST_AHB1_OHCI1>;
480 phys = <&usbphy 2>;
481 phy-names = "usb";
482 status = "disabled";
483 };
485 ohci2: usb@01c1c400 {
486 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
487 reg = <0x01c1c400 0x100>;
488 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
490 resets = <&ccu RST_AHB1_OHCI2>;
491 status = "disabled";
492 };
494 ccu: clock@01c20000 {
495 compatible = "allwinner,sun6i-a31-ccu";
496 reg = <0x01c20000 0x400>;
497 clocks = <&osc24M>, <&osc32k>;
498 clock-names = "hosc", "losc";
499 #clock-cells = <1>;
500 #reset-cells = <1>;
501 };
503 pio: pinctrl@01c20800 {
504 compatible = "allwinner,sun6i-a31-pinctrl";
505 reg = <0x01c20800 0x400>;
506 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
511 clock-names = "apb", "hosc", "losc";
512 gpio-controller;
513 interrupt-controller;
514 #interrupt-cells = <3>;
515 #gpio-cells = <3>;
517 gmac_pins_gmii_a: gmac_gmii@0 {
518 pins = "PA0", "PA1", "PA2", "PA3",
519 "PA4", "PA5", "PA6", "PA7",
520 "PA8", "PA9", "PA10", "PA11",
521 "PA12", "PA13", "PA14", "PA15",
522 "PA16", "PA17", "PA18", "PA19",
523 "PA20", "PA21", "PA22", "PA23",
524 "PA24", "PA25", "PA26", "PA27";
525 function = "gmac";
526 /*
527 * data lines in GMII mode run at 125MHz and
528 * might need a higher signal drive strength
529 */
530 drive-strength = <30>;
531 };
533 gmac_pins_mii_a: gmac_mii@0 {
534 pins = "PA0", "PA1", "PA2", "PA3",
535 "PA8", "PA9", "PA11",
536 "PA12", "PA13", "PA14", "PA19",
537 "PA20", "PA21", "PA22", "PA23",
538 "PA24", "PA26", "PA27";
539 function = "gmac";
540 };
542 gmac_pins_rgmii_a: gmac_rgmii@0 {
543 pins = "PA0", "PA1", "PA2", "PA3",
544 "PA9", "PA10", "PA11",
545 "PA12", "PA13", "PA14", "PA19",
546 "PA20", "PA25", "PA26", "PA27";
547 function = "gmac";
548 /*
549 * data lines in RGMII mode use DDR mode
550 * and need a higher signal drive strength
551 */
552 drive-strength = <40>;
553 };
555 i2c0_pins_a: i2c0@0 {
556 pins = "PH14", "PH15";
557 function = "i2c0";
558 };
560 i2c1_pins_a: i2c1@0 {
561 pins = "PH16", "PH17";
562 function = "i2c1";
563 };
565 i2c2_pins_a: i2c2@0 {
566 pins = "PH18", "PH19";
567 function = "i2c2";
568 };
570 lcd0_rgb888_pins: lcd0_rgb888 {
571 pins = "PD0", "PD1", "PD2", "PD3",
572 "PD4", "PD5", "PD6", "PD7",
573 "PD8", "PD9", "PD10", "PD11",
574 "PD12", "PD13", "PD14", "PD15",
575 "PD16", "PD17", "PD18", "PD19",
576 "PD20", "PD21", "PD22", "PD23",
577 "PD24", "PD25", "PD26", "PD27";
578 function = "lcd0";
579 };
581 mmc0_pins_a: mmc0@0 {
582 pins = "PF0", "PF1", "PF2",
583 "PF3", "PF4", "PF5";
584 function = "mmc0";
585 drive-strength = <30>;
586 bias-pull-up;
587 };
589 mmc1_pins_a: mmc1@0 {
590 pins = "PG0", "PG1", "PG2", "PG3",
591 "PG4", "PG5";
592 function = "mmc1";
593 drive-strength = <30>;
594 bias-pull-up;
595 };
597 mmc2_pins_a: mmc2@0 {
598 pins = "PC6", "PC7", "PC8", "PC9",
599 "PC10", "PC11";
600 function = "mmc2";
601 drive-strength = <30>;
602 bias-pull-up;
603 };
605 mmc2_8bit_emmc_pins: mmc2@1 {
606 pins = "PC6", "PC7", "PC8", "PC9",
607 "PC10", "PC11", "PC12",
608 "PC13", "PC14", "PC15",
609 "PC24";
610 function = "mmc2";
611 drive-strength = <30>;
612 bias-pull-up;
613 };
615 mmc3_8bit_emmc_pins: mmc3@1 {
616 pins = "PC6", "PC7", "PC8", "PC9",
617 "PC10", "PC11", "PC12",
618 "PC13", "PC14", "PC15",
619 "PC24";
620 function = "mmc3";
621 drive-strength = <40>;
622 bias-pull-up;
623 };
625 spdif_pins_a: spdif@0 {
626 pins = "PH28";
627 function = "spdif";
628 };
630 uart0_pins_a: uart0@0 {
631 pins = "PH20", "PH21";
632 function = "uart0";
633 };
634 };
636 timer@01c20c00 {
637 compatible = "allwinner,sun4i-a10-timer";
638 reg = <0x01c20c00 0xa0>;
639 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&osc24M>;
645 };
647 wdt1: watchdog@01c20ca0 {
648 compatible = "allwinner,sun6i-a31-wdt";
649 reg = <0x01c20ca0 0x20>;
650 };
652 spdif: spdif@01c21000 {
653 #sound-dai-cells = <0>;
654 compatible = "allwinner,sun6i-a31-spdif";
655 reg = <0x01c21000 0x400>;
656 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
658 resets = <&ccu RST_APB1_SPDIF>;
659 clock-names = "apb", "spdif";
660 dmas = <&dma 2>, <&dma 2>;
661 dma-names = "rx", "tx";
662 status = "disabled";
663 };
665 lradc: lradc@01c22800 {
666 compatible = "allwinner,sun4i-a10-lradc-keys";
667 reg = <0x01c22800 0x100>;
668 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
669 status = "disabled";
670 };
672 rtp: rtp@01c25000 {
673 compatible = "allwinner,sun6i-a31-ts";
674 reg = <0x01c25000 0x100>;
675 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
676 #thermal-sensor-cells = <0>;
677 };
679 uart0: serial@01c28000 {
680 compatible = "snps,dw-apb-uart";
681 reg = <0x01c28000 0x400>;
682 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
683 reg-shift = <2>;
684 reg-io-width = <4>;
685 clocks = <&ccu CLK_APB2_UART0>;
686 resets = <&ccu RST_APB2_UART0>;
687 dmas = <&dma 6>, <&dma 6>;
688 dma-names = "rx", "tx";
689 status = "disabled";
690 };
692 uart1: serial@01c28400 {
693 compatible = "snps,dw-apb-uart";
694 reg = <0x01c28400 0x400>;
695 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
696 reg-shift = <2>;
697 reg-io-width = <4>;
698 clocks = <&ccu CLK_APB2_UART1>;
699 resets = <&ccu RST_APB2_UART1>;
700 dmas = <&dma 7>, <&dma 7>;
701 dma-names = "rx", "tx";
702 status = "disabled";
703 };
705 uart2: serial@01c28800 {
706 compatible = "snps,dw-apb-uart";
707 reg = <0x01c28800 0x400>;
708 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
709 reg-shift = <2>;
710 reg-io-width = <4>;
711 clocks = <&ccu CLK_APB2_UART2>;
712 resets = <&ccu RST_APB2_UART2>;
713 dmas = <&dma 8>, <&dma 8>;
714 dma-names = "rx", "tx";
715 status = "disabled";
716 };
718 uart3: serial@01c28c00 {
719 compatible = "snps,dw-apb-uart";
720 reg = <0x01c28c00 0x400>;
721 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
722 reg-shift = <2>;
723 reg-io-width = <4>;
724 clocks = <&ccu CLK_APB2_UART3>;
725 resets = <&ccu RST_APB2_UART3>;
726 dmas = <&dma 9>, <&dma 9>;
727 dma-names = "rx", "tx";
728 status = "disabled";
729 };
731 uart4: serial@01c29000 {
732 compatible = "snps,dw-apb-uart";
733 reg = <0x01c29000 0x400>;
734 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
735 reg-shift = <2>;
736 reg-io-width = <4>;
737 clocks = <&ccu CLK_APB2_UART4>;
738 resets = <&ccu RST_APB2_UART4>;
739 dmas = <&dma 10>, <&dma 10>;
740 dma-names = "rx", "tx";
741 status = "disabled";
742 };
744 uart5: serial@01c29400 {
745 compatible = "snps,dw-apb-uart";
746 reg = <0x01c29400 0x400>;
747 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
748 reg-shift = <2>;
749 reg-io-width = <4>;
750 clocks = <&ccu CLK_APB2_UART5>;
751 resets = <&ccu RST_APB2_UART5>;
752 dmas = <&dma 22>, <&dma 22>;
753 dma-names = "rx", "tx";
754 status = "disabled";
755 };
757 i2c0: i2c@01c2ac00 {
758 compatible = "allwinner,sun6i-a31-i2c";
759 reg = <0x01c2ac00 0x400>;
760 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&ccu CLK_APB2_I2C0>;
762 resets = <&ccu RST_APB2_I2C0>;
763 status = "disabled";
764 #address-cells = <1>;
765 #size-cells = <0>;
766 };
768 i2c1: i2c@01c2b000 {
769 compatible = "allwinner,sun6i-a31-i2c";
770 reg = <0x01c2b000 0x400>;
771 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&ccu CLK_APB2_I2C1>;
773 resets = <&ccu RST_APB2_I2C1>;
774 status = "disabled";
775 #address-cells = <1>;
776 #size-cells = <0>;
777 };
779 i2c2: i2c@01c2b400 {
780 compatible = "allwinner,sun6i-a31-i2c";
781 reg = <0x01c2b400 0x400>;
782 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&ccu CLK_APB2_I2C2>;
784 resets = <&ccu RST_APB2_I2C2>;
785 status = "disabled";
786 #address-cells = <1>;
787 #size-cells = <0>;
788 };
790 i2c3: i2c@01c2b800 {
791 compatible = "allwinner,sun6i-a31-i2c";
792 reg = <0x01c2b800 0x400>;
793 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&ccu CLK_APB2_I2C3>;
795 resets = <&ccu RST_APB2_I2C3>;
796 status = "disabled";
797 #address-cells = <1>;
798 #size-cells = <0>;
799 };
801 gmac: ethernet@01c30000 {
802 compatible = "allwinner,sun7i-a20-gmac";
803 reg = <0x01c30000 0x1054>;
804 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
805 interrupt-names = "macirq";
806 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
807 clock-names = "stmmaceth", "allwinner_gmac_tx";
808 resets = <&ccu RST_AHB1_EMAC>;
809 reset-names = "stmmaceth";
810 snps,pbl = <2>;
811 snps,fixed-burst;
812 snps,force_sf_dma_mode;
813 status = "disabled";
814 #address-cells = <1>;
815 #size-cells = <0>;
816 };
818 crypto: crypto-engine@01c15000 {
819 compatible = "allwinner,sun6i-a31-crypto",
820 "allwinner,sun4i-a10-crypto";
821 reg = <0x01c15000 0x1000>;
822 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
824 clock-names = "ahb", "mod";
825 resets = <&ccu RST_AHB1_SS>;
826 reset-names = "ahb";
827 };
829 codec: codec@01c22c00 {
830 #sound-dai-cells = <0>;
831 compatible = "allwinner,sun6i-a31-codec";
832 reg = <0x01c22c00 0x400>;
833 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
835 clock-names = "apb", "codec";
836 resets = <&ccu RST_APB1_CODEC>;
837 dmas = <&dma 15>, <&dma 15>;
838 dma-names = "rx", "tx";
839 status = "disabled";
840 };
842 timer@01c60000 {
843 compatible = "allwinner,sun6i-a31-hstimer",
844 "allwinner,sun7i-a20-hstimer";
845 reg = <0x01c60000 0x1000>;
846 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&ccu CLK_AHB1_HSTIMER>;
851 resets = <&ccu RST_AHB1_HSTIMER>;
852 };
854 spi0: spi@01c68000 {
855 compatible = "allwinner,sun6i-a31-spi";
856 reg = <0x01c68000 0x1000>;
857 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
859 clock-names = "ahb", "mod";
860 dmas = <&dma 23>, <&dma 23>;
861 dma-names = "rx", "tx";
862 resets = <&ccu RST_AHB1_SPI0>;
863 status = "disabled";
864 };
866 spi1: spi@01c69000 {
867 compatible = "allwinner,sun6i-a31-spi";
868 reg = <0x01c69000 0x1000>;
869 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
871 clock-names = "ahb", "mod";
872 dmas = <&dma 24>, <&dma 24>;
873 dma-names = "rx", "tx";
874 resets = <&ccu RST_AHB1_SPI1>;
875 status = "disabled";
876 };
878 spi2: spi@01c6a000 {
879 compatible = "allwinner,sun6i-a31-spi";
880 reg = <0x01c6a000 0x1000>;
881 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
883 clock-names = "ahb", "mod";
884 dmas = <&dma 25>, <&dma 25>;
885 dma-names = "rx", "tx";
886 resets = <&ccu RST_AHB1_SPI2>;
887 status = "disabled";
888 };
890 spi3: spi@01c6b000 {
891 compatible = "allwinner,sun6i-a31-spi";
892 reg = <0x01c6b000 0x1000>;
893 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
895 clock-names = "ahb", "mod";
896 dmas = <&dma 26>, <&dma 26>;
897 dma-names = "rx", "tx";
898 resets = <&ccu RST_AHB1_SPI3>;
899 status = "disabled";
900 };
902 gic: interrupt-controller@01c81000 {
903 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
904 reg = <0x01c81000 0x1000>,
905 <0x01c82000 0x2000>,
906 <0x01c84000 0x2000>,
907 <0x01c86000 0x2000>;
908 interrupt-controller;
909 #interrupt-cells = <3>;
910 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
911 };
913 fe0: display-frontend@01e00000 {
914 compatible = "allwinner,sun6i-a31-display-frontend";
915 reg = <0x01e00000 0x20000>;
916 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
918 <&ccu CLK_DRAM_FE0>;
919 clock-names = "ahb", "mod",
920 "ram";
921 resets = <&ccu RST_AHB1_FE0>;
923 ports {
924 #address-cells = <1>;
925 #size-cells = <0>;
927 fe0_out: port@1 {
928 #address-cells = <1>;
929 #size-cells = <0>;
930 reg = <1>;
932 fe0_out_be0: endpoint@0 {
933 reg = <0>;
934 remote-endpoint = <&be0_in_fe0>;
935 };
937 fe0_out_be1: endpoint@1 {
938 reg = <1>;
939 remote-endpoint = <&be1_in_fe0>;
940 };
941 };
942 };
943 };
945 fe1: display-frontend@01e20000 {
946 compatible = "allwinner,sun6i-a31-display-frontend";
947 reg = <0x01e20000 0x20000>;
948 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
950 <&ccu CLK_DRAM_FE1>;
951 clock-names = "ahb", "mod",
952 "ram";
953 resets = <&ccu RST_AHB1_FE1>;
955 ports {
956 #address-cells = <1>;
957 #size-cells = <0>;
959 fe1_out: port@1 {
960 #address-cells = <1>;
961 #size-cells = <0>;
962 reg = <1>;
964 fe1_out_be0: endpoint@0 {
965 reg = <0>;
966 remote-endpoint = <&be0_in_fe1>;
967 };
969 fe1_out_be1: endpoint@1 {
970 reg = <1>;
971 remote-endpoint = <&be1_in_fe1>;
972 };
973 };
974 };
975 };
977 be1: display-backend@01e40000 {
978 compatible = "allwinner,sun6i-a31-display-backend";
979 reg = <0x01e40000 0x10000>;
980 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
982 <&ccu CLK_DRAM_BE1>;
983 clock-names = "ahb", "mod",
984 "ram";
985 resets = <&ccu RST_AHB1_BE1>;
987 assigned-clocks = <&ccu CLK_BE1>;
988 assigned-clock-rates = <300000000>;
990 ports {
991 #address-cells = <1>;
992 #size-cells = <0>;
994 be1_in: port@0 {
995 #address-cells = <1>;
996 #size-cells = <0>;
997 reg = <0>;
999 be1_in_fe0: endpoint@0 {
1000 reg = <0>;
1001 remote-endpoint = <&fe0_out_be1>;
1002 };
1004 be1_in_fe1: endpoint@1 {
1005 reg = <1>;
1006 remote-endpoint = <&fe1_out_be1>;
1007 };
1008 };
1010 be1_out: port@1 {
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1013 reg = <1>;
1015 be1_out_drc1: endpoint@0 {
1016 reg = <0>;
1017 remote-endpoint = <&drc1_in_be1>;
1018 };
1019 };
1020 };
1021 };
1023 drc1: drc@01e50000 {
1024 compatible = "allwinner,sun6i-a31-drc";
1025 reg = <0x01e50000 0x10000>;
1026 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1027 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1028 <&ccu CLK_DRAM_DRC1>;
1029 clock-names = "ahb", "mod",
1030 "ram";
1031 resets = <&ccu RST_AHB1_DRC1>;
1033 assigned-clocks = <&ccu CLK_IEP_DRC1>;
1034 assigned-clock-rates = <300000000>;
1036 ports {
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1040 drc1_in: port@0 {
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 reg = <0>;
1045 drc1_in_be1: endpoint@0 {
1046 reg = <0>;
1047 remote-endpoint = <&be1_out_drc1>;
1048 };
1049 };
1051 drc1_out: port@1 {
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1054 reg = <1>;
1056 drc1_out_tcon1: endpoint@0 {
1057 reg = <0>;
1058 remote-endpoint = <&tcon1_in_drc1>;
1059 };
1060 };
1061 };
1062 };
1064 be0: display-backend@01e60000 {
1065 compatible = "allwinner,sun6i-a31-display-backend";
1066 reg = <0x01e60000 0x10000>;
1067 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1069 <&ccu CLK_DRAM_BE0>;
1070 clock-names = "ahb", "mod",
1071 "ram";
1072 resets = <&ccu RST_AHB1_BE0>;
1074 assigned-clocks = <&ccu CLK_BE0>;
1075 assigned-clock-rates = <300000000>;
1077 ports {
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1081 be0_in: port@0 {
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1084 reg = <0>;
1086 be0_in_fe0: endpoint@0 {
1087 reg = <0>;
1088 remote-endpoint = <&fe0_out_be0>;
1089 };
1091 be0_in_fe1: endpoint@1 {
1092 reg = <1>;
1093 remote-endpoint = <&fe1_out_be0>;
1094 };
1095 };
1097 be0_out: port@1 {
1098 #address-cells = <1>;
1099 #size-cells = <0>;
1100 reg = <1>;
1102 be0_out_drc0: endpoint@0 {
1103 reg = <0>;
1104 remote-endpoint = <&drc0_in_be0>;
1105 };
1106 };
1107 };
1108 };
1110 drc0: drc@01e70000 {
1111 compatible = "allwinner,sun6i-a31-drc";
1112 reg = <0x01e70000 0x10000>;
1113 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1115 <&ccu CLK_DRAM_DRC0>;
1116 clock-names = "ahb", "mod",
1117 "ram";
1118 resets = <&ccu RST_AHB1_DRC0>;
1120 assigned-clocks = <&ccu CLK_IEP_DRC0>;
1121 assigned-clock-rates = <300000000>;
1123 ports {
1124 #address-cells = <1>;
1125 #size-cells = <0>;
1127 drc0_in: port@0 {
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1130 reg = <0>;
1132 drc0_in_be0: endpoint@0 {
1133 reg = <0>;
1134 remote-endpoint = <&be0_out_drc0>;
1135 };
1136 };
1138 drc0_out: port@1 {
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1141 reg = <1>;
1143 drc0_out_tcon0: endpoint@0 {
1144 reg = <0>;
1145 remote-endpoint = <&tcon0_in_drc0>;
1146 };
1147 };
1148 };
1149 };
1151 rtc: rtc@01f00000 {
1152 compatible = "allwinner,sun6i-a31-rtc";
1153 reg = <0x01f00000 0x54>;
1154 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1156 };
1158 nmi_intc: interrupt-controller@1f00c00 {
1159 compatible = "allwinner,sun6i-a31-r-intc";
1160 interrupt-controller;
1161 #interrupt-cells = <2>;
1162 reg = <0x01f00c00 0x400>;
1163 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1164 };
1166 prcm@01f01400 {
1167 compatible = "allwinner,sun6i-a31-prcm";
1168 reg = <0x01f01400 0x200>;
1170 ar100: ar100_clk {
1171 compatible = "allwinner,sun6i-a31-ar100-clk";
1172 #clock-cells = <0>;
1173 clocks = <&osc32k>, <&osc24M>,
1174 <&ccu CLK_PLL_PERIPH>,
1175 <&ccu CLK_PLL_PERIPH>;
1176 clock-output-names = "ar100";
1177 };
1179 ahb0: ahb0_clk {
1180 compatible = "fixed-factor-clock";
1181 #clock-cells = <0>;
1182 clock-div = <1>;
1183 clock-mult = <1>;
1184 clocks = <&ar100>;
1185 clock-output-names = "ahb0";
1186 };
1188 apb0: apb0_clk {
1189 compatible = "allwinner,sun6i-a31-apb0-clk";
1190 #clock-cells = <0>;
1191 clocks = <&ahb0>;
1192 clock-output-names = "apb0";
1193 };
1195 apb0_gates: apb0_gates_clk {
1196 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1197 #clock-cells = <1>;
1198 clocks = <&apb0>;
1199 clock-output-names = "apb0_pio", "apb0_ir",
1200 "apb0_timer", "apb0_p2wi",
1201 "apb0_uart", "apb0_1wire",
1202 "apb0_i2c";
1203 };
1205 ir_clk: ir_clk {
1206 #clock-cells = <0>;
1207 compatible = "allwinner,sun4i-a10-mod0-clk";
1208 clocks = <&osc32k>, <&osc24M>;
1209 clock-output-names = "ir";
1210 };
1212 apb0_rst: apb0_rst {
1213 compatible = "allwinner,sun6i-a31-clock-reset";
1214 #reset-cells = <1>;
1215 };
1216 };
1218 cpucfg@01f01c00 {
1219 compatible = "allwinner,sun6i-a31-cpuconfig";
1220 reg = <0x01f01c00 0x300>;
1221 };
1223 ir: ir@01f02000 {
1224 compatible = "allwinner,sun5i-a13-ir";
1225 clocks = <&apb0_gates 1>, <&ir_clk>;
1226 clock-names = "apb", "ir";
1227 resets = <&apb0_rst 1>;
1228 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1229 reg = <0x01f02000 0x40>;
1230 status = "disabled";
1231 };
1233 r_pio: pinctrl@01f02c00 {
1234 compatible = "allwinner,sun6i-a31-r-pinctrl";
1235 reg = <0x01f02c00 0x400>;
1236 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1238 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1239 clock-names = "apb", "hosc", "losc";
1240 resets = <&apb0_rst 0>;
1241 gpio-controller;
1242 interrupt-controller;
1243 #interrupt-cells = <3>;
1244 #size-cells = <0>;
1245 #gpio-cells = <3>;
1247 ir_pins_a: ir@0 {
1248 pins = "PL4";
1249 function = "s_ir";
1250 };
1252 p2wi_pins: p2wi {
1253 pins = "PL0", "PL1";
1254 function = "s_p2wi";
1255 };
1256 };
1258 p2wi: i2c@01f03400 {
1259 compatible = "allwinner,sun6i-a31-p2wi";
1260 reg = <0x01f03400 0x400>;
1261 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&apb0_gates 3>;
1263 clock-frequency = <100000>;
1264 resets = <&apb0_rst 3>;
1265 pinctrl-names = "default";
1266 pinctrl-0 = <&p2wi_pins>;
1267 status = "disabled";
1268 #address-cells = <1>;
1269 #size-cells = <0>;
1270 };
1271 };
1272 };