| blob | 96bee776e1456b2e8787390bbcadbaecfb8563cd |
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
51 #include <dt-bindings/dma/sun4i-a10.h>
53 / {
54 interrupt-parent = <&gic>;
56 aliases {
57 ethernet0 = &gmac;
58 };
60 chosen {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
65 framebuffer@0 {
66 compatible = "allwinner,simple-framebuffer",
67 "simple-framebuffer";
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
70 <&ahb_gates 44>, <&de_be0_clk>,
71 <&tcon0_ch1_clk>, <&dram_gates 26>;
72 status = "disabled";
73 };
75 framebuffer@1 {
76 compatible = "allwinner,simple-framebuffer",
77 "simple-framebuffer";
78 allwinner,pipeline = "de_be0-lcd0";
79 clocks = <&ahb_gates 36>, <&ahb_gates 44>,
80 <&de_be0_clk>, <&tcon0_ch0_clk>,
81 <&dram_gates 26>;
82 status = "disabled";
83 };
85 framebuffer@2 {
86 compatible = "allwinner,simple-framebuffer",
87 "simple-framebuffer";
88 allwinner,pipeline = "de_be0-lcd0-tve0";
89 clocks = <&ahb_gates 34>, <&ahb_gates 36>,
90 <&ahb_gates 44>,
91 <&de_be0_clk>, <&tcon0_ch1_clk>,
92 <&dram_gates 5>, <&dram_gates 26>;
93 status = "disabled";
94 };
95 };
97 cpus {
98 #address-cells = <1>;
99 #size-cells = <0>;
101 cpu0: cpu@0 {
102 compatible = "arm,cortex-a7";
103 device_type = "cpu";
104 reg = <0>;
105 clocks = <&cpu>;
106 clock-latency = <244144>; /* 8 32k periods */
107 operating-points = <
108 /* kHz uV */
109 960000 1400000
110 912000 1400000
111 864000 1300000
112 720000 1200000
113 528000 1100000
114 312000 1000000
115 144000 1000000
116 >;
117 #cooling-cells = <2>;
118 cooling-min-level = <0>;
119 cooling-max-level = <6>;
120 };
122 cpu@1 {
123 compatible = "arm,cortex-a7";
124 device_type = "cpu";
125 reg = <1>;
126 };
127 };
129 thermal-zones {
130 cpu_thermal {
131 /* milliseconds */
132 polling-delay-passive = <250>;
133 polling-delay = <1000>;
134 thermal-sensors = <&rtp>;
136 cooling-maps {
137 map0 {
138 trip = <&cpu_alert0>;
139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
140 };
141 };
143 trips {
144 cpu_alert0: cpu_alert0 {
145 /* milliCelsius */
146 temperature = <75000>;
147 hysteresis = <2000>;
148 type = "passive";
149 };
151 cpu_crit: cpu_crit {
152 /* milliCelsius */
153 temperature = <100000>;
154 hysteresis = <2000>;
155 type = "critical";
156 };
157 };
158 };
159 };
161 memory {
162 reg = <0x40000000 0x80000000>;
163 };
165 timer {
166 compatible = "arm,armv7-timer";
167 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
170 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
171 };
173 pmu {
174 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
175 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
177 };
179 clocks {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 ranges;
184 osc24M: clk@01c20050 {
185 #clock-cells = <0>;
186 compatible = "allwinner,sun4i-a10-osc-clk";
187 reg = <0x01c20050 0x4>;
188 clock-frequency = <24000000>;
189 clock-output-names = "osc24M";
190 };
192 osc3M: osc3M_clk {
193 #clock-cells = <0>;
194 compatible = "fixed-factor-clock";
195 clock-div = <8>;
196 clock-mult = <1>;
197 clocks = <&osc24M>;
198 clock-output-names = "osc3M";
199 };
201 osc32k: clk@0 {
202 #clock-cells = <0>;
203 compatible = "fixed-clock";
204 clock-frequency = <32768>;
205 clock-output-names = "osc32k";
206 };
208 pll1: clk@01c20000 {
209 #clock-cells = <0>;
210 compatible = "allwinner,sun4i-a10-pll1-clk";
211 reg = <0x01c20000 0x4>;
212 clocks = <&osc24M>;
213 clock-output-names = "pll1";
214 };
216 pll2: clk@01c20008 {
217 #clock-cells = <1>;
218 compatible = "allwinner,sun4i-a10-pll2-clk";
219 reg = <0x01c20008 0x8>;
220 clocks = <&osc24M>;
221 clock-output-names = "pll2-1x", "pll2-2x",
222 "pll2-4x", "pll2-8x";
223 };
225 pll3: clk@01c20010 {
226 #clock-cells = <0>;
227 compatible = "allwinner,sun4i-a10-pll3-clk";
228 reg = <0x01c20010 0x4>;
229 clocks = <&osc3M>;
230 clock-output-names = "pll3";
231 };
233 pll3x2: pll3x2_clk {
234 #clock-cells = <0>;
235 compatible = "fixed-factor-clock";
236 clocks = <&pll3>;
237 clock-div = <1>;
238 clock-mult = <2>;
239 clock-output-names = "pll3-2x";
240 };
242 pll4: clk@01c20018 {
243 #clock-cells = <0>;
244 compatible = "allwinner,sun7i-a20-pll4-clk";
245 reg = <0x01c20018 0x4>;
246 clocks = <&osc24M>;
247 clock-output-names = "pll4";
248 };
250 pll5: clk@01c20020 {
251 #clock-cells = <1>;
252 compatible = "allwinner,sun4i-a10-pll5-clk";
253 reg = <0x01c20020 0x4>;
254 clocks = <&osc24M>;
255 clock-output-names = "pll5_ddr", "pll5_other";
256 };
258 pll6: clk@01c20028 {
259 #clock-cells = <1>;
260 compatible = "allwinner,sun4i-a10-pll6-clk";
261 reg = <0x01c20028 0x4>;
262 clocks = <&osc24M>;
263 clock-output-names = "pll6_sata", "pll6_other", "pll6",
264 "pll6_div_4";
265 };
267 pll7: clk@01c20030 {
268 #clock-cells = <0>;
269 compatible = "allwinner,sun4i-a10-pll3-clk";
270 reg = <0x01c20030 0x4>;
271 clocks = <&osc3M>;
272 clock-output-names = "pll7";
273 };
275 pll7x2: pll7x2_clk {
276 #clock-cells = <0>;
277 compatible = "fixed-factor-clock";
278 clocks = <&pll7>;
279 clock-div = <1>;
280 clock-mult = <2>;
281 clock-output-names = "pll7-2x";
282 };
284 pll8: clk@01c20040 {
285 #clock-cells = <0>;
286 compatible = "allwinner,sun7i-a20-pll4-clk";
287 reg = <0x01c20040 0x4>;
288 clocks = <&osc24M>;
289 clock-output-names = "pll8";
290 };
292 cpu: cpu@01c20054 {
293 #clock-cells = <0>;
294 compatible = "allwinner,sun4i-a10-cpu-clk";
295 reg = <0x01c20054 0x4>;
296 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
297 clock-output-names = "cpu";
298 };
300 axi: axi@01c20054 {
301 #clock-cells = <0>;
302 compatible = "allwinner,sun4i-a10-axi-clk";
303 reg = <0x01c20054 0x4>;
304 clocks = <&cpu>;
305 clock-output-names = "axi";
306 };
308 ahb: ahb@01c20054 {
309 #clock-cells = <0>;
310 compatible = "allwinner,sun5i-a13-ahb-clk";
311 reg = <0x01c20054 0x4>;
312 clocks = <&axi>, <&pll6 3>, <&pll6 1>;
313 clock-output-names = "ahb";
314 /*
315 * Use PLL6 as parent, instead of CPU/AXI
316 * which has rate changes due to cpufreq
317 */
318 assigned-clocks = <&ahb>;
319 assigned-clock-parents = <&pll6 3>;
320 };
322 ahb_gates: clk@01c20060 {
323 #clock-cells = <1>;
324 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
325 reg = <0x01c20060 0x8>;
326 clocks = <&ahb>;
327 clock-indices = <0>, <1>,
328 <2>, <3>, <4>,
329 <5>, <6>, <7>, <8>,
330 <9>, <10>, <11>, <12>,
331 <13>, <14>, <16>,
332 <17>, <18>, <20>, <21>,
333 <22>, <23>, <25>,
334 <28>, <32>, <33>, <34>,
335 <35>, <36>, <37>, <40>,
336 <41>, <42>, <43>,
337 <44>, <45>, <46>,
338 <47>, <49>, <50>,
339 <52>;
340 clock-output-names = "ahb_usb0", "ahb_ehci0",
341 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
342 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
343 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
344 "ahb_nand", "ahb_sdram", "ahb_ace",
345 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
346 "ahb_spi2", "ahb_spi3", "ahb_sata",
347 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
348 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
349 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
350 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
351 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
352 "ahb_mali";
353 };
355 apb0: apb0@01c20054 {
356 #clock-cells = <0>;
357 compatible = "allwinner,sun4i-a10-apb0-clk";
358 reg = <0x01c20054 0x4>;
359 clocks = <&ahb>;
360 clock-output-names = "apb0";
361 };
363 apb0_gates: clk@01c20068 {
364 #clock-cells = <1>;
365 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
366 reg = <0x01c20068 0x4>;
367 clocks = <&apb0>;
368 clock-indices = <0>, <1>,
369 <2>, <3>, <4>,
370 <5>, <6>, <7>,
371 <8>, <10>;
372 clock-output-names = "apb0_codec", "apb0_spdif",
373 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
374 "apb0_pio", "apb0_ir0", "apb0_ir1",
375 "apb0_i2s2", "apb0_keypad";
376 };
378 apb1: clk@01c20058 {
379 #clock-cells = <0>;
380 compatible = "allwinner,sun4i-a10-apb1-clk";
381 reg = <0x01c20058 0x4>;
382 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
383 clock-output-names = "apb1";
384 };
386 apb1_gates: clk@01c2006c {
387 #clock-cells = <1>;
388 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
389 reg = <0x01c2006c 0x4>;
390 clocks = <&apb1>;
391 clock-indices = <0>, <1>,
392 <2>, <3>, <4>,
393 <5>, <6>, <7>,
394 <15>, <16>, <17>,
395 <18>, <19>, <20>,
396 <21>, <22>, <23>;
397 clock-output-names = "apb1_i2c0", "apb1_i2c1",
398 "apb1_i2c2", "apb1_i2c3", "apb1_can",
399 "apb1_scr", "apb1_ps20", "apb1_ps21",
400 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
401 "apb1_uart2", "apb1_uart3", "apb1_uart4",
402 "apb1_uart5", "apb1_uart6", "apb1_uart7";
403 };
405 nand_clk: clk@01c20080 {
406 #clock-cells = <0>;
407 compatible = "allwinner,sun4i-a10-mod0-clk";
408 reg = <0x01c20080 0x4>;
409 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
410 clock-output-names = "nand";
411 };
413 ms_clk: clk@01c20084 {
414 #clock-cells = <0>;
415 compatible = "allwinner,sun4i-a10-mod0-clk";
416 reg = <0x01c20084 0x4>;
417 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
418 clock-output-names = "ms";
419 };
421 mmc0_clk: clk@01c20088 {
422 #clock-cells = <1>;
423 compatible = "allwinner,sun4i-a10-mmc-clk";
424 reg = <0x01c20088 0x4>;
425 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
426 clock-output-names = "mmc0",
427 "mmc0_output",
428 "mmc0_sample";
429 };
431 mmc1_clk: clk@01c2008c {
432 #clock-cells = <1>;
433 compatible = "allwinner,sun4i-a10-mmc-clk";
434 reg = <0x01c2008c 0x4>;
435 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
436 clock-output-names = "mmc1",
437 "mmc1_output",
438 "mmc1_sample";
439 };
441 mmc2_clk: clk@01c20090 {
442 #clock-cells = <1>;
443 compatible = "allwinner,sun4i-a10-mmc-clk";
444 reg = <0x01c20090 0x4>;
445 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
446 clock-output-names = "mmc2",
447 "mmc2_output",
448 "mmc2_sample";
449 };
451 mmc3_clk: clk@01c20094 {
452 #clock-cells = <1>;
453 compatible = "allwinner,sun4i-a10-mmc-clk";
454 reg = <0x01c20094 0x4>;
455 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
456 clock-output-names = "mmc3",
457 "mmc3_output",
458 "mmc3_sample";
459 };
461 ts_clk: clk@01c20098 {
462 #clock-cells = <0>;
463 compatible = "allwinner,sun4i-a10-mod0-clk";
464 reg = <0x01c20098 0x4>;
465 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
466 clock-output-names = "ts";
467 };
469 ss_clk: clk@01c2009c {
470 #clock-cells = <0>;
471 compatible = "allwinner,sun4i-a10-mod0-clk";
472 reg = <0x01c2009c 0x4>;
473 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
474 clock-output-names = "ss";
475 };
477 spi0_clk: clk@01c200a0 {
478 #clock-cells = <0>;
479 compatible = "allwinner,sun4i-a10-mod0-clk";
480 reg = <0x01c200a0 0x4>;
481 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
482 clock-output-names = "spi0";
483 };
485 spi1_clk: clk@01c200a4 {
486 #clock-cells = <0>;
487 compatible = "allwinner,sun4i-a10-mod0-clk";
488 reg = <0x01c200a4 0x4>;
489 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
490 clock-output-names = "spi1";
491 };
493 spi2_clk: clk@01c200a8 {
494 #clock-cells = <0>;
495 compatible = "allwinner,sun4i-a10-mod0-clk";
496 reg = <0x01c200a8 0x4>;
497 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
498 clock-output-names = "spi2";
499 };
501 pata_clk: clk@01c200ac {
502 #clock-cells = <0>;
503 compatible = "allwinner,sun4i-a10-mod0-clk";
504 reg = <0x01c200ac 0x4>;
505 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
506 clock-output-names = "pata";
507 };
509 ir0_clk: clk@01c200b0 {
510 #clock-cells = <0>;
511 compatible = "allwinner,sun4i-a10-mod0-clk";
512 reg = <0x01c200b0 0x4>;
513 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
514 clock-output-names = "ir0";
515 };
517 ir1_clk: clk@01c200b4 {
518 #clock-cells = <0>;
519 compatible = "allwinner,sun4i-a10-mod0-clk";
520 reg = <0x01c200b4 0x4>;
521 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
522 clock-output-names = "ir1";
523 };
525 i2s0_clk: clk@01c200b8 {
526 #clock-cells = <0>;
527 compatible = "allwinner,sun4i-a10-mod1-clk";
528 reg = <0x01c200b8 0x4>;
529 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
530 <&pll2 SUN4I_A10_PLL2_4X>,
531 <&pll2 SUN4I_A10_PLL2_2X>,
532 <&pll2 SUN4I_A10_PLL2_1X>;
533 clock-output-names = "i2s0";
534 };
536 ac97_clk: clk@01c200bc {
537 #clock-cells = <0>;
538 compatible = "allwinner,sun4i-a10-mod1-clk";
539 reg = <0x01c200bc 0x4>;
540 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
541 <&pll2 SUN4I_A10_PLL2_4X>,
542 <&pll2 SUN4I_A10_PLL2_2X>,
543 <&pll2 SUN4I_A10_PLL2_1X>;
544 clock-output-names = "ac97";
545 };
547 spdif_clk: clk@01c200c0 {
548 #clock-cells = <0>;
549 compatible = "allwinner,sun4i-a10-mod1-clk";
550 reg = <0x01c200c0 0x4>;
551 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
552 <&pll2 SUN4I_A10_PLL2_4X>,
553 <&pll2 SUN4I_A10_PLL2_2X>,
554 <&pll2 SUN4I_A10_PLL2_1X>;
555 clock-output-names = "spdif";
556 };
558 keypad_clk: clk@01c200c4 {
559 #clock-cells = <0>;
560 compatible = "allwinner,sun4i-a10-mod0-clk";
561 reg = <0x01c200c4 0x4>;
562 clocks = <&osc24M>;
563 clock-output-names = "keypad";
564 };
566 usb_clk: clk@01c200cc {
567 #clock-cells = <1>;
568 #reset-cells = <1>;
569 compatible = "allwinner,sun4i-a10-usb-clk";
570 reg = <0x01c200cc 0x4>;
571 clocks = <&pll6 1>;
572 clock-output-names = "usb_ohci0", "usb_ohci1",
573 "usb_phy";
574 };
576 spi3_clk: clk@01c200d4 {
577 #clock-cells = <0>;
578 compatible = "allwinner,sun4i-a10-mod0-clk";
579 reg = <0x01c200d4 0x4>;
580 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
581 clock-output-names = "spi3";
582 };
584 i2s1_clk: clk@01c200d8 {
585 #clock-cells = <0>;
586 compatible = "allwinner,sun4i-a10-mod1-clk";
587 reg = <0x01c200d8 0x4>;
588 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
589 <&pll2 SUN4I_A10_PLL2_4X>,
590 <&pll2 SUN4I_A10_PLL2_2X>,
591 <&pll2 SUN4I_A10_PLL2_1X>;
592 clock-output-names = "i2s1";
593 };
595 i2s2_clk: clk@01c200dc {
596 #clock-cells = <0>;
597 compatible = "allwinner,sun4i-a10-mod1-clk";
598 reg = <0x01c200dc 0x4>;
599 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
600 <&pll2 SUN4I_A10_PLL2_4X>,
601 <&pll2 SUN4I_A10_PLL2_2X>,
602 <&pll2 SUN4I_A10_PLL2_1X>;
603 clock-output-names = "i2s2";
604 };
606 dram_gates: clk@01c20100 {
607 #clock-cells = <1>;
608 compatible = "allwinner,sun4i-a10-dram-gates-clk";
609 reg = <0x01c20100 0x4>;
610 clocks = <&pll5 0>;
611 clock-indices = <0>,
612 <1>, <2>,
613 <3>,
614 <4>,
615 <5>, <6>,
616 <15>,
617 <24>, <25>,
618 <26>, <27>,
619 <28>, <29>;
620 clock-output-names = "dram_ve",
621 "dram_csi0", "dram_csi1",
622 "dram_ts",
623 "dram_tvd",
624 "dram_tve0", "dram_tve1",
625 "dram_output",
626 "dram_de_fe1", "dram_de_fe0",
627 "dram_de_be0", "dram_de_be1",
628 "dram_de_mp", "dram_ace";
629 };
631 de_be0_clk: clk@01c20104 {
632 #clock-cells = <0>;
633 #reset-cells = <0>;
634 compatible = "allwinner,sun4i-a10-display-clk";
635 reg = <0x01c20104 0x4>;
636 clocks = <&pll3>, <&pll7>, <&pll5 1>;
637 clock-output-names = "de-be0";
638 };
640 de_be1_clk: clk@01c20108 {
641 #clock-cells = <0>;
642 #reset-cells = <0>;
643 compatible = "allwinner,sun4i-a10-display-clk";
644 reg = <0x01c20108 0x4>;
645 clocks = <&pll3>, <&pll7>, <&pll5 1>;
646 clock-output-names = "de-be1";
647 };
649 de_fe0_clk: clk@01c2010c {
650 #clock-cells = <0>;
651 #reset-cells = <0>;
652 compatible = "allwinner,sun4i-a10-display-clk";
653 reg = <0x01c2010c 0x4>;
654 clocks = <&pll3>, <&pll7>, <&pll5 1>;
655 clock-output-names = "de-fe0";
656 };
658 de_fe1_clk: clk@01c20110 {
659 #clock-cells = <0>;
660 #reset-cells = <0>;
661 compatible = "allwinner,sun4i-a10-display-clk";
662 reg = <0x01c20110 0x4>;
663 clocks = <&pll3>, <&pll7>, <&pll5 1>;
664 clock-output-names = "de-fe1";
665 };
667 tcon0_ch0_clk: clk@01c20118 {
668 #clock-cells = <0>;
669 #reset-cells = <1>;
670 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
671 reg = <0x01c20118 0x4>;
672 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
673 clock-output-names = "tcon0-ch0-sclk";
675 };
677 tcon1_ch0_clk: clk@01c2011c {
678 #clock-cells = <0>;
679 #reset-cells = <1>;
680 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
681 reg = <0x01c2011c 0x4>;
682 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
683 clock-output-names = "tcon1-ch0-sclk";
685 };
687 tcon0_ch1_clk: clk@01c2012c {
688 #clock-cells = <0>;
689 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
690 reg = <0x01c2012c 0x4>;
691 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
692 clock-output-names = "tcon0-ch1-sclk";
694 };
696 tcon1_ch1_clk: clk@01c20130 {
697 #clock-cells = <0>;
698 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
699 reg = <0x01c20130 0x4>;
700 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
701 clock-output-names = "tcon1-ch1-sclk";
703 };
705 ve_clk: clk@01c2013c {
706 #clock-cells = <0>;
707 #reset-cells = <0>;
708 compatible = "allwinner,sun4i-a10-ve-clk";
709 reg = <0x01c2013c 0x4>;
710 clocks = <&pll4>;
711 clock-output-names = "ve";
712 };
714 codec_clk: clk@01c20140 {
715 #clock-cells = <0>;
716 compatible = "allwinner,sun4i-a10-codec-clk";
717 reg = <0x01c20140 0x4>;
718 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
719 clock-output-names = "codec";
720 };
722 mbus_clk: clk@01c2015c {
723 #clock-cells = <0>;
724 compatible = "allwinner,sun5i-a13-mbus-clk";
725 reg = <0x01c2015c 0x4>;
726 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
727 clock-output-names = "mbus";
728 };
730 /*
731 * The following two are dummy clocks, placeholders
732 * used in the gmac_tx clock. The gmac driver will
733 * choose one parent depending on the PHY interface
734 * mode, using clk_set_rate auto-reparenting.
735 *
736 * The actual TX clock rate is not controlled by the
737 * gmac_tx clock.
738 */
739 mii_phy_tx_clk: clk@2 {
740 #clock-cells = <0>;
741 compatible = "fixed-clock";
742 clock-frequency = <25000000>;
743 clock-output-names = "mii_phy_tx";
744 };
746 gmac_int_tx_clk: clk@3 {
747 #clock-cells = <0>;
748 compatible = "fixed-clock";
749 clock-frequency = <125000000>;
750 clock-output-names = "gmac_int_tx";
751 };
753 gmac_tx_clk: clk@01c20164 {
754 #clock-cells = <0>;
755 compatible = "allwinner,sun7i-a20-gmac-clk";
756 reg = <0x01c20164 0x4>;
757 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
758 clock-output-names = "gmac_tx";
759 };
761 /*
762 * Dummy clock used by output clocks
763 */
764 osc24M_32k: clk@1 {
765 #clock-cells = <0>;
766 compatible = "fixed-factor-clock";
767 clock-div = <750>;
768 clock-mult = <1>;
769 clocks = <&osc24M>;
770 clock-output-names = "osc24M_32k";
771 };
773 clk_out_a: clk@01c201f0 {
774 #clock-cells = <0>;
775 compatible = "allwinner,sun7i-a20-out-clk";
776 reg = <0x01c201f0 0x4>;
777 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
778 clock-output-names = "clk_out_a";
779 };
781 clk_out_b: clk@01c201f4 {
782 #clock-cells = <0>;
783 compatible = "allwinner,sun7i-a20-out-clk";
784 reg = <0x01c201f4 0x4>;
785 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
786 clock-output-names = "clk_out_b";
787 };
788 };
790 soc@01c00000 {
791 compatible = "simple-bus";
792 #address-cells = <1>;
793 #size-cells = <1>;
794 ranges;
796 sram-controller@01c00000 {
797 compatible = "allwinner,sun4i-a10-sram-controller";
798 reg = <0x01c00000 0x30>;
799 #address-cells = <1>;
800 #size-cells = <1>;
801 ranges;
803 sram_a: sram@00000000 {
804 compatible = "mmio-sram";
805 reg = <0x00000000 0xc000>;
806 #address-cells = <1>;
807 #size-cells = <1>;
808 ranges = <0 0x00000000 0xc000>;
810 emac_sram: sram-section@8000 {
811 compatible = "allwinner,sun4i-a10-sram-a3-a4";
812 reg = <0x8000 0x4000>;
813 status = "disabled";
814 };
815 };
817 sram_d: sram@00010000 {
818 compatible = "mmio-sram";
819 reg = <0x00010000 0x1000>;
820 #address-cells = <1>;
821 #size-cells = <1>;
822 ranges = <0 0x00010000 0x1000>;
824 otg_sram: sram-section@0000 {
825 compatible = "allwinner,sun4i-a10-sram-d";
826 reg = <0x0000 0x1000>;
827 status = "disabled";
828 };
829 };
830 };
832 nmi_intc: interrupt-controller@01c00030 {
833 compatible = "allwinner,sun7i-a20-sc-nmi";
834 interrupt-controller;
835 #interrupt-cells = <2>;
836 reg = <0x01c00030 0x0c>;
837 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
838 };
840 dma: dma-controller@01c02000 {
841 compatible = "allwinner,sun4i-a10-dma";
842 reg = <0x01c02000 0x1000>;
843 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&ahb_gates 6>;
845 #dma-cells = <2>;
846 };
848 nfc: nand@01c03000 {
849 compatible = "allwinner,sun4i-a10-nand";
850 reg = <0x01c03000 0x1000>;
851 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&ahb_gates 13>, <&nand_clk>;
853 clock-names = "ahb", "mod";
854 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
855 dma-names = "rxtx";
856 status = "disabled";
857 #address-cells = <1>;
858 #size-cells = <0>;
859 };
861 spi0: spi@01c05000 {
862 compatible = "allwinner,sun4i-a10-spi";
863 reg = <0x01c05000 0x1000>;
864 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&ahb_gates 20>, <&spi0_clk>;
866 clock-names = "ahb", "mod";
867 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
868 <&dma SUN4I_DMA_DEDICATED 26>;
869 dma-names = "rx", "tx";
870 status = "disabled";
871 #address-cells = <1>;
872 #size-cells = <0>;
873 num-cs = <4>;
874 };
876 spi1: spi@01c06000 {
877 compatible = "allwinner,sun4i-a10-spi";
878 reg = <0x01c06000 0x1000>;
879 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&ahb_gates 21>, <&spi1_clk>;
881 clock-names = "ahb", "mod";
882 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
883 <&dma SUN4I_DMA_DEDICATED 8>;
884 dma-names = "rx", "tx";
885 status = "disabled";
886 #address-cells = <1>;
887 #size-cells = <0>;
888 num-cs = <1>;
889 };
891 emac: ethernet@01c0b000 {
892 compatible = "allwinner,sun4i-a10-emac";
893 reg = <0x01c0b000 0x1000>;
894 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&ahb_gates 17>;
896 allwinner,sram = <&emac_sram 1>;
897 status = "disabled";
898 };
900 mdio: mdio@01c0b080 {
901 compatible = "allwinner,sun4i-a10-mdio";
902 reg = <0x01c0b080 0x14>;
903 status = "disabled";
904 #address-cells = <1>;
905 #size-cells = <0>;
906 };
908 mmc0: mmc@01c0f000 {
909 compatible = "allwinner,sun7i-a20-mmc";
910 reg = <0x01c0f000 0x1000>;
911 clocks = <&ahb_gates 8>,
912 <&mmc0_clk 0>,
913 <&mmc0_clk 1>,
914 <&mmc0_clk 2>;
915 clock-names = "ahb",
916 "mmc",
917 "output",
918 "sample";
919 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
920 status = "disabled";
921 #address-cells = <1>;
922 #size-cells = <0>;
923 };
925 mmc1: mmc@01c10000 {
926 compatible = "allwinner,sun7i-a20-mmc";
927 reg = <0x01c10000 0x1000>;
928 clocks = <&ahb_gates 9>,
929 <&mmc1_clk 0>,
930 <&mmc1_clk 1>,
931 <&mmc1_clk 2>;
932 clock-names = "ahb",
933 "mmc",
934 "output",
935 "sample";
936 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
937 status = "disabled";
938 #address-cells = <1>;
939 #size-cells = <0>;
940 };
942 mmc2: mmc@01c11000 {
943 compatible = "allwinner,sun7i-a20-mmc";
944 reg = <0x01c11000 0x1000>;
945 clocks = <&ahb_gates 10>,
946 <&mmc2_clk 0>,
947 <&mmc2_clk 1>,
948 <&mmc2_clk 2>;
949 clock-names = "ahb",
950 "mmc",
951 "output",
952 "sample";
953 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
954 status = "disabled";
955 #address-cells = <1>;
956 #size-cells = <0>;
957 };
959 mmc3: mmc@01c12000 {
960 compatible = "allwinner,sun7i-a20-mmc";
961 reg = <0x01c12000 0x1000>;
962 clocks = <&ahb_gates 11>,
963 <&mmc3_clk 0>,
964 <&mmc3_clk 1>,
965 <&mmc3_clk 2>;
966 clock-names = "ahb",
967 "mmc",
968 "output",
969 "sample";
970 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
971 status = "disabled";
972 #address-cells = <1>;
973 #size-cells = <0>;
974 };
976 usb_otg: usb@01c13000 {
977 compatible = "allwinner,sun4i-a10-musb";
978 reg = <0x01c13000 0x0400>;
979 clocks = <&ahb_gates 0>;
980 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
981 interrupt-names = "mc";
982 phys = <&usbphy 0>;
983 phy-names = "usb";
984 extcon = <&usbphy 0>;
985 allwinner,sram = <&otg_sram 1>;
986 status = "disabled";
987 };
989 usbphy: phy@01c13400 {
990 #phy-cells = <1>;
991 compatible = "allwinner,sun7i-a20-usb-phy";
992 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
993 reg-names = "phy_ctrl", "pmu1", "pmu2";
994 clocks = <&usb_clk 8>;
995 clock-names = "usb_phy";
996 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
997 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
998 status = "disabled";
999 };
1001 ehci0: usb@01c14000 {
1002 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
1003 reg = <0x01c14000 0x100>;
1004 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1005 clocks = <&ahb_gates 1>;
1006 phys = <&usbphy 1>;
1007 phy-names = "usb";
1008 status = "disabled";
1009 };
1011 ohci0: usb@01c14400 {
1012 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
1013 reg = <0x01c14400 0x100>;
1014 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&usb_clk 6>, <&ahb_gates 2>;
1016 phys = <&usbphy 1>;
1017 phy-names = "usb";
1018 status = "disabled";
1019 };
1021 crypto: crypto-engine@01c15000 {
1022 compatible = "allwinner,sun7i-a20-crypto",
1023 "allwinner,sun4i-a10-crypto";
1024 reg = <0x01c15000 0x1000>;
1025 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&ahb_gates 5>, <&ss_clk>;
1027 clock-names = "ahb", "mod";
1028 };
1030 spi2: spi@01c17000 {
1031 compatible = "allwinner,sun4i-a10-spi";
1032 reg = <0x01c17000 0x1000>;
1033 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1034 clocks = <&ahb_gates 22>, <&spi2_clk>;
1035 clock-names = "ahb", "mod";
1036 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
1037 <&dma SUN4I_DMA_DEDICATED 28>;
1038 dma-names = "rx", "tx";
1039 status = "disabled";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1042 num-cs = <1>;
1043 };
1045 ahci: sata@01c18000 {
1046 compatible = "allwinner,sun4i-a10-ahci";
1047 reg = <0x01c18000 0x1000>;
1048 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&pll6 0>, <&ahb_gates 25>;
1050 status = "disabled";
1051 };
1053 ehci1: usb@01c1c000 {
1054 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
1055 reg = <0x01c1c000 0x100>;
1056 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&ahb_gates 3>;
1058 phys = <&usbphy 2>;
1059 phy-names = "usb";
1060 status = "disabled";
1061 };
1063 ohci1: usb@01c1c400 {
1064 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
1065 reg = <0x01c1c400 0x100>;
1066 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1067 clocks = <&usb_clk 7>, <&ahb_gates 4>;
1068 phys = <&usbphy 2>;
1069 phy-names = "usb";
1070 status = "disabled";
1071 };
1073 spi3: spi@01c1f000 {
1074 compatible = "allwinner,sun4i-a10-spi";
1075 reg = <0x01c1f000 0x1000>;
1076 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1077 clocks = <&ahb_gates 23>, <&spi3_clk>;
1078 clock-names = "ahb", "mod";
1079 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
1080 <&dma SUN4I_DMA_DEDICATED 30>;
1081 dma-names = "rx", "tx";
1082 status = "disabled";
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085 num-cs = <1>;
1086 };
1088 pio: pinctrl@01c20800 {
1089 compatible = "allwinner,sun7i-a20-pinctrl";
1090 reg = <0x01c20800 0x400>;
1091 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1092 clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
1093 clock-names = "apb", "hosc", "losc";
1094 gpio-controller;
1095 interrupt-controller;
1096 #interrupt-cells = <3>;
1097 #gpio-cells = <3>;
1099 can0_pins_a: can0@0 {
1100 pins = "PH20", "PH21";
1101 function = "can";
1102 };
1104 clk_out_a_pins_a: clk_out_a@0 {
1105 pins = "PI12";
1106 function = "clk_out_a";
1107 };
1109 clk_out_b_pins_a: clk_out_b@0 {
1110 pins = "PI13";
1111 function = "clk_out_b";
1112 };
1114 emac_pins_a: emac0@0 {
1115 pins = "PA0", "PA1", "PA2",
1116 "PA3", "PA4", "PA5", "PA6",
1117 "PA7", "PA8", "PA9", "PA10",
1118 "PA11", "PA12", "PA13", "PA14",
1119 "PA15", "PA16";
1120 function = "emac";
1121 };
1123 gmac_pins_mii_a: gmac_mii@0 {
1124 pins = "PA0", "PA1", "PA2",
1125 "PA3", "PA4", "PA5", "PA6",
1126 "PA7", "PA8", "PA9", "PA10",
1127 "PA11", "PA12", "PA13", "PA14",
1128 "PA15", "PA16";
1129 function = "gmac";
1130 };
1132 gmac_pins_rgmii_a: gmac_rgmii@0 {
1133 pins = "PA0", "PA1", "PA2",
1134 "PA3", "PA4", "PA5", "PA6",
1135 "PA7", "PA8", "PA10",
1136 "PA11", "PA12", "PA13",
1137 "PA15", "PA16";
1138 function = "gmac";
1139 /*
1140 * data lines in RGMII mode use DDR mode
1141 * and need a higher signal drive strength
1142 */
1143 drive-strength = <40>;
1144 };
1146 i2c0_pins_a: i2c0@0 {
1147 pins = "PB0", "PB1";
1148 function = "i2c0";
1149 };
1151 i2c1_pins_a: i2c1@0 {
1152 pins = "PB18", "PB19";
1153 function = "i2c1";
1154 };
1156 i2c2_pins_a: i2c2@0 {
1157 pins = "PB20", "PB21";
1158 function = "i2c2";
1159 };
1161 i2c3_pins_a: i2c3@0 {
1162 pins = "PI0", "PI1";
1163 function = "i2c3";
1164 };
1166 ir0_rx_pins_a: ir0@0 {
1167 pins = "PB4";
1168 function = "ir0";
1169 };
1171 ir0_tx_pins_a: ir0@1 {
1172 pins = "PB3";
1173 function = "ir0";
1174 };
1176 ir1_rx_pins_a: ir1@0 {
1177 pins = "PB23";
1178 function = "ir1";
1179 };
1181 ir1_tx_pins_a: ir1@1 {
1182 pins = "PB22";
1183 function = "ir1";
1184 };
1186 mmc0_pins_a: mmc0@0 {
1187 pins = "PF0", "PF1", "PF2",
1188 "PF3", "PF4", "PF5";
1189 function = "mmc0";
1190 drive-strength = <30>;
1191 bias-pull-up;
1192 };
1194 mmc2_pins_a: mmc2@0 {
1195 pins = "PC6", "PC7", "PC8",
1196 "PC9", "PC10", "PC11";
1197 function = "mmc2";
1198 drive-strength = <30>;
1199 bias-pull-up;
1200 };
1202 mmc3_pins_a: mmc3@0 {
1203 pins = "PI4", "PI5", "PI6",
1204 "PI7", "PI8", "PI9";
1205 function = "mmc3";
1206 drive-strength = <30>;
1207 bias-pull-up;
1208 };
1210 ps20_pins_a: ps20@0 {
1211 pins = "PI20", "PI21";
1212 function = "ps2";
1213 };
1215 ps21_pins_a: ps21@0 {
1216 pins = "PH12", "PH13";
1217 function = "ps2";
1218 };
1220 pwm0_pins_a: pwm0@0 {
1221 pins = "PB2";
1222 function = "pwm";
1223 };
1225 pwm1_pins_a: pwm1@0 {
1226 pins = "PI3";
1227 function = "pwm";
1228 };
1230 spdif_tx_pins_a: spdif@0 {
1231 pins = "PB13";
1232 function = "spdif";
1233 bias-pull-up;
1234 };
1236 spi0_pins_a: spi0@0 {
1237 pins = "PI11", "PI12", "PI13";
1238 function = "spi0";
1239 };
1241 spi0_cs0_pins_a: spi0_cs0@0 {
1242 pins = "PI10";
1243 function = "spi0";
1244 };
1246 spi0_cs1_pins_a: spi0_cs1@0 {
1247 pins = "PI14";
1248 function = "spi0";
1249 };
1251 spi1_pins_a: spi1@0 {
1252 pins = "PI17", "PI18", "PI19";
1253 function = "spi1";
1254 };
1256 spi1_cs0_pins_a: spi1_cs0@0 {
1257 pins = "PI16";
1258 function = "spi1";
1259 };
1261 spi2_pins_a: spi2@0 {
1262 pins = "PC20", "PC21", "PC22";
1263 function = "spi2";
1264 };
1266 spi2_pins_b: spi2@1 {
1267 pins = "PB15", "PB16", "PB17";
1268 function = "spi2";
1269 };
1271 spi2_cs0_pins_a: spi2_cs0@0 {
1272 pins = "PC19";
1273 function = "spi2";
1274 };
1276 spi2_cs0_pins_b: spi2_cs0@1 {
1277 pins = "PB14";
1278 function = "spi2";
1279 };
1281 uart0_pins_a: uart0@0 {
1282 pins = "PB22", "PB23";
1283 function = "uart0";
1284 };
1286 uart2_pins_a: uart2@0 {
1287 pins = "PI16", "PI17", "PI18", "PI19";
1288 function = "uart2";
1289 };
1291 uart3_pins_a: uart3@0 {
1292 pins = "PG6", "PG7", "PG8", "PG9";
1293 function = "uart3";
1294 };
1296 uart3_pins_b: uart3@1 {
1297 pins = "PH0", "PH1";
1298 function = "uart3";
1299 };
1301 uart4_pins_a: uart4@0 {
1302 pins = "PG10", "PG11";
1303 function = "uart4";
1304 };
1306 uart4_pins_b: uart4@1 {
1307 pins = "PH4", "PH5";
1308 function = "uart4";
1309 };
1311 uart5_pins_a: uart5@0 {
1312 pins = "PI10", "PI11";
1313 function = "uart5";
1314 };
1316 uart6_pins_a: uart6@0 {
1317 pins = "PI12", "PI13";
1318 function = "uart6";
1319 };
1321 uart7_pins_a: uart7@0 {
1322 pins = "PI20", "PI21";
1323 function = "uart7";
1324 };
1325 };
1327 timer@01c20c00 {
1328 compatible = "allwinner,sun4i-a10-timer";
1329 reg = <0x01c20c00 0x90>;
1330 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1336 clocks = <&osc24M>;
1337 };
1339 wdt: watchdog@01c20c90 {
1340 compatible = "allwinner,sun4i-a10-wdt";
1341 reg = <0x01c20c90 0x10>;
1342 };
1344 rtc: rtc@01c20d00 {
1345 compatible = "allwinner,sun7i-a20-rtc";
1346 reg = <0x01c20d00 0x20>;
1347 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1348 };
1350 pwm: pwm@01c20e00 {
1351 compatible = "allwinner,sun7i-a20-pwm";
1352 reg = <0x01c20e00 0xc>;
1353 clocks = <&osc24M>;
1354 #pwm-cells = <3>;
1355 status = "disabled";
1356 };
1358 spdif: spdif@01c21000 {
1359 #sound-dai-cells = <0>;
1360 compatible = "allwinner,sun4i-a10-spdif";
1361 reg = <0x01c21000 0x400>;
1362 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1363 clocks = <&apb0_gates 1>, <&spdif_clk>;
1364 clock-names = "apb", "spdif";
1365 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1366 <&dma SUN4I_DMA_NORMAL 2>;
1367 dma-names = "rx", "tx";
1368 status = "disabled";
1369 };
1371 ir0: ir@01c21800 {
1372 compatible = "allwinner,sun4i-a10-ir";
1373 clocks = <&apb0_gates 6>, <&ir0_clk>;
1374 clock-names = "apb", "ir";
1375 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1376 reg = <0x01c21800 0x40>;
1377 status = "disabled";
1378 };
1380 ir1: ir@01c21c00 {
1381 compatible = "allwinner,sun4i-a10-ir";
1382 clocks = <&apb0_gates 7>, <&ir1_clk>;
1383 clock-names = "apb", "ir";
1384 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1385 reg = <0x01c21c00 0x40>;
1386 status = "disabled";
1387 };
1389 i2s1: i2s@01c22000 {
1390 #sound-dai-cells = <0>;
1391 compatible = "allwinner,sun4i-a10-i2s";
1392 reg = <0x01c22000 0x400>;
1393 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1394 clocks = <&apb0_gates 4>, <&i2s1_clk>;
1395 clock-names = "apb", "mod";
1396 dmas = <&dma SUN4I_DMA_NORMAL 4>,
1397 <&dma SUN4I_DMA_NORMAL 4>;
1398 dma-names = "rx", "tx";
1399 status = "disabled";
1400 };
1402 i2s0: i2s@01c22400 {
1403 #sound-dai-cells = <0>;
1404 compatible = "allwinner,sun4i-a10-i2s";
1405 reg = <0x01c22400 0x400>;
1406 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1407 clocks = <&apb0_gates 3>, <&i2s0_clk>;
1408 clock-names = "apb", "mod";
1409 dmas = <&dma SUN4I_DMA_NORMAL 3>,
1410 <&dma SUN4I_DMA_NORMAL 3>;
1411 dma-names = "rx", "tx";
1412 status = "disabled";
1413 };
1415 lradc: lradc@01c22800 {
1416 compatible = "allwinner,sun4i-a10-lradc-keys";
1417 reg = <0x01c22800 0x100>;
1418 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1419 status = "disabled";
1420 };
1422 codec: codec@01c22c00 {
1423 #sound-dai-cells = <0>;
1424 compatible = "allwinner,sun7i-a20-codec";
1425 reg = <0x01c22c00 0x40>;
1426 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1427 clocks = <&apb0_gates 0>, <&codec_clk>;
1428 clock-names = "apb", "codec";
1429 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1430 <&dma SUN4I_DMA_NORMAL 19>;
1431 dma-names = "rx", "tx";
1432 status = "disabled";
1433 };
1435 sid: eeprom@01c23800 {
1436 compatible = "allwinner,sun7i-a20-sid";
1437 reg = <0x01c23800 0x200>;
1438 };
1440 i2s2: i2s@01c24400 {
1441 #sound-dai-cells = <0>;
1442 compatible = "allwinner,sun4i-a10-i2s";
1443 reg = <0x01c24400 0x400>;
1444 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1445 clocks = <&apb0_gates 8>, <&i2s2_clk>;
1446 clock-names = "apb", "mod";
1447 dmas = <&dma SUN4I_DMA_NORMAL 6>,
1448 <&dma SUN4I_DMA_NORMAL 6>;
1449 dma-names = "rx", "tx";
1450 status = "disabled";
1451 };
1453 rtp: rtp@01c25000 {
1454 compatible = "allwinner,sun5i-a13-ts";
1455 reg = <0x01c25000 0x100>;
1456 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1457 #thermal-sensor-cells = <0>;
1458 };
1460 uart0: serial@01c28000 {
1461 compatible = "snps,dw-apb-uart";
1462 reg = <0x01c28000 0x400>;
1463 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1464 reg-shift = <2>;
1465 reg-io-width = <4>;
1466 clocks = <&apb1_gates 16>;
1467 status = "disabled";
1468 };
1470 uart1: serial@01c28400 {
1471 compatible = "snps,dw-apb-uart";
1472 reg = <0x01c28400 0x400>;
1473 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1474 reg-shift = <2>;
1475 reg-io-width = <4>;
1476 clocks = <&apb1_gates 17>;
1477 status = "disabled";
1478 };
1480 uart2: serial@01c28800 {
1481 compatible = "snps,dw-apb-uart";
1482 reg = <0x01c28800 0x400>;
1483 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1484 reg-shift = <2>;
1485 reg-io-width = <4>;
1486 clocks = <&apb1_gates 18>;
1487 status = "disabled";
1488 };
1490 uart3: serial@01c28c00 {
1491 compatible = "snps,dw-apb-uart";
1492 reg = <0x01c28c00 0x400>;
1493 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1494 reg-shift = <2>;
1495 reg-io-width = <4>;
1496 clocks = <&apb1_gates 19>;
1497 status = "disabled";
1498 };
1500 uart4: serial@01c29000 {
1501 compatible = "snps,dw-apb-uart";
1502 reg = <0x01c29000 0x400>;
1503 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1504 reg-shift = <2>;
1505 reg-io-width = <4>;
1506 clocks = <&apb1_gates 20>;
1507 status = "disabled";
1508 };
1510 uart5: serial@01c29400 {
1511 compatible = "snps,dw-apb-uart";
1512 reg = <0x01c29400 0x400>;
1513 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1514 reg-shift = <2>;
1515 reg-io-width = <4>;
1516 clocks = <&apb1_gates 21>;
1517 status = "disabled";
1518 };
1520 uart6: serial@01c29800 {
1521 compatible = "snps,dw-apb-uart";
1522 reg = <0x01c29800 0x400>;
1523 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1524 reg-shift = <2>;
1525 reg-io-width = <4>;
1526 clocks = <&apb1_gates 22>;
1527 status = "disabled";
1528 };
1530 uart7: serial@01c29c00 {
1531 compatible = "snps,dw-apb-uart";
1532 reg = <0x01c29c00 0x400>;
1533 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1534 reg-shift = <2>;
1535 reg-io-width = <4>;
1536 clocks = <&apb1_gates 23>;
1537 status = "disabled";
1538 };
1540 ps20: ps2@01c2a000 {
1541 compatible = "allwinner,sun4i-a10-ps2";
1542 reg = <0x01c2a000 0x400>;
1543 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1544 clocks = <&apb1_gates 6>;
1545 status = "disabled";
1546 };
1548 ps21: ps2@01c2a400 {
1549 compatible = "allwinner,sun4i-a10-ps2";
1550 reg = <0x01c2a400 0x400>;
1551 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1552 clocks = <&apb1_gates 7>;
1553 status = "disabled";
1554 };
1556 i2c0: i2c@01c2ac00 {
1557 compatible = "allwinner,sun7i-a20-i2c",
1558 "allwinner,sun4i-a10-i2c";
1559 reg = <0x01c2ac00 0x400>;
1560 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1561 clocks = <&apb1_gates 0>;
1562 status = "disabled";
1563 #address-cells = <1>;
1564 #size-cells = <0>;
1565 };
1567 i2c1: i2c@01c2b000 {
1568 compatible = "allwinner,sun7i-a20-i2c",
1569 "allwinner,sun4i-a10-i2c";
1570 reg = <0x01c2b000 0x400>;
1571 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1572 clocks = <&apb1_gates 1>;
1573 status = "disabled";
1574 #address-cells = <1>;
1575 #size-cells = <0>;
1576 };
1578 i2c2: i2c@01c2b400 {
1579 compatible = "allwinner,sun7i-a20-i2c",
1580 "allwinner,sun4i-a10-i2c";
1581 reg = <0x01c2b400 0x400>;
1582 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1583 clocks = <&apb1_gates 2>;
1584 status = "disabled";
1585 #address-cells = <1>;
1586 #size-cells = <0>;
1587 };
1589 i2c3: i2c@01c2b800 {
1590 compatible = "allwinner,sun7i-a20-i2c",
1591 "allwinner,sun4i-a10-i2c";
1592 reg = <0x01c2b800 0x400>;
1593 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1594 clocks = <&apb1_gates 3>;
1595 status = "disabled";
1596 #address-cells = <1>;
1597 #size-cells = <0>;
1598 };
1600 can0: can@01c2bc00 {
1601 compatible = "allwinner,sun7i-a20-can",
1602 "allwinner,sun4i-a10-can";
1603 reg = <0x01c2bc00 0x400>;
1604 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1605 clocks = <&apb1_gates 4>;
1606 status = "disabled";
1607 };
1609 i2c4: i2c@01c2c000 {
1610 compatible = "allwinner,sun7i-a20-i2c",
1611 "allwinner,sun4i-a10-i2c";
1612 reg = <0x01c2c000 0x400>;
1613 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1614 clocks = <&apb1_gates 15>;
1615 status = "disabled";
1616 #address-cells = <1>;
1617 #size-cells = <0>;
1618 };
1620 gmac: ethernet@01c50000 {
1621 compatible = "allwinner,sun7i-a20-gmac";
1622 reg = <0x01c50000 0x10000>;
1623 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1624 interrupt-names = "macirq";
1625 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1626 clock-names = "stmmaceth", "allwinner_gmac_tx";
1627 snps,pbl = <2>;
1628 snps,fixed-burst;
1629 snps,force_sf_dma_mode;
1630 status = "disabled";
1631 #address-cells = <1>;
1632 #size-cells = <0>;
1633 };
1635 hstimer@01c60000 {
1636 compatible = "allwinner,sun7i-a20-hstimer";
1637 reg = <0x01c60000 0x1000>;
1638 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1639 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1640 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1641 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1642 clocks = <&ahb_gates 28>;
1643 };
1645 gic: interrupt-controller@01c81000 {
1646 compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1647 reg = <0x01c81000 0x1000>,
1648 <0x01c82000 0x2000>,
1649 <0x01c84000 0x2000>,
1650 <0x01c86000 0x2000>;
1651 interrupt-controller;
1652 #interrupt-cells = <3>;
1653 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1654 };
1656 };
1657 };