arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/memory/tegra124-mc.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/reset/tegra124-car.h>
   7 #include <dt-bindings/thermal/tegra124-soctherm.h>
   8
   9 #include "skeleton.dtsi"
  10
  11 / {
  12         compatible = "nvidia,tegra124";
  13         interrupt-parent = <&lic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         pcie@1003000 {
  18                 compatible = "nvidia,tegra124-pcie";
  19                 device_type = "pci";
  20                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  21                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  22                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  23                 reg-names = "pads", "afi", "cs";
  24                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  25                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  26                 interrupt-names = "intr", "msi";
  27
  28                 #interrupt-cells = <1>;
  29                 interrupt-map-mask = <0 0 0 0>;
  30                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  31
  32                 bus-range = <0x00 0xff>;
  33                 #address-cells = <3>;
  34                 #size-cells = <2>;
  35
  36                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  37                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  38                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  39                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  40                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  41
  42                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  43                          <&tegra_car TEGRA124_CLK_AFI>,
  44                          <&tegra_car TEGRA124_CLK_PLL_E>,
  45                          <&tegra_car TEGRA124_CLK_CML0>;
  46                 clock-names = "pex", "afi", "pll_e", "cml";
  47                 resets = <&tegra_car 70>,
  48                          <&tegra_car 72>,
  49                          <&tegra_car 74>;
  50                 reset-names = "pex", "afi", "pcie_x";
  51                 status = "disabled";
  52
  53                 pci@1,0 {
  54                         device_type = "pci";
  55                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  56                         reg = <0x000800 0 0 0 0>;
  57                         bus-range = <0x00 0xff>;
  58                         status = "disabled";
  59
  60                         #address-cells = <3>;
  61                         #size-cells = <2>;
  62                         ranges;
  63
  64                         nvidia,num-lanes = <2>;
  65                 };
  66
  67                 pci@2,0 {
  68                         device_type = "pci";
  69                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  70                         reg = <0x001000 0 0 0 0>;
  71                         bus-range = <0x00 0xff>;
  72                         status = "disabled";
  73
  74                         #address-cells = <3>;
  75                         #size-cells = <2>;
  76                         ranges;
  77
  78                         nvidia,num-lanes = <1>;
  79                 };
  80         };
  81
  82         host1x@50000000 {
  83                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  84                 reg = <0x0 0x50000000 0x0 0x00034000>;
  85                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  86                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  87                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  88                 resets = <&tegra_car 28>;
  89                 reset-names = "host1x";
  90                 iommus = <&mc TEGRA_SWGROUP_HC>;
  91
  92                 #address-cells = <2>;
  93                 #size-cells = <2>;
  94
  95                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  96
  97                 dc@54200000 {
  98                         compatible = "nvidia,tegra124-dc";
  99                         reg = <0x0 0x54200000 0x0 0x00040000>;
 100                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 101                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 102                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 103                         clock-names = "dc", "parent";
 104                         resets = <&tegra_car 27>;
 105                         reset-names = "dc";
 106
 107                         iommus = <&mc TEGRA_SWGROUP_DC>;
 108
 109                         nvidia,head = <0>;
 110                 };
 111
 112                 dc@54240000 {
 113                         compatible = "nvidia,tegra124-dc";
 114                         reg = <0x0 0x54240000 0x0 0x00040000>;
 115                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 116                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 117                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 118                         clock-names = "dc", "parent";
 119                         resets = <&tegra_car 26>;
 120                         reset-names = "dc";
 121
 122                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 123
 124                         nvidia,head = <1>;
 125                 };
 126
 127                 hdmi@54280000 {
 128                         compatible = "nvidia,tegra124-hdmi";
 129                         reg = <0x0 0x54280000 0x0 0x00040000>;
 130                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 131                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 132                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 133                         clock-names = "hdmi", "parent";
 134                         resets = <&tegra_car 51>;
 135                         reset-names = "hdmi";
 136                         status = "disabled";
 137                 };
 138
 139                 sor@54540000 {
 140                         compatible = "nvidia,tegra124-sor";
 141                         reg = <0x0 0x54540000 0x0 0x00040000>;
 142                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 143                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 144                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 145                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 146                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 147                         clock-names = "sor", "parent", "dp", "safe";
 148                         resets = <&tegra_car 182>;
 149                         reset-names = "sor";
 150                         status = "disabled";
 151                 };
 152
 153                 dpaux: dpaux@545c0000 {
 154                         compatible = "nvidia,tegra124-dpaux";
 155                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 156                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 157                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 158                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 159                         clock-names = "dpaux", "parent";
 160                         resets = <&tegra_car 181>;
 161                         reset-names = "dpaux";
 162                         status = "disabled";
 163                 };
 164         };
 165
 166         gic: interrupt-controller@50041000 {
 167                 compatible = "arm,cortex-a15-gic";
 168                 #interrupt-cells = <3>;
 169                 interrupt-controller;
 170                 reg = <0x0 0x50041000 0x0 0x1000>,
 171                       <0x0 0x50042000 0x0 0x1000>,
 172                       <0x0 0x50044000 0x0 0x2000>,
 173                       <0x0 0x50046000 0x0 0x2000>;
 174                 interrupts = <GIC_PPI 9
 175                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 176                 interrupt-parent = <&gic>;
 177         };
 178
 179         /*
 180          * Please keep the following 0, notation in place as a former mainline
 181          * U-Boot version was looking for that particular notation in order to
 182          * perform required fix-ups on that GPU node.
 183          */
 184         gpu@0,57000000 {
 185                 compatible = "nvidia,gk20a";
 186                 reg = <0x0 0x57000000 0x0 0x01000000>,
 187                       <0x0 0x58000000 0x0 0x01000000>;
 188                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 190                 interrupt-names = "stall", "nonstall";
 191                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 192                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 193                 clock-names = "gpu", "pwr";
 194                 resets = <&tegra_car 184>;
 195                 reset-names = "gpu";
 196
 197                 iommus = <&mc TEGRA_SWGROUP_GPU>;
 198
 199                 status = "disabled";
 200         };
 201
 202         lic: interrupt-controller@60004000 {
 203                 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
 204                 reg = <0x0 0x60004000 0x0 0x100>,
 205                       <0x0 0x60004100 0x0 0x100>,
 206                       <0x0 0x60004200 0x0 0x100>,
 207                       <0x0 0x60004300 0x0 0x100>,
 208                       <0x0 0x60004400 0x0 0x100>;
 209                 interrupt-controller;
 210                 #interrupt-cells = <3>;
 211                 interrupt-parent = <&gic>;
 212         };
 213
 214         timer@60005000 {
 215                 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 216                 reg = <0x0 0x60005000 0x0 0x400>;
 217                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 223                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 224         };
 225
 226         tegra_car: clock@60006000 {
 227                 compatible = "nvidia,tegra124-car";
 228                 reg = <0x0 0x60006000 0x0 0x1000>;
 229                 #clock-cells = <1>;
 230                 #reset-cells = <1>;
 231                 nvidia,external-memory-controller = <&emc>;
 232         };
 233
 234         flow-controller@60007000 {
 235                 compatible = "nvidia,tegra124-flowctrl";
 236                 reg = <0x0 0x60007000 0x0 0x1000>;
 237         };
 238
 239         actmon@6000c800 {
 240                 compatible = "nvidia,tegra124-actmon";
 241                 reg = <0x0 0x6000c800 0x0 0x400>;
 242                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 243                 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
 244                          <&tegra_car TEGRA124_CLK_EMC>;
 245                 clock-names = "actmon", "emc";
 246                 resets = <&tegra_car 119>;
 247                 reset-names = "actmon";
 248         };
 249
 250         gpio: gpio@6000d000 {
 251                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 252                 reg = <0x0 0x6000d000 0x0 0x1000>;
 253                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 261                 #gpio-cells = <2>;
 262                 gpio-controller;
 263                 #interrupt-cells = <2>;
 264                 interrupt-controller;
 265                 /*
 266                 gpio-ranges = <&pinmux 0 0 251>;
 267                 */
 268         };
 269
 270         apbdma: dma@60020000 {
 271                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 272                 reg = <0x0 0x60020000 0x0 0x1400>;
 273                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 298                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 301                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 302                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 305                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 306                 resets = <&tegra_car 34>;
 307                 reset-names = "dma";
 308                 #dma-cells = <1>;
 309         };
 310
 311         apbmisc@70000800 {
 312                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 313                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 314                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
 315         };
 316
 317         pinmux: pinmux@70000868 {
 318                 compatible = "nvidia,tegra124-pinmux";
 319                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 320                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
 321                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
 322         };
 323
 324         /*
 325          * There are two serial driver i.e. 8250 based simple serial
 326          * driver and APB DMA based serial driver for higher baudrate
 327          * and performace. To enable the 8250 based driver, the compatible
 328          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 329          * the APB DMA based serial driver, the compatible is
 330          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 331          */
 332         uarta: serial@70006000 {
 333                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 334                 reg = <0x0 0x70006000 0x0 0x40>;
 335                 reg-shift = <2>;
 336                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 337                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 338                 resets = <&tegra_car 6>;
 339                 reset-names = "serial";
 340                 dmas = <&apbdma 8>, <&apbdma 8>;
 341                 dma-names = "rx", "tx";
 342                 status = "disabled";
 343         };
 344
 345         uartb: serial@70006040 {
 346                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 347                 reg = <0x0 0x70006040 0x0 0x40>;
 348                 reg-shift = <2>;
 349                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 350                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 351                 resets = <&tegra_car 7>;
 352                 reset-names = "serial";
 353                 dmas = <&apbdma 9>, <&apbdma 9>;
 354                 dma-names = "rx", "tx";
 355                 status = "disabled";
 356         };
 357
 358         uartc: serial@70006200 {
 359                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 360                 reg = <0x0 0x70006200 0x0 0x40>;
 361                 reg-shift = <2>;
 362                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 364                 resets = <&tegra_car 55>;
 365                 reset-names = "serial";
 366                 dmas = <&apbdma 10>, <&apbdma 10>;
 367                 dma-names = "rx", "tx";
 368                 status = "disabled";
 369         };
 370
 371         uartd: serial@70006300 {
 372                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 373                 reg = <0x0 0x70006300 0x0 0x40>;
 374                 reg-shift = <2>;
 375                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 376                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 377                 resets = <&tegra_car 65>;
 378                 reset-names = "serial";
 379                 dmas = <&apbdma 19>, <&apbdma 19>;
 380                 dma-names = "rx", "tx";
 381                 status = "disabled";
 382         };
 383
 384         pwm: pwm@7000a000 {
 385                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 386                 reg = <0x0 0x7000a000 0x0 0x100>;
 387                 #pwm-cells = <2>;
 388                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 389                 resets = <&tegra_car 17>;
 390                 reset-names = "pwm";
 391                 status = "disabled";
 392         };
 393
 394         i2c@7000c000 {
 395                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 396                 reg = <0x0 0x7000c000 0x0 0x100>;
 397                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 401                 clock-names = "div-clk";
 402                 resets = <&tegra_car 12>;
 403                 reset-names = "i2c";
 404                 dmas = <&apbdma 21>, <&apbdma 21>;
 405                 dma-names = "rx", "tx";
 406                 status = "disabled";
 407         };
 408
 409         i2c@7000c400 {
 410                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 411                 reg = <0x0 0x7000c400 0x0 0x100>;
 412                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 413                 #address-cells = <1>;
 414                 #size-cells = <0>;
 415                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 416                 clock-names = "div-clk";
 417                 resets = <&tegra_car 54>;
 418                 reset-names = "i2c";
 419                 dmas = <&apbdma 22>, <&apbdma 22>;
 420                 dma-names = "rx", "tx";
 421                 status = "disabled";
 422         };
 423
 424         i2c@7000c500 {
 425                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 426                 reg = <0x0 0x7000c500 0x0 0x100>;
 427                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 428                 #address-cells = <1>;
 429                 #size-cells = <0>;
 430                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 431                 clock-names = "div-clk";
 432                 resets = <&tegra_car 67>;
 433                 reset-names = "i2c";
 434                 dmas = <&apbdma 23>, <&apbdma 23>;
 435                 dma-names = "rx", "tx";
 436                 status = "disabled";
 437         };
 438
 439         i2c@7000c700 {
 440                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 441                 reg = <0x0 0x7000c700 0x0 0x100>;
 442                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 446                 clock-names = "div-clk";
 447                 resets = <&tegra_car 103>;
 448                 reset-names = "i2c";
 449                 dmas = <&apbdma 26>, <&apbdma 26>;
 450                 dma-names = "rx", "tx";
 451                 status = "disabled";
 452         };
 453
 454         i2c@7000d000 {
 455                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 456                 reg = <0x0 0x7000d000 0x0 0x100>;
 457                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 458                 #address-cells = <1>;
 459                 #size-cells = <0>;
 460                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 461                 clock-names = "div-clk";
 462                 resets = <&tegra_car 47>;
 463                 reset-names = "i2c";
 464                 dmas = <&apbdma 24>, <&apbdma 24>;
 465                 dma-names = "rx", "tx";
 466                 status = "disabled";
 467         };
 468
 469         i2c@7000d100 {
 470                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 471                 reg = <0x0 0x7000d100 0x0 0x100>;
 472                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 476                 clock-names = "div-clk";
 477                 resets = <&tegra_car 166>;
 478                 reset-names = "i2c";
 479                 dmas = <&apbdma 30>, <&apbdma 30>;
 480                 dma-names = "rx", "tx";
 481                 status = "disabled";
 482         };
 483
 484         spi@7000d400 {
 485                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 486                 reg = <0x0 0x7000d400 0x0 0x200>;
 487                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 491                 clock-names = "spi";
 492                 resets = <&tegra_car 41>;
 493                 reset-names = "spi";
 494                 dmas = <&apbdma 15>, <&apbdma 15>;
 495                 dma-names = "rx", "tx";
 496                 status = "disabled";
 497         };
 498
 499         spi@7000d600 {
 500                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 501                 reg = <0x0 0x7000d600 0x0 0x200>;
 502                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 503                 #address-cells = <1>;
 504                 #size-cells = <0>;
 505                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 506                 clock-names = "spi";
 507                 resets = <&tegra_car 44>;
 508                 reset-names = "spi";
 509                 dmas = <&apbdma 16>, <&apbdma 16>;
 510                 dma-names = "rx", "tx";
 511                 status = "disabled";
 512         };
 513
 514         spi@7000d800 {
 515                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 516                 reg = <0x0 0x7000d800 0x0 0x200>;
 517                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 521                 clock-names = "spi";
 522                 resets = <&tegra_car 46>;
 523                 reset-names = "spi";
 524                 dmas = <&apbdma 17>, <&apbdma 17>;
 525                 dma-names = "rx", "tx";
 526                 status = "disabled";
 527         };
 528
 529         spi@7000da00 {
 530                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 531                 reg = <0x0 0x7000da00 0x0 0x200>;
 532                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 536                 clock-names = "spi";
 537                 resets = <&tegra_car 68>;
 538                 reset-names = "spi";
 539                 dmas = <&apbdma 18>, <&apbdma 18>;
 540                 dma-names = "rx", "tx";
 541                 status = "disabled";
 542         };
 543
 544         spi@7000dc00 {
 545                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 546                 reg = <0x0 0x7000dc00 0x0 0x200>;
 547                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 551                 clock-names = "spi";
 552                 resets = <&tegra_car 104>;
 553                 reset-names = "spi";
 554                 dmas = <&apbdma 27>, <&apbdma 27>;
 555                 dma-names = "rx", "tx";
 556                 status = "disabled";
 557         };
 558
 559         spi@7000de00 {
 560                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 561                 reg = <0x0 0x7000de00 0x0 0x200>;
 562                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 566                 clock-names = "spi";
 567                 resets = <&tegra_car 105>;
 568                 reset-names = "spi";
 569                 dmas = <&apbdma 28>, <&apbdma 28>;
 570                 dma-names = "rx", "tx";
 571                 status = "disabled";
 572         };
 573
 574         rtc@7000e000 {
 575                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 576                 reg = <0x0 0x7000e000 0x0 0x100>;
 577                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 578                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 579         };
 580
 581         pmc@7000e400 {
 582                 compatible = "nvidia,tegra124-pmc";
 583                 reg = <0x0 0x7000e400 0x0 0x400>;
 584                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 585                 clock-names = "pclk", "clk32k_in";
 586         };
 587
 588         fuse@7000f800 {
 589                 compatible = "nvidia,tegra124-efuse";
 590                 reg = <0x0 0x7000f800 0x0 0x400>;
 591                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 592                 clock-names = "fuse";
 593                 resets = <&tegra_car 39>;
 594                 reset-names = "fuse";
 595         };
 596
 597         mc: memory-controller@70019000 {
 598                 compatible = "nvidia,tegra124-mc";
 599                 reg = <0x0 0x70019000 0x0 0x1000>;
 600                 clocks = <&tegra_car TEGRA124_CLK_MC>;
 601                 clock-names = "mc";
 602
 603                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 604
 605                 #iommu-cells = <1>;
 606         };
 607
 608         emc: emc@7001b000 {
 609                 compatible = "nvidia,tegra124-emc";
 610                 reg = <0x0 0x7001b000 0x0 0x1000>;
 611
 612                 nvidia,memory-controller = <&mc>;
 613         };
 614
 615         sata@70020000 {
 616                 compatible = "nvidia,tegra124-ahci";
 617                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 618                       <0x0 0x70020000 0x0 0x7000>; /* SATA */
 619                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 620                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 621                          <&tegra_car TEGRA124_CLK_SATA_OOB>,
 622                          <&tegra_car TEGRA124_CLK_CML1>,
 623                          <&tegra_car TEGRA124_CLK_PLL_E>;
 624                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 625                 resets = <&tegra_car 124>,
 626                          <&tegra_car 123>,
 627                          <&tegra_car 129>;
 628                 reset-names = "sata", "sata-oob", "sata-cold";
 629                 status = "disabled";
 630         };
 631
 632         hda@70030000 {
 633                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 634                 reg = <0x0 0x70030000 0x0 0x10000>;
 635                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 636                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 637                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 638                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 639                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 640                 resets = <&tegra_car 125>, /* hda */
 641                          <&tegra_car 128>, /* hda2hdmi */
 642                          <&tegra_car 111>; /* hda2codec_2x */
 643                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 644                 status = "disabled";
 645         };
 646
 647         usb@70090000 {
 648                 compatible = "nvidia,tegra124-xusb";
 649                 reg = <0x0 0x70090000 0x0 0x8000>,
 650                       <0x0 0x70098000 0x0 0x1000>,
 651                       <0x0 0x70099000 0x0 0x1000>;
 652                 reg-names = "hcd", "fpci", "ipfs";
 653
 654                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 655                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 656
 657                 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
 658                          <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
 659                          <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
 660                          <&tegra_car TEGRA124_CLK_XUSB_SS>,
 661                          <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
 662                          <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
 663                          <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
 664                          <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
 665                          <&tegra_car TEGRA124_CLK_PLL_U_480M>,
 666                          <&tegra_car TEGRA124_CLK_CLK_M>,
 667                          <&tegra_car TEGRA124_CLK_PLL_E>;
 668                 clock-names = "xusb_host", "xusb_host_src",
 669                               "xusb_falcon_src", "xusb_ss",
 670                               "xusb_ss_div2", "xusb_ss_src",
 671                               "xusb_hs_src", "xusb_fs_src",
 672                               "pll_u_480m", "clk_m", "pll_e";
 673                 resets = <&tegra_car 89>, <&tegra_car 156>,
 674                          <&tegra_car 143>;
 675                 reset-names = "xusb_host", "xusb_ss", "xusb_src";
 676
 677                 nvidia,xusb-padctl = <&padctl>;
 678
 679                 status = "disabled";
 680         };
 681
 682         padctl: padctl@7009f000 {
 683                 compatible = "nvidia,tegra124-xusb-padctl";
 684                 reg = <0x0 0x7009f000 0x0 0x1000>;
 685                 resets = <&tegra_car 142>;
 686                 reset-names = "padctl";
 687
 688                 pads {
 689                         usb2 {
 690                                 status = "disabled";
 691
 692                                 lanes {
 693                                         usb2-0 {
 694                                                 status = "disabled";
 695                                                 #phy-cells = <0>;
 696                                         };
 697
 698                                         usb2-1 {
 699                                                 status = "disabled";
 700                                                 #phy-cells = <0>;
 701                                         };
 702
 703                                         usb2-2 {
 704                                                 status = "disabled";
 705                                                 #phy-cells = <0>;
 706                                         };
 707                                 };
 708                         };
 709
 710                         ulpi {
 711                                 status = "disabled";
 712
 713                                 lanes {
 714                                         ulpi-0 {
 715                                                 status = "disabled";
 716                                                 #phy-cells = <0>;
 717                                         };
 718                                 };
 719                         };
 720
 721                         hsic {
 722                                 status = "disabled";
 723
 724                                 lanes {
 725                                         hsic-0 {
 726                                                 status = "disabled";
 727                                                 #phy-cells = <0>;
 728                                         };
 729
 730                                         hsic-1 {
 731                                                 status = "disabled";
 732                                                 #phy-cells = <0>;
 733                                         };
 734                                 };
 735                         };
 736
 737                         pcie {
 738                                 status = "disabled";
 739
 740                                 lanes {
 741                                         pcie-0 {
 742                                                 status = "disabled";
 743                                                 #phy-cells = <0>;
 744                                         };
 745
 746                                         pcie-1 {
 747                                                 status = "disabled";
 748                                                 #phy-cells = <0>;
 749                                         };
 750
 751                                         pcie-2 {
 752                                                 status = "disabled";
 753                                                 #phy-cells = <0>;
 754                                         };
 755
 756                                         pcie-3 {
 757                                                 status = "disabled";
 758                                                 #phy-cells = <0>;
 759                                         };
 760
 761                                         pcie-4 {
 762                                                 status = "disabled";
 763                                                 #phy-cells = <0>;
 764                                         };
 765                                 };
 766                         };
 767
 768                         sata {
 769                                 status = "disabled";
 770
 771                                 lanes {
 772                                         sata-0 {
 773                                                 status = "disabled";
 774                                                 #phy-cells = <0>;
 775                                         };
 776                                 };
 777                         };
 778                 };
 779
 780                 ports {
 781                         usb2-0 {
 782                                 status = "disabled";
 783                         };
 784
 785                         usb2-1 {
 786                                 status = "disabled";
 787                         };
 788
 789                         usb2-2 {
 790                                 status = "disabled";
 791                         };
 792
 793                         ulpi-0 {
 794                                 status = "disabled";
 795                         };
 796
 797                         hsic-0 {
 798                                 status = "disabled";
 799                         };
 800
 801                         hsic-1 {
 802                                 status = "disabled";
 803                         };
 804
 805                         usb3-0 {
 806                                 status = "disabled";
 807                         };
 808
 809                         usb3-1 {
 810                                 status = "disabled";
 811                         };
 812                 };
 813         };
 814
 815         sdhci@700b0000 {
 816                 compatible = "nvidia,tegra124-sdhci";
 817                 reg = <0x0 0x700b0000 0x0 0x200>;
 818                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 819                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 820                 resets = <&tegra_car 14>;
 821                 reset-names = "sdhci";
 822                 status = "disabled";
 823         };
 824
 825         sdhci@700b0200 {
 826                 compatible = "nvidia,tegra124-sdhci";
 827                 reg = <0x0 0x700b0200 0x0 0x200>;
 828                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 829                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 830                 resets = <&tegra_car 9>;
 831                 reset-names = "sdhci";
 832                 status = "disabled";
 833         };
 834
 835         sdhci@700b0400 {
 836                 compatible = "nvidia,tegra124-sdhci";
 837                 reg = <0x0 0x700b0400 0x0 0x200>;
 838                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 839                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 840                 resets = <&tegra_car 69>;
 841                 reset-names = "sdhci";
 842                 status = "disabled";
 843         };
 844
 845         sdhci@700b0600 {
 846                 compatible = "nvidia,tegra124-sdhci";
 847                 reg = <0x0 0x700b0600 0x0 0x200>;
 848                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 849                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 850                 resets = <&tegra_car 15>;
 851                 reset-names = "sdhci";
 852                 status = "disabled";
 853         };
 854
 855         soctherm: thermal-sensor@700e2000 {
 856                 compatible = "nvidia,tegra124-soctherm";
 857                 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
 858                         0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
 859                 reg-names = "soctherm-reg", "car-reg";
 860                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 861                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
 862                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
 863                 clock-names = "tsensor", "soctherm";
 864                 resets = <&tegra_car 78>;
 865                 reset-names = "soctherm";
 866                 #thermal-sensor-cells = <1>;
 867
 868                 throttle-cfgs {
 869                         throttle_heavy: heavy {
 870                                 nvidia,priority = <100>;
 871                                 nvidia,cpu-throt-percent = <85>;
 872
 873                                 #cooling-cells = <2>;
 874                         };
 875                 };
 876         };
 877
 878         dfll: clock@70110000 {
 879                 compatible = "nvidia,tegra124-dfll";
 880                 reg = <0 0x70110000 0 0x100>, /* DFLL control */
 881                       <0 0x70110000 0 0x100>, /* I2C output control */
 882                       <0 0x70110100 0 0x100>, /* Integrated I2C controller */
 883                       <0 0x70110200 0 0x100>; /* Look-up table RAM */
 884                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 885                 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
 886                          <&tegra_car TEGRA124_CLK_DFLL_REF>,
 887                          <&tegra_car TEGRA124_CLK_I2C5>;
 888                 clock-names = "soc", "ref", "i2c";
 889                 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
 890                 reset-names = "dvco";
 891                 #clock-cells = <0>;
 892                 clock-output-names = "dfllCPU_out";
 893                 nvidia,sample-rate = <12500>;
 894                 nvidia,droop-ctrl = <0x00000f00>;
 895                 nvidia,force-mode = <1>;
 896                 nvidia,cf = <10>;
 897                 nvidia,ci = <0>;
 898                 nvidia,cg = <2>;
 899                 status = "disabled";
 900         };
 901
 902         ahub@70300000 {
 903                 compatible = "nvidia,tegra124-ahub";
 904                 reg = <0x0 0x70300000 0x0 0x200>,
 905                       <0x0 0x70300800 0x0 0x800>,
 906                       <0x0 0x70300200 0x0 0x600>;
 907                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 908                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 909                          <&tegra_car TEGRA124_CLK_APBIF>;
 910                 clock-names = "d_audio", "apbif";
 911                 resets = <&tegra_car 106>, /* d_audio */
 912                          <&tegra_car 107>, /* apbif */
 913                          <&tegra_car 30>,  /* i2s0 */
 914                          <&tegra_car 11>,  /* i2s1 */
 915                          <&tegra_car 18>,  /* i2s2 */
 916                          <&tegra_car 101>, /* i2s3 */
 917                          <&tegra_car 102>, /* i2s4 */
 918                          <&tegra_car 108>, /* dam0 */
 919                          <&tegra_car 109>, /* dam1 */
 920                          <&tegra_car 110>, /* dam2 */
 921                          <&tegra_car 10>,  /* spdif */
 922                          <&tegra_car 153>, /* amx */
 923                          <&tegra_car 185>, /* amx1 */
 924                          <&tegra_car 154>, /* adx */
 925                          <&tegra_car 180>, /* adx1 */
 926                          <&tegra_car 186>, /* afc0 */
 927                          <&tegra_car 187>, /* afc1 */
 928                          <&tegra_car 188>, /* afc2 */
 929                          <&tegra_car 189>, /* afc3 */
 930                          <&tegra_car 190>, /* afc4 */
 931                          <&tegra_car 191>; /* afc5 */
 932                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 933                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 934                               "spdif", "amx", "amx1", "adx", "adx1",
 935                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 936                 dmas = <&apbdma 1>, <&apbdma 1>,
 937                        <&apbdma 2>, <&apbdma 2>,
 938                        <&apbdma 3>, <&apbdma 3>,
 939                        <&apbdma 4>, <&apbdma 4>,
 940                        <&apbdma 6>, <&apbdma 6>,
 941                        <&apbdma 7>, <&apbdma 7>,
 942                        <&apbdma 12>, <&apbdma 12>,
 943                        <&apbdma 13>, <&apbdma 13>,
 944                        <&apbdma 14>, <&apbdma 14>,
 945                        <&apbdma 29>, <&apbdma 29>;
 946                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 947                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 948                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 949                             "rx9", "tx9";
 950                 ranges;
 951                 #address-cells = <2>;
 952                 #size-cells = <2>;
 953
 954                 tegra_i2s0: i2s@70301000 {
 955                         compatible = "nvidia,tegra124-i2s";
 956                         reg = <0x0 0x70301000 0x0 0x100>;
 957                         nvidia,ahub-cif-ids = <4 4>;
 958                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 959                         resets = <&tegra_car 30>;
 960                         reset-names = "i2s";
 961                         status = "disabled";
 962                 };
 963
 964                 tegra_i2s1: i2s@70301100 {
 965                         compatible = "nvidia,tegra124-i2s";
 966                         reg = <0x0 0x70301100 0x0 0x100>;
 967                         nvidia,ahub-cif-ids = <5 5>;
 968                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 969                         resets = <&tegra_car 11>;
 970                         reset-names = "i2s";
 971                         status = "disabled";
 972                 };
 973
 974                 tegra_i2s2: i2s@70301200 {
 975                         compatible = "nvidia,tegra124-i2s";
 976                         reg = <0x0 0x70301200 0x0 0x100>;
 977                         nvidia,ahub-cif-ids = <6 6>;
 978                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 979                         resets = <&tegra_car 18>;
 980                         reset-names = "i2s";
 981                         status = "disabled";
 982                 };
 983
 984                 tegra_i2s3: i2s@70301300 {
 985                         compatible = "nvidia,tegra124-i2s";
 986                         reg = <0x0 0x70301300 0x0 0x100>;
 987                         nvidia,ahub-cif-ids = <7 7>;
 988                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 989                         resets = <&tegra_car 101>;
 990                         reset-names = "i2s";
 991                         status = "disabled";
 992                 };
 993
 994                 tegra_i2s4: i2s@70301400 {
 995                         compatible = "nvidia,tegra124-i2s";
 996                         reg = <0x0 0x70301400 0x0 0x100>;
 997                         nvidia,ahub-cif-ids = <8 8>;
 998                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 999                         resets = <&tegra_car 102>;
1000                         reset-names = "i2s";
1001                         status = "disabled";
1002                 };
1003         };
1004
1005         usb@7d000000 {
1006                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1007                 reg = <0x0 0x7d000000 0x0 0x4000>;
1008                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1009                 phy_type = "utmi";
1010                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1011                 resets = <&tegra_car 22>;
1012                 reset-names = "usb";
1013                 nvidia,phy = <&phy1>;
1014                 status = "disabled";
1015         };
1016
1017         phy1: usb-phy@7d000000 {
1018                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1019                 reg = <0x0 0x7d000000 0x0 0x4000>,
1020                       <0x0 0x7d000000 0x0 0x4000>;
1021                 phy_type = "utmi";
1022                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1023                          <&tegra_car TEGRA124_CLK_PLL_U>,
1024                          <&tegra_car TEGRA124_CLK_USBD>;
1025                 clock-names = "reg", "pll_u", "utmi-pads";
1026                 resets = <&tegra_car 22>, <&tegra_car 22>;
1027                 reset-names = "usb", "utmi-pads";
1028                 nvidia,hssync-start-delay = <0>;
1029                 nvidia,idle-wait-delay = <17>;
1030                 nvidia,elastic-limit = <16>;
1031                 nvidia,term-range-adj = <6>;
1032                 nvidia,xcvr-setup = <9>;
1033                 nvidia,xcvr-lsfslew = <0>;
1034                 nvidia,xcvr-lsrslew = <3>;
1035                 nvidia,hssquelch-level = <2>;
1036                 nvidia,hsdiscon-level = <5>;
1037                 nvidia,xcvr-hsslew = <12>;
1038                 nvidia,has-utmi-pad-registers;
1039                 status = "disabled";
1040         };
1041
1042         usb@7d004000 {
1043                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1044                 reg = <0x0 0x7d004000 0x0 0x4000>;
1045                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1046                 phy_type = "utmi";
1047                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1048                 resets = <&tegra_car 58>;
1049                 reset-names = "usb";
1050                 nvidia,phy = <&phy2>;
1051                 status = "disabled";
1052         };
1053
1054         phy2: usb-phy@7d004000 {
1055                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1056                 reg = <0x0 0x7d004000 0x0 0x4000>,
1057                       <0x0 0x7d000000 0x0 0x4000>;
1058                 phy_type = "utmi";
1059                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1060                          <&tegra_car TEGRA124_CLK_PLL_U>,
1061                          <&tegra_car TEGRA124_CLK_USBD>;
1062                 clock-names = "reg", "pll_u", "utmi-pads";
1063                 resets = <&tegra_car 58>, <&tegra_car 22>;
1064                 reset-names = "usb", "utmi-pads";
1065                 nvidia,hssync-start-delay = <0>;
1066                 nvidia,idle-wait-delay = <17>;
1067                 nvidia,elastic-limit = <16>;
1068                 nvidia,term-range-adj = <6>;
1069                 nvidia,xcvr-setup = <9>;
1070                 nvidia,xcvr-lsfslew = <0>;
1071                 nvidia,xcvr-lsrslew = <3>;
1072                 nvidia,hssquelch-level = <2>;
1073                 nvidia,hsdiscon-level = <5>;
1074                 nvidia,xcvr-hsslew = <12>;
1075                 status = "disabled";
1076         };
1077
1078         usb@7d008000 {
1079                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1080                 reg = <0x0 0x7d008000 0x0 0x4000>;
1081                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1082                 phy_type = "utmi";
1083                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1084                 resets = <&tegra_car 59>;
1085                 reset-names = "usb";
1086                 nvidia,phy = <&phy3>;
1087                 status = "disabled";
1088         };
1089
1090         phy3: usb-phy@7d008000 {
1091                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1092                 reg = <0x0 0x7d008000 0x0 0x4000>,
1093                       <0x0 0x7d000000 0x0 0x4000>;
1094                 phy_type = "utmi";
1095                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1096                          <&tegra_car TEGRA124_CLK_PLL_U>,
1097                          <&tegra_car TEGRA124_CLK_USBD>;
1098                 clock-names = "reg", "pll_u", "utmi-pads";
1099                 resets = <&tegra_car 59>, <&tegra_car 22>;
1100                 reset-names = "usb", "utmi-pads";
1101                 nvidia,hssync-start-delay = <0>;
1102                 nvidia,idle-wait-delay = <17>;
1103                 nvidia,elastic-limit = <16>;
1104                 nvidia,term-range-adj = <6>;
1105                 nvidia,xcvr-setup = <9>;
1106                 nvidia,xcvr-lsfslew = <0>;
1107                 nvidia,xcvr-lsrslew = <3>;
1108                 nvidia,hssquelch-level = <2>;
1109                 nvidia,hsdiscon-level = <5>;
1110                 nvidia,xcvr-hsslew = <12>;
1111                 status = "disabled";
1112         };
1113
1114         cpus {
1115                 #address-cells = <1>;
1116                 #size-cells = <0>;
1117
1118                 cpu@0 {
1119                         device_type = "cpu";
1120                         compatible = "arm,cortex-a15";
1121                         reg = <0>;
1122
1123                         clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1124                                  <&tegra_car TEGRA124_CLK_CCLK_LP>,
1125                                  <&tegra_car TEGRA124_CLK_PLL_X>,
1126                                  <&tegra_car TEGRA124_CLK_PLL_P>,
1127                                  <&dfll>;
1128                         clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1129                         /* FIXME: what's the actual transition time? */
1130                         clock-latency = <300000>;
1131                 };
1132
1133                 cpu@1 {
1134                         device_type = "cpu";
1135                         compatible = "arm,cortex-a15";
1136                         reg = <1>;
1137                 };
1138
1139                 cpu@2 {
1140                         device_type = "cpu";
1141                         compatible = "arm,cortex-a15";
1142                         reg = <2>;
1143                 };
1144
1145                 cpu@3 {
1146                         device_type = "cpu";
1147                         compatible = "arm,cortex-a15";
1148                         reg = <3>;
1149                 };
1150         };
1151
1152         pmu {
1153                 compatible = "arm,cortex-a15-pmu";
1154                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1155                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1156                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1157                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1158                 interrupt-affinity = <&{/cpus/cpu@0}>,
1159                                      <&{/cpus/cpu@1}>,
1160                                      <&{/cpus/cpu@2}>,
1161                                      <&{/cpus/cpu@3}>;
1162         };
1163
1164         thermal-zones {
1165                 cpu {
1166                         polling-delay-passive = <1000>;
1167                         polling-delay = <1000>;
1168
1169                         thermal-sensors =
1170                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1171
1172                         trips {
1173                                 cpu-shutdown-trip {
1174                                         temperature = <103000>;
1175                                         hysteresis = <0>;
1176                                         type = "critical";
1177                                 };
1178                                 cpu_throttle_trip: throttle-trip {
1179                                         temperature = <100000>;
1180                                         hysteresis = <1000>;
1181                                         type = "hot";
1182                                 };
1183                         };
1184
1185                         cooling-maps {
1186                                 map0 {
1187                                         trip = <&cpu_throttle_trip>;
1188                                         cooling-device = <&throttle_heavy 1 1>;
1189                                 };
1190                         };
1191                 };
1192
1193                 mem {
1194                         polling-delay-passive = <1000>;
1195                         polling-delay = <1000>;
1196
1197                         thermal-sensors =
1198                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1199
1200                         trips {
1201                                 mem-shutdown-trip {
1202                                         temperature = <103000>;
1203                                         hysteresis = <0>;
1204                                         type = "critical";
1205                                 };
1206                         };
1207
1208                         cooling-maps {
1209                                 /*
1210                                  * There are currently no cooling maps,
1211                                  * because there are no cooling devices.
1212                                  */
1213                         };
1214                 };
1215
1216                 gpu {
1217                         polling-delay-passive = <1000>;
1218                         polling-delay = <1000>;
1219
1220                         thermal-sensors =
1221                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1222
1223                         trips {
1224                                 gpu-shutdown-trip {
1225                                         temperature = <101000>;
1226                                         hysteresis = <0>;
1227                                         type = "critical";
1228                                 };
1229                                 gpu_throttle_trip: throttle-trip {
1230                                         temperature = <99000>;
1231                                         hysteresis = <1000>;
1232                                         type = "hot";
1233                                 };
1234                         };
1235
1236                         cooling-maps {
1237                                 map0 {
1238                                         trip = <&gpu_throttle_trip>;
1239                                         cooling-device = <&throttle_heavy 1 1>;
1240                                 };
1241                         };
1242                 };
1243
1244                 pllx {
1245                         polling-delay-passive = <1000>;
1246                         polling-delay = <1000>;
1247
1248                         thermal-sensors =
1249                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1250
1251                         trips {
1252                                 pllx-shutdown-trip {
1253                                         temperature = <103000>;
1254                                         hysteresis = <0>;
1255                                         type = "critical";
1256                                 };
1257                         };
1258
1259                         cooling-maps {
1260                                 /*
1261                                  * There are currently no cooling maps,
1262                                  * because there are no cooling devices.
1263                                  */
1264                         };
1265                 };
1266         };
1267
1268         timer {
1269                 compatible = "arm,armv7-timer";
1270                 interrupts = <GIC_PPI 13
1271                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1272                              <GIC_PPI 14
1273                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1274                              <GIC_PPI 11
1275                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1276                              <GIC_PPI 10
1277                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1278                 interrupt-parent = <&gic>;
1279         };
1280 };