arch/ia64/include/asm/mmu_context.h

   1 #ifndef _ASM_IA64_MMU_CONTEXT_H
   2 #define _ASM_IA64_MMU_CONTEXT_H
   3
   4 /*
   5  * Copyright (C) 1998-2002 Hewlett-Packard Co
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  */
   8
   9 /*
  10  * Routines to manage the allocation of task context numbers.  Task context
  11  * numbers are used to reduce or eliminate the need to perform TLB flushes
  12  * due to context switches.  Context numbers are implemented using ia-64
  13  * region ids.  Since the IA-64 TLB does not consider the region number when
  14  * performing a TLB lookup, we need to assign a unique region id to each
  15  * region in a process.  We use the least significant three bits in aregion
  16  * id for this purpose.
  17  */
  18
  19 #define IA64_REGION_ID_KERNEL   0 /* the kernel's region id (tlb.c depends on this being 0) */
  20
  21 #define ia64_rid(ctx,addr)      (((ctx) << 3) | (addr >> 61))
  22
  23 # include <asm/page.h>
  24 # ifndef __ASSEMBLY__
  25
  26 #include <linux/compiler.h>
  27 #include <linux/percpu.h>
  28 #include <linux/sched.h>
  29 #include <linux/mm_types.h>
  30 #include <linux/spinlock.h>
  31
  32 #include <asm/processor.h>
  33 #include <asm-generic/mm_hooks.h>
  34
  35 struct ia64_ctx {
  36         spinlock_t lock;
  37         unsigned int next;      /* next context number to use */
  38         unsigned int limit;     /* available free range */
  39         unsigned int max_ctx;   /* max. context value supported by all CPUs */
  40                                 /* call wrap_mmu_context when next >= max */
  41         unsigned long *bitmap;  /* bitmap size is max_ctx+1 */
  42         unsigned long *flushmap;/* pending rid to be flushed */
  43 };
  44
  45 extern struct ia64_ctx ia64_ctx;
  46 DECLARE_PER_CPU(u8, ia64_need_tlb_flush);
  47
  48 extern void mmu_context_init (void);
  49 extern void wrap_mmu_context (struct mm_struct *mm);
  50
  51 static inline void
  52 enter_lazy_tlb (struct mm_struct *mm, struct task_struct *tsk)
  53 {
  54 }
  55
  56 /*
  57  * When the context counter wraps around all TLBs need to be flushed because
  58  * an old context number might have been reused. This is signalled by the
  59  * ia64_need_tlb_flush per-CPU variable, which is checked in the routine
  60  * below. Called by activate_mm(). <efocht@ess.nec.de>
  61  */
  62 static inline void
  63 delayed_tlb_flush (void)
  64 {
  65         extern void local_flush_tlb_all (void);
  66         unsigned long flags;
  67
  68         if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) {
  69                 spin_lock_irqsave(&ia64_ctx.lock, flags);
  70                 if (__ia64_per_cpu_var(ia64_need_tlb_flush)) {
  71                         local_flush_tlb_all();
  72                         __ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
  73                 }
  74                 spin_unlock_irqrestore(&ia64_ctx.lock, flags);
  75         }
  76 }
  77
  78 static inline nv_mm_context_t
  79 get_mmu_context (struct mm_struct *mm)
  80 {
  81         unsigned long flags;
  82         nv_mm_context_t context = mm->context;
  83
  84         if (likely(context))
  85                 goto out;
  86
  87         spin_lock_irqsave(&ia64_ctx.lock, flags);
  88         /* re-check, now that we've got the lock: */
  89         context = mm->context;
  90         if (context == 0) {
  91                 cpumask_clear(mm_cpumask(mm));
  92                 if (ia64_ctx.next >= ia64_ctx.limit) {
  93                         ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
  94                                         ia64_ctx.max_ctx, ia64_ctx.next);
  95                         ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
  96                                         ia64_ctx.max_ctx, ia64_ctx.next);
  97                         if (ia64_ctx.next >= ia64_ctx.max_ctx)
  98                                 wrap_mmu_context(mm);
  99                 }
 100                 mm->context = context = ia64_ctx.next++;
 101                 __set_bit(context, ia64_ctx.bitmap);
 102         }
 103         spin_unlock_irqrestore(&ia64_ctx.lock, flags);
 104 out:
 105         /*
 106          * Ensure we're not starting to use "context" before any old
 107          * uses of it are gone from our TLB.
 108          */
 109         delayed_tlb_flush();
 110
 111         return context;
 112 }
 113
 114 /*
 115  * Initialize context number to some sane value.  MM is guaranteed to be a
 116  * brand-new address-space, so no TLB flushing is needed, ever.
 117  */
 118 static inline int
 119 init_new_context (struct task_struct *p, struct mm_struct *mm)
 120 {
 121         mm->context = 0;
 122         return 0;
 123 }
 124
 125 static inline void
 126 destroy_context (struct mm_struct *mm)
 127 {
 128         /* Nothing to do.  */
 129 }
 130
 131 static inline void
 132 reload_context (nv_mm_context_t context)
 133 {
 134         unsigned long rid;
 135         unsigned long rid_incr = 0;
 136         unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4;
 137
 138         old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE));
 139         rid = context << 3;     /* make space for encoding the region number */
 140         rid_incr = 1 << 8;
 141
 142         /* encode the region id, preferred page size, and VHPT enable bit: */
 143         rr0 = (rid << 8) | (PAGE_SHIFT << 2) | 1;
 144         rr1 = rr0 + 1*rid_incr;
 145         rr2 = rr0 + 2*rid_incr;
 146         rr3 = rr0 + 3*rid_incr;
 147         rr4 = rr0 + 4*rid_incr;
 148 #ifdef  CONFIG_HUGETLB_PAGE
 149         rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc);
 150
 151 #  if RGN_HPAGE != 4
 152 #    error "reload_context assumes RGN_HPAGE is 4"
 153 #  endif
 154 #endif
 155
 156         ia64_set_rr0_to_rr4(rr0, rr1, rr2, rr3, rr4);
 157         ia64_srlz_i();                  /* srlz.i implies srlz.d */
 158 }
 159
 160 /*
 161  * Must be called with preemption off
 162  */
 163 static inline void
 164 activate_context (struct mm_struct *mm)
 165 {
 166         nv_mm_context_t context;
 167
 168         do {
 169                 context = get_mmu_context(mm);
 170                 if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
 171                         cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
 172                 reload_context(context);
 173                 /*
 174                  * in the unlikely event of a TLB-flush by another thread,
 175                  * redo the load.
 176                  */
 177         } while (unlikely(context != mm->context));
 178 }
 179
 180 #define deactivate_mm(tsk,mm)   do { } while (0)
 181
 182 /*
 183  * Switch from address space PREV to address space NEXT.
 184  */
 185 static inline void
 186 activate_mm (struct mm_struct *prev, struct mm_struct *next)
 187 {
 188         /*
 189          * We may get interrupts here, but that's OK because interrupt
 190          * handlers cannot touch user-space.
 191          */
 192         ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd));
 193         activate_context(next);
 194 }
 195
 196 #define switch_mm(prev_mm,next_mm,next_task)    activate_mm(prev_mm, next_mm)
 197
 198 # endif /* ! __ASSEMBLY__ */
 199 #endif /* _ASM_IA64_MMU_CONTEXT_H */