| blob | ff8511d6d8eadbd03e48ce9c0b639c8d3c80e8aa |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 *
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
14 *
15 * This file contains the entry point for the 64-bit kernel along
16 * with some early initialization code common to all 64-bit powerpc
17 * variants.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
25 #include <linux/threads.h>
26 #include <linux/init.h>
27 #include <asm/reg.h>
28 #include <asm/page.h>
29 #include <asm/mmu.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/head-64.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/bug.h>
34 #include <asm/cputable.h>
35 #include <asm/setup.h>
36 #include <asm/hvcall.h>
37 #include <asm/thread_info.h>
38 #include <asm/firmware.h>
39 #include <asm/page_64.h>
40 #include <asm/irqflags.h>
41 #include <asm/kvm_book3s_asm.h>
42 #include <asm/ptrace.h>
43 #include <asm/hw_irq.h>
44 #include <asm/cputhreads.h>
45 #include <asm/ppc-opcode.h>
46 #include <asm/export.h>
48 /* The physical memory is laid out such that the secondary processor
49 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
50 * using the layout described in exceptions-64s.S
51 */
53 /*
54 * Entering into this code we make the following assumptions:
55 *
56 * For pSeries or server processors:
57 * 1. The MMU is off & open firmware is running in real mode.
58 * 2. The kernel is entered at __start
59 * -or- For OPAL entry:
60 * 1. The MMU is off, processor in HV mode, primary CPU enters at 0
61 * with device-tree in gpr3. We also get OPAL base in r8 and
62 * entry in r9 for debugging purposes
63 * 2. Secondary processors enter at 0x60 with PIR in gpr3
64 *
65 * For Book3E processors:
66 * 1. The MMU is on running in AS0 in a state defined in ePAPR
67 * 2. The kernel is entered at __start
68 */
70 OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
71 USE_FIXED_SECTION(first_256B)
72 /*
73 * Offsets are relative from the start of fixed section, and
74 * first_256B starts at 0. Offsets are a bit easier to use here
75 * than the fixed section entry macros.
76 */
77 . = 0x0
78 _GLOBAL(__start)
79 /* NOP this out unconditionally */
80 BEGIN_FTR_SECTION
81 FIXUP_ENDIAN
82 b __start_initialization_multiplatform
83 END_FTR_SECTION(0, 1)
85 /* Catch branch to 0 in real mode */
86 trap
88 /* Secondary processors spin on this value until it becomes non-zero.
89 * When non-zero, it contains the real address of the function the cpu
90 * should jump to.
91 */
92 .balign 8
93 .globl __secondary_hold_spinloop
94 __secondary_hold_spinloop:
95 .8byte 0x0
97 /* Secondary processors write this value with their cpu # */
98 /* after they enter the spin loop immediately below. */
99 .globl __secondary_hold_acknowledge
100 __secondary_hold_acknowledge:
101 .8byte 0x0
103 #ifdef CONFIG_RELOCATABLE
104 /* This flag is set to 1 by a loader if the kernel should run
105 * at the loaded address instead of the linked address. This
106 * is used by kexec-tools to keep the the kdump kernel in the
107 * crash_kernel region. The loader is responsible for
108 * observing the alignment requirement.
109 */
111 #ifdef CONFIG_RELOCATABLE_TEST
112 #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */
113 #else
114 #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */
115 #endif
117 /* Do not move this variable as kexec-tools knows about it. */
118 . = 0x5c
119 .globl __run_at_load
120 __run_at_load:
121 DEFINE_FIXED_SYMBOL(__run_at_load)
122 .long RUN_AT_LOAD_DEFAULT
123 #endif
125 . = 0x60
126 /*
127 * The following code is used to hold secondary processors
128 * in a spin loop after they have entered the kernel, but
129 * before the bulk of the kernel has been relocated. This code
130 * is relocated to physical address 0x60 before prom_init is run.
131 * All of it must fit below the first exception vector at 0x100.
132 * Use .globl here not _GLOBAL because we want __secondary_hold
133 * to be the actual text address, not a descriptor.
134 */
135 .globl __secondary_hold
136 __secondary_hold:
137 FIXUP_ENDIAN
138 #ifndef CONFIG_PPC_BOOK3E
139 mfmsr r24
140 ori r24,r24,MSR_RI
141 mtmsrd r24 /* RI on */
142 #endif
143 /* Grab our physical cpu number */
144 mr r24,r3
145 /* stash r4 for book3e */
146 mr r25,r4
148 /* Tell the master cpu we're here */
149 /* Relocation is off & we are located at an address less */
150 /* than 0x100, so only need to grab low order offset. */
151 std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0)
152 sync
154 li r26,0
155 #ifdef CONFIG_PPC_BOOK3E
156 tovirt(r26,r26)
157 #endif
158 /* All secondary cpus wait here until told to start. */
159 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26)
160 cmpdi 0,r12,0
161 beq 100b
163 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
164 #ifdef CONFIG_PPC_BOOK3E
165 tovirt(r12,r12)
166 #endif
167 mtctr r12
168 mr r3,r24
169 /*
170 * it may be the case that other platforms have r4 right to
171 * begin with, this gives us some safety in case it is not
172 */
173 #ifdef CONFIG_PPC_BOOK3E
174 mr r4,r25
175 #else
176 li r4,0
177 #endif
178 /* Make sure that patched code is visible */
179 isync
180 bctr
181 #else
182 BUG_OPCODE
183 #endif
184 CLOSE_FIXED_SECTION(first_256B)
186 /* This value is used to mark exception frames on the stack. */
187 .section ".toc","aw"
188 exception_marker:
189 .tc ID_72656773_68657265[TC],0x7265677368657265
190 .previous
192 /*
193 * On server, we include the exception vectors code here as it
194 * relies on absolute addressing which is only possible within
195 * this compilation unit
196 */
197 #ifdef CONFIG_PPC_BOOK3S
198 #include "exceptions-64s.S"
199 #else
200 OPEN_TEXT_SECTION(0x100)
201 #endif
203 USE_TEXT_SECTION()
205 #ifdef CONFIG_PPC_BOOK3E
206 /*
207 * The booting_thread_hwid holds the thread id we want to boot in cpu
208 * hotplug case. It is set by cpu hotplug code, and is invalid by default.
209 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
210 * bit field.
211 */
212 .globl booting_thread_hwid
213 booting_thread_hwid:
214 .long INVALID_THREAD_HWID
215 .align 3
216 /*
217 * start a thread in the same core
218 * input parameters:
219 * r3 = the thread physical id
220 * r4 = the entry point where thread starts
221 */
222 _GLOBAL(book3e_start_thread)
223 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
224 cmpwi r3, 0
225 beq 10f
226 cmpwi r3, 1
227 beq 11f
228 /* If the thread id is invalid, just exit. */
229 b 13f
230 10:
231 MTTMR(TMRN_IMSR0, 5)
232 MTTMR(TMRN_INIA0, 4)
233 b 12f
234 11:
235 MTTMR(TMRN_IMSR1, 5)
236 MTTMR(TMRN_INIA1, 4)
237 12:
238 isync
239 li r6, 1
240 sld r6, r6, r3
241 mtspr SPRN_TENS, r6
242 13:
243 blr
245 /*
246 * stop a thread in the same core
247 * input parameter:
248 * r3 = the thread physical id
249 */
250 _GLOBAL(book3e_stop_thread)
251 cmpwi r3, 0
252 beq 10f
253 cmpwi r3, 1
254 beq 10f
255 /* If the thread id is invalid, just exit. */
256 b 13f
257 10:
258 li r4, 1
259 sld r4, r4, r3
260 mtspr SPRN_TENC, r4
261 13:
262 blr
264 _GLOBAL(fsl_secondary_thread_init)
265 mfspr r4,SPRN_BUCSR
267 /* Enable branch prediction */
268 lis r3,BUCSR_INIT@h
269 ori r3,r3,BUCSR_INIT@l
270 mtspr SPRN_BUCSR,r3
271 isync
273 /*
274 * Fix PIR to match the linear numbering in the device tree.
275 *
276 * On e6500, the reset value of PIR uses the low three bits for
277 * the thread within a core, and the upper bits for the core
278 * number. There are two threads per core, so shift everything
279 * but the low bit right by two bits so that the cpu numbering is
280 * continuous.
281 *
282 * If the old value of BUCSR is non-zero, this thread has run
283 * before. Thus, we assume we are coming from kexec or a similar
284 * scenario, and PIR is already set to the correct value. This
285 * is a bit of a hack, but there are limited opportunities for
286 * getting information into the thread and the alternatives
287 * seemed like they'd be overkill. We can't tell just by looking
288 * at the old PIR value which state it's in, since the same value
289 * could be valid for one thread out of reset and for a different
290 * thread in Linux.
291 */
293 mfspr r3, SPRN_PIR
294 cmpwi r4,0
295 bne 1f
296 rlwimi r3, r3, 30, 2, 30
297 mtspr SPRN_PIR, r3
298 1:
299 #endif
301 _GLOBAL(generic_secondary_thread_init)
302 mr r24,r3
304 /* turn on 64-bit mode */
305 bl enable_64b_mode
307 /* get a valid TOC pointer, wherever we're mapped at */
308 bl relative_toc
309 tovirt(r2,r2)
311 #ifdef CONFIG_PPC_BOOK3E
312 /* Book3E initialization */
313 mr r3,r24
314 bl book3e_secondary_thread_init
315 #endif
316 b generic_secondary_common_init
318 /*
319 * On pSeries and most other platforms, secondary processors spin
320 * in the following code.
321 * At entry, r3 = this processor's number (physical cpu id)
322 *
323 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
324 * this core already exists (setup via some other mechanism such
325 * as SCOM before entry).
326 */
327 _GLOBAL(generic_secondary_smp_init)
328 FIXUP_ENDIAN
329 mr r24,r3
330 mr r25,r4
332 /* turn on 64-bit mode */
333 bl enable_64b_mode
335 /* get a valid TOC pointer, wherever we're mapped at */
336 bl relative_toc
337 tovirt(r2,r2)
339 #ifdef CONFIG_PPC_BOOK3E
340 /* Book3E initialization */
341 mr r3,r24
342 mr r4,r25
343 bl book3e_secondary_core_init
345 /*
346 * After common core init has finished, check if the current thread is the
347 * one we wanted to boot. If not, start the specified thread and stop the
348 * current thread.
349 */
350 LOAD_REG_ADDR(r4, booting_thread_hwid)
351 lwz r3, 0(r4)
352 li r5, INVALID_THREAD_HWID
353 cmpw r3, r5
354 beq 20f
356 /*
357 * The value of booting_thread_hwid has been stored in r3,
358 * so make it invalid.
359 */
360 stw r5, 0(r4)
362 /*
363 * Get the current thread id and check if it is the one we wanted.
364 * If not, start the one specified in booting_thread_hwid and stop
365 * the current thread.
366 */
367 mfspr r8, SPRN_TIR
368 cmpw r3, r8
369 beq 20f
371 /* start the specified thread */
372 LOAD_REG_ADDR(r5, fsl_secondary_thread_init)
373 ld r4, 0(r5)
374 bl book3e_start_thread
376 /* stop the current thread */
377 mr r3, r8
378 bl book3e_stop_thread
379 10:
380 b 10b
381 20:
382 #endif
384 generic_secondary_common_init:
385 /* Set up a paca value for this processor. Since we have the
386 * physical cpu id in r24, we need to search the pacas to find
387 * which logical id maps to our physical one.
388 */
389 LOAD_REG_ADDR(r13, paca) /* Load paca pointer */
390 ld r13,0(r13) /* Get base vaddr of paca array */
391 #ifndef CONFIG_SMP
392 addi r13,r13,PACA_SIZE /* know r13 if used accidentally */
393 b kexec_wait /* wait for next kernel if !SMP */
394 #else
395 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
396 lwz r7,0(r7) /* also the max paca allocated */
397 li r5,0 /* logical cpu id */
398 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
399 cmpw r6,r24 /* Compare to our id */
400 beq 2f
401 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
402 addi r5,r5,1
403 cmpw r5,r7 /* Check if more pacas exist */
404 blt 1b
406 mr r3,r24 /* not found, copy phys to r3 */
407 b kexec_wait /* next kernel might do better */
409 2: SET_PACA(r13)
410 #ifdef CONFIG_PPC_BOOK3E
411 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
412 mtspr SPRN_SPRG_TLB_EXFRAME,r12
413 #endif
415 /* From now on, r24 is expected to be logical cpuid */
416 mr r24,r5
418 /* See if we need to call a cpu state restore handler */
419 LOAD_REG_ADDR(r23, cur_cpu_spec)
420 ld r23,0(r23)
421 ld r12,CPU_SPEC_RESTORE(r23)
422 cmpdi 0,r12,0
423 beq 3f
424 #ifdef PPC64_ELF_ABI_v1
425 ld r12,0(r12)
426 #endif
427 mtctr r12
428 bctrl
430 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
431 lwarx r4,0,r3
432 subi r4,r4,1
433 stwcx. r4,0,r3
434 bne 3b
435 isync
437 4: HMT_LOW
438 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
439 /* start. */
440 cmpwi 0,r23,0
441 beq 4b /* Loop until told to go */
443 sync /* order paca.run and cur_cpu_spec */
444 isync /* In case code patching happened */
446 /* Create a temp kernel stack for use before relocation is on. */
447 ld r1,PACAEMERGSP(r13)
448 subi r1,r1,STACK_FRAME_OVERHEAD
450 b __secondary_start
451 #endif /* SMP */
453 /*
454 * Turn the MMU off.
455 * Assumes we're mapped EA == RA if the MMU is on.
456 */
457 #ifdef CONFIG_PPC_BOOK3S
458 __mmu_off:
459 mfmsr r3
460 andi. r0,r3,MSR_IR|MSR_DR
461 beqlr
462 mflr r4
463 andc r3,r3,r0
464 mtspr SPRN_SRR0,r4
465 mtspr SPRN_SRR1,r3
466 sync
467 rfid
468 b . /* prevent speculative execution */
469 #endif
472 /*
473 * Here is our main kernel entry point. We support currently 2 kind of entries
474 * depending on the value of r5.
475 *
476 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
477 * in r3...r7
478 *
479 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
480 * DT block, r4 is a physical pointer to the kernel itself
481 *
482 */
483 __start_initialization_multiplatform:
484 /* Make sure we are running in 64 bits mode */
485 bl enable_64b_mode
487 /* Get TOC pointer (current runtime address) */
488 bl relative_toc
490 /* find out where we are now */
491 bcl 20,31,$+4
492 0: mflr r26 /* r26 = runtime addr here */
493 addis r26,r26,(_stext - 0b)@ha
494 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
496 /*
497 * Are we booted from a PROM Of-type client-interface ?
498 */
499 cmpldi cr0,r5,0
500 beq 1f
501 b __boot_from_prom /* yes -> prom */
502 1:
503 /* Save parameters */
504 mr r31,r3
505 mr r30,r4
506 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
507 /* Save OPAL entry */
508 mr r28,r8
509 mr r29,r9
510 #endif
512 #ifdef CONFIG_PPC_BOOK3E
513 bl start_initialization_book3e
514 b __after_prom_start
515 #else
516 /* Setup some critical 970 SPRs before switching MMU off */
517 mfspr r0,SPRN_PVR
518 srwi r0,r0,16
519 cmpwi r0,0x39 /* 970 */
520 beq 1f
521 cmpwi r0,0x3c /* 970FX */
522 beq 1f
523 cmpwi r0,0x44 /* 970MP */
524 beq 1f
525 cmpwi r0,0x45 /* 970GX */
526 bne 2f
527 1: bl __cpu_preinit_ppc970
528 2:
530 /* Switch off MMU if not already off */
531 bl __mmu_off
532 b __after_prom_start
533 #endif /* CONFIG_PPC_BOOK3E */
535 __boot_from_prom:
536 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
537 /* Save parameters */
538 mr r31,r3
539 mr r30,r4
540 mr r29,r5
541 mr r28,r6
542 mr r27,r7
544 /*
545 * Align the stack to 16-byte boundary
546 * Depending on the size and layout of the ELF sections in the initial
547 * boot binary, the stack pointer may be unaligned on PowerMac
548 */
549 rldicr r1,r1,0,59
551 #ifdef CONFIG_RELOCATABLE
552 /* Relocate code for where we are now */
553 mr r3,r26
554 bl relocate
555 #endif
557 /* Restore parameters */
558 mr r3,r31
559 mr r4,r30
560 mr r5,r29
561 mr r6,r28
562 mr r7,r27
564 /* Do all of the interaction with OF client interface */
565 mr r8,r26
566 bl prom_init
567 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
569 /* We never return. We also hit that trap if trying to boot
570 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
571 trap
573 __after_prom_start:
574 #ifdef CONFIG_RELOCATABLE
575 /* process relocations for the final address of the kernel */
576 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
577 sldi r25,r25,32
578 #if defined(CONFIG_PPC_BOOK3E)
579 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
580 #endif
581 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
582 #if defined(CONFIG_PPC_BOOK3E)
583 tophys(r26,r26)
584 #endif
585 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
586 bne 1f
587 add r25,r25,r26
588 1: mr r3,r25
589 bl relocate
590 #if defined(CONFIG_PPC_BOOK3E)
591 /* IVPR needs to be set after relocation. */
592 bl init_core_book3e
593 #endif
594 #endif
596 /*
597 * We need to run with _stext at physical address PHYSICAL_START.
598 * This will leave some code in the first 256B of
599 * real memory, which are reserved for software use.
600 *
601 * Note: This process overwrites the OF exception vectors.
602 */
603 li r3,0 /* target addr */
604 #ifdef CONFIG_PPC_BOOK3E
605 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
606 #endif
607 mr. r4,r26 /* In some cases the loader may */
608 #if defined(CONFIG_PPC_BOOK3E)
609 tovirt(r4,r4)
610 #endif
611 beq 9f /* have already put us at zero */
612 li r6,0x100 /* Start offset, the first 0x100 */
613 /* bytes were copied earlier. */
615 #ifdef CONFIG_RELOCATABLE
616 /*
617 * Check if the kernel has to be running as relocatable kernel based on the
618 * variable __run_at_load, if it is set the kernel is treated as relocatable
619 * kernel, otherwise it will be moved to PHYSICAL_START
620 */
621 #if defined(CONFIG_PPC_BOOK3E)
622 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
623 #endif
624 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
625 cmplwi cr0,r7,1
626 bne 3f
628 #ifdef CONFIG_PPC_BOOK3E
629 LOAD_REG_ADDR(r5, __end_interrupts)
630 LOAD_REG_ADDR(r11, _stext)
631 sub r5,r5,r11
632 #else
633 /* just copy interrupts */
634 LOAD_REG_IMMEDIATE(r5, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
635 #endif
636 b 5f
637 3:
638 #endif
639 /* # bytes of memory to copy */
640 lis r5,(ABS_ADDR(copy_to_here))@ha
641 addi r5,r5,(ABS_ADDR(copy_to_here))@l
643 bl copy_and_flush /* copy the first n bytes */
644 /* this includes the code being */
645 /* executed here. */
646 /* Jump to the copy of this code that we just made */
647 addis r8,r3,(ABS_ADDR(4f))@ha
648 addi r12,r8,(ABS_ADDR(4f))@l
649 mtctr r12
650 bctr
652 .balign 8
653 p_end: .8byte _end - copy_to_here
655 4:
656 /*
657 * Now copy the rest of the kernel up to _end, add
658 * _end - copy_to_here to the copy limit and run again.
659 */
660 addis r8,r26,(ABS_ADDR(p_end))@ha
661 ld r8,(ABS_ADDR(p_end))@l(r8)
662 add r5,r5,r8
663 5: bl copy_and_flush /* copy the rest */
665 9: b start_here_multiplatform
667 /*
668 * Copy routine used to copy the kernel to start at physical address 0
669 * and flush and invalidate the caches as needed.
670 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
671 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
672 *
673 * Note: this routine *only* clobbers r0, r6 and lr
674 */
675 _GLOBAL(copy_and_flush)
676 addi r5,r5,-8
677 addi r6,r6,-8
678 4: li r0,8 /* Use the smallest common */
679 /* denominator cache line */
680 /* size. This results in */
681 /* extra cache line flushes */
682 /* but operation is correct. */
683 /* Can't get cache line size */
684 /* from NACA as it is being */
685 /* moved too. */
687 mtctr r0 /* put # words/line in ctr */
688 3: addi r6,r6,8 /* copy a cache line */
689 ldx r0,r6,r4
690 stdx r0,r6,r3
691 bdnz 3b
692 dcbst r6,r3 /* write it to memory */
693 sync
694 icbi r6,r3 /* flush the icache line */
695 cmpld 0,r6,r5
696 blt 4b
697 sync
698 addi r5,r5,8
699 addi r6,r6,8
700 isync
701 blr
703 .align 8
704 copy_to_here:
706 #ifdef CONFIG_SMP
707 #ifdef CONFIG_PPC_PMAC
708 /*
709 * On PowerMac, secondary processors starts from the reset vector, which
710 * is temporarily turned into a call to one of the functions below.
711 */
712 .section ".text";
713 .align 2 ;
715 .globl __secondary_start_pmac_0
716 __secondary_start_pmac_0:
717 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
718 li r24,0
719 b 1f
720 li r24,1
721 b 1f
722 li r24,2
723 b 1f
724 li r24,3
725 1:
727 _GLOBAL(pmac_secondary_start)
728 /* turn on 64-bit mode */
729 bl enable_64b_mode
731 li r0,0
732 mfspr r3,SPRN_HID4
733 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
734 sync
735 mtspr SPRN_HID4,r3
736 isync
737 sync
738 slbia
740 /* get TOC pointer (real address) */
741 bl relative_toc
742 tovirt(r2,r2)
744 /* Copy some CPU settings from CPU 0 */
745 bl __restore_cpu_ppc970
747 /* pSeries do that early though I don't think we really need it */
748 mfmsr r3
749 ori r3,r3,MSR_RI
750 mtmsrd r3 /* RI on */
752 /* Set up a paca value for this processor. */
753 LOAD_REG_ADDR(r4,paca) /* Load paca pointer */
754 ld r4,0(r4) /* Get base vaddr of paca array */
755 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
756 add r13,r13,r4 /* for this processor. */
757 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
759 /* Mark interrupts soft and hard disabled (they might be enabled
760 * in the PACA when doing hotplug)
761 */
762 li r0,0
763 stb r0,PACASOFTIRQEN(r13)
764 li r0,PACA_IRQ_HARD_DIS
765 stb r0,PACAIRQHAPPENED(r13)
767 /* Create a temp kernel stack for use before relocation is on. */
768 ld r1,PACAEMERGSP(r13)
769 subi r1,r1,STACK_FRAME_OVERHEAD
771 b __secondary_start
773 #endif /* CONFIG_PPC_PMAC */
775 /*
776 * This function is called after the master CPU has released the
777 * secondary processors. The execution environment is relocation off.
778 * The paca for this processor has the following fields initialized at
779 * this point:
780 * 1. Processor number
781 * 2. Segment table pointer (virtual address)
782 * On entry the following are set:
783 * r1 = stack pointer (real addr of temp stack)
784 * r24 = cpu# (in Linux terms)
785 * r13 = paca virtual address
786 * SPRG_PACA = paca virtual address
787 */
788 .section ".text";
789 .align 2 ;
791 .globl __secondary_start
792 __secondary_start:
793 /* Set thread priority to MEDIUM */
794 HMT_MEDIUM
796 /* Initialize the kernel stack */
797 LOAD_REG_ADDR(r3, current_set)
798 sldi r28,r24,3 /* get current_set[cpu#] */
799 ldx r14,r3,r28
800 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD
801 std r14,PACAKSAVE(r13)
803 /* Do early setup for that CPU (SLB and hash table pointer) */
804 bl early_setup_secondary
806 /*
807 * setup the new stack pointer, but *don't* use this until
808 * translation is on.
809 */
810 mr r1, r14
812 /* Clear backchain so we get nice backtraces */
813 li r7,0
814 mtlr r7
816 /* Mark interrupts soft and hard disabled (they might be enabled
817 * in the PACA when doing hotplug)
818 */
819 stb r7,PACASOFTIRQEN(r13)
820 li r0,PACA_IRQ_HARD_DIS
821 stb r0,PACAIRQHAPPENED(r13)
823 /* enable MMU and jump to start_secondary */
824 LOAD_REG_ADDR(r3, start_secondary_prolog)
825 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
827 mtspr SPRN_SRR0,r3
828 mtspr SPRN_SRR1,r4
829 RFI
830 b . /* prevent speculative execution */
832 /*
833 * Running with relocation on at this point. All we want to do is
834 * zero the stack back-chain pointer and get the TOC virtual address
835 * before going into C code.
836 */
837 start_secondary_prolog:
838 ld r2,PACATOC(r13)
839 li r3,0
840 std r3,0(r1) /* Zero the stack frame pointer */
841 bl start_secondary
842 b .
843 /*
844 * Reset stack pointer and call start_secondary
845 * to continue with online operation when woken up
846 * from cede in cpu offline.
847 */
848 _GLOBAL(start_secondary_resume)
849 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
850 li r3,0
851 std r3,0(r1) /* Zero the stack frame pointer */
852 bl start_secondary
853 b .
854 #endif
856 /*
857 * This subroutine clobbers r11 and r12
858 */
859 enable_64b_mode:
860 mfmsr r11 /* grab the current MSR */
861 #ifdef CONFIG_PPC_BOOK3E
862 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
863 mtmsr r11
864 #else /* CONFIG_PPC_BOOK3E */
865 li r12,(MSR_64BIT | MSR_ISF)@highest
866 sldi r12,r12,48
867 or r11,r11,r12
868 mtmsrd r11
869 isync
870 #endif
871 blr
873 /*
874 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
875 * by the toolchain). It computes the correct value for wherever we
876 * are running at the moment, using position-independent code.
877 *
878 * Note: The compiler constructs pointers using offsets from the
879 * TOC in -mcmodel=medium mode. After we relocate to 0 but before
880 * the MMU is on we need our TOC to be a virtual address otherwise
881 * these pointers will be real addresses which may get stored and
882 * accessed later with the MMU on. We use tovirt() at the call
883 * sites to handle this.
884 */
885 _GLOBAL(relative_toc)
886 mflr r0
887 bcl 20,31,$+4
888 0: mflr r11
889 ld r2,(p_toc - 0b)(r11)
890 add r2,r2,r11
891 mtlr r0
892 blr
894 .balign 8
895 p_toc: .8byte __toc_start + 0x8000 - 0b
897 /*
898 * This is where the main kernel code starts.
899 */
900 start_here_multiplatform:
901 /* set up the TOC */
902 bl relative_toc
903 tovirt(r2,r2)
905 /* Clear out the BSS. It may have been done in prom_init,
906 * already but that's irrelevant since prom_init will soon
907 * be detached from the kernel completely. Besides, we need
908 * to clear it now for kexec-style entry.
909 */
910 LOAD_REG_ADDR(r11,__bss_stop)
911 LOAD_REG_ADDR(r8,__bss_start)
912 sub r11,r11,r8 /* bss size */
913 addi r11,r11,7 /* round up to an even double word */
914 srdi. r11,r11,3 /* shift right by 3 */
915 beq 4f
916 addi r8,r8,-8
917 li r0,0
918 mtctr r11 /* zero this many doublewords */
919 3: stdu r0,8(r8)
920 bdnz 3b
921 4:
923 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
924 /* Setup OPAL entry */
925 LOAD_REG_ADDR(r11, opal)
926 std r28,0(r11);
927 std r29,8(r11);
928 #endif
930 #ifndef CONFIG_PPC_BOOK3E
931 mfmsr r6
932 ori r6,r6,MSR_RI
933 mtmsrd r6 /* RI on */
934 #endif
936 #ifdef CONFIG_RELOCATABLE
937 /* Save the physical address we're running at in kernstart_addr */
938 LOAD_REG_ADDR(r4, kernstart_addr)
939 clrldi r0,r25,2
940 std r0,0(r4)
941 #endif
943 /* The following gets the stack set up with the regs */
944 /* pointing to the real addr of the kernel stack. This is */
945 /* all done to support the C function call below which sets */
946 /* up the htab. This is done because we have relocated the */
947 /* kernel but are still running in real mode. */
949 LOAD_REG_ADDR(r3,init_thread_union)
951 /* set up a stack pointer */
952 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
953 add r1,r3,r1
954 li r0,0
955 stdu r0,-STACK_FRAME_OVERHEAD(r1)
957 /*
958 * Do very early kernel initializations, including initial hash table
959 * and SLB setup before we turn on relocation.
960 */
962 /* Restore parameters passed from prom_init/kexec */
963 mr r3,r31
964 bl early_setup /* also sets r13 and SPRG_PACA */
966 LOAD_REG_ADDR(r3, start_here_common)
967 ld r4,PACAKMSR(r13)
968 mtspr SPRN_SRR0,r3
969 mtspr SPRN_SRR1,r4
970 RFI
971 b . /* prevent speculative execution */
973 /* This is where all platforms converge execution */
975 start_here_common:
976 /* relocation is on at this point */
977 std r1,PACAKSAVE(r13)
979 /* Load the TOC (virtual address) */
980 ld r2,PACATOC(r13)
982 /* Mark interrupts soft and hard disabled (they might be enabled
983 * in the PACA when doing hotplug)
984 */
985 li r0,0
986 stb r0,PACASOFTIRQEN(r13)
987 li r0,PACA_IRQ_HARD_DIS
988 stb r0,PACAIRQHAPPENED(r13)
990 /* Generic kernel entry */
991 bl start_kernel
993 /* Not reached */
994 BUG_OPCODE
996 /*
997 * We put a few things here that have to be page-aligned.
998 * This stuff goes at the beginning of the bss, which is page-aligned.
999 */
1000 .section ".bss"
1001 /*
1002 * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K.
1003 * We will need to find a better way to fix this
1004 */
1005 .align 16
1007 .globl swapper_pg_dir
1008 swapper_pg_dir:
1009 .space PGD_TABLE_SIZE
1011 .globl empty_zero_page
1012 empty_zero_page:
1013 .space PAGE_SIZE
1014 EXPORT_SYMBOL(empty_zero_page)