| blob | bf4c6021515f8aedff5a8c2cfc39f37b39850982 |
1 /*
2 * Kernel execution entry point code.
3 *
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Rewritten for PReP
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
26 *
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
31 */
33 #include <linux/init.h>
34 #include <linux/threads.h>
35 #include <asm/processor.h>
36 #include <asm/page.h>
37 #include <asm/mmu.h>
38 #include <asm/pgtable.h>
39 #include <asm/cputable.h>
40 #include <asm/thread_info.h>
41 #include <asm/ppc_asm.h>
42 #include <asm/asm-offsets.h>
43 #include <asm/cache.h>
44 #include <asm/ptrace.h>
45 #include <asm/export.h>
46 #include "head_booke.h"
48 /* As with the other PowerPC ports, it is expected that when code
49 * execution begins here, the following registers contain valid, yet
50 * optional, information:
51 *
52 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
53 * r4 - Starting address of the init RAM disk
54 * r5 - Ending address of the init RAM disk
55 * r6 - Start of kernel command line string (e.g. "mem=128")
56 * r7 - End of kernel command line string
57 *
58 */
59 __HEAD
60 _ENTRY(_stext);
61 _ENTRY(_start);
62 /*
63 * Reserve a word at a fixed location to store the address
64 * of abatron_pteptrs
65 */
66 nop
68 /* Translate device tree address to physical, save in r30/r31 */
69 bl get_phys_addr
70 mr r30,r3
71 mr r31,r4
73 li r25,0 /* phys kernel start (low) */
74 li r24,0 /* CPU number */
75 li r23,0 /* phys kernel start (high) */
77 #ifdef CONFIG_RELOCATABLE
78 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */
80 /* Translate _stext address to physical, save in r23/r25 */
81 bl get_phys_addr
82 mr r23,r3
83 mr r25,r4
85 bl 0f
86 0: mflr r8
87 addis r3,r8,(is_second_reloc - 0b)@ha
88 lwz r19,(is_second_reloc - 0b)@l(r3)
90 /* Check if this is the second relocation. */
91 cmpwi r19,1
92 bne 1f
94 /*
95 * For the second relocation, we already get the real memstart_addr
96 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
97 * then the virtual address of start kernel should be:
98 * PAGE_OFFSET + (kernstart_addr - memstart_addr)
99 * Since the offset between kernstart_addr and memstart_addr should
100 * never be beyond 1G, so we can just use the lower 32bit of them
101 * for the calculation.
102 */
103 lis r3,PAGE_OFFSET@h
105 addis r4,r8,(kernstart_addr - 0b)@ha
106 addi r4,r4,(kernstart_addr - 0b)@l
107 lwz r5,4(r4)
109 addis r6,r8,(memstart_addr - 0b)@ha
110 addi r6,r6,(memstart_addr - 0b)@l
111 lwz r7,4(r6)
113 subf r5,r7,r5
114 add r3,r3,r5
115 b 2f
117 1:
118 /*
119 * We have the runtime (virutal) address of our base.
120 * We calculate our shift of offset from a 64M page.
121 * We could map the 64M page we belong to at PAGE_OFFSET and
122 * get going from there.
123 */
124 lis r4,KERNELBASE@h
125 ori r4,r4,KERNELBASE@l
126 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */
127 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
128 subf r3,r5,r6 /* r3 = r6 - r5 */
129 add r3,r4,r3 /* Required Virtual Address */
131 2: bl relocate
133 /*
134 * For the second relocation, we already set the right tlb entries
135 * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
136 */
137 cmpwi r19,1
138 beq set_ivor
139 #endif
141 /* We try to not make any assumptions about how the boot loader
142 * setup or used the TLBs. We invalidate all mappings from the
143 * boot loader and load a single entry in TLB1[0] to map the
144 * first 64M of kernel memory. Any boot info passed from the
145 * bootloader needs to live in this first 64M.
146 *
147 * Requirement on bootloader:
148 * - The page we're executing in needs to reside in TLB1 and
149 * have IPROT=1. If not an invalidate broadcast could
150 * evict the entry we're currently executing in.
151 *
152 * r3 = Index of TLB1 were executing in
153 * r4 = Current MSR[IS]
154 * r5 = Index of TLB1 temp mapping
155 *
156 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
157 * if needed
158 */
160 _ENTRY(__early_start)
162 #define ENTRY_MAPPING_BOOT_SETUP
163 #include "fsl_booke_entry_mapping.S"
164 #undef ENTRY_MAPPING_BOOT_SETUP
166 set_ivor:
167 /* Establish the interrupt vector offsets */
168 SET_IVOR(0, CriticalInput);
169 SET_IVOR(1, MachineCheck);
170 SET_IVOR(2, DataStorage);
171 SET_IVOR(3, InstructionStorage);
172 SET_IVOR(4, ExternalInput);
173 SET_IVOR(5, Alignment);
174 SET_IVOR(6, Program);
175 SET_IVOR(7, FloatingPointUnavailable);
176 SET_IVOR(8, SystemCall);
177 SET_IVOR(9, AuxillaryProcessorUnavailable);
178 SET_IVOR(10, Decrementer);
179 SET_IVOR(11, FixedIntervalTimer);
180 SET_IVOR(12, WatchdogTimer);
181 SET_IVOR(13, DataTLBError);
182 SET_IVOR(14, InstructionTLBError);
183 SET_IVOR(15, DebugCrit);
185 /* Establish the interrupt vector base */
186 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
187 mtspr SPRN_IVPR,r4
189 /* Setup the defaults for TLB entries */
190 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
191 #ifdef CONFIG_E200
192 oris r2,r2,MAS4_TLBSELD(1)@h
193 #endif
194 mtspr SPRN_MAS4, r2
196 #if 0
197 /* Enable DOZE */
198 mfspr r2,SPRN_HID0
199 oris r2,r2,HID0_DOZE@h
200 mtspr SPRN_HID0, r2
201 #endif
203 #if !defined(CONFIG_BDI_SWITCH)
204 /*
205 * The Abatron BDI JTAG debugger does not tolerate others
206 * mucking with the debug registers.
207 */
208 lis r2,DBCR0_IDM@h
209 mtspr SPRN_DBCR0,r2
210 isync
211 /* clear any residual debug events */
212 li r2,-1
213 mtspr SPRN_DBSR,r2
214 #endif
216 #ifdef CONFIG_SMP
217 /* Check to see if we're the second processor, and jump
218 * to the secondary_start code if so
219 */
220 LOAD_REG_ADDR_PIC(r24, boot_cpuid)
221 lwz r24, 0(r24)
222 cmpwi r24, -1
223 mfspr r24,SPRN_PIR
224 bne __secondary_start
225 #endif
227 /*
228 * This is where the main kernel code starts.
229 */
231 /* ptr to current */
232 lis r2,init_task@h
233 ori r2,r2,init_task@l
235 /* ptr to current thread */
236 addi r4,r2,THREAD /* init task's THREAD */
237 mtspr SPRN_SPRG_THREAD,r4
239 /* stack */
240 lis r1,init_thread_union@h
241 ori r1,r1,init_thread_union@l
242 li r0,0
243 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
245 CURRENT_THREAD_INFO(r22, r1)
246 stw r24, TI_CPU(r22)
248 bl early_init
250 #ifdef CONFIG_RELOCATABLE
251 mr r3,r30
252 mr r4,r31
253 #ifdef CONFIG_PHYS_64BIT
254 mr r5,r23
255 mr r6,r25
256 #else
257 mr r5,r25
258 #endif
259 bl relocate_init
260 #endif
262 #ifdef CONFIG_DYNAMIC_MEMSTART
263 lis r3,kernstart_addr@ha
264 la r3,kernstart_addr@l(r3)
265 #ifdef CONFIG_PHYS_64BIT
266 stw r23,0(r3)
267 stw r25,4(r3)
268 #else
269 stw r25,0(r3)
270 #endif
271 #endif
273 /*
274 * Decide what sort of machine this is and initialize the MMU.
275 */
276 mr r3,r30
277 mr r4,r31
278 bl machine_init
279 bl MMU_init
281 /* Setup PTE pointers for the Abatron bdiGDB */
282 lis r6, swapper_pg_dir@h
283 ori r6, r6, swapper_pg_dir@l
284 lis r5, abatron_pteptrs@h
285 ori r5, r5, abatron_pteptrs@l
286 lis r4, KERNELBASE@h
287 ori r4, r4, KERNELBASE@l
288 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
289 stw r6, 0(r5)
291 /* Let's move on */
292 lis r4,start_kernel@h
293 ori r4,r4,start_kernel@l
294 lis r3,MSR_KERNEL@h
295 ori r3,r3,MSR_KERNEL@l
296 mtspr SPRN_SRR0,r4
297 mtspr SPRN_SRR1,r3
298 rfi /* change context and jump to start_kernel */
300 /* Macros to hide the PTE size differences
301 *
302 * FIND_PTE -- walks the page tables given EA & pgdir pointer
303 * r10 -- EA of fault
304 * r11 -- PGDIR pointer
305 * r12 -- free
306 * label 2: is the bailout case
307 *
308 * if we find the pte (fall through):
309 * r11 is low pte word
310 * r12 is pointer to the pte
311 * r10 is the pshift from the PGD, if we're a hugepage
312 */
313 #ifdef CONFIG_PTE_64BIT
314 #ifdef CONFIG_HUGETLB_PAGE
315 #define FIND_PTE \
316 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
317 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
318 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
319 blt 1000f; /* Normal non-huge page */ \
320 beq 2f; /* Bail if no table */ \
321 oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
322 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
323 xor r12, r10, r11; /* drop size bits from pointer */ \
324 b 1001f; \
325 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
326 li r10, 0; /* clear r10 */ \
327 1001: lwz r11, 4(r12); /* Get pte entry */
328 #else
329 #define FIND_PTE \
330 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
331 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
332 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
333 beq 2f; /* Bail if no table */ \
334 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
335 lwz r11, 4(r12); /* Get pte entry */
336 #endif /* HUGEPAGE */
337 #else /* !PTE_64BIT */
338 #define FIND_PTE \
339 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
340 lwz r11, 0(r11); /* Get L1 entry */ \
341 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
342 beq 2f; /* Bail if no table */ \
343 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
344 lwz r11, 0(r12); /* Get Linux PTE */
345 #endif
347 /*
348 * Interrupt vector entry code
349 *
350 * The Book E MMUs are always on so we don't need to handle
351 * interrupts in real mode as with previous PPC processors. In
352 * this case we handle interrupts in the kernel virtual address
353 * space.
354 *
355 * Interrupt vectors are dynamically placed relative to the
356 * interrupt prefix as determined by the address of interrupt_base.
357 * The interrupt vectors offsets are programmed using the labels
358 * for each interrupt vector entry.
359 *
360 * Interrupt vectors must be aligned on a 16 byte boundary.
361 * We align on a 32 byte cache line boundary for good measure.
362 */
364 interrupt_base:
365 /* Critical Input Interrupt */
366 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
368 /* Machine Check Interrupt */
369 #ifdef CONFIG_E200
370 /* no RFMCI, MCSRRs on E200 */
371 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
372 machine_check_exception)
373 #else
374 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
375 #endif
377 /* Data Storage Interrupt */
378 START_EXCEPTION(DataStorage)
379 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
380 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
381 stw r5,_ESR(r11)
382 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
383 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
384 bne 1f
385 EXC_XFER_LITE(0x0300, handle_page_fault)
386 1:
387 addi r3,r1,STACK_FRAME_OVERHEAD
388 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
390 /* Instruction Storage Interrupt */
391 INSTRUCTION_STORAGE_EXCEPTION
393 /* External Input Interrupt */
394 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
396 /* Alignment Interrupt */
397 ALIGNMENT_EXCEPTION
399 /* Program Interrupt */
400 PROGRAM_EXCEPTION
402 /* Floating Point Unavailable Interrupt */
403 #ifdef CONFIG_PPC_FPU
404 FP_UNAVAILABLE_EXCEPTION
405 #else
406 #ifdef CONFIG_E200
407 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
408 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
409 program_check_exception, EXC_XFER_EE)
410 #else
411 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
412 unknown_exception, EXC_XFER_EE)
413 #endif
414 #endif
416 /* System Call Interrupt */
417 START_EXCEPTION(SystemCall)
418 NORMAL_EXCEPTION_PROLOG(SYSCALL)
419 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
421 /* Auxiliary Processor Unavailable Interrupt */
422 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
423 unknown_exception, EXC_XFER_EE)
425 /* Decrementer Interrupt */
426 DECREMENTER_EXCEPTION
428 /* Fixed Internal Timer Interrupt */
429 /* TODO: Add FIT support */
430 EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
431 unknown_exception, EXC_XFER_EE)
433 /* Watchdog Timer Interrupt */
434 #ifdef CONFIG_BOOKE_WDT
435 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
436 #else
437 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
438 #endif
440 /* Data TLB Error Interrupt */
441 START_EXCEPTION(DataTLBError)
442 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
443 mfspr r10, SPRN_SPRG_THREAD
444 stw r11, THREAD_NORMSAVE(0)(r10)
445 #ifdef CONFIG_KVM_BOOKE_HV
446 BEGIN_FTR_SECTION
447 mfspr r11, SPRN_SRR1
448 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
449 #endif
450 stw r12, THREAD_NORMSAVE(1)(r10)
451 stw r13, THREAD_NORMSAVE(2)(r10)
452 mfcr r13
453 stw r13, THREAD_NORMSAVE(3)(r10)
454 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
455 mfspr r10, SPRN_DEAR /* Get faulting address */
457 /* If we are faulting a kernel address, we have to use the
458 * kernel page tables.
459 */
460 lis r11, PAGE_OFFSET@h
461 cmplw 5, r10, r11
462 blt 5, 3f
463 lis r11, swapper_pg_dir@h
464 ori r11, r11, swapper_pg_dir@l
466 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
467 rlwinm r12,r12,0,16,1
468 mtspr SPRN_MAS1,r12
470 b 4f
472 /* Get the PGD for the current thread */
473 3:
474 mfspr r11,SPRN_SPRG_THREAD
475 lwz r11,PGDIR(r11)
477 4:
478 /* Mask of required permission bits. Note that while we
479 * do copy ESR:ST to _PAGE_RW position as trying to write
480 * to an RO page is pretty common, we don't do it with
481 * _PAGE_DIRTY. We could do it, but it's a fairly rare
482 * event so I'd rather take the overhead when it happens
483 * rather than adding an instruction here. We should measure
484 * whether the whole thing is worth it in the first place
485 * as we could avoid loading SPRN_ESR completely in the first
486 * place...
487 *
488 * TODO: Is it worth doing that mfspr & rlwimi in the first
489 * place or can we save a couple of instructions here ?
490 */
491 mfspr r12,SPRN_ESR
492 #ifdef CONFIG_PTE_64BIT
493 li r13,_PAGE_PRESENT
494 oris r13,r13,_PAGE_ACCESSED@h
495 #else
496 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
497 #endif
498 rlwimi r13,r12,11,29,29
500 FIND_PTE
501 andc. r13,r13,r11 /* Check permission */
503 #ifdef CONFIG_PTE_64BIT
504 #ifdef CONFIG_SMP
505 subf r13,r11,r12 /* create false data dep */
506 lwzx r13,r11,r13 /* Get upper pte bits */
507 #else
508 lwz r13,0(r12) /* Get upper pte bits */
509 #endif
510 #endif
512 bne 2f /* Bail if permission/valid mismach */
514 /* Jump to common tlb load */
515 b finish_tlb_load
516 2:
517 /* The bailout. Restore registers to pre-exception conditions
518 * and call the heavyweights to help us out.
519 */
520 mfspr r10, SPRN_SPRG_THREAD
521 lwz r11, THREAD_NORMSAVE(3)(r10)
522 mtcr r11
523 lwz r13, THREAD_NORMSAVE(2)(r10)
524 lwz r12, THREAD_NORMSAVE(1)(r10)
525 lwz r11, THREAD_NORMSAVE(0)(r10)
526 mfspr r10, SPRN_SPRG_RSCRATCH0
527 b DataStorage
529 /* Instruction TLB Error Interrupt */
530 /*
531 * Nearly the same as above, except we get our
532 * information from different registers and bailout
533 * to a different point.
534 */
535 START_EXCEPTION(InstructionTLBError)
536 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
537 mfspr r10, SPRN_SPRG_THREAD
538 stw r11, THREAD_NORMSAVE(0)(r10)
539 #ifdef CONFIG_KVM_BOOKE_HV
540 BEGIN_FTR_SECTION
541 mfspr r11, SPRN_SRR1
542 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
543 #endif
544 stw r12, THREAD_NORMSAVE(1)(r10)
545 stw r13, THREAD_NORMSAVE(2)(r10)
546 mfcr r13
547 stw r13, THREAD_NORMSAVE(3)(r10)
548 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
549 mfspr r10, SPRN_SRR0 /* Get faulting address */
551 /* If we are faulting a kernel address, we have to use the
552 * kernel page tables.
553 */
554 lis r11, PAGE_OFFSET@h
555 cmplw 5, r10, r11
556 blt 5, 3f
557 lis r11, swapper_pg_dir@h
558 ori r11, r11, swapper_pg_dir@l
560 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
561 rlwinm r12,r12,0,16,1
562 mtspr SPRN_MAS1,r12
564 /* Make up the required permissions for kernel code */
565 #ifdef CONFIG_PTE_64BIT
566 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
567 oris r13,r13,_PAGE_ACCESSED@h
568 #else
569 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
570 #endif
571 b 4f
573 /* Get the PGD for the current thread */
574 3:
575 mfspr r11,SPRN_SPRG_THREAD
576 lwz r11,PGDIR(r11)
578 /* Make up the required permissions for user code */
579 #ifdef CONFIG_PTE_64BIT
580 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
581 oris r13,r13,_PAGE_ACCESSED@h
582 #else
583 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
584 #endif
586 4:
587 FIND_PTE
588 andc. r13,r13,r11 /* Check permission */
590 #ifdef CONFIG_PTE_64BIT
591 #ifdef CONFIG_SMP
592 subf r13,r11,r12 /* create false data dep */
593 lwzx r13,r11,r13 /* Get upper pte bits */
594 #else
595 lwz r13,0(r12) /* Get upper pte bits */
596 #endif
597 #endif
599 bne 2f /* Bail if permission mismach */
601 /* Jump to common TLB load point */
602 b finish_tlb_load
604 2:
605 /* The bailout. Restore registers to pre-exception conditions
606 * and call the heavyweights to help us out.
607 */
608 mfspr r10, SPRN_SPRG_THREAD
609 lwz r11, THREAD_NORMSAVE(3)(r10)
610 mtcr r11
611 lwz r13, THREAD_NORMSAVE(2)(r10)
612 lwz r12, THREAD_NORMSAVE(1)(r10)
613 lwz r11, THREAD_NORMSAVE(0)(r10)
614 mfspr r10, SPRN_SPRG_RSCRATCH0
615 b InstructionStorage
617 /* Define SPE handlers for e200 and e500v2 */
618 #ifdef CONFIG_SPE
619 /* SPE Unavailable */
620 START_EXCEPTION(SPEUnavailable)
621 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
622 beq 1f
623 bl load_up_spe
624 b fast_exception_return
625 1: addi r3,r1,STACK_FRAME_OVERHEAD
626 EXC_XFER_EE_LITE(0x2010, KernelSPE)
627 #elif defined(CONFIG_SPE_POSSIBLE)
628 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
629 unknown_exception, EXC_XFER_EE)
630 #endif /* CONFIG_SPE_POSSIBLE */
632 /* SPE Floating Point Data */
633 #ifdef CONFIG_SPE
634 EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData,
635 SPEFloatingPointException, EXC_XFER_EE)
637 /* SPE Floating Point Round */
638 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
639 SPEFloatingPointRoundException, EXC_XFER_EE)
640 #elif defined(CONFIG_SPE_POSSIBLE)
641 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData,
642 unknown_exception, EXC_XFER_EE)
643 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
644 unknown_exception, EXC_XFER_EE)
645 #endif /* CONFIG_SPE_POSSIBLE */
648 /* Performance Monitor */
649 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
650 performance_monitor_exception, EXC_XFER_STD)
652 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
654 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
655 CriticalDoorbell, unknown_exception)
657 /* Debug Interrupt */
658 DEBUG_DEBUG_EXCEPTION
659 DEBUG_CRIT_EXCEPTION
661 GUEST_DOORBELL_EXCEPTION
663 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
664 unknown_exception)
666 /* Hypercall */
667 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_EE)
669 /* Embedded Hypervisor Privilege */
670 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE)
672 interrupt_end:
674 /*
675 * Local functions
676 */
678 /*
679 * Both the instruction and data TLB miss get to this
680 * point to load the TLB.
681 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use
682 * r11 - TLB (info from Linux PTE)
683 * r12 - available to use
684 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
685 * CR5 - results of addr >= PAGE_OFFSET
686 * MAS0, MAS1 - loaded with proper value when we get here
687 * MAS2, MAS3 - will need additional info from Linux PTE
688 * Upon exit, we reload everything and RFI.
689 */
690 finish_tlb_load:
691 #ifdef CONFIG_HUGETLB_PAGE
692 cmpwi 6, r10, 0 /* check for huge page */
693 beq 6, finish_tlb_load_cont /* !huge */
695 /* Alas, we need more scratch registers for hugepages */
696 mfspr r12, SPRN_SPRG_THREAD
697 stw r14, THREAD_NORMSAVE(4)(r12)
698 stw r15, THREAD_NORMSAVE(5)(r12)
699 stw r16, THREAD_NORMSAVE(6)(r12)
700 stw r17, THREAD_NORMSAVE(7)(r12)
702 /* Get the next_tlbcam_idx percpu var */
703 #ifdef CONFIG_SMP
704 lwz r12, THREAD_INFO-THREAD(r12)
705 lwz r15, TI_CPU(r12)
706 lis r14, __per_cpu_offset@h
707 ori r14, r14, __per_cpu_offset@l
708 rlwinm r15, r15, 2, 0, 29
709 lwzx r16, r14, r15
710 #else
711 li r16, 0
712 #endif
713 lis r17, next_tlbcam_idx@h
714 ori r17, r17, next_tlbcam_idx@l
715 add r17, r17, r16 /* r17 = *next_tlbcam_idx */
716 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
718 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
719 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
720 mtspr SPRN_MAS0, r14
722 /* Extract TLB1CFG(NENTRY) */
723 mfspr r16, SPRN_TLB1CFG
724 andi. r16, r16, 0xfff
726 /* Update next_tlbcam_idx, wrapping when necessary */
727 addi r15, r15, 1
728 cmpw r15, r16
729 blt 100f
730 lis r14, tlbcam_index@h
731 ori r14, r14, tlbcam_index@l
732 lwz r15, 0(r14)
733 100: stw r15, 0(r17)
735 /*
736 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
737 * tlb_enc = (pshift - 10).
738 */
739 subi r15, r10, 10
740 mfspr r16, SPRN_MAS1
741 rlwimi r16, r15, 7, 20, 24
742 mtspr SPRN_MAS1, r16
744 /* copy the pshift for use later */
745 mr r14, r10
747 /* fall through */
749 #endif /* CONFIG_HUGETLB_PAGE */
751 /*
752 * We set execute, because we don't have the granularity to
753 * properly set this at the page level (Linux problem).
754 * Many of these bits are software only. Bits we don't set
755 * here we (properly should) assume have the appropriate value.
756 */
757 finish_tlb_load_cont:
758 #ifdef CONFIG_PTE_64BIT
759 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
760 andi. r10, r11, _PAGE_DIRTY
761 bne 1f
762 li r10, MAS3_SW | MAS3_UW
763 andc r12, r12, r10
764 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
765 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
766 2: mtspr SPRN_MAS3, r12
767 BEGIN_MMU_FTR_SECTION
768 srwi r10, r13, 12 /* grab RPN[12:31] */
769 mtspr SPRN_MAS7, r10
770 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
771 #else
772 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
773 mr r13, r11
774 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
775 and r12, r11, r10
776 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
777 slwi r10, r12, 1
778 or r10, r10, r12
779 iseleq r12, r12, r10
780 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
781 mtspr SPRN_MAS3, r13
782 #endif
784 mfspr r12, SPRN_MAS2
785 #ifdef CONFIG_PTE_64BIT
786 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
787 #else
788 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
789 #endif
790 #ifdef CONFIG_HUGETLB_PAGE
791 beq 6, 3f /* don't mask if page isn't huge */
792 li r13, 1
793 slw r13, r13, r14
794 subi r13, r13, 1
795 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
796 andc r12, r12, r13 /* mask off ea bits within the page */
797 #endif
798 3: mtspr SPRN_MAS2, r12
800 #ifdef CONFIG_E200
801 /* Round robin TLB1 entries assignment */
802 mfspr r12, SPRN_MAS0
804 /* Extract TLB1CFG(NENTRY) */
805 mfspr r11, SPRN_TLB1CFG
806 andi. r11, r11, 0xfff
808 /* Extract MAS0(NV) */
809 andi. r13, r12, 0xfff
810 addi r13, r13, 1
811 cmpw 0, r13, r11
812 addi r12, r12, 1
814 /* check if we need to wrap */
815 blt 7f
817 /* wrap back to first free tlbcam entry */
818 lis r13, tlbcam_index@ha
819 lwz r13, tlbcam_index@l(r13)
820 rlwimi r12, r13, 0, 20, 31
821 7:
822 mtspr SPRN_MAS0,r12
823 #endif /* CONFIG_E200 */
825 tlb_write_entry:
826 tlbwe
828 /* Done...restore registers and get out of here. */
829 mfspr r10, SPRN_SPRG_THREAD
830 #ifdef CONFIG_HUGETLB_PAGE
831 beq 6, 8f /* skip restore for 4k page faults */
832 lwz r14, THREAD_NORMSAVE(4)(r10)
833 lwz r15, THREAD_NORMSAVE(5)(r10)
834 lwz r16, THREAD_NORMSAVE(6)(r10)
835 lwz r17, THREAD_NORMSAVE(7)(r10)
836 #endif
837 8: lwz r11, THREAD_NORMSAVE(3)(r10)
838 mtcr r11
839 lwz r13, THREAD_NORMSAVE(2)(r10)
840 lwz r12, THREAD_NORMSAVE(1)(r10)
841 lwz r11, THREAD_NORMSAVE(0)(r10)
842 mfspr r10, SPRN_SPRG_RSCRATCH0
843 rfi /* Force context change */
845 #ifdef CONFIG_SPE
846 /* Note that the SPE support is closely modeled after the AltiVec
847 * support. Changes to one are likely to be applicable to the
848 * other! */
849 _GLOBAL(load_up_spe)
850 /*
851 * Disable SPE for the task which had SPE previously,
852 * and save its SPE registers in its thread_struct.
853 * Enables SPE for use in the kernel on return.
854 * On SMP we know the SPE units are free, since we give it up every
855 * switch. -- Kumar
856 */
857 mfmsr r5
858 oris r5,r5,MSR_SPE@h
859 mtmsr r5 /* enable use of SPE now */
860 isync
861 /* enable use of SPE after return */
862 oris r9,r9,MSR_SPE@h
863 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
864 li r4,1
865 li r10,THREAD_ACC
866 stw r4,THREAD_USED_SPE(r5)
867 evlddx evr4,r10,r5
868 evmra evr4,evr4
869 REST_32EVRS(0,r10,r5,THREAD_EVR0)
870 blr
872 /*
873 * SPE unavailable trap from kernel - print a message, but let
874 * the task use SPE in the kernel until it returns to user mode.
875 */
876 KernelSPE:
877 lwz r3,_MSR(r1)
878 oris r3,r3,MSR_SPE@h
879 stw r3,_MSR(r1) /* enable use of SPE after return */
880 #ifdef CONFIG_PRINTK
881 lis r3,87f@h
882 ori r3,r3,87f@l
883 mr r4,r2 /* current */
884 lwz r5,_NIP(r1)
885 bl printk
886 #endif
887 b ret_from_except
888 #ifdef CONFIG_PRINTK
889 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
890 #endif
891 .align 4,0
893 #endif /* CONFIG_SPE */
895 /*
896 * Translate the effec addr in r3 to phys addr. The phys addr will be put
897 * into r3(higher 32bit) and r4(lower 32bit)
898 */
899 get_phys_addr:
900 mfmsr r8
901 mfspr r9,SPRN_PID
902 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */
903 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
904 mtspr SPRN_MAS6,r9
906 tlbsx 0,r3 /* must succeed */
908 mfspr r8,SPRN_MAS1
909 mfspr r12,SPRN_MAS3
910 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */
911 li r10,1024
912 slw r10,r10,r9 /* r10 = page size */
913 addi r10,r10,-1
914 and r11,r3,r10 /* r11 = page offset */
915 andc r4,r12,r10 /* r4 = page base */
916 or r4,r4,r11 /* r4 = devtree phys addr */
917 #ifdef CONFIG_PHYS_64BIT
918 mfspr r3,SPRN_MAS7
919 #endif
920 blr
922 /*
923 * Global functions
924 */
926 #ifdef CONFIG_E200
927 /* Adjust or setup IVORs for e200 */
928 _GLOBAL(__setup_e200_ivors)
929 li r3,DebugDebug@l
930 mtspr SPRN_IVOR15,r3
931 li r3,SPEUnavailable@l
932 mtspr SPRN_IVOR32,r3
933 li r3,SPEFloatingPointData@l
934 mtspr SPRN_IVOR33,r3
935 li r3,SPEFloatingPointRound@l
936 mtspr SPRN_IVOR34,r3
937 sync
938 blr
939 #endif
941 #ifdef CONFIG_E500
942 #ifndef CONFIG_PPC_E500MC
943 /* Adjust or setup IVORs for e500v1/v2 */
944 _GLOBAL(__setup_e500_ivors)
945 li r3,DebugCrit@l
946 mtspr SPRN_IVOR15,r3
947 li r3,SPEUnavailable@l
948 mtspr SPRN_IVOR32,r3
949 li r3,SPEFloatingPointData@l
950 mtspr SPRN_IVOR33,r3
951 li r3,SPEFloatingPointRound@l
952 mtspr SPRN_IVOR34,r3
953 li r3,PerformanceMonitor@l
954 mtspr SPRN_IVOR35,r3
955 sync
956 blr
957 #else
958 /* Adjust or setup IVORs for e500mc */
959 _GLOBAL(__setup_e500mc_ivors)
960 li r3,DebugDebug@l
961 mtspr SPRN_IVOR15,r3
962 li r3,PerformanceMonitor@l
963 mtspr SPRN_IVOR35,r3
964 li r3,Doorbell@l
965 mtspr SPRN_IVOR36,r3
966 li r3,CriticalDoorbell@l
967 mtspr SPRN_IVOR37,r3
968 sync
969 blr
971 /* setup ehv ivors for */
972 _GLOBAL(__setup_ehv_ivors)
973 li r3,GuestDoorbell@l
974 mtspr SPRN_IVOR38,r3
975 li r3,CriticalGuestDoorbell@l
976 mtspr SPRN_IVOR39,r3
977 li r3,Hypercall@l
978 mtspr SPRN_IVOR40,r3
979 li r3,Ehvpriv@l
980 mtspr SPRN_IVOR41,r3
981 sync
982 blr
983 #endif /* CONFIG_PPC_E500MC */
984 #endif /* CONFIG_E500 */
986 #ifdef CONFIG_SPE
987 /*
988 * extern void __giveup_spe(struct task_struct *prev)
989 *
990 */
991 _GLOBAL(__giveup_spe)
992 addi r3,r3,THREAD /* want THREAD of task */
993 lwz r5,PT_REGS(r3)
994 cmpi 0,r5,0
995 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
996 evxor evr6, evr6, evr6 /* clear out evr6 */
997 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
998 li r4,THREAD_ACC
999 evstddx evr6, r4, r3 /* save off accumulator */
1000 beq 1f
1001 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1002 lis r3,MSR_SPE@h
1003 andc r4,r4,r3 /* disable SPE for previous task */
1004 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1005 1:
1006 blr
1007 #endif /* CONFIG_SPE */
1009 /*
1010 * extern void abort(void)
1011 *
1012 * At present, this routine just applies a system reset.
1013 */
1014 _GLOBAL(abort)
1015 li r13,0
1016 mtspr SPRN_DBCR0,r13 /* disable all debug events */
1017 isync
1018 mfmsr r13
1019 ori r13,r13,MSR_DE@l /* Enable Debug Events */
1020 mtmsr r13
1021 isync
1022 mfspr r13,SPRN_DBCR0
1023 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1024 mtspr SPRN_DBCR0,r13
1025 isync
1027 _GLOBAL(set_context)
1029 #ifdef CONFIG_BDI_SWITCH
1030 /* Context switch the PTE pointer for the Abatron BDI2000.
1031 * The PGDIR is the second parameter.
1032 */
1033 lis r5, abatron_pteptrs@h
1034 ori r5, r5, abatron_pteptrs@l
1035 stw r4, 0x4(r5)
1036 #endif
1037 mtspr SPRN_PID,r3
1038 isync /* Force context change */
1039 blr
1041 #ifdef CONFIG_SMP
1042 /* When we get here, r24 needs to hold the CPU # */
1043 .globl __secondary_start
1044 __secondary_start:
1045 LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1046 lwz r3,0(r3)
1047 mtctr r3
1048 li r26,0 /* r26 safe? */
1050 bl switch_to_as1
1051 mr r27,r3 /* tlb entry */
1052 /* Load each CAM entry */
1053 1: mr r3,r26
1054 bl loadcam_entry
1055 addi r26,r26,1
1056 bdnz 1b
1057 mr r3,r27 /* tlb entry */
1058 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1059 lwz r4,0(r4)
1060 mr r5,r25 /* phys kernel start */
1061 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */
1062 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1063 li r5,0 /* no device tree */
1064 li r6,0 /* not boot cpu */
1065 bl restore_to_as0
1068 lis r3,__secondary_hold_acknowledge@h
1069 ori r3,r3,__secondary_hold_acknowledge@l
1070 stw r24,0(r3)
1072 li r3,0
1073 mr r4,r24 /* Why? */
1074 bl call_setup_cpu
1076 /* get current_thread_info and current */
1077 lis r1,secondary_ti@ha
1078 lwz r1,secondary_ti@l(r1)
1079 lwz r2,TI_TASK(r1)
1081 /* stack */
1082 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1083 li r0,0
1084 stw r0,0(r1)
1086 /* ptr to current thread */
1087 addi r4,r2,THREAD /* address of our thread_struct */
1088 mtspr SPRN_SPRG_THREAD,r4
1090 /* Setup the defaults for TLB entries */
1091 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1092 mtspr SPRN_MAS4,r4
1094 /* Jump to start_secondary */
1095 lis r4,MSR_KERNEL@h
1096 ori r4,r4,MSR_KERNEL@l
1097 lis r3,start_secondary@h
1098 ori r3,r3,start_secondary@l
1099 mtspr SPRN_SRR0,r3
1100 mtspr SPRN_SRR1,r4
1101 sync
1102 rfi
1103 sync
1105 .globl __secondary_hold_acknowledge
1106 __secondary_hold_acknowledge:
1107 .long -1
1108 #endif
1110 /*
1111 * Create a tlb entry with the same effective and physical address as
1112 * the tlb entry used by the current running code. But set the TS to 1.
1113 * Then switch to the address space 1. It will return with the r3 set to
1114 * the ESEL of the new created tlb.
1115 */
1116 _GLOBAL(switch_to_as1)
1117 mflr r5
1119 /* Find a entry not used */
1120 mfspr r3,SPRN_TLB1CFG
1121 andi. r3,r3,0xfff
1122 mfspr r4,SPRN_PID
1123 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1124 mtspr SPRN_MAS6,r4
1125 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1126 addi r3,r3,-1
1127 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1128 mtspr SPRN_MAS0,r4
1129 tlbre
1130 mfspr r4,SPRN_MAS1
1131 andis. r4,r4,MAS1_VALID@h
1132 bne 1b
1134 /* Get the tlb entry used by the current running code */
1135 bl 0f
1136 0: mflr r4
1137 tlbsx 0,r4
1139 mfspr r4,SPRN_MAS1
1140 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1141 mtspr SPRN_MAS1,r4
1143 mfspr r4,SPRN_MAS0
1144 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1145 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1146 mtspr SPRN_MAS0,r4
1147 tlbwe
1148 isync
1149 sync
1151 mfmsr r4
1152 ori r4,r4,MSR_IS | MSR_DS
1153 mtspr SPRN_SRR0,r5
1154 mtspr SPRN_SRR1,r4
1155 sync
1156 rfi
1158 /*
1159 * Restore to the address space 0 and also invalidate the tlb entry created
1160 * by switch_to_as1.
1161 * r3 - the tlb entry which should be invalidated
1162 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1163 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1164 * r6 - boot cpu
1165 */
1166 _GLOBAL(restore_to_as0)
1167 mflr r0
1169 bl 0f
1170 0: mflr r9
1171 addi r9,r9,1f - 0b
1173 /*
1174 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1175 * so we need calculate the right jump and device tree address based
1176 * on the offset passed by r4.
1177 */
1178 add r9,r9,r4
1179 add r5,r5,r4
1180 add r0,r0,r4
1182 2: mfmsr r7
1183 li r8,(MSR_IS | MSR_DS)
1184 andc r7,r7,r8
1186 mtspr SPRN_SRR0,r9
1187 mtspr SPRN_SRR1,r7
1188 sync
1189 rfi
1191 /* Invalidate the temporary tlb entry for AS1 */
1192 1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */
1193 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1194 mtspr SPRN_MAS0,r9
1195 tlbre
1196 mfspr r9,SPRN_MAS1
1197 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */
1198 mtspr SPRN_MAS1,r9
1199 tlbwe
1200 isync
1202 cmpwi r4,0
1203 cmpwi cr1,r6,0
1204 cror eq,4*cr1+eq,eq
1205 bne 3f /* offset != 0 && is_boot_cpu */
1206 mtlr r0
1207 blr
1209 /*
1210 * The PAGE_OFFSET will map to a different physical address,
1211 * jump to _start to do another relocation again.
1212 */
1213 3: mr r3,r5
1214 bl _start
1216 /*
1217 * We put a few things here that have to be page-aligned. This stuff
1218 * goes at the beginning of the data segment, which is page-aligned.
1219 */
1220 .data
1221 .align 12
1222 .globl sdata
1223 sdata:
1224 .globl empty_zero_page
1225 empty_zero_page:
1226 .space 4096
1227 EXPORT_SYMBOL(empty_zero_page)
1228 .globl swapper_pg_dir
1229 swapper_pg_dir:
1230 .space PGD_TABLE_SIZE
1232 /*
1233 * Room for two PTE pointers, usually the kernel and current user pointers
1234 * to their respective root page table.
1235 */
1236 abatron_pteptrs:
1237 .space 8