2 * PPC Huge TLB Page Support for Book3E MMU
4 * Copyright (C) 2009 David Gibson, IBM Corporation.
5 * Copyright (C) 2011 Becky Bruce, Freescale Semiconductor
9 #include <linux/hugetlb.h>
13 #ifdef CONFIG_PPC_FSL_BOOK3E
15 static inline int tlb1_next(void)
17 struct paca_struct
*paca
= get_paca();
18 struct tlb_core_data
*tcd
;
22 this = tcd
->esel_next
;
25 if (next
>= tcd
->esel_max
)
26 next
= tcd
->esel_first
;
28 tcd
->esel_next
= next
;
32 static inline int tlb1_next(void)
36 ncams
= mfspr(SPRN_TLB1CFG
) & TLBnCFG_N_ENTRY
;
38 index
= this_cpu_read(next_tlbcam_idx
);
40 /* Just round-robin the entries and wrap when we hit the end */
41 if (unlikely(index
== ncams
- 1))
42 __this_cpu_write(next_tlbcam_idx
, tlbcam_index
);
44 __this_cpu_inc(next_tlbcam_idx
);
51 static inline int mmu_get_tsize(int psize
)
53 return mmu_psize_defs
[psize
].enc
;
56 #if defined(CONFIG_PPC_FSL_BOOK3E) && defined(CONFIG_PPC64)
59 static inline void book3e_tlb_lock(void)
61 struct paca_struct
*paca
= get_paca();
63 int token
= smp_processor_id() + 1;
66 * Besides being unnecessary in the absence of SMT, this
67 * check prevents trying to do lbarx/stbcx. on e5500 which
68 * doesn't implement either feature.
70 if (!cpu_has_feature(CPU_FTR_SMT
))
73 asm volatile("1: lbarx %0, 0, %1;"
85 : "r" (&paca
->tcd_ptr
->lock
), "r" (token
)
89 static inline void book3e_tlb_unlock(void)
91 struct paca_struct
*paca
= get_paca();
93 if (!cpu_has_feature(CPU_FTR_SMT
))
97 paca
->tcd_ptr
->lock
= 0;
100 static inline void book3e_tlb_lock(void)
104 static inline void book3e_tlb_unlock(void)
109 static inline int book3e_tlb_exists(unsigned long ea
, unsigned long pid
)
113 mtspr(SPRN_MAS6
, pid
<< 16);
114 if (mmu_has_feature(MMU_FTR_USE_TLBRSRV
)) {
121 : "=&r"(found
) : "r"(ea
));
127 : "=&r"(found
) : "r"(ea
));
133 void book3e_hugetlb_preload(struct vm_area_struct
*vma
, unsigned long ea
,
136 unsigned long mas1
, mas2
;
138 unsigned long psize
, tsize
, shift
;
140 struct mm_struct
*mm
;
142 #ifdef CONFIG_PPC_FSL_BOOK3E
146 if (unlikely(is_kernel_addr(ea
)))
151 psize
= vma_mmu_pagesize(vma
);
152 shift
= __ilog2(psize
);
155 * We can't be interrupted while we're setting up the MAS
156 * regusters or after we've confirmed that no tlb exists.
158 local_irq_save(flags
);
162 if (unlikely(book3e_tlb_exists(ea
, mm
->context
.id
))) {
164 local_irq_restore(flags
);
168 #ifdef CONFIG_PPC_FSL_BOOK3E
169 /* We have to use the CAM(TLB1) on FSL parts for hugepages */
171 mtspr(SPRN_MAS0
, MAS0_ESEL(index
) | MAS0_TLBSEL(1));
174 mas1
= MAS1_VALID
| MAS1_TID(mm
->context
.id
) | MAS1_TSIZE(tsize
);
175 mas2
= ea
& ~((1UL << shift
) - 1);
176 mas2
|= (pte_val(pte
) >> PTE_WIMGE_SHIFT
) & MAS2_WIMGE_MASK
;
177 mas7_3
= (u64
)pte_pfn(pte
) << PAGE_SHIFT
;
178 mas7_3
|= (pte_val(pte
) >> PTE_BAP_SHIFT
) & MAS3_BAP_MASK
;
180 mas7_3
&= ~(MAS3_SW
|MAS3_UW
);
182 mtspr(SPRN_MAS1
, mas1
);
183 mtspr(SPRN_MAS2
, mas2
);
185 if (mmu_has_feature(MMU_FTR_USE_PAIRED_MAS
)) {
186 mtspr(SPRN_MAS7_MAS3
, mas7_3
);
188 if (mmu_has_feature(MMU_FTR_BIG_PHYS
))
189 mtspr(SPRN_MAS7
, upper_32_bits(mas7_3
));
190 mtspr(SPRN_MAS3
, lower_32_bits(mas7_3
));
193 asm volatile ("tlbwe");
196 local_irq_restore(flags
);
199 void flush_hugetlb_page(struct vm_area_struct
*vma
, unsigned long vmaddr
)
201 struct hstate
*hstate
= hstate_file(vma
->vm_file
);
202 unsigned long tsize
= huge_page_shift(hstate
) - 10;
204 __flush_tlb_page(vma
->vm_mm
, vmaddr
, tsize
, 0);