arch/powerpc/mm/tlb_hash64.c

   1 /*
   2  * This file contains the routines for flushing entries from the
   3  * TLB and MMU hash table.
   4  *
   5  *  Derived from arch/ppc64/mm/init.c:
   6  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   7  *
   8  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
   9  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  10  *    Copyright (C) 1996 Paul Mackerras
  11  *
  12  *  Derived from "arch/i386/mm/init.c"
  13  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  14  *
  15  *  Dave Engebretsen <engebret@us.ibm.com>
  16  *      Rework for PPC64 port.
  17  *
  18  *  This program is free software; you can redistribute it and/or
  19  *  modify it under the terms of the GNU General Public License
  20  *  as published by the Free Software Foundation; either version
  21  *  2 of the License, or (at your option) any later version.
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/percpu.h>
  27 #include <linux/hardirq.h>
  28 #include <asm/pgalloc.h>
  29 #include <asm/tlbflush.h>
  30 #include <asm/tlb.h>
  31 #include <asm/bug.h>
  32 #include <asm/pte-walk.h>
  33
  34
  35 #include <trace/events/thp.h>
  36
  37 DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
  38
  39 /*
  40  * A linux PTE was changed and the corresponding hash table entry
  41  * neesd to be flushed. This function will either perform the flush
  42  * immediately or will batch it up if the current CPU has an active
  43  * batch on it.
  44  */
  45 void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
  46                      pte_t *ptep, unsigned long pte, int huge)
  47 {
  48         unsigned long vpn;
  49         struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
  50         unsigned long vsid;
  51         unsigned int psize;
  52         int ssize;
  53         real_pte_t rpte;
  54         int i;
  55
  56         i = batch->index;
  57
  58         /* Get page size (maybe move back to caller).
  59          *
  60          * NOTE: when using special 64K mappings in 4K environment like
  61          * for SPEs, we obtain the page size from the slice, which thus
  62          * must still exist (and thus the VMA not reused) at the time
  63          * of this call
  64          */
  65         if (huge) {
  66 #ifdef CONFIG_HUGETLB_PAGE
  67                 psize = get_slice_psize(mm, addr);
  68                 /* Mask the address for the correct page size */
  69                 addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);
  70 #else
  71                 BUG();
  72                 psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
  73 #endif
  74         } else {
  75                 psize = pte_pagesize_index(mm, addr, pte);
  76                 /* Mask the address for the standard page size.  If we
  77                  * have a 64k page kernel, but the hardware does not
  78                  * support 64k pages, this might be different from the
  79                  * hardware page size encoded in the slice table. */
  80                 addr &= PAGE_MASK;
  81         }
  82
  83
  84         /* Build full vaddr */
  85         if (!is_kernel_addr(addr)) {
  86                 ssize = user_segment_size(addr);
  87                 vsid = get_vsid(mm->context.id, addr, ssize);
  88         } else {
  89                 vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
  90                 ssize = mmu_kernel_ssize;
  91         }
  92         WARN_ON(vsid == 0);
  93         vpn = hpt_vpn(addr, vsid, ssize);
  94         rpte = __real_pte(__pte(pte), ptep);
  95
  96         /*
  97          * Check if we have an active batch on this CPU. If not, just
  98          * flush now and return.
  99          */
 100         if (!batch->active) {
 101                 flush_hash_page(vpn, rpte, psize, ssize, mm_is_thread_local(mm));
 102                 put_cpu_var(ppc64_tlb_batch);
 103                 return;
 104         }
 105
 106         /*
 107          * This can happen when we are in the middle of a TLB batch and
 108          * we encounter memory pressure (eg copy_page_range when it tries
 109          * to allocate a new pte). If we have to reclaim memory and end
 110          * up scanning and resetting referenced bits then our batch context
 111          * will change mid stream.
 112          *
 113          * We also need to ensure only one page size is present in a given
 114          * batch
 115          */
 116         if (i != 0 && (mm != batch->mm || batch->psize != psize ||
 117                        batch->ssize != ssize)) {
 118                 __flush_tlb_pending(batch);
 119                 i = 0;
 120         }
 121         if (i == 0) {
 122                 batch->mm = mm;
 123                 batch->psize = psize;
 124                 batch->ssize = ssize;
 125         }
 126         batch->pte[i] = rpte;
 127         batch->vpn[i] = vpn;
 128         batch->index = ++i;
 129         if (i >= PPC64_TLB_BATCH_NR)
 130                 __flush_tlb_pending(batch);
 131         put_cpu_var(ppc64_tlb_batch);
 132 }
 133
 134 /*
 135  * This function is called when terminating an mmu batch or when a batch
 136  * is full. It will perform the flush of all the entries currently stored
 137  * in a batch.
 138  *
 139  * Must be called from within some kind of spinlock/non-preempt region...
 140  */
 141 void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
 142 {
 143         int i, local;
 144
 145         i = batch->index;
 146         local = mm_is_thread_local(batch->mm);
 147         if (i == 1)
 148                 flush_hash_page(batch->vpn[0], batch->pte[0],
 149                                 batch->psize, batch->ssize, local);
 150         else
 151                 flush_hash_range(i, local);
 152         batch->index = 0;
 153 }
 154
 155 void hash__tlb_flush(struct mmu_gather *tlb)
 156 {
 157         struct ppc64_tlb_batch *tlbbatch = &get_cpu_var(ppc64_tlb_batch);
 158
 159         /* If there's a TLB batch pending, then we must flush it because the
 160          * pages are going to be freed and we really don't want to have a CPU
 161          * access a freed page because it has a stale TLB
 162          */
 163         if (tlbbatch->index)
 164                 __flush_tlb_pending(tlbbatch);
 165
 166         put_cpu_var(ppc64_tlb_batch);
 167 }
 168
 169 /**
 170  * __flush_hash_table_range - Flush all HPTEs for a given address range
 171  *                            from the hash table (and the TLB). But keeps
 172  *                            the linux PTEs intact.
 173  *
 174  * @mm          : mm_struct of the target address space (generally init_mm)
 175  * @start       : starting address
 176  * @end         : ending address (not included in the flush)
 177  *
 178  * This function is mostly to be used by some IO hotplug code in order
 179  * to remove all hash entries from a given address range used to map IO
 180  * space on a removed PCI-PCI bidge without tearing down the full mapping
 181  * since 64K pages may overlap with other bridges when using 64K pages
 182  * with 4K HW pages on IO space.
 183  *
 184  * Because of that usage pattern, it is implemented for small size rather
 185  * than speed.
 186  */
 187 void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
 188                               unsigned long end)
 189 {
 190         bool is_thp;
 191         int hugepage_shift;
 192         unsigned long flags;
 193
 194         start = _ALIGN_DOWN(start, PAGE_SIZE);
 195         end = _ALIGN_UP(end, PAGE_SIZE);
 196
 197         BUG_ON(!mm->pgd);
 198
 199         /* Note: Normally, we should only ever use a batch within a
 200          * PTE locked section. This violates the rule, but will work
 201          * since we don't actually modify the PTEs, we just flush the
 202          * hash while leaving the PTEs intact (including their reference
 203          * to being hashed). This is not the most performance oriented
 204          * way to do things but is fine for our needs here.
 205          */
 206         local_irq_save(flags);
 207         arch_enter_lazy_mmu_mode();
 208         for (; start < end; start += PAGE_SIZE) {
 209                 pte_t *ptep = find_current_mm_pte(mm->pgd, start, &is_thp,
 210                                                   &hugepage_shift);
 211                 unsigned long pte;
 212
 213                 if (ptep == NULL)
 214                         continue;
 215                 pte = pte_val(*ptep);
 216                 if (is_thp)
 217                         trace_hugepage_invalidate(start, pte);
 218                 if (!(pte & H_PAGE_HASHPTE))
 219                         continue;
 220                 if (unlikely(is_thp))
 221                         hpte_do_hugepage_flush(mm, start, (pmd_t *)ptep, pte);
 222                 else
 223                         hpte_need_flush(mm, start, ptep, pte, hugepage_shift);
 224         }
 225         arch_leave_lazy_mmu_mode();
 226         local_irq_restore(flags);
 227 }
 228
 229 void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd, unsigned long addr)
 230 {
 231         pte_t *pte;
 232         pte_t *start_pte;
 233         unsigned long flags;
 234
 235         addr = _ALIGN_DOWN(addr, PMD_SIZE);
 236         /* Note: Normally, we should only ever use a batch within a
 237          * PTE locked section. This violates the rule, but will work
 238          * since we don't actually modify the PTEs, we just flush the
 239          * hash while leaving the PTEs intact (including their reference
 240          * to being hashed). This is not the most performance oriented
 241          * way to do things but is fine for our needs here.
 242          */
 243         local_irq_save(flags);
 244         arch_enter_lazy_mmu_mode();
 245         start_pte = pte_offset_map(pmd, addr);
 246         for (pte = start_pte; pte < start_pte + PTRS_PER_PTE; pte++) {
 247                 unsigned long pteval = pte_val(*pte);
 248                 if (pteval & H_PAGE_HASHPTE)
 249                         hpte_need_flush(mm, addr, pte, pteval, 0);
 250                 addr += PAGE_SIZE;
 251         }
 252         arch_leave_lazy_mmu_mode();
 253         local_irq_restore(flags);
 254 }