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iwlegacy: s/il_txq_mem/il_free_txq_mem/g
[linux/fpc-iii.git] / drivers / net / wireless / iwlegacy / 3945.c
blob456f32da6b26e2a1f5d60241e20739c7f423b825
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/sched.h>
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/firmware.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40 #include <net/mac80211.h>
41
42 #include "common.h"
43 #include "3945.h"
44
45 /* Send led command */
46 static int
47 il3945_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd)
48 {
49 struct il_host_cmd cmd = {
50 .id = C_LEDS,
51 .len = sizeof(struct il_led_cmd),
52 .data = led_cmd,
53 .flags = CMD_ASYNC,
54 .callback = NULL,
55 };
56
57 return il_send_cmd(il, &cmd);
58 }
59
60 #define IL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
61 [RATE_##r##M_IDX] = { RATE_##r##M_PLCP, \
62 RATE_##r##M_IEEE, \
63 RATE_##ip##M_IDX, \
64 RATE_##in##M_IDX, \
65 RATE_##rp##M_IDX, \
66 RATE_##rn##M_IDX, \
67 RATE_##pp##M_IDX, \
68 RATE_##np##M_IDX, \
69 RATE_##r##M_IDX_TBL, \
70 RATE_##ip##M_IDX_TBL }
71
72 /*
73 * Parameter order:
74 * rate, prev rate, next rate, prev tgg rate, next tgg rate
75 *
76 * If there isn't a valid next or previous rate then INV is used which
77 * maps to RATE_INVALID
78 *
79 */
80 const struct il3945_rate_info il3945_rates[RATE_COUNT_3945] = {
81 IL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
82 IL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
83 IL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
84 IL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
85 IL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
86 IL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
87 IL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
88 IL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
89 IL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
90 IL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
91 IL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
92 IL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV), /* 54mbps */
93 };
94
95 static inline u8
96 il3945_get_prev_ieee_rate(u8 rate_idx)
97 {
98 u8 rate = il3945_rates[rate_idx].prev_ieee;
99
100 if (rate == RATE_INVALID)
101 rate = rate_idx;
102 return rate;
103 }
104
105 /* 1 = enable the il3945_disable_events() function */
106 #define IL_EVT_DISABLE (0)
107 #define IL_EVT_DISABLE_SIZE (1532/32)
108
109 /**
110 * il3945_disable_events - Disable selected events in uCode event log
111 *
112 * Disable an event by writing "1"s into "disable"
113 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
114 * Default values of 0 enable uCode events to be logged.
115 * Use for only special debugging. This function is just a placeholder as-is,
116 * you'll need to provide the special bits! ...
117 * ... and set IL_EVT_DISABLE to 1. */
118 void
119 il3945_disable_events(struct il_priv *il)
120 {
121 int i;
122 u32 base; /* SRAM address of event log header */
123 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
124 u32 array_size; /* # of u32 entries in array */
125 static const u32 evt_disable[IL_EVT_DISABLE_SIZE] = {
126 0x00000000, /* 31 - 0 Event id numbers */
127 0x00000000, /* 63 - 32 */
128 0x00000000, /* 95 - 64 */
129 0x00000000, /* 127 - 96 */
130 0x00000000, /* 159 - 128 */
131 0x00000000, /* 191 - 160 */
132 0x00000000, /* 223 - 192 */
133 0x00000000, /* 255 - 224 */
134 0x00000000, /* 287 - 256 */
135 0x00000000, /* 319 - 288 */
136 0x00000000, /* 351 - 320 */
137 0x00000000, /* 383 - 352 */
138 0x00000000, /* 415 - 384 */
139 0x00000000, /* 447 - 416 */
140 0x00000000, /* 479 - 448 */
141 0x00000000, /* 511 - 480 */
142 0x00000000, /* 543 - 512 */
143 0x00000000, /* 575 - 544 */
144 0x00000000, /* 607 - 576 */
145 0x00000000, /* 639 - 608 */
146 0x00000000, /* 671 - 640 */
147 0x00000000, /* 703 - 672 */
148 0x00000000, /* 735 - 704 */
149 0x00000000, /* 767 - 736 */
150 0x00000000, /* 799 - 768 */
151 0x00000000, /* 831 - 800 */
152 0x00000000, /* 863 - 832 */
153 0x00000000, /* 895 - 864 */
154 0x00000000, /* 927 - 896 */
155 0x00000000, /* 959 - 928 */
156 0x00000000, /* 991 - 960 */
157 0x00000000, /* 1023 - 992 */
158 0x00000000, /* 1055 - 1024 */
159 0x00000000, /* 1087 - 1056 */
160 0x00000000, /* 1119 - 1088 */
161 0x00000000, /* 1151 - 1120 */
162 0x00000000, /* 1183 - 1152 */
163 0x00000000, /* 1215 - 1184 */
164 0x00000000, /* 1247 - 1216 */
165 0x00000000, /* 1279 - 1248 */
166 0x00000000, /* 1311 - 1280 */
167 0x00000000, /* 1343 - 1312 */
168 0x00000000, /* 1375 - 1344 */
169 0x00000000, /* 1407 - 1376 */
170 0x00000000, /* 1439 - 1408 */
171 0x00000000, /* 1471 - 1440 */
172 0x00000000, /* 1503 - 1472 */
173 };
174
175 base = le32_to_cpu(il->card_alive.log_event_table_ptr);
176 if (!il3945_hw_valid_rtc_data_addr(base)) {
177 IL_ERR("Invalid event log pointer 0x%08X\n", base);
178 return;
179 }
180
181 disable_ptr = il_read_targ_mem(il, base + (4 * sizeof(u32)));
182 array_size = il_read_targ_mem(il, base + (5 * sizeof(u32)));
183
184 if (IL_EVT_DISABLE && array_size == IL_EVT_DISABLE_SIZE) {
185 D_INFO("Disabling selected uCode log events at 0x%x\n",
186 disable_ptr);
187 for (i = 0; i < IL_EVT_DISABLE_SIZE; i++)
188 il_write_targ_mem(il, disable_ptr + (i * sizeof(u32)),
189 evt_disable[i]);
190
191 } else {
192 D_INFO("Selected uCode log events may be disabled\n");
193 D_INFO(" by writing \"1\"s into disable bitmap\n");
194 D_INFO(" in SRAM at 0x%x, size %d u32s\n", disable_ptr,
195 array_size);
196 }
197
198 }
199
200 static int
201 il3945_hwrate_to_plcp_idx(u8 plcp)
202 {
203 int idx;
204
205 for (idx = 0; idx < RATE_COUNT_3945; idx++)
206 if (il3945_rates[idx].plcp == plcp)
207 return idx;
208 return -1;
209 }
210
211 #ifdef CONFIG_IWLEGACY_DEBUG
212 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
213
214 static const char *
215 il3945_get_tx_fail_reason(u32 status)
216 {
217 switch (status & TX_STATUS_MSK) {
218 case TX_3945_STATUS_SUCCESS:
219 return "SUCCESS";
220 TX_STATUS_ENTRY(SHORT_LIMIT);
221 TX_STATUS_ENTRY(LONG_LIMIT);
222 TX_STATUS_ENTRY(FIFO_UNDERRUN);
223 TX_STATUS_ENTRY(MGMNT_ABORT);
224 TX_STATUS_ENTRY(NEXT_FRAG);
225 TX_STATUS_ENTRY(LIFE_EXPIRE);
226 TX_STATUS_ENTRY(DEST_PS);
227 TX_STATUS_ENTRY(ABORTED);
228 TX_STATUS_ENTRY(BT_RETRY);
229 TX_STATUS_ENTRY(STA_INVALID);
230 TX_STATUS_ENTRY(FRAG_DROPPED);
231 TX_STATUS_ENTRY(TID_DISABLE);
232 TX_STATUS_ENTRY(FRAME_FLUSHED);
233 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
234 TX_STATUS_ENTRY(TX_LOCKED);
235 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
236 }
237
238 return "UNKNOWN";
239 }
240 #else
241 static inline const char *
242 il3945_get_tx_fail_reason(u32 status)
243 {
244 return "";
245 }
246 #endif
247
248 /*
249 * get ieee prev rate from rate scale table.
250 * for A and B mode we need to overright prev
251 * value
252 */
253 int
254 il3945_rs_next_rate(struct il_priv *il, int rate)
255 {
256 int next_rate = il3945_get_prev_ieee_rate(rate);
257
258 switch (il->band) {
259 case IEEE80211_BAND_5GHZ:
260 if (rate == RATE_12M_IDX)
261 next_rate = RATE_9M_IDX;
262 else if (rate == RATE_6M_IDX)
263 next_rate = RATE_6M_IDX;
264 break;
265 case IEEE80211_BAND_2GHZ:
266 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
267 il_is_associated(il)) {
268 if (rate == RATE_11M_IDX)
269 next_rate = RATE_5M_IDX;
270 }
271 break;
272
273 default:
274 break;
275 }
276
277 return next_rate;
278 }
279
280 /**
281 * il3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
282 *
283 * When FW advances 'R' idx, all entries between old and new 'R' idx
284 * need to be reclaimed. As result, some free space forms. If there is
285 * enough free space (> low mark), wake the stack that feeds us.
286 */
287 static void
288 il3945_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
289 {
290 struct il_tx_queue *txq = &il->txq[txq_id];
291 struct il_queue *q = &txq->q;
292 struct sk_buff *skb;
293
294 BUG_ON(txq_id == IL39_CMD_QUEUE_NUM);
295
296 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
297 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
298
299 skb = txq->skbs[txq->q.read_ptr];
300 ieee80211_tx_status_irqsafe(il->hw, skb);
301 txq->skbs[txq->q.read_ptr] = NULL;
302 il->ops->txq_free_tfd(il, txq);
303 }
304
305 if (il_queue_space(q) > q->low_mark && txq_id >= 0 &&
306 txq_id != IL39_CMD_QUEUE_NUM && il->mac80211_registered)
307 il_wake_queue(il, txq);
308 }
309
310 /**
311 * il3945_hdl_tx - Handle Tx response
312 */
313 static void
314 il3945_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
315 {
316 struct il_rx_pkt *pkt = rxb_addr(rxb);
317 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
318 int txq_id = SEQ_TO_QUEUE(sequence);
319 int idx = SEQ_TO_IDX(sequence);
320 struct il_tx_queue *txq = &il->txq[txq_id];
321 struct ieee80211_tx_info *info;
322 struct il3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
323 u32 status = le32_to_cpu(tx_resp->status);
324 int rate_idx;
325 int fail;
326
327 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
328 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
329 "is out of range [0-%d] %d %d\n", txq_id, idx,
330 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
331 return;
332 }
333
334 txq->time_stamp = jiffies;
335 info = IEEE80211_SKB_CB(txq->skbs[txq->q.read_ptr]);
336 ieee80211_tx_info_clear_status(info);
337
338 /* Fill the MRR chain with some info about on-chip retransmissions */
339 rate_idx = il3945_hwrate_to_plcp_idx(tx_resp->rate);
340 if (info->band == IEEE80211_BAND_5GHZ)
341 rate_idx -= IL_FIRST_OFDM_RATE;
342
343 fail = tx_resp->failure_frame;
344
345 info->status.rates[0].idx = rate_idx;
346 info->status.rates[0].count = fail + 1; /* add final attempt */
347
348 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
349 info->flags |=
350 ((status & TX_STATUS_MSK) ==
351 TX_STATUS_SUCCESS) ? IEEE80211_TX_STAT_ACK : 0;
352
353 D_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", txq_id,
354 il3945_get_tx_fail_reason(status), status, tx_resp->rate,
355 tx_resp->failure_frame);
356
357 D_TX_REPLY("Tx queue reclaim %d\n", idx);
358 il3945_tx_queue_reclaim(il, txq_id, idx);
359
360 if (status & TX_ABORT_REQUIRED_MSK)
361 IL_ERR("TODO: Implement Tx ABORT REQUIRED!!!\n");
362 }
363
364 /*****************************************************************************
365 *
366 * Intel PRO/Wireless 3945ABG/BG Network Connection
367 *
368 * RX handler implementations
369 *
370 *****************************************************************************/
371 #ifdef CONFIG_IWLEGACY_DEBUGFS
372 static void
373 il3945_accumulative_stats(struct il_priv *il, __le32 * stats)
374 {
375 int i;
376 __le32 *prev_stats;
377 u32 *accum_stats;
378 u32 *delta, *max_delta;
379
380 prev_stats = (__le32 *) &il->_3945.stats;
381 accum_stats = (u32 *) &il->_3945.accum_stats;
382 delta = (u32 *) &il->_3945.delta_stats;
383 max_delta = (u32 *) &il->_3945.max_delta;
384
385 for (i = sizeof(__le32); i < sizeof(struct il3945_notif_stats);
386 i +=
387 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
388 accum_stats++) {
389 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
390 *delta =
391 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
392 *accum_stats += *delta;
393 if (*delta > *max_delta)
394 *max_delta = *delta;
395 }
396 }
397
398 /* reset accumulative stats for "no-counter" type stats */
399 il->_3945.accum_stats.general.temperature =
400 il->_3945.stats.general.temperature;
401 il->_3945.accum_stats.general.ttl_timestamp =
402 il->_3945.stats.general.ttl_timestamp;
403 }
404 #endif
405
406 void
407 il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
408 {
409 struct il_rx_pkt *pkt = rxb_addr(rxb);
410
411 D_RX("Statistics notification received (%d vs %d).\n",
412 (int)sizeof(struct il3945_notif_stats),
413 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
414 #ifdef CONFIG_IWLEGACY_DEBUGFS
415 il3945_accumulative_stats(il, (__le32 *) &pkt->u.raw);
416 #endif
417
418 memcpy(&il->_3945.stats, pkt->u.raw, sizeof(il->_3945.stats));
419 }
420
421 void
422 il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
423 {
424 struct il_rx_pkt *pkt = rxb_addr(rxb);
425 __le32 *flag = (__le32 *) &pkt->u.raw;
426
427 if (le32_to_cpu(*flag) & UCODE_STATS_CLEAR_MSK) {
428 #ifdef CONFIG_IWLEGACY_DEBUGFS
429 memset(&il->_3945.accum_stats, 0,
430 sizeof(struct il3945_notif_stats));
431 memset(&il->_3945.delta_stats, 0,
432 sizeof(struct il3945_notif_stats));
433 memset(&il->_3945.max_delta, 0,
434 sizeof(struct il3945_notif_stats));
435 #endif
436 D_RX("Statistics have been cleared\n");
437 }
438 il3945_hdl_stats(il, rxb);
439 }
440
441 /******************************************************************************
442 *
443 * Misc. internal state and helper functions
444 *
445 ******************************************************************************/
446
447 /* This is necessary only for a number of stats, see the caller. */
448 static int
449 il3945_is_network_packet(struct il_priv *il, struct ieee80211_hdr *header)
450 {
451 /* Filter incoming packets to determine if they are targeted toward
452 * this network, discarding packets coming from ourselves */
453 switch (il->iw_mode) {
454 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
455 /* packets to our IBSS update information */
456 return !compare_ether_addr(header->addr3, il->bssid);
457 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
458 /* packets to our IBSS update information */
459 return !compare_ether_addr(header->addr2, il->bssid);
460 default:
461 return 1;
462 }
463 }
464
465 static void
466 il3945_pass_packet_to_mac80211(struct il_priv *il, struct il_rx_buf *rxb,
467 struct ieee80211_rx_status *stats)
468 {
469 struct il_rx_pkt *pkt = rxb_addr(rxb);
470 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
471 struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
472 struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
473 u16 len = le16_to_cpu(rx_hdr->len);
474 struct sk_buff *skb;
475 __le16 fc = hdr->frame_control;
476
477 /* We received data from the HW, so stop the watchdog */
478 if (unlikely
479 (len + IL39_RX_FRAME_SIZE >
480 PAGE_SIZE << il->hw_params.rx_page_order)) {
481 D_DROP("Corruption detected!\n");
482 return;
483 }
484
485 /* We only process data packets if the interface is open */
486 if (unlikely(!il->is_open)) {
487 D_DROP("Dropping packet while interface is not open.\n");
488 return;
489 }
490
491 skb = dev_alloc_skb(128);
492 if (!skb) {
493 IL_ERR("dev_alloc_skb failed\n");
494 return;
495 }
496
497 if (!il3945_mod_params.sw_crypto)
498 il_set_decrypted_flag(il, (struct ieee80211_hdr *)rxb_addr(rxb),
499 le32_to_cpu(rx_end->status), stats);
500
501 skb_add_rx_frag(skb, 0, rxb->page,
502 (void *)rx_hdr->payload - (void *)pkt, len);
503
504 il_update_stats(il, false, fc, len);
505 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
506
507 ieee80211_rx(il->hw, skb);
508 il->alloc_rxb_page--;
509 rxb->page = NULL;
510 }
511
512 #define IL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
513
514 static void
515 il3945_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
516 {
517 struct ieee80211_hdr *header;
518 struct ieee80211_rx_status rx_status;
519 struct il_rx_pkt *pkt = rxb_addr(rxb);
520 struct il3945_rx_frame_stats *rx_stats = IL_RX_STATS(pkt);
521 struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
522 struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
523 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
524 u16 rx_stats_noise_diff __maybe_unused =
525 le16_to_cpu(rx_stats->noise_diff);
526 u8 network_packet;
527
528 rx_status.flag = 0;
529 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
530 rx_status.band =
531 (rx_hdr->
532 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
533 IEEE80211_BAND_5GHZ;
534 rx_status.freq =
535 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel),
536 rx_status.band);
537
538 rx_status.rate_idx = il3945_hwrate_to_plcp_idx(rx_hdr->rate);
539 if (rx_status.band == IEEE80211_BAND_5GHZ)
540 rx_status.rate_idx -= IL_FIRST_OFDM_RATE;
541
542 rx_status.antenna =
543 (le16_to_cpu(rx_hdr->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
544 4;
545
546 /* set the preamble flag if appropriate */
547 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
548 rx_status.flag |= RX_FLAG_SHORTPRE;
549
550 if ((unlikely(rx_stats->phy_count > 20))) {
551 D_DROP("dsp size out of range [0,20]: %d/n",
552 rx_stats->phy_count);
553 return;
554 }
555
556 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR) ||
557 !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
558 D_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
559 return;
560 }
561
562 /* Convert 3945's rssi indicator to dBm */
563 rx_status.signal = rx_stats->rssi - IL39_RSSI_OFFSET;
564
565 D_STATS("Rssi %d sig_avg %d noise_diff %d\n", rx_status.signal,
566 rx_stats_sig_avg, rx_stats_noise_diff);
567
568 header = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
569
570 network_packet = il3945_is_network_packet(il, header);
571
572 D_STATS("[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
573 network_packet ? '*' : ' ', le16_to_cpu(rx_hdr->channel),
574 rx_status.signal, rx_status.signal, rx_status.rate_idx);
575
576 if (network_packet) {
577 il->_3945.last_beacon_time =
578 le32_to_cpu(rx_end->beacon_timestamp);
579 il->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
580 il->_3945.last_rx_rssi = rx_status.signal;
581 }
582
583 il3945_pass_packet_to_mac80211(il, rxb, &rx_status);
584 }
585
586 int
587 il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
588 dma_addr_t addr, u16 len, u8 reset, u8 pad)
589 {
590 int count;
591 struct il_queue *q;
592 struct il3945_tfd *tfd, *tfd_tmp;
593
594 q = &txq->q;
595 tfd_tmp = (struct il3945_tfd *)txq->tfds;
596 tfd = &tfd_tmp[q->write_ptr];
597
598 if (reset)
599 memset(tfd, 0, sizeof(*tfd));
600
601 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
602
603 if (count >= NUM_TFD_CHUNKS || count < 0) {
604 IL_ERR("Error can not send more than %d chunks\n",
605 NUM_TFD_CHUNKS);
606 return -EINVAL;
607 }
608
609 tfd->tbs[count].addr = cpu_to_le32(addr);
610 tfd->tbs[count].len = cpu_to_le32(len);
611
612 count++;
613
614 tfd->control_flags =
615 cpu_to_le32(TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad));
616
617 return 0;
618 }
619
620 /**
621 * il3945_hw_txq_free_tfd - Free one TFD, those at idx [txq->q.read_ptr]
622 *
623 * Does NOT advance any idxes
624 */
625 void
626 il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
627 {
628 struct il3945_tfd *tfd_tmp = (struct il3945_tfd *)txq->tfds;
629 int idx = txq->q.read_ptr;
630 struct il3945_tfd *tfd = &tfd_tmp[idx];
631 struct pci_dev *dev = il->pci_dev;
632 int i;
633 int counter;
634
635 /* sanity check */
636 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
637 if (counter > NUM_TFD_CHUNKS) {
638 IL_ERR("Too many chunks: %i\n", counter);
639 /* @todo issue fatal error, it is quite serious situation */
640 return;
641 }
642
643 /* Unmap tx_cmd */
644 if (counter)
645 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
646 dma_unmap_len(&txq->meta[idx], len),
647 PCI_DMA_TODEVICE);
648
649 /* unmap chunks if any */
650
651 for (i = 1; i < counter; i++)
652 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
653 le32_to_cpu(tfd->tbs[i].len),
654 PCI_DMA_TODEVICE);
655
656 /* free SKB */
657 if (txq->skbs) {
658 struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
659
660 /* can be called from irqs-disabled context */
661 if (skb) {
662 dev_kfree_skb_any(skb);
663 txq->skbs[txq->q.read_ptr] = NULL;
664 }
665 }
666 }
667
668 /**
669 * il3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
670 *
671 */
672 void
673 il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
674 struct ieee80211_tx_info *info,
675 struct ieee80211_hdr *hdr, int sta_id)
676 {
677 u16 hw_value = ieee80211_get_tx_rate(il->hw, info)->hw_value;
678 u16 rate_idx = min(hw_value & 0xffff, RATE_COUNT_3945 - 1);
679 u16 rate_mask;
680 int rate;
681 const u8 rts_retry_limit = 7;
682 u8 data_retry_limit;
683 __le32 tx_flags;
684 __le16 fc = hdr->frame_control;
685 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
686
687 rate = il3945_rates[rate_idx].plcp;
688 tx_flags = tx_cmd->tx_flags;
689
690 /* We need to figure out how to get the sta->supp_rates while
691 * in this running context */
692 rate_mask = RATES_MASK_3945;
693
694 /* Set retry limit on DATA packets and Probe Responses */
695 if (ieee80211_is_probe_resp(fc))
696 data_retry_limit = 3;
697 else
698 data_retry_limit = IL_DEFAULT_TX_RETRY;
699 tx_cmd->data_retry_limit = data_retry_limit;
700 /* Set retry limit on RTS packets */
701 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
702
703 tx_cmd->rate = rate;
704 tx_cmd->tx_flags = tx_flags;
705
706 /* OFDM */
707 tx_cmd->supp_rates[0] =
708 ((rate_mask & IL_OFDM_RATES_MASK) >> IL_FIRST_OFDM_RATE) & 0xFF;
709
710 /* CCK */
711 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
712
713 D_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
714 "cck/ofdm mask: 0x%x/0x%x\n", sta_id, tx_cmd->rate,
715 le32_to_cpu(tx_cmd->tx_flags), tx_cmd->supp_rates[1],
716 tx_cmd->supp_rates[0]);
717 }
718
719 static u8
720 il3945_sync_sta(struct il_priv *il, int sta_id, u16 tx_rate)
721 {
722 unsigned long flags_spin;
723 struct il_station_entry *station;
724
725 if (sta_id == IL_INVALID_STATION)
726 return IL_INVALID_STATION;
727
728 spin_lock_irqsave(&il->sta_lock, flags_spin);
729 station = &il->stations[sta_id];
730
731 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
732 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
733 station->sta.mode = STA_CONTROL_MODIFY_MSK;
734 il_send_add_sta(il, &station->sta, CMD_ASYNC);
735 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
736
737 D_RATE("SCALE sync station %d to rate %d\n", sta_id, tx_rate);
738 return sta_id;
739 }
740
741 static void
742 il3945_set_pwr_vmain(struct il_priv *il)
743 {
744 /*
745 * (for documentation purposes)
746 * to set power to V_AUX, do
747
748 if (pci_pme_capable(il->pci_dev, PCI_D3cold)) {
749 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
750 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
751 ~APMG_PS_CTRL_MSK_PWR_SRC);
752
753 _il_poll_bit(il, CSR_GPIO_IN,
754 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
755 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
756 }
757 */
758
759 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
760 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
761 ~APMG_PS_CTRL_MSK_PWR_SRC);
762
763 _il_poll_bit(il, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
764 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
765 }
766
767 static int
768 il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
769 {
770 il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
771 il_wr(il, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
772 il_wr(il, FH39_RCSR_WPTR(0), 0);
773 il_wr(il, FH39_RCSR_CONFIG(0),
774 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
775 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
776 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
777 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 | (RX_QUEUE_SIZE_LOG
778 <<
779 FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE)
780 | FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST | (1 <<
781 FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH)
782 | FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
783
784 /* fake read to flush all prev I/O */
785 il_rd(il, FH39_RSSR_CTRL);
786
787 return 0;
788 }
789
790 static int
791 il3945_tx_reset(struct il_priv *il)
792 {
793 /* bypass mode */
794 il_wr_prph(il, ALM_SCD_MODE_REG, 0x2);
795
796 /* RA 0 is active */
797 il_wr_prph(il, ALM_SCD_ARASTAT_REG, 0x01);
798
799 /* all 6 fifo are active */
800 il_wr_prph(il, ALM_SCD_TXFACT_REG, 0x3f);
801
802 il_wr_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
803 il_wr_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
804 il_wr_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);
805 il_wr_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);
806
807 il_wr(il, FH39_TSSR_CBB_BASE, il->_3945.shared_phys);
808
809 il_wr(il, FH39_TSSR_MSG_CONFIG,
810 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
811 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
812 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
813 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
814 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
815 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
816 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
817
818 return 0;
819 }
820
821 /**
822 * il3945_txq_ctx_reset - Reset TX queue context
823 *
824 * Destroys all DMA structures and initialize them again
825 */
826 static int
827 il3945_txq_ctx_reset(struct il_priv *il)
828 {
829 int rc, txq_id;
830
831 il3945_hw_txq_ctx_free(il);
832
833 /* allocate tx queue structure */
834 rc = il_alloc_txq_mem(il);
835 if (rc)
836 return rc;
837
838 /* Tx CMD queue */
839 rc = il3945_tx_reset(il);
840 if (rc)
841 goto error;
842
843 /* Tx queue(s) */
844 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
845 rc = il_tx_queue_init(il, txq_id);
846 if (rc) {
847 IL_ERR("Tx %d queue init failed\n", txq_id);
848 goto error;
849 }
850 }
851
852 return rc;
853
854 error:
855 il3945_hw_txq_ctx_free(il);
856 return rc;
857 }
858
859 /*
860 * Start up 3945's basic functionality after it has been reset
861 * (e.g. after platform boot, or shutdown via il_apm_stop())
862 * NOTE: This does not load uCode nor start the embedded processor
863 */
864 static int
865 il3945_apm_init(struct il_priv *il)
866 {
867 int ret = il_apm_init(il);
868
869 /* Clear APMG (NIC's internal power management) interrupts */
870 il_wr_prph(il, APMG_RTC_INT_MSK_REG, 0x0);
871 il_wr_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
872
873 /* Reset radio chip */
874 il_set_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
875 udelay(5);
876 il_clear_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
877
878 return ret;
879 }
880
881 static void
882 il3945_nic_config(struct il_priv *il)
883 {
884 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
885 unsigned long flags;
886 u8 rev_id = il->pci_dev->revision;
887
888 spin_lock_irqsave(&il->lock, flags);
889
890 /* Determine HW type */
891 D_INFO("HW Revision ID = 0x%X\n", rev_id);
892
893 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
894 D_INFO("RTP type\n");
895 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
896 D_INFO("3945 RADIO-MB type\n");
897 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
898 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
899 } else {
900 D_INFO("3945 RADIO-MM type\n");
901 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
902 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
903 }
904
905 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
906 D_INFO("SKU OP mode is mrc\n");
907 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
908 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
909 } else
910 D_INFO("SKU OP mode is basic\n");
911
912 if ((eeprom->board_revision & 0xF0) == 0xD0) {
913 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision);
914 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
915 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
916 } else {
917 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision);
918 il_clear_bit(il, CSR_HW_IF_CONFIG_REG,
919 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
920 }
921
922 if (eeprom->almgor_m_version <= 1) {
923 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
924 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
925 D_INFO("Card M type A version is 0x%X\n",
926 eeprom->almgor_m_version);
927 } else {
928 D_INFO("Card M type B version is 0x%X\n",
929 eeprom->almgor_m_version);
930 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
931 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
932 }
933 spin_unlock_irqrestore(&il->lock, flags);
934
935 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
936 D_RF_KILL("SW RF KILL supported in EEPROM.\n");
937
938 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
939 D_RF_KILL("HW RF KILL supported in EEPROM.\n");
940 }
941
942 int
943 il3945_hw_nic_init(struct il_priv *il)
944 {
945 int rc;
946 unsigned long flags;
947 struct il_rx_queue *rxq = &il->rxq;
948
949 spin_lock_irqsave(&il->lock, flags);
950 il3945_apm_init(il);
951 spin_unlock_irqrestore(&il->lock, flags);
952
953 il3945_set_pwr_vmain(il);
954 il3945_nic_config(il);
955
956 /* Allocate the RX queue, or reset if it is already allocated */
957 if (!rxq->bd) {
958 rc = il_rx_queue_alloc(il);
959 if (rc) {
960 IL_ERR("Unable to initialize Rx queue\n");
961 return -ENOMEM;
962 }
963 } else
964 il3945_rx_queue_reset(il, rxq);
965
966 il3945_rx_replenish(il);
967
968 il3945_rx_init(il, rxq);
969
970 /* Look at using this instead:
971 rxq->need_update = 1;
972 il_rx_queue_update_write_ptr(il, rxq);
973 */
974
975 il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7);
976
977 rc = il3945_txq_ctx_reset(il);
978 if (rc)
979 return rc;
980
981 set_bit(S_INIT, &il->status);
982
983 return 0;
984 }
985
986 /**
987 * il3945_hw_txq_ctx_free - Free TXQ Context
988 *
989 * Destroy all TX DMA queues and structures
990 */
991 void
992 il3945_hw_txq_ctx_free(struct il_priv *il)
993 {
994 int txq_id;
995
996 /* Tx queues */
997 if (il->txq)
998 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
999 if (txq_id == IL39_CMD_QUEUE_NUM)
1000 il_cmd_queue_free(il);
1001 else
1002 il_tx_queue_free(il, txq_id);
1003
1004 /* free tx queue structure */
1005 il_free_txq_mem(il);
1006 }
1007
1008 void
1009 il3945_hw_txq_ctx_stop(struct il_priv *il)
1010 {
1011 int txq_id;
1012
1013 /* stop SCD */
1014 _il_wr_prph(il, ALM_SCD_MODE_REG, 0);
1015 _il_wr_prph(il, ALM_SCD_TXFACT_REG, 0);
1016
1017 /* reset TFD queues */
1018 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
1019 _il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0);
1020 _il_poll_bit(il, FH39_TSSR_TX_STATUS,
1021 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1022 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1023 1000);
1024 }
1025 }
1026
1027 /**
1028 * il3945_hw_reg_adjust_power_by_temp
1029 * return idx delta into power gain settings table
1030 */
1031 static int
1032 il3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1033 {
1034 return (new_reading - old_reading) * (-11) / 100;
1035 }
1036
1037 /**
1038 * il3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1039 */
1040 static inline int
1041 il3945_hw_reg_temp_out_of_range(int temperature)
1042 {
1043 return (temperature < -260 || temperature > 25) ? 1 : 0;
1044 }
1045
1046 int
1047 il3945_hw_get_temperature(struct il_priv *il)
1048 {
1049 return _il_rd(il, CSR_UCODE_DRV_GP2);
1050 }
1051
1052 /**
1053 * il3945_hw_reg_txpower_get_temperature
1054 * get the current temperature by reading from NIC
1055 */
1056 static int
1057 il3945_hw_reg_txpower_get_temperature(struct il_priv *il)
1058 {
1059 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1060 int temperature;
1061
1062 temperature = il3945_hw_get_temperature(il);
1063
1064 /* driver's okay range is -260 to +25.
1065 * human readable okay range is 0 to +285 */
1066 D_INFO("Temperature: %d\n", temperature + IL_TEMP_CONVERT);
1067
1068 /* handle insane temp reading */
1069 if (il3945_hw_reg_temp_out_of_range(temperature)) {
1070 IL_ERR("Error bad temperature value %d\n", temperature);
1071
1072 /* if really really hot(?),
1073 * substitute the 3rd band/group's temp measured at factory */
1074 if (il->last_temperature > 100)
1075 temperature = eeprom->groups[2].temperature;
1076 else /* else use most recent "sane" value from driver */
1077 temperature = il->last_temperature;
1078 }
1079
1080 return temperature; /* raw, not "human readable" */
1081 }
1082
1083 /* Adjust Txpower only if temperature variance is greater than threshold.
1084 *
1085 * Both are lower than older versions' 9 degrees */
1086 #define IL_TEMPERATURE_LIMIT_TIMER 6
1087
1088 /**
1089 * il3945_is_temp_calib_needed - determines if new calibration is needed
1090 *
1091 * records new temperature in tx_mgr->temperature.
1092 * replaces tx_mgr->last_temperature *only* if calib needed
1093 * (assumes caller will actually do the calibration!). */
1094 static int
1095 il3945_is_temp_calib_needed(struct il_priv *il)
1096 {
1097 int temp_diff;
1098
1099 il->temperature = il3945_hw_reg_txpower_get_temperature(il);
1100 temp_diff = il->temperature - il->last_temperature;
1101
1102 /* get absolute value */
1103 if (temp_diff < 0) {
1104 D_POWER("Getting cooler, delta %d,\n", temp_diff);
1105 temp_diff = -temp_diff;
1106 } else if (temp_diff == 0)
1107 D_POWER("Same temp,\n");
1108 else
1109 D_POWER("Getting warmer, delta %d,\n", temp_diff);
1110
1111 /* if we don't need calibration, *don't* update last_temperature */
1112 if (temp_diff < IL_TEMPERATURE_LIMIT_TIMER) {
1113 D_POWER("Timed thermal calib not needed\n");
1114 return 0;
1115 }
1116
1117 D_POWER("Timed thermal calib needed\n");
1118
1119 /* assume that caller will actually do calib ...
1120 * update the "last temperature" value */
1121 il->last_temperature = il->temperature;
1122 return 1;
1123 }
1124
1125 #define IL_MAX_GAIN_ENTRIES 78
1126 #define IL_CCK_FROM_OFDM_POWER_DIFF -5
1127 #define IL_CCK_FROM_OFDM_IDX_DIFF (10)
1128
1129 /* radio and DSP power table, each step is 1/2 dB.
1130 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1131 static struct il3945_tx_power power_gain_table[2][IL_MAX_GAIN_ENTRIES] = {
1132 {
1133 {251, 127}, /* 2.4 GHz, highest power */
1134 {251, 127},
1135 {251, 127},
1136 {251, 127},
1137 {251, 125},
1138 {251, 110},
1139 {251, 105},
1140 {251, 98},
1141 {187, 125},
1142 {187, 115},
1143 {187, 108},
1144 {187, 99},
1145 {243, 119},
1146 {243, 111},
1147 {243, 105},
1148 {243, 97},
1149 {243, 92},
1150 {211, 106},
1151 {211, 100},
1152 {179, 120},
1153 {179, 113},
1154 {179, 107},
1155 {147, 125},
1156 {147, 119},
1157 {147, 112},
1158 {147, 106},
1159 {147, 101},
1160 {147, 97},
1161 {147, 91},
1162 {115, 107},
1163 {235, 121},
1164 {235, 115},
1165 {235, 109},
1166 {203, 127},
1167 {203, 121},
1168 {203, 115},
1169 {203, 108},
1170 {203, 102},
1171 {203, 96},
1172 {203, 92},
1173 {171, 110},
1174 {171, 104},
1175 {171, 98},
1176 {139, 116},
1177 {227, 125},
1178 {227, 119},
1179 {227, 113},
1180 {227, 107},
1181 {227, 101},
1182 {227, 96},
1183 {195, 113},
1184 {195, 106},
1185 {195, 102},
1186 {195, 95},
1187 {163, 113},
1188 {163, 106},
1189 {163, 102},
1190 {163, 95},
1191 {131, 113},
1192 {131, 106},
1193 {131, 102},
1194 {131, 95},
1195 {99, 113},
1196 {99, 106},
1197 {99, 102},
1198 {99, 95},
1199 {67, 113},
1200 {67, 106},
1201 {67, 102},
1202 {67, 95},
1203 {35, 113},
1204 {35, 106},
1205 {35, 102},
1206 {35, 95},
1207 {3, 113},
1208 {3, 106},
1209 {3, 102},
1210 {3, 95} /* 2.4 GHz, lowest power */
1211 },
1212 {
1213 {251, 127}, /* 5.x GHz, highest power */
1214 {251, 120},
1215 {251, 114},
1216 {219, 119},
1217 {219, 101},
1218 {187, 113},
1219 {187, 102},
1220 {155, 114},
1221 {155, 103},
1222 {123, 117},
1223 {123, 107},
1224 {123, 99},
1225 {123, 92},
1226 {91, 108},
1227 {59, 125},
1228 {59, 118},
1229 {59, 109},
1230 {59, 102},
1231 {59, 96},
1232 {59, 90},
1233 {27, 104},
1234 {27, 98},
1235 {27, 92},
1236 {115, 118},
1237 {115, 111},
1238 {115, 104},
1239 {83, 126},
1240 {83, 121},
1241 {83, 113},
1242 {83, 105},
1243 {83, 99},
1244 {51, 118},
1245 {51, 111},
1246 {51, 104},
1247 {51, 98},
1248 {19, 116},
1249 {19, 109},
1250 {19, 102},
1251 {19, 98},
1252 {19, 93},
1253 {171, 113},
1254 {171, 107},
1255 {171, 99},
1256 {139, 120},
1257 {139, 113},
1258 {139, 107},
1259 {139, 99},
1260 {107, 120},
1261 {107, 113},
1262 {107, 107},
1263 {107, 99},
1264 {75, 120},
1265 {75, 113},
1266 {75, 107},
1267 {75, 99},
1268 {43, 120},
1269 {43, 113},
1270 {43, 107},
1271 {43, 99},
1272 {11, 120},
1273 {11, 113},
1274 {11, 107},
1275 {11, 99},
1276 {131, 107},
1277 {131, 99},
1278 {99, 120},
1279 {99, 113},
1280 {99, 107},
1281 {99, 99},
1282 {67, 120},
1283 {67, 113},
1284 {67, 107},
1285 {67, 99},
1286 {35, 120},
1287 {35, 113},
1288 {35, 107},
1289 {35, 99},
1290 {3, 120} /* 5.x GHz, lowest power */
1291 }
1292 };
1293
1294 static inline u8
1295 il3945_hw_reg_fix_power_idx(int idx)
1296 {
1297 if (idx < 0)
1298 return 0;
1299 if (idx >= IL_MAX_GAIN_ENTRIES)
1300 return IL_MAX_GAIN_ENTRIES - 1;
1301 return (u8) idx;
1302 }
1303
1304 /* Kick off thermal recalibration check every 60 seconds */
1305 #define REG_RECALIB_PERIOD (60)
1306
1307 /**
1308 * il3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1309 *
1310 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1311 * or 6 Mbit (OFDM) rates.
1312 */
1313 static void
1314 il3945_hw_reg_set_scan_power(struct il_priv *il, u32 scan_tbl_idx, s32 rate_idx,
1315 const s8 *clip_pwrs,
1316 struct il_channel_info *ch_info, int band_idx)
1317 {
1318 struct il3945_scan_power_info *scan_power_info;
1319 s8 power;
1320 u8 power_idx;
1321
1322 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_idx];
1323
1324 /* use this channel group's 6Mbit clipping/saturation pwr,
1325 * but cap at regulatory scan power restriction (set during init
1326 * based on eeprom channel data) for this channel. */
1327 power = min(ch_info->scan_power, clip_pwrs[RATE_6M_IDX_TBL]);
1328
1329 power = min(power, il->tx_power_user_lmt);
1330 scan_power_info->requested_power = power;
1331
1332 /* find difference between new scan *power* and current "normal"
1333 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1334 * current "normal" temperature-compensated Tx power *idx* for
1335 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1336 * *idx*. */
1337 power_idx =
1338 ch_info->power_info[rate_idx].power_table_idx - (power -
1339 ch_info->
1340 power_info
1341 [RATE_6M_IDX_TBL].
1342 requested_power) *
1343 2;
1344
1345 /* store reference idx that we use when adjusting *all* scan
1346 * powers. So we can accommodate user (all channel) or spectrum
1347 * management (single channel) power changes "between" temperature
1348 * feedback compensation procedures.
1349 * don't force fit this reference idx into gain table; it may be a
1350 * negative number. This will help avoid errors when we're at
1351 * the lower bounds (highest gains, for warmest temperatures)
1352 * of the table. */
1353
1354 /* don't exceed table bounds for "real" setting */
1355 power_idx = il3945_hw_reg_fix_power_idx(power_idx);
1356
1357 scan_power_info->power_table_idx = power_idx;
1358 scan_power_info->tpc.tx_gain =
1359 power_gain_table[band_idx][power_idx].tx_gain;
1360 scan_power_info->tpc.dsp_atten =
1361 power_gain_table[band_idx][power_idx].dsp_atten;
1362 }
1363
1364 /**
1365 * il3945_send_tx_power - fill in Tx Power command with gain settings
1366 *
1367 * Configures power settings for all rates for the current channel,
1368 * using values from channel info struct, and send to NIC
1369 */
1370 static int
1371 il3945_send_tx_power(struct il_priv *il)
1372 {
1373 int rate_idx, i;
1374 const struct il_channel_info *ch_info = NULL;
1375 struct il3945_txpowertable_cmd txpower = {
1376 .channel = il->active.channel,
1377 };
1378 u16 chan;
1379
1380 if (WARN_ONCE
1381 (test_bit(S_SCAN_HW, &il->status),
1382 "TX Power requested while scanning!\n"))
1383 return -EAGAIN;
1384
1385 chan = le16_to_cpu(il->active.channel);
1386
1387 txpower.band = (il->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1388 ch_info = il_get_channel_info(il, il->band, chan);
1389 if (!ch_info) {
1390 IL_ERR("Failed to get channel info for channel %d [%d]\n", chan,
1391 il->band);
1392 return -EINVAL;
1393 }
1394
1395 if (!il_is_channel_valid(ch_info)) {
1396 D_POWER("Not calling TX_PWR_TBL_CMD on " "non-Tx channel.\n");
1397 return 0;
1398 }
1399
1400 /* fill cmd with power settings for all rates for current channel */
1401 /* Fill OFDM rate */
1402 for (rate_idx = IL_FIRST_OFDM_RATE, i = 0;
1403 rate_idx <= IL39_LAST_OFDM_RATE; rate_idx++, i++) {
1404
1405 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1406 txpower.power[i].rate = il3945_rates[rate_idx].plcp;
1407
1408 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1409 le16_to_cpu(txpower.channel), txpower.band,
1410 txpower.power[i].tpc.tx_gain,
1411 txpower.power[i].tpc.dsp_atten, txpower.power[i].rate);
1412 }
1413 /* Fill CCK rates */
1414 for (rate_idx = IL_FIRST_CCK_RATE; rate_idx <= IL_LAST_CCK_RATE;
1415 rate_idx++, i++) {
1416 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1417 txpower.power[i].rate = il3945_rates[rate_idx].plcp;
1418
1419 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1420 le16_to_cpu(txpower.channel), txpower.band,
1421 txpower.power[i].tpc.tx_gain,
1422 txpower.power[i].tpc.dsp_atten, txpower.power[i].rate);
1423 }
1424
1425 return il_send_cmd_pdu(il, C_TX_PWR_TBL,
1426 sizeof(struct il3945_txpowertable_cmd),
1427 &txpower);
1428
1429 }
1430
1431 /**
1432 * il3945_hw_reg_set_new_power - Configures power tables at new levels
1433 * @ch_info: Channel to update. Uses power_info.requested_power.
1434 *
1435 * Replace requested_power and base_power_idx ch_info fields for
1436 * one channel.
1437 *
1438 * Called if user or spectrum management changes power preferences.
1439 * Takes into account h/w and modulation limitations (clip power).
1440 *
1441 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1442 *
1443 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1444 * properly fill out the scan powers, and actual h/w gain settings,
1445 * and send changes to NIC
1446 */
1447 static int
1448 il3945_hw_reg_set_new_power(struct il_priv *il, struct il_channel_info *ch_info)
1449 {
1450 struct il3945_channel_power_info *power_info;
1451 int power_changed = 0;
1452 int i;
1453 const s8 *clip_pwrs;
1454 int power;
1455
1456 /* Get this chnlgrp's rate-to-max/clip-powers table */
1457 clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers;
1458
1459 /* Get this channel's rate-to-current-power settings table */
1460 power_info = ch_info->power_info;
1461
1462 /* update OFDM Txpower settings */
1463 for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++, ++power_info) {
1464 int delta_idx;
1465
1466 /* limit new power to be no more than h/w capability */
1467 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1468 if (power == power_info->requested_power)
1469 continue;
1470
1471 /* find difference between old and new requested powers,
1472 * update base (non-temp-compensated) power idx */
1473 delta_idx = (power - power_info->requested_power) * 2;
1474 power_info->base_power_idx -= delta_idx;
1475
1476 /* save new requested power value */
1477 power_info->requested_power = power;
1478
1479 power_changed = 1;
1480 }
1481
1482 /* update CCK Txpower settings, based on OFDM 12M setting ...
1483 * ... all CCK power settings for a given channel are the *same*. */
1484 if (power_changed) {
1485 power =
1486 ch_info->power_info[RATE_12M_IDX_TBL].requested_power +
1487 IL_CCK_FROM_OFDM_POWER_DIFF;
1488
1489 /* do all CCK rates' il3945_channel_power_info structures */
1490 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++) {
1491 power_info->requested_power = power;
1492 power_info->base_power_idx =
1493 ch_info->power_info[RATE_12M_IDX_TBL].
1494 base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
1495 ++power_info;
1496 }
1497 }
1498
1499 return 0;
1500 }
1501
1502 /**
1503 * il3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1504 *
1505 * NOTE: Returned power limit may be less (but not more) than requested,
1506 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1507 * (no consideration for h/w clipping limitations).
1508 */
1509 static int
1510 il3945_hw_reg_get_ch_txpower_limit(struct il_channel_info *ch_info)
1511 {
1512 s8 max_power;
1513
1514 #if 0
1515 /* if we're using TGd limits, use lower of TGd or EEPROM */
1516 if (ch_info->tgd_data.max_power != 0)
1517 max_power =
1518 min(ch_info->tgd_data.max_power,
1519 ch_info->eeprom.max_power_avg);
1520
1521 /* else just use EEPROM limits */
1522 else
1523 #endif
1524 max_power = ch_info->eeprom.max_power_avg;
1525
1526 return min(max_power, ch_info->max_power_avg);
1527 }
1528
1529 /**
1530 * il3945_hw_reg_comp_txpower_temp - Compensate for temperature
1531 *
1532 * Compensate txpower settings of *all* channels for temperature.
1533 * This only accounts for the difference between current temperature
1534 * and the factory calibration temperatures, and bases the new settings
1535 * on the channel's base_power_idx.
1536 *
1537 * If RxOn is "associated", this sends the new Txpower to NIC!
1538 */
1539 static int
1540 il3945_hw_reg_comp_txpower_temp(struct il_priv *il)
1541 {
1542 struct il_channel_info *ch_info = NULL;
1543 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1544 int delta_idx;
1545 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1546 u8 a_band;
1547 u8 rate_idx;
1548 u8 scan_tbl_idx;
1549 u8 i;
1550 int ref_temp;
1551 int temperature = il->temperature;
1552
1553 if (il->disable_tx_power_cal || test_bit(S_SCANNING, &il->status)) {
1554 /* do not perform tx power calibration */
1555 return 0;
1556 }
1557 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1558 for (i = 0; i < il->channel_count; i++) {
1559 ch_info = &il->channel_info[i];
1560 a_band = il_is_channel_a_band(ch_info);
1561
1562 /* Get this chnlgrp's factory calibration temperature */
1563 ref_temp = (s16) eeprom->groups[ch_info->group_idx].temperature;
1564
1565 /* get power idx adjustment based on current and factory
1566 * temps */
1567 delta_idx =
1568 il3945_hw_reg_adjust_power_by_temp(temperature, ref_temp);
1569
1570 /* set tx power value for all rates, OFDM and CCK */
1571 for (rate_idx = 0; rate_idx < RATE_COUNT_3945; rate_idx++) {
1572 int power_idx =
1573 ch_info->power_info[rate_idx].base_power_idx;
1574
1575 /* temperature compensate */
1576 power_idx += delta_idx;
1577
1578 /* stay within table range */
1579 power_idx = il3945_hw_reg_fix_power_idx(power_idx);
1580 ch_info->power_info[rate_idx].power_table_idx =
1581 (u8) power_idx;
1582 ch_info->power_info[rate_idx].tpc =
1583 power_gain_table[a_band][power_idx];
1584 }
1585
1586 /* Get this chnlgrp's rate-to-max/clip-powers table */
1587 clip_pwrs =
1588 il->_3945.clip_groups[ch_info->group_idx].clip_powers;
1589
1590 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1591 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES;
1592 scan_tbl_idx++) {
1593 s32 actual_idx =
1594 (scan_tbl_idx ==
1595 0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
1596 il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
1597 actual_idx, clip_pwrs,
1598 ch_info, a_band);
1599 }
1600 }
1601
1602 /* send Txpower command for current channel to ucode */
1603 return il->ops->send_tx_power(il);
1604 }
1605
1606 int
1607 il3945_hw_reg_set_txpower(struct il_priv *il, s8 power)
1608 {
1609 struct il_channel_info *ch_info;
1610 s8 max_power;
1611 u8 a_band;
1612 u8 i;
1613
1614 if (il->tx_power_user_lmt == power) {
1615 D_POWER("Requested Tx power same as current " "limit: %ddBm.\n",
1616 power);
1617 return 0;
1618 }
1619
1620 D_POWER("Setting upper limit clamp to %ddBm.\n", power);
1621 il->tx_power_user_lmt = power;
1622
1623 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1624
1625 for (i = 0; i < il->channel_count; i++) {
1626 ch_info = &il->channel_info[i];
1627 a_band = il_is_channel_a_band(ch_info);
1628
1629 /* find minimum power of all user and regulatory constraints
1630 * (does not consider h/w clipping limitations) */
1631 max_power = il3945_hw_reg_get_ch_txpower_limit(ch_info);
1632 max_power = min(power, max_power);
1633 if (max_power != ch_info->curr_txpow) {
1634 ch_info->curr_txpow = max_power;
1635
1636 /* this considers the h/w clipping limitations */
1637 il3945_hw_reg_set_new_power(il, ch_info);
1638 }
1639 }
1640
1641 /* update txpower settings for all channels,
1642 * send to NIC if associated. */
1643 il3945_is_temp_calib_needed(il);
1644 il3945_hw_reg_comp_txpower_temp(il);
1645
1646 return 0;
1647 }
1648
1649 static int
1650 il3945_send_rxon_assoc(struct il_priv *il)
1651 {
1652 int rc = 0;
1653 struct il_rx_pkt *pkt;
1654 struct il3945_rxon_assoc_cmd rxon_assoc;
1655 struct il_host_cmd cmd = {
1656 .id = C_RXON_ASSOC,
1657 .len = sizeof(rxon_assoc),
1658 .flags = CMD_WANT_SKB,
1659 .data = &rxon_assoc,
1660 };
1661 const struct il_rxon_cmd *rxon1 = &il->staging;
1662 const struct il_rxon_cmd *rxon2 = &il->active;
1663
1664 if (rxon1->flags == rxon2->flags &&
1665 rxon1->filter_flags == rxon2->filter_flags &&
1666 rxon1->cck_basic_rates == rxon2->cck_basic_rates &&
1667 rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates) {
1668 D_INFO("Using current RXON_ASSOC. Not resending.\n");
1669 return 0;
1670 }
1671
1672 rxon_assoc.flags = il->staging.flags;
1673 rxon_assoc.filter_flags = il->staging.filter_flags;
1674 rxon_assoc.ofdm_basic_rates = il->staging.ofdm_basic_rates;
1675 rxon_assoc.cck_basic_rates = il->staging.cck_basic_rates;
1676 rxon_assoc.reserved = 0;
1677
1678 rc = il_send_cmd_sync(il, &cmd);
1679 if (rc)
1680 return rc;
1681
1682 pkt = (struct il_rx_pkt *)cmd.reply_page;
1683 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
1684 IL_ERR("Bad return from C_RXON_ASSOC command\n");
1685 rc = -EIO;
1686 }
1687
1688 il_free_pages(il, cmd.reply_page);
1689
1690 return rc;
1691 }
1692
1693 /**
1694 * il3945_commit_rxon - commit staging_rxon to hardware
1695 *
1696 * The RXON command in staging_rxon is committed to the hardware and
1697 * the active_rxon structure is updated with the new data. This
1698 * function correctly transitions out of the RXON_ASSOC_MSK state if
1699 * a HW tune is required based on the RXON structure changes.
1700 */
1701 int
1702 il3945_commit_rxon(struct il_priv *il)
1703 {
1704 /* cast away the const for active_rxon in this function */
1705 struct il3945_rxon_cmd *active_rxon = (void *)&il->active;
1706 struct il3945_rxon_cmd *staging_rxon = (void *)&il->staging;
1707 int rc = 0;
1708 bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
1709
1710 if (test_bit(S_EXIT_PENDING, &il->status))
1711 return -EINVAL;
1712
1713 if (!il_is_alive(il))
1714 return -1;
1715
1716 /* always get timestamp with Rx frame */
1717 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1718
1719 /* select antenna */
1720 staging_rxon->flags &= ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1721 staging_rxon->flags |= il3945_get_antenna_flags(il);
1722
1723 rc = il_check_rxon_cmd(il);
1724 if (rc) {
1725 IL_ERR("Invalid RXON configuration. Not committing.\n");
1726 return -EINVAL;
1727 }
1728
1729 /* If we don't need to send a full RXON, we can use
1730 * il3945_rxon_assoc_cmd which is used to reconfigure filter
1731 * and other flags for the current radio configuration. */
1732 if (!il_full_rxon_required(il)) {
1733 rc = il_send_rxon_assoc(il);
1734 if (rc) {
1735 IL_ERR("Error setting RXON_ASSOC "
1736 "configuration (%d).\n", rc);
1737 return rc;
1738 }
1739
1740 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1741 /*
1742 * We do not commit tx power settings while channel changing,
1743 * do it now if tx power changed.
1744 */
1745 il_set_tx_power(il, il->tx_power_next, false);
1746 return 0;
1747 }
1748
1749 /* If we are currently associated and the new config requires
1750 * an RXON_ASSOC and the new config wants the associated mask enabled,
1751 * we must clear the associated from the active configuration
1752 * before we apply the new config */
1753 if (il_is_associated(il) && new_assoc) {
1754 D_INFO("Toggling associated bit on current RXON\n");
1755 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1756
1757 /*
1758 * reserved4 and 5 could have been filled by the iwlcore code.
1759 * Let's clear them before pushing to the 3945.
1760 */
1761 active_rxon->reserved4 = 0;
1762 active_rxon->reserved5 = 0;
1763 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1764 &il->active);
1765
1766 /* If the mask clearing failed then we set
1767 * active_rxon back to what it was previously */
1768 if (rc) {
1769 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1770 IL_ERR("Error clearing ASSOC_MSK on current "
1771 "configuration (%d).\n", rc);
1772 return rc;
1773 }
1774 il_clear_ucode_stations(il);
1775 il_restore_stations(il);
1776 }
1777
1778 D_INFO("Sending RXON\n" "* with%s RXON_FILTER_ASSOC_MSK\n"
1779 "* channel = %d\n" "* bssid = %pM\n", (new_assoc ? "" : "out"),
1780 le16_to_cpu(staging_rxon->channel), staging_rxon->bssid_addr);
1781
1782 /*
1783 * reserved4 and 5 could have been filled by the iwlcore code.
1784 * Let's clear them before pushing to the 3945.
1785 */
1786 staging_rxon->reserved4 = 0;
1787 staging_rxon->reserved5 = 0;
1788
1789 il_set_rxon_hwcrypto(il, !il3945_mod_params.sw_crypto);
1790
1791 /* Apply the new configuration */
1792 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1793 staging_rxon);
1794 if (rc) {
1795 IL_ERR("Error setting new configuration (%d).\n", rc);
1796 return rc;
1797 }
1798
1799 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1800
1801 if (!new_assoc) {
1802 il_clear_ucode_stations(il);
1803 il_restore_stations(il);
1804 }
1805
1806 /* If we issue a new RXON command which required a tune then we must
1807 * send a new TXPOWER command or we won't be able to Tx any frames */
1808 rc = il_set_tx_power(il, il->tx_power_next, true);
1809 if (rc) {
1810 IL_ERR("Error setting Tx power (%d).\n", rc);
1811 return rc;
1812 }
1813
1814 /* Init the hardware's rate fallback order based on the band */
1815 rc = il3945_init_hw_rate_table(il);
1816 if (rc) {
1817 IL_ERR("Error setting HW rate table: %02X\n", rc);
1818 return -EIO;
1819 }
1820
1821 return 0;
1822 }
1823
1824 /**
1825 * il3945_reg_txpower_periodic - called when time to check our temperature.
1826 *
1827 * -- reset periodic timer
1828 * -- see if temp has changed enough to warrant re-calibration ... if so:
1829 * -- correct coeffs for temp (can reset temp timer)
1830 * -- save this temp as "last",
1831 * -- send new set of gain settings to NIC
1832 * NOTE: This should continue working, even when we're not associated,
1833 * so we can keep our internal table of scan powers current. */
1834 void
1835 il3945_reg_txpower_periodic(struct il_priv *il)
1836 {
1837 /* This will kick in the "brute force"
1838 * il3945_hw_reg_comp_txpower_temp() below */
1839 if (!il3945_is_temp_calib_needed(il))
1840 goto reschedule;
1841
1842 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1843 * This is based *only* on current temperature,
1844 * ignoring any previous power measurements */
1845 il3945_hw_reg_comp_txpower_temp(il);
1846
1847 reschedule:
1848 queue_delayed_work(il->workqueue, &il->_3945.thermal_periodic,
1849 REG_RECALIB_PERIOD * HZ);
1850 }
1851
1852 static void
1853 il3945_bg_reg_txpower_periodic(struct work_struct *work)
1854 {
1855 struct il_priv *il = container_of(work, struct il_priv,
1856 _3945.thermal_periodic.work);
1857
1858 if (test_bit(S_EXIT_PENDING, &il->status))
1859 return;
1860
1861 mutex_lock(&il->mutex);
1862 il3945_reg_txpower_periodic(il);
1863 mutex_unlock(&il->mutex);
1864 }
1865
1866 /**
1867 * il3945_hw_reg_get_ch_grp_idx - find the channel-group idx (0-4) for channel.
1868 *
1869 * This function is used when initializing channel-info structs.
1870 *
1871 * NOTE: These channel groups do *NOT* match the bands above!
1872 * These channel groups are based on factory-tested channels;
1873 * on A-band, EEPROM's "group frequency" entries represent the top
1874 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1875 */
1876 static u16
1877 il3945_hw_reg_get_ch_grp_idx(struct il_priv *il,
1878 const struct il_channel_info *ch_info)
1879 {
1880 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1881 struct il3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1882 u8 group;
1883 u16 group_idx = 0; /* based on factory calib frequencies */
1884 u8 grp_channel;
1885
1886 /* Find the group idx for the channel ... don't use idx 1(?) */
1887 if (il_is_channel_a_band(ch_info)) {
1888 for (group = 1; group < 5; group++) {
1889 grp_channel = ch_grp[group].group_channel;
1890 if (ch_info->channel <= grp_channel) {
1891 group_idx = group;
1892 break;
1893 }
1894 }
1895 /* group 4 has a few channels *above* its factory cal freq */
1896 if (group == 5)
1897 group_idx = 4;
1898 } else
1899 group_idx = 0; /* 2.4 GHz, group 0 */
1900
1901 D_POWER("Chnl %d mapped to grp %d\n", ch_info->channel, group_idx);
1902 return group_idx;
1903 }
1904
1905 /**
1906 * il3945_hw_reg_get_matched_power_idx - Interpolate to get nominal idx
1907 *
1908 * Interpolate to get nominal (i.e. at factory calibration temperature) idx
1909 * into radio/DSP gain settings table for requested power.
1910 */
1911 static int
1912 il3945_hw_reg_get_matched_power_idx(struct il_priv *il, s8 requested_power,
1913 s32 setting_idx, s32 *new_idx)
1914 {
1915 const struct il3945_eeprom_txpower_group *chnl_grp = NULL;
1916 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1917 s32 idx0, idx1;
1918 s32 power = 2 * requested_power;
1919 s32 i;
1920 const struct il3945_eeprom_txpower_sample *samples;
1921 s32 gains0, gains1;
1922 s32 res;
1923 s32 denominator;
1924
1925 chnl_grp = &eeprom->groups[setting_idx];
1926 samples = chnl_grp->samples;
1927 for (i = 0; i < 5; i++) {
1928 if (power == samples[i].power) {
1929 *new_idx = samples[i].gain_idx;
1930 return 0;
1931 }
1932 }
1933
1934 if (power > samples[1].power) {
1935 idx0 = 0;
1936 idx1 = 1;
1937 } else if (power > samples[2].power) {
1938 idx0 = 1;
1939 idx1 = 2;
1940 } else if (power > samples[3].power) {
1941 idx0 = 2;
1942 idx1 = 3;
1943 } else {
1944 idx0 = 3;
1945 idx1 = 4;
1946 }
1947
1948 denominator = (s32) samples[idx1].power - (s32) samples[idx0].power;
1949 if (denominator == 0)
1950 return -EINVAL;
1951 gains0 = (s32) samples[idx0].gain_idx * (1 << 19);
1952 gains1 = (s32) samples[idx1].gain_idx * (1 << 19);
1953 res =
1954 gains0 + (gains1 - gains0) * ((s32) power -
1955 (s32) samples[idx0].power) /
1956 denominator + (1 << 18);
1957 *new_idx = res >> 19;
1958 return 0;
1959 }
1960
1961 static void
1962 il3945_hw_reg_init_channel_groups(struct il_priv *il)
1963 {
1964 u32 i;
1965 s32 rate_idx;
1966 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1967 const struct il3945_eeprom_txpower_group *group;
1968
1969 D_POWER("Initializing factory calib info from EEPROM\n");
1970
1971 for (i = 0; i < IL_NUM_TX_CALIB_GROUPS; i++) {
1972 s8 *clip_pwrs; /* table of power levels for each rate */
1973 s8 satur_pwr; /* saturation power for each chnl group */
1974 group = &eeprom->groups[i];
1975
1976 /* sanity check on factory saturation power value */
1977 if (group->saturation_power < 40) {
1978 IL_WARN("Error: saturation power is %d, "
1979 "less than minimum expected 40\n",
1980 group->saturation_power);
1981 return;
1982 }
1983
1984 /*
1985 * Derive requested power levels for each rate, based on
1986 * hardware capabilities (saturation power for band).
1987 * Basic value is 3dB down from saturation, with further
1988 * power reductions for highest 3 data rates. These
1989 * backoffs provide headroom for high rate modulation
1990 * power peaks, without too much distortion (clipping).
1991 */
1992 /* we'll fill in this array with h/w max power levels */
1993 clip_pwrs = (s8 *) il->_3945.clip_groups[i].clip_powers;
1994
1995 /* divide factory saturation power by 2 to find -3dB level */
1996 satur_pwr = (s8) (group->saturation_power >> 1);
1997
1998 /* fill in channel group's nominal powers for each rate */
1999 for (rate_idx = 0; rate_idx < RATE_COUNT_3945;
2000 rate_idx++, clip_pwrs++) {
2001 switch (rate_idx) {
2002 case RATE_36M_IDX_TBL:
2003 if (i == 0) /* B/G */
2004 *clip_pwrs = satur_pwr;
2005 else /* A */
2006 *clip_pwrs = satur_pwr - 5;
2007 break;
2008 case RATE_48M_IDX_TBL:
2009 if (i == 0)
2010 *clip_pwrs = satur_pwr - 7;
2011 else
2012 *clip_pwrs = satur_pwr - 10;
2013 break;
2014 case RATE_54M_IDX_TBL:
2015 if (i == 0)
2016 *clip_pwrs = satur_pwr - 9;
2017 else
2018 *clip_pwrs = satur_pwr - 12;
2019 break;
2020 default:
2021 *clip_pwrs = satur_pwr;
2022 break;
2023 }
2024 }
2025 }
2026 }
2027
2028 /**
2029 * il3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2030 *
2031 * Second pass (during init) to set up il->channel_info
2032 *
2033 * Set up Tx-power settings in our channel info database for each VALID
2034 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2035 * and current temperature.
2036 *
2037 * Since this is based on current temperature (at init time), these values may
2038 * not be valid for very long, but it gives us a starting/default point,
2039 * and allows us to active (i.e. using Tx) scan.
2040 *
2041 * This does *not* write values to NIC, just sets up our internal table.
2042 */
2043 int
2044 il3945_txpower_set_from_eeprom(struct il_priv *il)
2045 {
2046 struct il_channel_info *ch_info = NULL;
2047 struct il3945_channel_power_info *pwr_info;
2048 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
2049 int delta_idx;
2050 u8 rate_idx;
2051 u8 scan_tbl_idx;
2052 const s8 *clip_pwrs; /* array of power levels for each rate */
2053 u8 gain, dsp_atten;
2054 s8 power;
2055 u8 pwr_idx, base_pwr_idx, a_band;
2056 u8 i;
2057 int temperature;
2058
2059 /* save temperature reference,
2060 * so we can determine next time to calibrate */
2061 temperature = il3945_hw_reg_txpower_get_temperature(il);
2062 il->last_temperature = temperature;
2063
2064 il3945_hw_reg_init_channel_groups(il);
2065
2066 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2067 for (i = 0, ch_info = il->channel_info; i < il->channel_count;
2068 i++, ch_info++) {
2069 a_band = il_is_channel_a_band(ch_info);
2070 if (!il_is_channel_valid(ch_info))
2071 continue;
2072
2073 /* find this channel's channel group (*not* "band") idx */
2074 ch_info->group_idx = il3945_hw_reg_get_ch_grp_idx(il, ch_info);
2075
2076 /* Get this chnlgrp's rate->max/clip-powers table */
2077 clip_pwrs =
2078 il->_3945.clip_groups[ch_info->group_idx].clip_powers;
2079
2080 /* calculate power idx *adjustment* value according to
2081 * diff between current temperature and factory temperature */
2082 delta_idx =
2083 il3945_hw_reg_adjust_power_by_temp(temperature,
2084 eeprom->groups[ch_info->
2085 group_idx].
2086 temperature);
2087
2088 D_POWER("Delta idx for channel %d: %d [%d]\n", ch_info->channel,
2089 delta_idx, temperature + IL_TEMP_CONVERT);
2090
2091 /* set tx power value for all OFDM rates */
2092 for (rate_idx = 0; rate_idx < IL_OFDM_RATES; rate_idx++) {
2093 s32 uninitialized_var(power_idx);
2094 int rc;
2095
2096 /* use channel group's clip-power table,
2097 * but don't exceed channel's max power */
2098 s8 pwr = min(ch_info->max_power_avg,
2099 clip_pwrs[rate_idx]);
2100
2101 pwr_info = &ch_info->power_info[rate_idx];
2102
2103 /* get base (i.e. at factory-measured temperature)
2104 * power table idx for this rate's power */
2105 rc = il3945_hw_reg_get_matched_power_idx(il, pwr,
2106 ch_info->
2107 group_idx,
2108 &power_idx);
2109 if (rc) {
2110 IL_ERR("Invalid power idx\n");
2111 return rc;
2112 }
2113 pwr_info->base_power_idx = (u8) power_idx;
2114
2115 /* temperature compensate */
2116 power_idx += delta_idx;
2117
2118 /* stay within range of gain table */
2119 power_idx = il3945_hw_reg_fix_power_idx(power_idx);
2120
2121 /* fill 1 OFDM rate's il3945_channel_power_info struct */
2122 pwr_info->requested_power = pwr;
2123 pwr_info->power_table_idx = (u8) power_idx;
2124 pwr_info->tpc.tx_gain =
2125 power_gain_table[a_band][power_idx].tx_gain;
2126 pwr_info->tpc.dsp_atten =
2127 power_gain_table[a_band][power_idx].dsp_atten;
2128 }
2129
2130 /* set tx power for CCK rates, based on OFDM 12 Mbit settings */
2131 pwr_info = &ch_info->power_info[RATE_12M_IDX_TBL];
2132 power = pwr_info->requested_power + IL_CCK_FROM_OFDM_POWER_DIFF;
2133 pwr_idx = pwr_info->power_table_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
2134 base_pwr_idx =
2135 pwr_info->base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
2136
2137 /* stay within table range */
2138 pwr_idx = il3945_hw_reg_fix_power_idx(pwr_idx);
2139 gain = power_gain_table[a_band][pwr_idx].tx_gain;
2140 dsp_atten = power_gain_table[a_band][pwr_idx].dsp_atten;
2141
2142 /* fill each CCK rate's il3945_channel_power_info structure
2143 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2144 * NOTE: CCK rates start at end of OFDM rates! */
2145 for (rate_idx = 0; rate_idx < IL_CCK_RATES; rate_idx++) {
2146 pwr_info =
2147 &ch_info->power_info[rate_idx + IL_OFDM_RATES];
2148 pwr_info->requested_power = power;
2149 pwr_info->power_table_idx = pwr_idx;
2150 pwr_info->base_power_idx = base_pwr_idx;
2151 pwr_info->tpc.tx_gain = gain;
2152 pwr_info->tpc.dsp_atten = dsp_atten;
2153 }
2154
2155 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2156 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES;
2157 scan_tbl_idx++) {
2158 s32 actual_idx =
2159 (scan_tbl_idx ==
2160 0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
2161 il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
2162 actual_idx, clip_pwrs,
2163 ch_info, a_band);
2164 }
2165 }
2166
2167 return 0;
2168 }
2169
2170 int
2171 il3945_hw_rxq_stop(struct il_priv *il)
2172 {
2173 int ret;
2174
2175 _il_wr(il, FH39_RCSR_CONFIG(0), 0);
2176 ret = _il_poll_bit(il, FH39_RSSR_STATUS,
2177 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
2178 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
2179 1000);
2180 if (ret < 0)
2181 IL_ERR("Can't stop Rx DMA.\n");
2182
2183 return 0;
2184 }
2185
2186 int
2187 il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
2188 {
2189 int txq_id = txq->q.id;
2190
2191 struct il3945_shared *shared_data = il->_3945.shared_virt;
2192
2193 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32) txq->q.dma_addr);
2194
2195 il_wr(il, FH39_CBCC_CTRL(txq_id), 0);
2196 il_wr(il, FH39_CBCC_BASE(txq_id), 0);
2197
2198 il_wr(il, FH39_TCSR_CONFIG(txq_id),
2199 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2200 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2201 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2202 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2203 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2204
2205 /* fake read to flush all prev. writes */
2206 _il_rd(il, FH39_TSSR_CBB_BASE);
2207
2208 return 0;
2209 }
2210
2211 /*
2212 * HCMD utils
2213 */
2214 static u16
2215 il3945_get_hcmd_size(u8 cmd_id, u16 len)
2216 {
2217 switch (cmd_id) {
2218 case C_RXON:
2219 return sizeof(struct il3945_rxon_cmd);
2220 case C_POWER_TBL:
2221 return sizeof(struct il3945_powertable_cmd);
2222 default:
2223 return len;
2224 }
2225 }
2226
2227 static u16
2228 il3945_build_addsta_hcmd(const struct il_addsta_cmd *cmd, u8 * data)
2229 {
2230 struct il3945_addsta_cmd *addsta = (struct il3945_addsta_cmd *)data;
2231 addsta->mode = cmd->mode;
2232 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2233 memcpy(&addsta->key, &cmd->key, sizeof(struct il4965_keyinfo));
2234 addsta->station_flags = cmd->station_flags;
2235 addsta->station_flags_msk = cmd->station_flags_msk;
2236 addsta->tid_disable_tx = cpu_to_le16(0);
2237 addsta->rate_n_flags = cmd->rate_n_flags;
2238 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2239 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2240 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2241
2242 return (u16) sizeof(struct il3945_addsta_cmd);
2243 }
2244
2245 static int
2246 il3945_add_bssid_station(struct il_priv *il, const u8 * addr, u8 * sta_id_r)
2247 {
2248 int ret;
2249 u8 sta_id;
2250 unsigned long flags;
2251
2252 if (sta_id_r)
2253 *sta_id_r = IL_INVALID_STATION;
2254
2255 ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
2256 if (ret) {
2257 IL_ERR("Unable to add station %pM\n", addr);
2258 return ret;
2259 }
2260
2261 if (sta_id_r)
2262 *sta_id_r = sta_id;
2263
2264 spin_lock_irqsave(&il->sta_lock, flags);
2265 il->stations[sta_id].used |= IL_STA_LOCAL;
2266 spin_unlock_irqrestore(&il->sta_lock, flags);
2267
2268 return 0;
2269 }
2270
2271 static int
2272 il3945_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
2273 bool add)
2274 {
2275 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
2276 int ret;
2277
2278 if (add) {
2279 ret =
2280 il3945_add_bssid_station(il, vif->bss_conf.bssid,
2281 &vif_priv->ibss_bssid_sta_id);
2282 if (ret)
2283 return ret;
2284
2285 il3945_sync_sta(il, vif_priv->ibss_bssid_sta_id,
2286 (il->band ==
2287 IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP :
2288 RATE_1M_PLCP);
2289 il3945_rate_scale_init(il->hw, vif_priv->ibss_bssid_sta_id);
2290
2291 return 0;
2292 }
2293
2294 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
2295 vif->bss_conf.bssid);
2296 }
2297
2298 /**
2299 * il3945_init_hw_rate_table - Initialize the hardware rate fallback table
2300 */
2301 int
2302 il3945_init_hw_rate_table(struct il_priv *il)
2303 {
2304 int rc, i, idx, prev_idx;
2305 struct il3945_rate_scaling_cmd rate_cmd = {
2306 .reserved = {0, 0, 0},
2307 };
2308 struct il3945_rate_scaling_info *table = rate_cmd.table;
2309
2310 for (i = 0; i < ARRAY_SIZE(il3945_rates); i++) {
2311 idx = il3945_rates[i].table_rs_idx;
2312
2313 table[idx].rate_n_flags = cpu_to_le16(il3945_rates[i].plcp);
2314 table[idx].try_cnt = il->retry_rate;
2315 prev_idx = il3945_get_prev_ieee_rate(i);
2316 table[idx].next_rate_idx = il3945_rates[prev_idx].table_rs_idx;
2317 }
2318
2319 switch (il->band) {
2320 case IEEE80211_BAND_5GHZ:
2321 D_RATE("Select A mode rate scale\n");
2322 /* If one of the following CCK rates is used,
2323 * have it fall back to the 6M OFDM rate */
2324 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++)
2325 table[i].next_rate_idx =
2326 il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
2327
2328 /* Don't fall back to CCK rates */
2329 table[RATE_12M_IDX_TBL].next_rate_idx = RATE_9M_IDX_TBL;
2330
2331 /* Don't drop out of OFDM rates */
2332 table[RATE_6M_IDX_TBL].next_rate_idx =
2333 il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
2334 break;
2335
2336 case IEEE80211_BAND_2GHZ:
2337 D_RATE("Select B/G mode rate scale\n");
2338 /* If an OFDM rate is used, have it fall back to the
2339 * 1M CCK rates */
2340
2341 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
2342 il_is_associated(il)) {
2343
2344 idx = IL_FIRST_CCK_RATE;
2345 for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++)
2346 table[i].next_rate_idx =
2347 il3945_rates[idx].table_rs_idx;
2348
2349 idx = RATE_11M_IDX_TBL;
2350 /* CCK shouldn't fall back to OFDM... */
2351 table[idx].next_rate_idx = RATE_5M_IDX_TBL;
2352 }
2353 break;
2354
2355 default:
2356 WARN_ON(1);
2357 break;
2358 }
2359
2360 /* Update the rate scaling for control frame Tx */
2361 rate_cmd.table_id = 0;
2362 rc = il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
2363 if (rc)
2364 return rc;
2365
2366 /* Update the rate scaling for data frame Tx */
2367 rate_cmd.table_id = 1;
2368 return il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
2369 }
2370
2371 /* Called when initializing driver */
2372 int
2373 il3945_hw_set_hw_params(struct il_priv *il)
2374 {
2375 memset((void *)&il->hw_params, 0, sizeof(struct il_hw_params));
2376
2377 il->_3945.shared_virt =
2378 dma_alloc_coherent(&il->pci_dev->dev, sizeof(struct il3945_shared),
2379 &il->_3945.shared_phys, GFP_KERNEL);
2380 if (!il->_3945.shared_virt) {
2381 IL_ERR("failed to allocate pci memory\n");
2382 return -ENOMEM;
2383 }
2384
2385 il->hw_params.bcast_id = IL3945_BROADCAST_ID;
2386
2387 /* Assign number of Usable TX queues */
2388 il->hw_params.max_txq_num = il->cfg->num_of_queues;
2389
2390 il->hw_params.tfd_size = sizeof(struct il3945_tfd);
2391 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_3K);
2392 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2393 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2394 il->hw_params.max_stations = IL3945_STATION_COUNT;
2395
2396 il->sta_key_max_num = STA_KEY_MAX_NUM;
2397
2398 il->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2399 il->hw_params.max_beacon_itrvl = IL39_MAX_UCODE_BEACON_INTERVAL;
2400 il->hw_params.beacon_time_tsf_bits = IL3945_EXT_BEACON_TIME_POS;
2401
2402 return 0;
2403 }
2404
2405 unsigned int
2406 il3945_hw_get_beacon_cmd(struct il_priv *il, struct il3945_frame *frame,
2407 u8 rate)
2408 {
2409 struct il3945_tx_beacon_cmd *tx_beacon_cmd;
2410 unsigned int frame_size;
2411
2412 tx_beacon_cmd = (struct il3945_tx_beacon_cmd *)&frame->u;
2413 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2414
2415 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
2416 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2417
2418 frame_size =
2419 il3945_fill_beacon_frame(il, tx_beacon_cmd->frame,
2420 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2421
2422 BUG_ON(frame_size > MAX_MPDU_SIZE);
2423 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
2424
2425 tx_beacon_cmd->tx.rate = rate;
2426 tx_beacon_cmd->tx.tx_flags =
2427 (TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK);
2428
2429 /* supp_rates[0] == OFDM start at IL_FIRST_OFDM_RATE */
2430 tx_beacon_cmd->tx.supp_rates[0] =
2431 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
2432
2433 tx_beacon_cmd->tx.supp_rates[1] = (IL_CCK_BASIC_RATES_MASK & 0xF);
2434
2435 return sizeof(struct il3945_tx_beacon_cmd) + frame_size;
2436 }
2437
2438 void
2439 il3945_hw_handler_setup(struct il_priv *il)
2440 {
2441 il->handlers[C_TX] = il3945_hdl_tx;
2442 il->handlers[N_3945_RX] = il3945_hdl_rx;
2443 }
2444
2445 void
2446 il3945_hw_setup_deferred_work(struct il_priv *il)
2447 {
2448 INIT_DELAYED_WORK(&il->_3945.thermal_periodic,
2449 il3945_bg_reg_txpower_periodic);
2450 }
2451
2452 void
2453 il3945_hw_cancel_deferred_work(struct il_priv *il)
2454 {
2455 cancel_delayed_work(&il->_3945.thermal_periodic);
2456 }
2457
2458 /* check contents of special bootstrap uCode SRAM */
2459 static int
2460 il3945_verify_bsm(struct il_priv *il)
2461 {
2462 __le32 *image = il->ucode_boot.v_addr;
2463 u32 len = il->ucode_boot.len;
2464 u32 reg;
2465 u32 val;
2466
2467 D_INFO("Begin verify bsm\n");
2468
2469 /* verify BSM SRAM contents */
2470 val = il_rd_prph(il, BSM_WR_DWCOUNT_REG);
2471 for (reg = BSM_SRAM_LOWER_BOUND; reg < BSM_SRAM_LOWER_BOUND + len;
2472 reg += sizeof(u32), image++) {
2473 val = il_rd_prph(il, reg);
2474 if (val != le32_to_cpu(*image)) {
2475 IL_ERR("BSM uCode verification failed at "
2476 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2477 BSM_SRAM_LOWER_BOUND, reg - BSM_SRAM_LOWER_BOUND,
2478 len, val, le32_to_cpu(*image));
2479 return -EIO;
2480 }
2481 }
2482
2483 D_INFO("BSM bootstrap uCode image OK\n");
2484
2485 return 0;
2486 }
2487
2488 /******************************************************************************
2489 *
2490 * EEPROM related functions
2491 *
2492 ******************************************************************************/
2493
2494 /*
2495 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2496 * embedded controller) as EEPROM reader; each read is a series of pulses
2497 * to/from the EEPROM chip, not a single event, so even reads could conflict
2498 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2499 * simply claims ownership, which should be safe when this function is called
2500 * (i.e. before loading uCode!).
2501 */
2502 static int
2503 il3945_eeprom_acquire_semaphore(struct il_priv *il)
2504 {
2505 _il_clear_bit(il, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2506 return 0;
2507 }
2508
2509 static void
2510 il3945_eeprom_release_semaphore(struct il_priv *il)
2511 {
2512 return;
2513 }
2514
2515 /**
2516 * il3945_load_bsm - Load bootstrap instructions
2517 *
2518 * BSM operation:
2519 *
2520 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2521 * in special SRAM that does not power down during RFKILL. When powering back
2522 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2523 * the bootstrap program into the on-board processor, and starts it.
2524 *
2525 * The bootstrap program loads (via DMA) instructions and data for a new
2526 * program from host DRAM locations indicated by the host driver in the
2527 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2528 * automatically.
2529 *
2530 * When initializing the NIC, the host driver points the BSM to the
2531 * "initialize" uCode image. This uCode sets up some internal data, then
2532 * notifies host via "initialize alive" that it is complete.
2533 *
2534 * The host then replaces the BSM_DRAM_* pointer values to point to the
2535 * normal runtime uCode instructions and a backup uCode data cache buffer
2536 * (filled initially with starting data values for the on-board processor),
2537 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2538 * which begins normal operation.
2539 *
2540 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2541 * the backup data cache in DRAM before SRAM is powered down.
2542 *
2543 * When powering back up, the BSM loads the bootstrap program. This reloads
2544 * the runtime uCode instructions and the backup data cache into SRAM,
2545 * and re-launches the runtime uCode from where it left off.
2546 */
2547 static int
2548 il3945_load_bsm(struct il_priv *il)
2549 {
2550 __le32 *image = il->ucode_boot.v_addr;
2551 u32 len = il->ucode_boot.len;
2552 dma_addr_t pinst;
2553 dma_addr_t pdata;
2554 u32 inst_len;
2555 u32 data_len;
2556 int rc;
2557 int i;
2558 u32 done;
2559 u32 reg_offset;
2560
2561 D_INFO("Begin load bsm\n");
2562
2563 /* make sure bootstrap program is no larger than BSM's SRAM size */
2564 if (len > IL39_MAX_BSM_SIZE)
2565 return -EINVAL;
2566
2567 /* Tell bootstrap uCode where to find the "Initialize" uCode
2568 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2569 * NOTE: il3945_initialize_alive_start() will replace these values,
2570 * after the "initialize" uCode has run, to point to
2571 * runtime/protocol instructions and backup data cache. */
2572 pinst = il->ucode_init.p_addr;
2573 pdata = il->ucode_init_data.p_addr;
2574 inst_len = il->ucode_init.len;
2575 data_len = il->ucode_init_data.len;
2576
2577 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2578 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2579 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2580 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2581
2582 /* Fill BSM memory with bootstrap instructions */
2583 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2584 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2585 reg_offset += sizeof(u32), image++)
2586 _il_wr_prph(il, reg_offset, le32_to_cpu(*image));
2587
2588 rc = il3945_verify_bsm(il);
2589 if (rc)
2590 return rc;
2591
2592 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2593 il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
2594 il_wr_prph(il, BSM_WR_MEM_DST_REG, IL39_RTC_INST_LOWER_BOUND);
2595 il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2596
2597 /* Load bootstrap code into instruction SRAM now,
2598 * to prepare to load "initialize" uCode */
2599 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
2600
2601 /* Wait for load of bootstrap uCode to finish */
2602 for (i = 0; i < 100; i++) {
2603 done = il_rd_prph(il, BSM_WR_CTRL_REG);
2604 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2605 break;
2606 udelay(10);
2607 }
2608 if (i < 100)
2609 D_INFO("BSM write complete, poll %d iterations\n", i);
2610 else {
2611 IL_ERR("BSM write did not complete!\n");
2612 return -EIO;
2613 }
2614
2615 /* Enable future boot loads whenever power management unit triggers it
2616 * (e.g. when powering back up after power-save shutdown) */
2617 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
2618
2619 return 0;
2620 }
2621
2622 const struct il_ops il3945_ops = {
2623 .txq_attach_buf_to_tfd = il3945_hw_txq_attach_buf_to_tfd,
2624 .txq_free_tfd = il3945_hw_txq_free_tfd,
2625 .txq_init = il3945_hw_tx_queue_init,
2626 .load_ucode = il3945_load_bsm,
2627 .dump_nic_error_log = il3945_dump_nic_error_log,
2628 .apm_init = il3945_apm_init,
2629 .send_tx_power = il3945_send_tx_power,
2630 .is_valid_rtc_data_addr = il3945_hw_valid_rtc_data_addr,
2631 .eeprom_acquire_semaphore = il3945_eeprom_acquire_semaphore,
2632 .eeprom_release_semaphore = il3945_eeprom_release_semaphore,
2633
2634 .rxon_assoc = il3945_send_rxon_assoc,
2635 .commit_rxon = il3945_commit_rxon,
2636
2637 .get_hcmd_size = il3945_get_hcmd_size,
2638 .build_addsta_hcmd = il3945_build_addsta_hcmd,
2639 .request_scan = il3945_request_scan,
2640 .post_scan = il3945_post_scan,
2641
2642 .post_associate = il3945_post_associate,
2643 .config_ap = il3945_config_ap,
2644 .manage_ibss_station = il3945_manage_ibss_station,
2645
2646 .send_led_cmd = il3945_send_led_cmd,
2647 };
2648
2649 static struct il_cfg il3945_bg_cfg = {
2650 .name = "3945BG",
2651 .fw_name_pre = IL3945_FW_PRE,
2652 .ucode_api_max = IL3945_UCODE_API_MAX,
2653 .ucode_api_min = IL3945_UCODE_API_MIN,
2654 .sku = IL_SKU_G,
2655 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2656 .mod_params = &il3945_mod_params,
2657 .led_mode = IL_LED_BLINK,
2658
2659 .eeprom_size = IL3945_EEPROM_IMG_SIZE,
2660 .num_of_queues = IL39_NUM_QUEUES,
2661 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2662 .set_l0s = false,
2663 .use_bsm = true,
2664 .led_compensation = 64,
2665 .wd_timeout = IL_DEF_WD_TIMEOUT,
2666
2667 .regulatory_bands = {
2668 EEPROM_REGULATORY_BAND_1_CHANNELS,
2669 EEPROM_REGULATORY_BAND_2_CHANNELS,
2670 EEPROM_REGULATORY_BAND_3_CHANNELS,
2671 EEPROM_REGULATORY_BAND_4_CHANNELS,
2672 EEPROM_REGULATORY_BAND_5_CHANNELS,
2673 EEPROM_REGULATORY_BAND_NO_HT40,
2674 EEPROM_REGULATORY_BAND_NO_HT40,
2675 },
2676 };
2677
2678 static struct il_cfg il3945_abg_cfg = {
2679 .name = "3945ABG",
2680 .fw_name_pre = IL3945_FW_PRE,
2681 .ucode_api_max = IL3945_UCODE_API_MAX,
2682 .ucode_api_min = IL3945_UCODE_API_MIN,
2683 .sku = IL_SKU_A | IL_SKU_G,
2684 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2685 .mod_params = &il3945_mod_params,
2686 .led_mode = IL_LED_BLINK,
2687
2688 .eeprom_size = IL3945_EEPROM_IMG_SIZE,
2689 .num_of_queues = IL39_NUM_QUEUES,
2690 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2691 .set_l0s = false,
2692 .use_bsm = true,
2693 .led_compensation = 64,
2694 .wd_timeout = IL_DEF_WD_TIMEOUT,
2695
2696 .regulatory_bands = {
2697 EEPROM_REGULATORY_BAND_1_CHANNELS,
2698 EEPROM_REGULATORY_BAND_2_CHANNELS,
2699 EEPROM_REGULATORY_BAND_3_CHANNELS,
2700 EEPROM_REGULATORY_BAND_4_CHANNELS,
2701 EEPROM_REGULATORY_BAND_5_CHANNELS,
2702 EEPROM_REGULATORY_BAND_NO_HT40,
2703 EEPROM_REGULATORY_BAND_NO_HT40,
2704 },
2705 };
2706
2707 DEFINE_PCI_DEVICE_TABLE(il3945_hw_card_ids) = {
2708 {IL_PCI_DEVICE(0x4222, 0x1005, il3945_bg_cfg)},
2709 {IL_PCI_DEVICE(0x4222, 0x1034, il3945_bg_cfg)},
2710 {IL_PCI_DEVICE(0x4222, 0x1044, il3945_bg_cfg)},
2711 {IL_PCI_DEVICE(0x4227, 0x1014, il3945_bg_cfg)},
2712 {IL_PCI_DEVICE(0x4222, PCI_ANY_ID, il3945_abg_cfg)},
2713 {IL_PCI_DEVICE(0x4227, PCI_ANY_ID, il3945_abg_cfg)},
2714 {0}
2715 };
2716
2717 MODULE_DEVICE_TABLE(pci, il3945_hw_card_ids);
Linux with added FPC-III support