2 * Support for the GPIO/IRQ expander chips present on several HTC phones.
3 * These are implemented in CPLD chips present on the board.
5 * Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
8 * This file may be distributed under the terms of the GNU GPL license.
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_data/gpio-htc-egpio.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
27 struct gpio_chip chip
;
34 void __iomem
*base_addr
;
35 int bus_shift
; /* byte shift */
36 int reg_shift
; /* bit shift */
48 struct egpio_chip
*chip
;
52 static inline void egpio_writew(u16 value
, struct egpio_info
*ei
, int reg
)
54 writew(value
, ei
->base_addr
+ (reg
<< ei
->bus_shift
));
57 static inline u16
egpio_readw(struct egpio_info
*ei
, int reg
)
59 return readw(ei
->base_addr
+ (reg
<< ei
->bus_shift
));
66 static inline void ack_irqs(struct egpio_info
*ei
)
68 egpio_writew(ei
->ack_write
, ei
, ei
->ack_register
);
69 pr_debug("EGPIO ack - write %x to base+%x\n",
70 ei
->ack_write
, ei
->ack_register
<< ei
->bus_shift
);
73 static void egpio_ack(struct irq_data
*data
)
77 /* There does not appear to be a way to proactively mask interrupts
78 * on the egpio chip itself. So, we simply ignore interrupts that
80 static void egpio_mask(struct irq_data
*data
)
82 struct egpio_info
*ei
= irq_data_get_irq_chip_data(data
);
83 ei
->irqs_enabled
&= ~(1 << (data
->irq
- ei
->irq_start
));
84 pr_debug("EGPIO mask %d %04x\n", data
->irq
, ei
->irqs_enabled
);
87 static void egpio_unmask(struct irq_data
*data
)
89 struct egpio_info
*ei
= irq_data_get_irq_chip_data(data
);
90 ei
->irqs_enabled
|= 1 << (data
->irq
- ei
->irq_start
);
91 pr_debug("EGPIO unmask %d %04x\n", data
->irq
, ei
->irqs_enabled
);
94 static struct irq_chip egpio_muxed_chip
= {
97 .irq_mask
= egpio_mask
,
98 .irq_unmask
= egpio_unmask
,
101 static void egpio_handler(struct irq_desc
*desc
)
103 struct egpio_info
*ei
= irq_desc_get_handler_data(desc
);
106 /* Read current pins. */
107 unsigned long readval
= egpio_readw(ei
, ei
->ack_register
);
108 pr_debug("IRQ reg: %x\n", (unsigned int)readval
);
109 /* Ack/unmask interrupts. */
111 /* Process all set pins. */
112 readval
&= ei
->irqs_enabled
;
113 for_each_set_bit(irqpin
, &readval
, ei
->nirqs
) {
114 /* Run irq handler */
115 pr_debug("got IRQ %d\n", irqpin
);
116 generic_handle_irq(ei
->irq_start
+ irqpin
);
120 int htc_egpio_get_wakeup_irq(struct device
*dev
)
122 struct egpio_info
*ei
= dev_get_drvdata(dev
);
124 /* Read current pins. */
125 u16 readval
= egpio_readw(ei
, ei
->ack_register
);
126 /* Ack/unmask interrupts. */
128 /* Return first set pin. */
129 readval
&= ei
->irqs_enabled
;
130 return ei
->irq_start
+ ffs(readval
) - 1;
132 EXPORT_SYMBOL(htc_egpio_get_wakeup_irq
);
134 static inline int egpio_pos(struct egpio_info
*ei
, int bit
)
136 return bit
>> ei
->reg_shift
;
139 static inline int egpio_bit(struct egpio_info
*ei
, int bit
)
141 return 1 << (bit
& ((1 << ei
->reg_shift
)-1));
148 static int egpio_get(struct gpio_chip
*chip
, unsigned offset
)
150 struct egpio_chip
*egpio
;
151 struct egpio_info
*ei
;
156 pr_debug("egpio_get_value(%d)\n", chip
->base
+ offset
);
158 egpio
= gpiochip_get_data(chip
);
159 ei
= dev_get_drvdata(egpio
->dev
);
160 bit
= egpio_bit(ei
, offset
);
161 reg
= egpio
->reg_start
+ egpio_pos(ei
, offset
);
163 if (test_bit(offset
, &egpio
->is_out
)) {
164 return !!(egpio
->cached_values
& (1 << offset
));
166 value
= egpio_readw(ei
, reg
);
167 pr_debug("readw(%p + %x) = %x\n",
168 ei
->base_addr
, reg
<< ei
->bus_shift
, value
);
169 return !!(value
& bit
);
173 static int egpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
175 struct egpio_chip
*egpio
;
177 egpio
= gpiochip_get_data(chip
);
178 return test_bit(offset
, &egpio
->is_out
) ? -EINVAL
: 0;
186 static void egpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
189 struct egpio_chip
*egpio
;
190 struct egpio_info
*ei
;
196 pr_debug("egpio_set(%s, %d(%d), %d)\n",
197 chip
->label
, offset
, offset
+chip
->base
, value
);
199 egpio
= gpiochip_get_data(chip
);
200 ei
= dev_get_drvdata(egpio
->dev
);
201 bit
= egpio_bit(ei
, offset
);
202 pos
= egpio_pos(ei
, offset
);
203 reg
= egpio
->reg_start
+ pos
;
204 shift
= pos
<< ei
->reg_shift
;
206 pr_debug("egpio %s: reg %d = 0x%04x\n", value
? "set" : "clear",
207 reg
, (egpio
->cached_values
>> shift
) & ei
->reg_mask
);
209 spin_lock_irqsave(&ei
->lock
, flag
);
211 egpio
->cached_values
|= (1 << offset
);
213 egpio
->cached_values
&= ~(1 << offset
);
214 egpio_writew((egpio
->cached_values
>> shift
) & ei
->reg_mask
, ei
, reg
);
215 spin_unlock_irqrestore(&ei
->lock
, flag
);
218 static int egpio_direction_output(struct gpio_chip
*chip
,
219 unsigned offset
, int value
)
221 struct egpio_chip
*egpio
;
223 egpio
= gpiochip_get_data(chip
);
224 if (test_bit(offset
, &egpio
->is_out
)) {
225 egpio_set(chip
, offset
, value
);
232 static int egpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
234 struct egpio_chip
*egpio
;
236 egpio
= gpiochip_get_data(chip
);
238 return !test_bit(offset
, &egpio
->is_out
);
241 static void egpio_write_cache(struct egpio_info
*ei
)
244 struct egpio_chip
*egpio
;
247 for (i
= 0; i
< ei
->nchips
; i
++) {
248 egpio
= &(ei
->chip
[i
]);
252 for (shift
= 0; shift
< egpio
->chip
.ngpio
;
253 shift
+= (1<<ei
->reg_shift
)) {
255 int reg
= egpio
->reg_start
+ egpio_pos(ei
, shift
);
257 if (!((egpio
->is_out
>> shift
) & ei
->reg_mask
))
260 pr_debug("EGPIO: setting %x to %x, was %x\n", reg
,
261 (egpio
->cached_values
>> shift
) & ei
->reg_mask
,
262 egpio_readw(ei
, reg
));
264 egpio_writew((egpio
->cached_values
>> shift
)
265 & ei
->reg_mask
, ei
, reg
);
275 static int __init
egpio_probe(struct platform_device
*pdev
)
277 struct htc_egpio_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
278 struct resource
*res
;
279 struct egpio_info
*ei
;
280 struct gpio_chip
*chip
;
281 unsigned int irq
, irq_end
;
285 /* Initialize ei data structure. */
286 ei
= devm_kzalloc(&pdev
->dev
, sizeof(*ei
), GFP_KERNEL
);
290 spin_lock_init(&ei
->lock
);
292 /* Find chained irq */
294 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
296 ei
->chained_irq
= res
->start
;
298 /* Map egpio chip into virtual address space. */
299 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
302 ei
->base_addr
= devm_ioremap_nocache(&pdev
->dev
, res
->start
,
306 pr_debug("EGPIO phys=%08x virt=%p\n", (u32
)res
->start
, ei
->base_addr
);
308 if ((pdata
->bus_width
!= 16) && (pdata
->bus_width
!= 32))
310 ei
->bus_shift
= fls(pdata
->bus_width
- 1) - 3;
311 pr_debug("bus_shift = %d\n", ei
->bus_shift
);
313 if ((pdata
->reg_width
!= 8) && (pdata
->reg_width
!= 16))
315 ei
->reg_shift
= fls(pdata
->reg_width
- 1);
316 pr_debug("reg_shift = %d\n", ei
->reg_shift
);
318 ei
->reg_mask
= (1 << pdata
->reg_width
) - 1;
320 platform_set_drvdata(pdev
, ei
);
322 ei
->nchips
= pdata
->num_chips
;
323 ei
->chip
= devm_kzalloc(&pdev
->dev
,
324 sizeof(struct egpio_chip
) * ei
->nchips
,
330 for (i
= 0; i
< ei
->nchips
; i
++) {
331 ei
->chip
[i
].reg_start
= pdata
->chip
[i
].reg_start
;
332 ei
->chip
[i
].cached_values
= pdata
->chip
[i
].initial_values
;
333 ei
->chip
[i
].is_out
= pdata
->chip
[i
].direction
;
334 ei
->chip
[i
].dev
= &(pdev
->dev
);
335 chip
= &(ei
->chip
[i
].chip
);
336 chip
->label
= "htc-egpio";
337 chip
->parent
= &pdev
->dev
;
338 chip
->owner
= THIS_MODULE
;
339 chip
->get
= egpio_get
;
340 chip
->set
= egpio_set
;
341 chip
->direction_input
= egpio_direction_input
;
342 chip
->direction_output
= egpio_direction_output
;
343 chip
->get_direction
= egpio_get_direction
;
344 chip
->base
= pdata
->chip
[i
].gpio_base
;
345 chip
->ngpio
= pdata
->chip
[i
].num_gpios
;
347 gpiochip_add_data(chip
, &ei
->chip
[i
]);
350 /* Set initial pin values */
351 egpio_write_cache(ei
);
353 ei
->irq_start
= pdata
->irq_base
;
354 ei
->nirqs
= pdata
->num_irqs
;
355 ei
->ack_register
= pdata
->ack_register
;
357 if (ei
->chained_irq
) {
358 /* Setup irq handlers */
359 ei
->ack_write
= 0xFFFF;
360 if (pdata
->invert_acks
)
362 irq_end
= ei
->irq_start
+ ei
->nirqs
;
363 for (irq
= ei
->irq_start
; irq
< irq_end
; irq
++) {
364 irq_set_chip_and_handler(irq
, &egpio_muxed_chip
,
366 irq_set_chip_data(irq
, ei
);
367 irq_clear_status_flags(irq
, IRQ_NOREQUEST
| IRQ_NOPROBE
);
369 irq_set_irq_type(ei
->chained_irq
, IRQ_TYPE_EDGE_RISING
);
370 irq_set_chained_handler_and_data(ei
->chained_irq
,
374 device_init_wakeup(&pdev
->dev
, 1);
380 printk(KERN_ERR
"EGPIO failed to setup\n");
385 static int egpio_suspend(struct platform_device
*pdev
, pm_message_t state
)
387 struct egpio_info
*ei
= platform_get_drvdata(pdev
);
389 if (ei
->chained_irq
&& device_may_wakeup(&pdev
->dev
))
390 enable_irq_wake(ei
->chained_irq
);
394 static int egpio_resume(struct platform_device
*pdev
)
396 struct egpio_info
*ei
= platform_get_drvdata(pdev
);
398 if (ei
->chained_irq
&& device_may_wakeup(&pdev
->dev
))
399 disable_irq_wake(ei
->chained_irq
);
401 /* Update registers from the cache, in case
402 the CPLD was powered off during suspend */
403 egpio_write_cache(ei
);
407 #define egpio_suspend NULL
408 #define egpio_resume NULL
412 static struct platform_driver egpio_driver
= {
415 .suppress_bind_attrs
= true,
417 .suspend
= egpio_suspend
,
418 .resume
= egpio_resume
,
421 static int __init
egpio_init(void)
423 return platform_driver_probe(&egpio_driver
, egpio_probe
);
425 /* start early for dependencies */
426 subsys_initcall(egpio_init
);