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USB: idmouse: fix interface sanity checks
[linux/fpc-iii.git] / sound / soc / codecs / rt5677.c
blob315a3d39bc09103653ac03f4ebcc9c1775473a51
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rt5677.c -- RT5677 ALSA SoC audio codec driver
4 *
5 * Copyright 2013 Realtek Semiconductor Corp.
6 * Author: Oder Chiou <oder_chiou@realtek.com>
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/fs.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/pm.h>
16 #include <linux/regmap.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/firmware.h>
21 #include <linux/of_device.h>
22 #include <linux/property.h>
23 #include <linux/irq.h>
24 #include <linux/interrupt.h>
25 #include <linux/irqdomain.h>
26 #include <linux/workqueue.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/soc-dapm.h>
32 #include <sound/initval.h>
33 #include <sound/tlv.h>
34
35 #include "rl6231.h"
36 #include "rt5677.h"
37 #include "rt5677-spi.h"
38
39 #define RT5677_DEVICE_ID 0x6327
40
41 #define RT5677_PR_RANGE_BASE (0xff + 1)
42 #define RT5677_PR_SPACING 0x100
43
44 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
45
46 static const struct regmap_range_cfg rt5677_ranges[] = {
47 {
48 .name = "PR",
49 .range_min = RT5677_PR_BASE,
50 .range_max = RT5677_PR_BASE + 0xfd,
51 .selector_reg = RT5677_PRIV_INDEX,
52 .selector_mask = 0xff,
53 .selector_shift = 0x0,
54 .window_start = RT5677_PRIV_DATA,
55 .window_len = 0x1,
56 },
57 };
58
59 static const struct reg_sequence init_list[] = {
60 {RT5677_ASRC_12, 0x0018},
61 {RT5677_PR_BASE + 0x3d, 0x364d},
62 {RT5677_PR_BASE + 0x17, 0x4fc0},
63 {RT5677_PR_BASE + 0x13, 0x0312},
64 {RT5677_PR_BASE + 0x1e, 0x0000},
65 {RT5677_PR_BASE + 0x12, 0x0eaa},
66 {RT5677_PR_BASE + 0x14, 0x018a},
67 {RT5677_PR_BASE + 0x15, 0x0490},
68 {RT5677_PR_BASE + 0x38, 0x0f71},
69 {RT5677_PR_BASE + 0x39, 0x0f71},
70 };
71 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
72
73 static const struct reg_default rt5677_reg[] = {
74 {RT5677_RESET , 0x0000},
75 {RT5677_LOUT1 , 0xa800},
76 {RT5677_IN1 , 0x0000},
77 {RT5677_MICBIAS , 0x0000},
78 {RT5677_SLIMBUS_PARAM , 0x0000},
79 {RT5677_SLIMBUS_RX , 0x0000},
80 {RT5677_SLIMBUS_CTRL , 0x0000},
81 {RT5677_SIDETONE_CTRL , 0x000b},
82 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
83 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
84 {RT5677_DAC4_DIG_VOL , 0xafaf},
85 {RT5677_DAC3_DIG_VOL , 0xafaf},
86 {RT5677_DAC1_DIG_VOL , 0xafaf},
87 {RT5677_DAC2_DIG_VOL , 0xafaf},
88 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
89 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
90 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO1_2_ADC_BST , 0x0000},
92 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
93 {RT5677_ADC_BST_CTRL2 , 0x0000},
94 {RT5677_STO3_4_ADC_BST , 0x0000},
95 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
96 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
97 {RT5677_STO4_ADC_MIXER , 0xd4c0},
98 {RT5677_STO3_ADC_MIXER , 0xd4c0},
99 {RT5677_STO2_ADC_MIXER , 0xd4c0},
100 {RT5677_STO1_ADC_MIXER , 0xd4c0},
101 {RT5677_MONO_ADC_MIXER , 0xd4d1},
102 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
103 {RT5677_STO1_DAC_MIXER , 0xaaaa},
104 {RT5677_MONO_DAC_MIXER , 0xaaaa},
105 {RT5677_DD1_MIXER , 0xaaaa},
106 {RT5677_DD2_MIXER , 0xaaaa},
107 {RT5677_IF3_DATA , 0x0000},
108 {RT5677_IF4_DATA , 0x0000},
109 {RT5677_PDM_OUT_CTRL , 0x8888},
110 {RT5677_PDM_DATA_CTRL1 , 0x0000},
111 {RT5677_PDM_DATA_CTRL2 , 0x0000},
112 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
113 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
114 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
115 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
116 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
117 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
118 {RT5677_TDM1_CTRL1 , 0x0300},
119 {RT5677_TDM1_CTRL2 , 0x0000},
120 {RT5677_TDM1_CTRL3 , 0x4000},
121 {RT5677_TDM1_CTRL4 , 0x0123},
122 {RT5677_TDM1_CTRL5 , 0x4567},
123 {RT5677_TDM2_CTRL1 , 0x0300},
124 {RT5677_TDM2_CTRL2 , 0x0000},
125 {RT5677_TDM2_CTRL3 , 0x4000},
126 {RT5677_TDM2_CTRL4 , 0x0123},
127 {RT5677_TDM2_CTRL5 , 0x4567},
128 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
129 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
131 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
132 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
133 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
134 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
135 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
136 {RT5677_DMIC_CTRL1 , 0x1505},
137 {RT5677_DMIC_CTRL2 , 0x0055},
138 {RT5677_HAP_GENE_CTRL1 , 0x0111},
139 {RT5677_HAP_GENE_CTRL2 , 0x0064},
140 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
141 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
142 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
143 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
144 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
145 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
146 {RT5677_HAP_GENE_CTRL9 , 0xf000},
147 {RT5677_HAP_GENE_CTRL10 , 0x0000},
148 {RT5677_PWR_DIG1 , 0x0000},
149 {RT5677_PWR_DIG2 , 0x0000},
150 {RT5677_PWR_ANLG1 , 0x0055},
151 {RT5677_PWR_ANLG2 , 0x0000},
152 {RT5677_PWR_DSP1 , 0x0001},
153 {RT5677_PWR_DSP_ST , 0x0000},
154 {RT5677_PWR_DSP2 , 0x0000},
155 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
156 {RT5677_PRIV_INDEX , 0x0000},
157 {RT5677_PRIV_DATA , 0x0000},
158 {RT5677_I2S4_SDP , 0x8000},
159 {RT5677_I2S1_SDP , 0x8000},
160 {RT5677_I2S2_SDP , 0x8000},
161 {RT5677_I2S3_SDP , 0x8000},
162 {RT5677_CLK_TREE_CTRL1 , 0x1111},
163 {RT5677_CLK_TREE_CTRL2 , 0x1111},
164 {RT5677_CLK_TREE_CTRL3 , 0x0000},
165 {RT5677_PLL1_CTRL1 , 0x0000},
166 {RT5677_PLL1_CTRL2 , 0x0000},
167 {RT5677_PLL2_CTRL1 , 0x0c60},
168 {RT5677_PLL2_CTRL2 , 0x2000},
169 {RT5677_GLB_CLK1 , 0x0000},
170 {RT5677_GLB_CLK2 , 0x0000},
171 {RT5677_ASRC_1 , 0x0000},
172 {RT5677_ASRC_2 , 0x0000},
173 {RT5677_ASRC_3 , 0x0000},
174 {RT5677_ASRC_4 , 0x0000},
175 {RT5677_ASRC_5 , 0x0000},
176 {RT5677_ASRC_6 , 0x0000},
177 {RT5677_ASRC_7 , 0x0000},
178 {RT5677_ASRC_8 , 0x0000},
179 {RT5677_ASRC_9 , 0x0000},
180 {RT5677_ASRC_10 , 0x0000},
181 {RT5677_ASRC_11 , 0x0000},
182 {RT5677_ASRC_12 , 0x0018},
183 {RT5677_ASRC_13 , 0x0000},
184 {RT5677_ASRC_14 , 0x0000},
185 {RT5677_ASRC_15 , 0x0000},
186 {RT5677_ASRC_16 , 0x0000},
187 {RT5677_ASRC_17 , 0x0000},
188 {RT5677_ASRC_18 , 0x0000},
189 {RT5677_ASRC_19 , 0x0000},
190 {RT5677_ASRC_20 , 0x0000},
191 {RT5677_ASRC_21 , 0x000c},
192 {RT5677_ASRC_22 , 0x0000},
193 {RT5677_ASRC_23 , 0x0000},
194 {RT5677_VAD_CTRL1 , 0x2184},
195 {RT5677_VAD_CTRL2 , 0x010a},
196 {RT5677_VAD_CTRL3 , 0x0aea},
197 {RT5677_VAD_CTRL4 , 0x000c},
198 {RT5677_VAD_CTRL5 , 0x0000},
199 {RT5677_DSP_INB_CTRL1 , 0x0000},
200 {RT5677_DSP_INB_CTRL2 , 0x0000},
201 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
202 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
203 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
204 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
205 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
206 {RT5677_ADC_EQ_CTRL1 , 0x6000},
207 {RT5677_ADC_EQ_CTRL2 , 0x0000},
208 {RT5677_EQ_CTRL1 , 0xc000},
209 {RT5677_EQ_CTRL2 , 0x0000},
210 {RT5677_EQ_CTRL3 , 0x0000},
211 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
212 {RT5677_JD_CTRL1 , 0x0000},
213 {RT5677_JD_CTRL2 , 0x0000},
214 {RT5677_JD_CTRL3 , 0x0000},
215 {RT5677_IRQ_CTRL1 , 0x0000},
216 {RT5677_IRQ_CTRL2 , 0x0000},
217 {RT5677_GPIO_ST , 0x0000},
218 {RT5677_GPIO_CTRL1 , 0x0000},
219 {RT5677_GPIO_CTRL2 , 0x0000},
220 {RT5677_GPIO_CTRL3 , 0x0000},
221 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
222 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
223 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
224 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
225 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
226 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
227 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
228 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
229 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
230 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
231 {RT5677_MB_DRC_CTRL1 , 0x0f20},
232 {RT5677_DRC1_CTRL1 , 0x001f},
233 {RT5677_DRC1_CTRL2 , 0x020c},
234 {RT5677_DRC1_CTRL3 , 0x1f00},
235 {RT5677_DRC1_CTRL4 , 0x0000},
236 {RT5677_DRC1_CTRL5 , 0x0000},
237 {RT5677_DRC1_CTRL6 , 0x0029},
238 {RT5677_DRC2_CTRL1 , 0x001f},
239 {RT5677_DRC2_CTRL2 , 0x020c},
240 {RT5677_DRC2_CTRL3 , 0x1f00},
241 {RT5677_DRC2_CTRL4 , 0x0000},
242 {RT5677_DRC2_CTRL5 , 0x0000},
243 {RT5677_DRC2_CTRL6 , 0x0029},
244 {RT5677_DRC1_HL_CTRL1 , 0x8000},
245 {RT5677_DRC1_HL_CTRL2 , 0x0200},
246 {RT5677_DRC2_HL_CTRL1 , 0x8000},
247 {RT5677_DRC2_HL_CTRL2 , 0x0200},
248 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
249 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
250 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
251 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
252 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
253 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
254 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
255 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
256 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
257 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
258 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
259 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
260 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
261 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
262 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
263 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
264 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
265 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
266 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
267 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
268 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
269 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
270 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
271 {RT5677_DIG_MISC , 0x0000},
272 {RT5677_GEN_CTRL1 , 0x0000},
273 {RT5677_GEN_CTRL2 , 0x0000},
274 {RT5677_VENDOR_ID , 0x0000},
275 {RT5677_VENDOR_ID1 , 0x10ec},
276 {RT5677_VENDOR_ID2 , 0x6327},
277 };
278
279 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
280 {
281 int i;
282
283 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
284 if (reg >= rt5677_ranges[i].range_min &&
285 reg <= rt5677_ranges[i].range_max) {
286 return true;
287 }
288 }
289
290 switch (reg) {
291 case RT5677_RESET:
292 case RT5677_SLIMBUS_PARAM:
293 case RT5677_PDM_DATA_CTRL1:
294 case RT5677_PDM_DATA_CTRL2:
295 case RT5677_PDM1_DATA_CTRL4:
296 case RT5677_PDM2_DATA_CTRL4:
297 case RT5677_I2C_MASTER_CTRL1:
298 case RT5677_I2C_MASTER_CTRL7:
299 case RT5677_I2C_MASTER_CTRL8:
300 case RT5677_HAP_GENE_CTRL2:
301 case RT5677_PWR_DSP_ST:
302 case RT5677_PRIV_DATA:
303 case RT5677_ASRC_22:
304 case RT5677_ASRC_23:
305 case RT5677_VAD_CTRL5:
306 case RT5677_ADC_EQ_CTRL1:
307 case RT5677_EQ_CTRL1:
308 case RT5677_IRQ_CTRL1:
309 case RT5677_IRQ_CTRL2:
310 case RT5677_GPIO_ST:
311 case RT5677_DSP_INB1_SRC_CTRL4:
312 case RT5677_DSP_INB2_SRC_CTRL4:
313 case RT5677_DSP_INB3_SRC_CTRL4:
314 case RT5677_DSP_OUTB1_SRC_CTRL4:
315 case RT5677_DSP_OUTB2_SRC_CTRL4:
316 case RT5677_VENDOR_ID:
317 case RT5677_VENDOR_ID1:
318 case RT5677_VENDOR_ID2:
319 return true;
320 default:
321 return false;
322 }
323 }
324
325 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
326 {
327 int i;
328
329 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
330 if (reg >= rt5677_ranges[i].range_min &&
331 reg <= rt5677_ranges[i].range_max) {
332 return true;
333 }
334 }
335
336 switch (reg) {
337 case RT5677_RESET:
338 case RT5677_LOUT1:
339 case RT5677_IN1:
340 case RT5677_MICBIAS:
341 case RT5677_SLIMBUS_PARAM:
342 case RT5677_SLIMBUS_RX:
343 case RT5677_SLIMBUS_CTRL:
344 case RT5677_SIDETONE_CTRL:
345 case RT5677_ANA_DAC1_2_3_SRC:
346 case RT5677_IF_DSP_DAC3_4_MIXER:
347 case RT5677_DAC4_DIG_VOL:
348 case RT5677_DAC3_DIG_VOL:
349 case RT5677_DAC1_DIG_VOL:
350 case RT5677_DAC2_DIG_VOL:
351 case RT5677_IF_DSP_DAC2_MIXER:
352 case RT5677_STO1_ADC_DIG_VOL:
353 case RT5677_MONO_ADC_DIG_VOL:
354 case RT5677_STO1_2_ADC_BST:
355 case RT5677_STO2_ADC_DIG_VOL:
356 case RT5677_ADC_BST_CTRL2:
357 case RT5677_STO3_4_ADC_BST:
358 case RT5677_STO3_ADC_DIG_VOL:
359 case RT5677_STO4_ADC_DIG_VOL:
360 case RT5677_STO4_ADC_MIXER:
361 case RT5677_STO3_ADC_MIXER:
362 case RT5677_STO2_ADC_MIXER:
363 case RT5677_STO1_ADC_MIXER:
364 case RT5677_MONO_ADC_MIXER:
365 case RT5677_ADC_IF_DSP_DAC1_MIXER:
366 case RT5677_STO1_DAC_MIXER:
367 case RT5677_MONO_DAC_MIXER:
368 case RT5677_DD1_MIXER:
369 case RT5677_DD2_MIXER:
370 case RT5677_IF3_DATA:
371 case RT5677_IF4_DATA:
372 case RT5677_PDM_OUT_CTRL:
373 case RT5677_PDM_DATA_CTRL1:
374 case RT5677_PDM_DATA_CTRL2:
375 case RT5677_PDM1_DATA_CTRL2:
376 case RT5677_PDM1_DATA_CTRL3:
377 case RT5677_PDM1_DATA_CTRL4:
378 case RT5677_PDM2_DATA_CTRL2:
379 case RT5677_PDM2_DATA_CTRL3:
380 case RT5677_PDM2_DATA_CTRL4:
381 case RT5677_TDM1_CTRL1:
382 case RT5677_TDM1_CTRL2:
383 case RT5677_TDM1_CTRL3:
384 case RT5677_TDM1_CTRL4:
385 case RT5677_TDM1_CTRL5:
386 case RT5677_TDM2_CTRL1:
387 case RT5677_TDM2_CTRL2:
388 case RT5677_TDM2_CTRL3:
389 case RT5677_TDM2_CTRL4:
390 case RT5677_TDM2_CTRL5:
391 case RT5677_I2C_MASTER_CTRL1:
392 case RT5677_I2C_MASTER_CTRL2:
393 case RT5677_I2C_MASTER_CTRL3:
394 case RT5677_I2C_MASTER_CTRL4:
395 case RT5677_I2C_MASTER_CTRL5:
396 case RT5677_I2C_MASTER_CTRL6:
397 case RT5677_I2C_MASTER_CTRL7:
398 case RT5677_I2C_MASTER_CTRL8:
399 case RT5677_DMIC_CTRL1:
400 case RT5677_DMIC_CTRL2:
401 case RT5677_HAP_GENE_CTRL1:
402 case RT5677_HAP_GENE_CTRL2:
403 case RT5677_HAP_GENE_CTRL3:
404 case RT5677_HAP_GENE_CTRL4:
405 case RT5677_HAP_GENE_CTRL5:
406 case RT5677_HAP_GENE_CTRL6:
407 case RT5677_HAP_GENE_CTRL7:
408 case RT5677_HAP_GENE_CTRL8:
409 case RT5677_HAP_GENE_CTRL9:
410 case RT5677_HAP_GENE_CTRL10:
411 case RT5677_PWR_DIG1:
412 case RT5677_PWR_DIG2:
413 case RT5677_PWR_ANLG1:
414 case RT5677_PWR_ANLG2:
415 case RT5677_PWR_DSP1:
416 case RT5677_PWR_DSP_ST:
417 case RT5677_PWR_DSP2:
418 case RT5677_ADC_DAC_HPF_CTRL1:
419 case RT5677_PRIV_INDEX:
420 case RT5677_PRIV_DATA:
421 case RT5677_I2S4_SDP:
422 case RT5677_I2S1_SDP:
423 case RT5677_I2S2_SDP:
424 case RT5677_I2S3_SDP:
425 case RT5677_CLK_TREE_CTRL1:
426 case RT5677_CLK_TREE_CTRL2:
427 case RT5677_CLK_TREE_CTRL3:
428 case RT5677_PLL1_CTRL1:
429 case RT5677_PLL1_CTRL2:
430 case RT5677_PLL2_CTRL1:
431 case RT5677_PLL2_CTRL2:
432 case RT5677_GLB_CLK1:
433 case RT5677_GLB_CLK2:
434 case RT5677_ASRC_1:
435 case RT5677_ASRC_2:
436 case RT5677_ASRC_3:
437 case RT5677_ASRC_4:
438 case RT5677_ASRC_5:
439 case RT5677_ASRC_6:
440 case RT5677_ASRC_7:
441 case RT5677_ASRC_8:
442 case RT5677_ASRC_9:
443 case RT5677_ASRC_10:
444 case RT5677_ASRC_11:
445 case RT5677_ASRC_12:
446 case RT5677_ASRC_13:
447 case RT5677_ASRC_14:
448 case RT5677_ASRC_15:
449 case RT5677_ASRC_16:
450 case RT5677_ASRC_17:
451 case RT5677_ASRC_18:
452 case RT5677_ASRC_19:
453 case RT5677_ASRC_20:
454 case RT5677_ASRC_21:
455 case RT5677_ASRC_22:
456 case RT5677_ASRC_23:
457 case RT5677_VAD_CTRL1:
458 case RT5677_VAD_CTRL2:
459 case RT5677_VAD_CTRL3:
460 case RT5677_VAD_CTRL4:
461 case RT5677_VAD_CTRL5:
462 case RT5677_DSP_INB_CTRL1:
463 case RT5677_DSP_INB_CTRL2:
464 case RT5677_DSP_IN_OUTB_CTRL:
465 case RT5677_DSP_OUTB0_1_DIG_VOL:
466 case RT5677_DSP_OUTB2_3_DIG_VOL:
467 case RT5677_DSP_OUTB4_5_DIG_VOL:
468 case RT5677_DSP_OUTB6_7_DIG_VOL:
469 case RT5677_ADC_EQ_CTRL1:
470 case RT5677_ADC_EQ_CTRL2:
471 case RT5677_EQ_CTRL1:
472 case RT5677_EQ_CTRL2:
473 case RT5677_EQ_CTRL3:
474 case RT5677_SOFT_VOL_ZERO_CROSS1:
475 case RT5677_JD_CTRL1:
476 case RT5677_JD_CTRL2:
477 case RT5677_JD_CTRL3:
478 case RT5677_IRQ_CTRL1:
479 case RT5677_IRQ_CTRL2:
480 case RT5677_GPIO_ST:
481 case RT5677_GPIO_CTRL1:
482 case RT5677_GPIO_CTRL2:
483 case RT5677_GPIO_CTRL3:
484 case RT5677_STO1_ADC_HI_FILTER1:
485 case RT5677_STO1_ADC_HI_FILTER2:
486 case RT5677_MONO_ADC_HI_FILTER1:
487 case RT5677_MONO_ADC_HI_FILTER2:
488 case RT5677_STO2_ADC_HI_FILTER1:
489 case RT5677_STO2_ADC_HI_FILTER2:
490 case RT5677_STO3_ADC_HI_FILTER1:
491 case RT5677_STO3_ADC_HI_FILTER2:
492 case RT5677_STO4_ADC_HI_FILTER1:
493 case RT5677_STO4_ADC_HI_FILTER2:
494 case RT5677_MB_DRC_CTRL1:
495 case RT5677_DRC1_CTRL1:
496 case RT5677_DRC1_CTRL2:
497 case RT5677_DRC1_CTRL3:
498 case RT5677_DRC1_CTRL4:
499 case RT5677_DRC1_CTRL5:
500 case RT5677_DRC1_CTRL6:
501 case RT5677_DRC2_CTRL1:
502 case RT5677_DRC2_CTRL2:
503 case RT5677_DRC2_CTRL3:
504 case RT5677_DRC2_CTRL4:
505 case RT5677_DRC2_CTRL5:
506 case RT5677_DRC2_CTRL6:
507 case RT5677_DRC1_HL_CTRL1:
508 case RT5677_DRC1_HL_CTRL2:
509 case RT5677_DRC2_HL_CTRL1:
510 case RT5677_DRC2_HL_CTRL2:
511 case RT5677_DSP_INB1_SRC_CTRL1:
512 case RT5677_DSP_INB1_SRC_CTRL2:
513 case RT5677_DSP_INB1_SRC_CTRL3:
514 case RT5677_DSP_INB1_SRC_CTRL4:
515 case RT5677_DSP_INB2_SRC_CTRL1:
516 case RT5677_DSP_INB2_SRC_CTRL2:
517 case RT5677_DSP_INB2_SRC_CTRL3:
518 case RT5677_DSP_INB2_SRC_CTRL4:
519 case RT5677_DSP_INB3_SRC_CTRL1:
520 case RT5677_DSP_INB3_SRC_CTRL2:
521 case RT5677_DSP_INB3_SRC_CTRL3:
522 case RT5677_DSP_INB3_SRC_CTRL4:
523 case RT5677_DSP_OUTB1_SRC_CTRL1:
524 case RT5677_DSP_OUTB1_SRC_CTRL2:
525 case RT5677_DSP_OUTB1_SRC_CTRL3:
526 case RT5677_DSP_OUTB1_SRC_CTRL4:
527 case RT5677_DSP_OUTB2_SRC_CTRL1:
528 case RT5677_DSP_OUTB2_SRC_CTRL2:
529 case RT5677_DSP_OUTB2_SRC_CTRL3:
530 case RT5677_DSP_OUTB2_SRC_CTRL4:
531 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
532 case RT5677_DSP_OUTB_45_MIXER_CTRL:
533 case RT5677_DSP_OUTB_67_MIXER_CTRL:
534 case RT5677_DIG_MISC:
535 case RT5677_GEN_CTRL1:
536 case RT5677_GEN_CTRL2:
537 case RT5677_VENDOR_ID:
538 case RT5677_VENDOR_ID1:
539 case RT5677_VENDOR_ID2:
540 return true;
541 default:
542 return false;
543 }
544 }
545
546 /**
547 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
548 * @rt5677: Private Data.
549 * @addr: Address index.
550 * @value: Address data.
551 * @opcode: opcode value
552 *
553 * Returns 0 for success or negative error code.
554 */
555 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
556 unsigned int addr, unsigned int value, unsigned int opcode)
557 {
558 struct snd_soc_component *component = rt5677->component;
559 int ret;
560
561 mutex_lock(&rt5677->dsp_cmd_lock);
562
563 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
564 addr >> 16);
565 if (ret < 0) {
566 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
567 goto err;
568 }
569
570 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
571 addr & 0xffff);
572 if (ret < 0) {
573 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
574 goto err;
575 }
576
577 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
578 value >> 16);
579 if (ret < 0) {
580 dev_err(component->dev, "Failed to set data msb value: %d\n", ret);
581 goto err;
582 }
583
584 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
585 value & 0xffff);
586 if (ret < 0) {
587 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret);
588 goto err;
589 }
590
591 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
592 opcode);
593 if (ret < 0) {
594 dev_err(component->dev, "Failed to set op code value: %d\n", ret);
595 goto err;
596 }
597
598 err:
599 mutex_unlock(&rt5677->dsp_cmd_lock);
600
601 return ret;
602 }
603
604 /**
605 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
606 * @rt5677: Private Data.
607 * @addr: Address index.
608 * @value: Address data.
609 *
610 *
611 * Returns 0 for success or negative error code.
612 */
613 static int rt5677_dsp_mode_i2c_read_addr(
614 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
615 {
616 struct snd_soc_component *component = rt5677->component;
617 int ret;
618 unsigned int msb, lsb;
619
620 mutex_lock(&rt5677->dsp_cmd_lock);
621
622 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
623 addr >> 16);
624 if (ret < 0) {
625 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
626 goto err;
627 }
628
629 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
630 addr & 0xffff);
631 if (ret < 0) {
632 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
633 goto err;
634 }
635
636 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
637 0x0002);
638 if (ret < 0) {
639 dev_err(component->dev, "Failed to set op code value: %d\n", ret);
640 goto err;
641 }
642
643 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
644 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
645 *value = (msb << 16) | lsb;
646
647 err:
648 mutex_unlock(&rt5677->dsp_cmd_lock);
649
650 return ret;
651 }
652
653 /**
654 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
655 * @rt5677: Private Data.
656 * @reg: Register index.
657 * @value: Register data.
658 *
659 *
660 * Returns 0 for success or negative error code.
661 */
662 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
663 unsigned int reg, unsigned int value)
664 {
665 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
666 value, 0x0001);
667 }
668
669 /**
670 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
671 * @rt5677: Private Data
672 * @reg: Register index.
673 * @value: Register data.
674 *
675 *
676 * Returns 0 for success or negative error code.
677 */
678 static int rt5677_dsp_mode_i2c_read(
679 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
680 {
681 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
682 value);
683
684 *value &= 0xffff;
685
686 return ret;
687 }
688
689 static void rt5677_set_dsp_mode(struct snd_soc_component *component, bool on)
690 {
691 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
692
693 if (on) {
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
695 RT5677_PWR_DSP, RT5677_PWR_DSP);
696 rt5677->is_dsp_mode = true;
697 } else {
698 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
699 RT5677_PWR_DSP, 0x0);
700 rt5677->is_dsp_mode = false;
701 }
702 }
703
704 static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on)
705 {
706 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
707 static bool activity;
708 int ret;
709
710 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
711 return -ENXIO;
712
713 if (on && !activity) {
714 activity = true;
715
716 regcache_cache_only(rt5677->regmap, false);
717 regcache_cache_bypass(rt5677->regmap, true);
718
719 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
720 regmap_update_bits(rt5677->regmap,
721 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
722 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
723 RT5677_LDO1_SEL_MASK, 0x0);
724 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
725 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
726 switch (rt5677->type) {
727 case RT5677:
728 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
729 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
730 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
731 RT5677_PLL2_PR_SRC_MASK |
732 RT5677_DSP_CLK_SRC_MASK,
733 RT5677_PLL2_PR_SRC_MCLK2 |
734 RT5677_DSP_CLK_SRC_BYPASS);
735 break;
736 case RT5676:
737 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
738 RT5677_DSP_CLK_SRC_MASK,
739 RT5677_DSP_CLK_SRC_BYPASS);
740 break;
741 default:
742 break;
743 }
744 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
745 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
746 rt5677_set_dsp_mode(component, true);
747
748 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
749 component->dev);
750 if (ret == 0) {
751 rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
752 release_firmware(rt5677->fw1);
753 }
754
755 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
756 component->dev);
757 if (ret == 0) {
758 rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
759 release_firmware(rt5677->fw2);
760 }
761
762 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
763
764 regcache_cache_bypass(rt5677->regmap, false);
765 regcache_cache_only(rt5677->regmap, true);
766 } else if (!on && activity) {
767 activity = false;
768
769 regcache_cache_only(rt5677->regmap, false);
770 regcache_cache_bypass(rt5677->regmap, true);
771
772 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
773 rt5677_set_dsp_mode(component, false);
774 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
775
776 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
777
778 regcache_cache_bypass(rt5677->regmap, false);
779 regcache_mark_dirty(rt5677->regmap);
780 regcache_sync(rt5677->regmap);
781 }
782
783 return 0;
784 }
785
786 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
787 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
788 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
789 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
790
791 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
792 static const DECLARE_TLV_DB_RANGE(bst_tlv,
793 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
794 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
795 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
796 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
797 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
798 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
799 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
800 );
801
802 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
803 struct snd_ctl_elem_value *ucontrol)
804 {
805 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
806 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
807
808 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
809
810 return 0;
811 }
812
813 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
814 struct snd_ctl_elem_value *ucontrol)
815 {
816 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
817 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
818
819 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
820
821 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
822 rt5677_set_dsp_vad(component, rt5677->dsp_vad_en);
823
824 return 0;
825 }
826
827 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
828 /* OUTPUT Control */
829 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
830 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
831 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
832 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
833 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
834 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
835
836 /* DAC Digital Volume */
837 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
838 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
839 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
840 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
841 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
842 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
843 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
844 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
845
846 /* IN1/IN2 Control */
847 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
848 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
849
850 /* ADC Digital Volume Control */
851 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
852 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
853 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
854 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
855 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
856 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
857 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
858 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
859 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
860 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
861
862 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
863 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
864 adc_vol_tlv),
865 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
866 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
867 adc_vol_tlv),
868 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
869 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
870 adc_vol_tlv),
871 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
872 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
873 adc_vol_tlv),
874 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
875 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
876 adc_vol_tlv),
877
878 /* Sidetone Control */
879 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
880 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
881
882 /* ADC Boost Volume Control */
883 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
884 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
885 adc_bst_tlv),
886 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
887 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
888 adc_bst_tlv),
889 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
890 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
891 adc_bst_tlv),
892 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
893 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
894 adc_bst_tlv),
895 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
896 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
897 adc_bst_tlv),
898
899 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
900 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
901 };
902
903 /**
904 * set_dmic_clk - Set parameter of dmic.
905 *
906 * @w: DAPM widget.
907 * @kcontrol: The kcontrol of this widget.
908 * @event: Event id.
909 *
910 * Choose dmic clock between 1MHz and 3MHz.
911 * It is better for clock to approximate 3MHz.
912 */
913 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
914 struct snd_kcontrol *kcontrol, int event)
915 {
916 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
917 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
918 int idx, rate;
919
920 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
921 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
922 idx = rl6231_calc_dmic_clk(rate);
923 if (idx < 0)
924 dev_err(component->dev, "Failed to set DMIC clock\n");
925 else
926 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
927 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
928 return idx;
929 }
930
931 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
932 struct snd_soc_dapm_widget *sink)
933 {
934 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
935 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
936 unsigned int val;
937
938 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
939 val &= RT5677_SCLK_SRC_MASK;
940 if (val == RT5677_SCLK_SRC_PLL1)
941 return 1;
942 else
943 return 0;
944 }
945
946 static int is_using_asrc(struct snd_soc_dapm_widget *source,
947 struct snd_soc_dapm_widget *sink)
948 {
949 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
950 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
951 unsigned int reg, shift, val;
952
953 if (source->reg == RT5677_ASRC_1) {
954 switch (source->shift) {
955 case 12:
956 reg = RT5677_ASRC_4;
957 shift = 0;
958 break;
959 case 13:
960 reg = RT5677_ASRC_4;
961 shift = 4;
962 break;
963 case 14:
964 reg = RT5677_ASRC_4;
965 shift = 8;
966 break;
967 case 15:
968 reg = RT5677_ASRC_4;
969 shift = 12;
970 break;
971 default:
972 return 0;
973 }
974 } else {
975 switch (source->shift) {
976 case 0:
977 reg = RT5677_ASRC_6;
978 shift = 8;
979 break;
980 case 1:
981 reg = RT5677_ASRC_6;
982 shift = 12;
983 break;
984 case 2:
985 reg = RT5677_ASRC_5;
986 shift = 0;
987 break;
988 case 3:
989 reg = RT5677_ASRC_5;
990 shift = 4;
991 break;
992 case 4:
993 reg = RT5677_ASRC_5;
994 shift = 8;
995 break;
996 case 5:
997 reg = RT5677_ASRC_5;
998 shift = 12;
999 break;
1000 case 12:
1001 reg = RT5677_ASRC_3;
1002 shift = 0;
1003 break;
1004 case 13:
1005 reg = RT5677_ASRC_3;
1006 shift = 4;
1007 break;
1008 case 14:
1009 reg = RT5677_ASRC_3;
1010 shift = 12;
1011 break;
1012 default:
1013 return 0;
1014 }
1015 }
1016
1017 regmap_read(rt5677->regmap, reg, &val);
1018 val = (val >> shift) & 0xf;
1019
1020 switch (val) {
1021 case 1 ... 6:
1022 return 1;
1023 default:
1024 return 0;
1025 }
1026
1027 }
1028
1029 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1030 struct snd_soc_dapm_widget *sink)
1031 {
1032 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1033 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1034
1035 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1036 return 1;
1037
1038 return 0;
1039 }
1040
1041 /**
1042 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1043 * @component: SoC audio component device.
1044 * @filter_mask: mask of filters.
1045 * @clk_src: clock source
1046 *
1047 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1048 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1049 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1050 * ASRC function will track i2s clock and generate a corresponding system clock
1051 * for codec. This function provides an API to select the clock source for a
1052 * set of filters specified by the mask. And the codec driver will turn on ASRC
1053 * for these filters if ASRC is selected as their clock source.
1054 */
1055 int rt5677_sel_asrc_clk_src(struct snd_soc_component *component,
1056 unsigned int filter_mask, unsigned int clk_src)
1057 {
1058 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1059 unsigned int asrc3_mask = 0, asrc3_value = 0;
1060 unsigned int asrc4_mask = 0, asrc4_value = 0;
1061 unsigned int asrc5_mask = 0, asrc5_value = 0;
1062 unsigned int asrc6_mask = 0, asrc6_value = 0;
1063 unsigned int asrc7_mask = 0, asrc7_value = 0;
1064 unsigned int asrc8_mask = 0, asrc8_value = 0;
1065
1066 switch (clk_src) {
1067 case RT5677_CLK_SEL_SYS:
1068 case RT5677_CLK_SEL_I2S1_ASRC:
1069 case RT5677_CLK_SEL_I2S2_ASRC:
1070 case RT5677_CLK_SEL_I2S3_ASRC:
1071 case RT5677_CLK_SEL_I2S4_ASRC:
1072 case RT5677_CLK_SEL_I2S5_ASRC:
1073 case RT5677_CLK_SEL_I2S6_ASRC:
1074 case RT5677_CLK_SEL_SYS2:
1075 case RT5677_CLK_SEL_SYS3:
1076 case RT5677_CLK_SEL_SYS4:
1077 case RT5677_CLK_SEL_SYS5:
1078 case RT5677_CLK_SEL_SYS6:
1079 case RT5677_CLK_SEL_SYS7:
1080 break;
1081
1082 default:
1083 return -EINVAL;
1084 }
1085
1086 /* ASRC 3 */
1087 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1088 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1089 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1090 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1091 }
1092
1093 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1094 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1095 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1096 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1097 }
1098
1099 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1100 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1101 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1102 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1103 }
1104
1105 if (asrc3_mask)
1106 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1107 asrc3_value);
1108
1109 /* ASRC 4 */
1110 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1111 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1112 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1113 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1114 }
1115
1116 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1117 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1118 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1119 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1120 }
1121
1122 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1123 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1124 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1125 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1126 }
1127
1128 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1129 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1130 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1131 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1132 }
1133
1134 if (asrc4_mask)
1135 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1136 asrc4_value);
1137
1138 /* ASRC 5 */
1139 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1140 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1141 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1142 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1143 }
1144
1145 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1146 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1147 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1148 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1149 }
1150
1151 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1152 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1153 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1154 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1155 }
1156
1157 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1158 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1159 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1160 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1161 }
1162
1163 if (asrc5_mask)
1164 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1165 asrc5_value);
1166
1167 /* ASRC 6 */
1168 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1169 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1170 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1171 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1172 }
1173
1174 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1175 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1176 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1177 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1178 }
1179
1180 if (asrc6_mask)
1181 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1182 asrc6_value);
1183
1184 /* ASRC 7 */
1185 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1186 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1187 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1188 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1189 }
1190
1191 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1192 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1193 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1194 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1195 }
1196
1197 if (asrc7_mask)
1198 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1199 asrc7_value);
1200
1201 /* ASRC 8 */
1202 if (filter_mask & RT5677_I2S1_SOURCE) {
1203 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1204 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1205 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1206 }
1207
1208 if (filter_mask & RT5677_I2S2_SOURCE) {
1209 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1210 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1211 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1212 }
1213
1214 if (filter_mask & RT5677_I2S3_SOURCE) {
1215 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1216 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1217 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1218 }
1219
1220 if (filter_mask & RT5677_I2S4_SOURCE) {
1221 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1222 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1223 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1224 }
1225
1226 if (asrc8_mask)
1227 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1228 asrc8_value);
1229
1230 return 0;
1231 }
1232 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1233
1234 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1235 struct snd_soc_dapm_widget *sink)
1236 {
1237 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1238 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1239 unsigned int asrc_setting;
1240
1241 switch (source->shift) {
1242 case 11:
1243 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1244 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1245 RT5677_AD_STO1_CLK_SEL_SFT;
1246 break;
1247
1248 case 10:
1249 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1250 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1251 RT5677_AD_STO2_CLK_SEL_SFT;
1252 break;
1253
1254 case 9:
1255 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1256 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1257 RT5677_AD_STO3_CLK_SEL_SFT;
1258 break;
1259
1260 case 8:
1261 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1262 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1263 RT5677_AD_STO4_CLK_SEL_SFT;
1264 break;
1265
1266 case 7:
1267 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1268 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1269 RT5677_AD_MONOL_CLK_SEL_SFT;
1270 break;
1271
1272 case 6:
1273 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1274 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1275 RT5677_AD_MONOR_CLK_SEL_SFT;
1276 break;
1277
1278 default:
1279 return 0;
1280 }
1281
1282 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1283 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1284 return 1;
1285
1286 return 0;
1287 }
1288
1289 /* Digital Mixer */
1290 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1291 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1292 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1293 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1294 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1295 };
1296
1297 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1298 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1299 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1300 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1301 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1302 };
1303
1304 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1305 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1306 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1307 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1308 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1309 };
1310
1311 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1312 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1313 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1314 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1315 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1316 };
1317
1318 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1319 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1320 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1321 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1322 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1323 };
1324
1325 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1326 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1327 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1328 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1329 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1330 };
1331
1332 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1333 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1334 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1335 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1336 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1337 };
1338
1339 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1340 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1341 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1342 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1343 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1344 };
1345
1346 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1347 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1348 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1349 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1350 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1351 };
1352
1353 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1354 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1355 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1356 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1357 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1358 };
1359
1360 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1361 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1362 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1363 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1364 RT5677_M_DAC1_L_SFT, 1, 1),
1365 };
1366
1367 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1368 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1369 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1370 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1371 RT5677_M_DAC1_R_SFT, 1, 1),
1372 };
1373
1374 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1375 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1376 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1377 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1378 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1379 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1380 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1381 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1382 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1383 };
1384
1385 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1386 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1387 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1388 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1389 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1390 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1391 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1392 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1393 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1394 };
1395
1396 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1397 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1398 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1399 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1400 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1401 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1402 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1403 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1404 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1405 };
1406
1407 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1408 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1409 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1410 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1411 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1412 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1413 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1414 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1415 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1416 };
1417
1418 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1419 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1420 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1421 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1422 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1423 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1424 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1425 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1426 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1427 };
1428
1429 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1430 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1431 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1432 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1433 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1434 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1435 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1436 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1437 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1438 };
1439
1440 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1441 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1442 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1443 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1444 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1445 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1446 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1447 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1448 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1449 };
1450
1451 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1452 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1453 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1454 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1455 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1456 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1457 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1458 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1459 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1460 };
1461
1462 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1463 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1464 RT5677_DSP_IB_01_H_SFT, 1, 1),
1465 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1466 RT5677_DSP_IB_23_H_SFT, 1, 1),
1467 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1468 RT5677_DSP_IB_45_H_SFT, 1, 1),
1469 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1470 RT5677_DSP_IB_6_H_SFT, 1, 1),
1471 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1472 RT5677_DSP_IB_7_H_SFT, 1, 1),
1473 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1474 RT5677_DSP_IB_8_H_SFT, 1, 1),
1475 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1476 RT5677_DSP_IB_9_H_SFT, 1, 1),
1477 };
1478
1479 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1480 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1481 RT5677_DSP_IB_01_L_SFT, 1, 1),
1482 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1483 RT5677_DSP_IB_23_L_SFT, 1, 1),
1484 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1485 RT5677_DSP_IB_45_L_SFT, 1, 1),
1486 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1487 RT5677_DSP_IB_6_L_SFT, 1, 1),
1488 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1489 RT5677_DSP_IB_7_L_SFT, 1, 1),
1490 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1491 RT5677_DSP_IB_8_L_SFT, 1, 1),
1492 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1493 RT5677_DSP_IB_9_L_SFT, 1, 1),
1494 };
1495
1496 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1497 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1498 RT5677_DSP_IB_01_H_SFT, 1, 1),
1499 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1500 RT5677_DSP_IB_23_H_SFT, 1, 1),
1501 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1502 RT5677_DSP_IB_45_H_SFT, 1, 1),
1503 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1504 RT5677_DSP_IB_6_H_SFT, 1, 1),
1505 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1506 RT5677_DSP_IB_7_H_SFT, 1, 1),
1507 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1508 RT5677_DSP_IB_8_H_SFT, 1, 1),
1509 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1510 RT5677_DSP_IB_9_H_SFT, 1, 1),
1511 };
1512
1513 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1514 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1515 RT5677_DSP_IB_01_L_SFT, 1, 1),
1516 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1517 RT5677_DSP_IB_23_L_SFT, 1, 1),
1518 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1519 RT5677_DSP_IB_45_L_SFT, 1, 1),
1520 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1521 RT5677_DSP_IB_6_L_SFT, 1, 1),
1522 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1523 RT5677_DSP_IB_7_L_SFT, 1, 1),
1524 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1525 RT5677_DSP_IB_8_L_SFT, 1, 1),
1526 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1527 RT5677_DSP_IB_9_L_SFT, 1, 1),
1528 };
1529
1530 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1531 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1532 RT5677_DSP_IB_01_H_SFT, 1, 1),
1533 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1534 RT5677_DSP_IB_23_H_SFT, 1, 1),
1535 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1536 RT5677_DSP_IB_45_H_SFT, 1, 1),
1537 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1538 RT5677_DSP_IB_6_H_SFT, 1, 1),
1539 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1540 RT5677_DSP_IB_7_H_SFT, 1, 1),
1541 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1542 RT5677_DSP_IB_8_H_SFT, 1, 1),
1543 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1544 RT5677_DSP_IB_9_H_SFT, 1, 1),
1545 };
1546
1547 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1548 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1549 RT5677_DSP_IB_01_L_SFT, 1, 1),
1550 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1551 RT5677_DSP_IB_23_L_SFT, 1, 1),
1552 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1553 RT5677_DSP_IB_45_L_SFT, 1, 1),
1554 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1555 RT5677_DSP_IB_6_L_SFT, 1, 1),
1556 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1557 RT5677_DSP_IB_7_L_SFT, 1, 1),
1558 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1559 RT5677_DSP_IB_8_L_SFT, 1, 1),
1560 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1561 RT5677_DSP_IB_9_L_SFT, 1, 1),
1562 };
1563
1564
1565 /* Mux */
1566 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1567 static const char * const rt5677_dac1_src[] = {
1568 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1569 "OB 01"
1570 };
1571
1572 static SOC_ENUM_SINGLE_DECL(
1573 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1574 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1575
1576 static const struct snd_kcontrol_new rt5677_dac1_mux =
1577 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1578
1579 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1580 static const char * const rt5677_adda1_src[] = {
1581 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1582 };
1583
1584 static SOC_ENUM_SINGLE_DECL(
1585 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1586 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1587
1588 static const struct snd_kcontrol_new rt5677_adda1_mux =
1589 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1590
1591
1592 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1593 static const char * const rt5677_dac2l_src[] = {
1594 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1595 "OB 2",
1596 };
1597
1598 static SOC_ENUM_SINGLE_DECL(
1599 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1600 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1601
1602 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1603 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1604
1605 static const char * const rt5677_dac2r_src[] = {
1606 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1607 "OB 3", "Haptic Generator", "VAD ADC"
1608 };
1609
1610 static SOC_ENUM_SINGLE_DECL(
1611 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1612 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1613
1614 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1615 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1616
1617 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1618 static const char * const rt5677_dac3l_src[] = {
1619 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1620 "SLB DAC 4", "OB 4"
1621 };
1622
1623 static SOC_ENUM_SINGLE_DECL(
1624 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1625 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1626
1627 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1628 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1629
1630 static const char * const rt5677_dac3r_src[] = {
1631 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1632 "SLB DAC 5", "OB 5"
1633 };
1634
1635 static SOC_ENUM_SINGLE_DECL(
1636 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1637 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1638
1639 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1640 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1641
1642 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1643 static const char * const rt5677_dac4l_src[] = {
1644 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1645 "SLB DAC 6", "OB 6"
1646 };
1647
1648 static SOC_ENUM_SINGLE_DECL(
1649 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1650 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1651
1652 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1653 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1654
1655 static const char * const rt5677_dac4r_src[] = {
1656 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1657 "SLB DAC 7", "OB 7"
1658 };
1659
1660 static SOC_ENUM_SINGLE_DECL(
1661 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1662 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1663
1664 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1665 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1666
1667 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1668 static const char * const rt5677_iob_bypass_src[] = {
1669 "Bypass", "Pass SRC"
1670 };
1671
1672 static SOC_ENUM_SINGLE_DECL(
1673 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1674 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1675
1676 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1677 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1678
1679 static SOC_ENUM_SINGLE_DECL(
1680 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1681 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1682
1683 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1684 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1685
1686 static SOC_ENUM_SINGLE_DECL(
1687 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1688 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1689
1690 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1691 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1692
1693 static SOC_ENUM_SINGLE_DECL(
1694 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1695 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1696
1697 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1698 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1699
1700 static SOC_ENUM_SINGLE_DECL(
1701 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1702 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1703
1704 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1705 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1706
1707 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1708 static const char * const rt5677_stereo_adc2_src[] = {
1709 "DD MIX1", "DMIC", "Stereo DAC MIX"
1710 };
1711
1712 static SOC_ENUM_SINGLE_DECL(
1713 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1714 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1715
1716 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1717 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1718
1719 static SOC_ENUM_SINGLE_DECL(
1720 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1721 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1722
1723 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1724 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1725
1726 static SOC_ENUM_SINGLE_DECL(
1727 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1728 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1729
1730 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1731 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1732
1733 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1734 static const char * const rt5677_dmic_src[] = {
1735 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1736 };
1737
1738 static SOC_ENUM_SINGLE_DECL(
1739 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1740 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1741
1742 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1743 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1744
1745 static SOC_ENUM_SINGLE_DECL(
1746 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1747 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1748
1749 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1750 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1751
1752 static SOC_ENUM_SINGLE_DECL(
1753 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1754 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1755
1756 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1757 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1758
1759 static SOC_ENUM_SINGLE_DECL(
1760 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1761 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1762
1763 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1764 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1765
1766 static SOC_ENUM_SINGLE_DECL(
1767 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1768 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1769
1770 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1771 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1772
1773 static SOC_ENUM_SINGLE_DECL(
1774 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1775 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1776
1777 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1778 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1779
1780 /* Stereo2 ADC Source */ /* MX-26 [0] */
1781 static const char * const rt5677_stereo2_adc_lr_src[] = {
1782 "L", "LR"
1783 };
1784
1785 static SOC_ENUM_SINGLE_DECL(
1786 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1787 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1788
1789 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1790 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1791
1792 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1793 static const char * const rt5677_stereo_adc1_src[] = {
1794 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1795 };
1796
1797 static SOC_ENUM_SINGLE_DECL(
1798 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1799 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1800
1801 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1802 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1803
1804 static SOC_ENUM_SINGLE_DECL(
1805 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1806 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1807
1808 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1809 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1810
1811 static SOC_ENUM_SINGLE_DECL(
1812 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1813 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1814
1815 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1816 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1817
1818 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1819 static const char * const rt5677_mono_adc2_l_src[] = {
1820 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1821 };
1822
1823 static SOC_ENUM_SINGLE_DECL(
1824 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1825 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1826
1827 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1828 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1829
1830 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1831 static const char * const rt5677_mono_adc1_l_src[] = {
1832 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1833 };
1834
1835 static SOC_ENUM_SINGLE_DECL(
1836 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1837 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1838
1839 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1840 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1841
1842 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1843 static const char * const rt5677_mono_adc2_r_src[] = {
1844 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1845 };
1846
1847 static SOC_ENUM_SINGLE_DECL(
1848 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1849 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1850
1851 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1852 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1853
1854 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1855 static const char * const rt5677_mono_adc1_r_src[] = {
1856 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1857 };
1858
1859 static SOC_ENUM_SINGLE_DECL(
1860 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1861 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1862
1863 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1864 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1865
1866 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1867 static const char * const rt5677_stereo4_adc2_src[] = {
1868 "DD MIX1", "DMIC", "DD MIX2"
1869 };
1870
1871 static SOC_ENUM_SINGLE_DECL(
1872 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1873 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1874
1875 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1876 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1877
1878
1879 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1880 static const char * const rt5677_stereo4_adc1_src[] = {
1881 "DD MIX1", "ADC1/2", "DD MIX2"
1882 };
1883
1884 static SOC_ENUM_SINGLE_DECL(
1885 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1886 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1887
1888 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1889 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1890
1891 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1892 static const char * const rt5677_inbound01_src[] = {
1893 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1894 "VAD ADC/DAC1 FS"
1895 };
1896
1897 static SOC_ENUM_SINGLE_DECL(
1898 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1899 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1900
1901 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1902 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1903
1904 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1905 static const char * const rt5677_inbound23_src[] = {
1906 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1907 "DAC1 FS", "IF4 DAC"
1908 };
1909
1910 static SOC_ENUM_SINGLE_DECL(
1911 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1912 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1913
1914 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1915 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1916
1917 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1918 static const char * const rt5677_inbound45_src[] = {
1919 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1920 "IF3 DAC"
1921 };
1922
1923 static SOC_ENUM_SINGLE_DECL(
1924 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1925 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1926
1927 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1928 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1929
1930 /* InBound6 Source */ /* MX-A3 [2:0] */
1931 static const char * const rt5677_inbound6_src[] = {
1932 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1933 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1934 };
1935
1936 static SOC_ENUM_SINGLE_DECL(
1937 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1938 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1939
1940 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1941 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1942
1943 /* InBound7 Source */ /* MX-A4 [14:12] */
1944 static const char * const rt5677_inbound7_src[] = {
1945 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1946 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1947 };
1948
1949 static SOC_ENUM_SINGLE_DECL(
1950 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1951 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1952
1953 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1954 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1955
1956 /* InBound8 Source */ /* MX-A4 [10:8] */
1957 static const char * const rt5677_inbound8_src[] = {
1958 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1959 "MONO ADC MIX L", "DACL1 FS"
1960 };
1961
1962 static SOC_ENUM_SINGLE_DECL(
1963 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1964 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1965
1966 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1967 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1968
1969 /* InBound9 Source */ /* MX-A4 [6:4] */
1970 static const char * const rt5677_inbound9_src[] = {
1971 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1972 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1973 };
1974
1975 static SOC_ENUM_SINGLE_DECL(
1976 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1977 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1978
1979 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1980 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1981
1982 /* VAD Source */ /* MX-9F [6:4] */
1983 static const char * const rt5677_vad_src[] = {
1984 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1985 "STO3 ADC MIX L"
1986 };
1987
1988 static SOC_ENUM_SINGLE_DECL(
1989 rt5677_vad_enum, RT5677_VAD_CTRL4,
1990 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1991
1992 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1993 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1994
1995 /* Sidetone Source */ /* MX-13 [11:9] */
1996 static const char * const rt5677_sidetone_src[] = {
1997 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1998 };
1999
2000 static SOC_ENUM_SINGLE_DECL(
2001 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
2002 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
2003
2004 static const struct snd_kcontrol_new rt5677_sidetone_mux =
2005 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2006
2007 /* DAC1/2 Source */ /* MX-15 [1:0] */
2008 static const char * const rt5677_dac12_src[] = {
2009 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2010 };
2011
2012 static SOC_ENUM_SINGLE_DECL(
2013 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2014 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2015
2016 static const struct snd_kcontrol_new rt5677_dac12_mux =
2017 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2018
2019 /* DAC3 Source */ /* MX-15 [5:4] */
2020 static const char * const rt5677_dac3_src[] = {
2021 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2022 };
2023
2024 static SOC_ENUM_SINGLE_DECL(
2025 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2026 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2027
2028 static const struct snd_kcontrol_new rt5677_dac3_mux =
2029 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2030
2031 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2032 static const char * const rt5677_pdm_src[] = {
2033 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2034 };
2035
2036 static SOC_ENUM_SINGLE_DECL(
2037 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2038 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2039
2040 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
2041 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
2042
2043 static SOC_ENUM_SINGLE_DECL(
2044 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2045 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2046
2047 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
2048 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
2049
2050 static SOC_ENUM_SINGLE_DECL(
2051 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2052 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2053
2054 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
2055 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
2056
2057 static SOC_ENUM_SINGLE_DECL(
2058 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2059 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2060
2061 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
2062 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
2063
2064 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2065 static const char * const rt5677_if12_adc1_src[] = {
2066 "STO1 ADC MIX", "OB01", "VAD ADC"
2067 };
2068
2069 static SOC_ENUM_SINGLE_DECL(
2070 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2071 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2072
2073 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
2074 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
2075
2076 static SOC_ENUM_SINGLE_DECL(
2077 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2078 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2079
2080 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
2081 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
2082
2083 static SOC_ENUM_SINGLE_DECL(
2084 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2085 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2086
2087 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
2088 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
2089
2090 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2091 static const char * const rt5677_if12_adc2_src[] = {
2092 "STO2 ADC MIX", "OB23"
2093 };
2094
2095 static SOC_ENUM_SINGLE_DECL(
2096 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2097 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2098
2099 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
2100 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
2101
2102 static SOC_ENUM_SINGLE_DECL(
2103 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2104 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2105
2106 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
2107 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
2108
2109 static SOC_ENUM_SINGLE_DECL(
2110 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2111 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2112
2113 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
2114 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
2115
2116 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2117 static const char * const rt5677_if12_adc3_src[] = {
2118 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2119 };
2120
2121 static SOC_ENUM_SINGLE_DECL(
2122 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2123 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2124
2125 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
2126 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
2127
2128 static SOC_ENUM_SINGLE_DECL(
2129 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2130 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2131
2132 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
2133 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
2134
2135 static SOC_ENUM_SINGLE_DECL(
2136 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2137 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2138
2139 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
2140 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
2141
2142 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2143 static const char * const rt5677_if12_adc4_src[] = {
2144 "STO4 ADC MIX", "OB67", "OB01"
2145 };
2146
2147 static SOC_ENUM_SINGLE_DECL(
2148 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2149 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2150
2151 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
2152 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
2153
2154 static SOC_ENUM_SINGLE_DECL(
2155 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2156 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2157
2158 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
2159 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
2160
2161 static SOC_ENUM_SINGLE_DECL(
2162 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2163 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2164
2165 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
2166 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
2167
2168 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2169 static const char * const rt5677_if34_adc_src[] = {
2170 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2171 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2172 };
2173
2174 static SOC_ENUM_SINGLE_DECL(
2175 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2176 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2177
2178 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
2179 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
2180
2181 static SOC_ENUM_SINGLE_DECL(
2182 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2183 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2184
2185 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
2186 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
2187
2188 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2189 static const char * const rt5677_if12_adc_swap_src[] = {
2190 "L/R", "R/L", "L/L", "R/R"
2191 };
2192
2193 static SOC_ENUM_SINGLE_DECL(
2194 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2195 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2196
2197 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2198 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2199
2200 static SOC_ENUM_SINGLE_DECL(
2201 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2202 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2203
2204 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2205 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2206
2207 static SOC_ENUM_SINGLE_DECL(
2208 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2209 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2210
2211 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2212 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2213
2214 static SOC_ENUM_SINGLE_DECL(
2215 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2216 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2217
2218 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2219 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2220
2221 static SOC_ENUM_SINGLE_DECL(
2222 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2223 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2224
2225 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2226 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2227
2228 static SOC_ENUM_SINGLE_DECL(
2229 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2230 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2231
2232 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2233 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2234
2235 static SOC_ENUM_SINGLE_DECL(
2236 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2237 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2238
2239 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2240 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2241
2242 static SOC_ENUM_SINGLE_DECL(
2243 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2244 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2245
2246 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2247 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2248
2249 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2250 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2251 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2252 "3/1/2/4", "3/4/1/2"
2253 };
2254
2255 static SOC_ENUM_SINGLE_DECL(
2256 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2257 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2258
2259 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2260 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2261
2262 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2263 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2264 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2265 "2/3/1/4", "3/4/1/2"
2266 };
2267
2268 static SOC_ENUM_SINGLE_DECL(
2269 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2270 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2271
2272 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2273 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2274
2275 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2276 MX-3F[14:12][10:8][6:4][2:0]
2277 MX-43[14:12][10:8][6:4][2:0]
2278 MX-44[14:12][10:8][6:4][2:0] */
2279 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2280 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2281 };
2282
2283 static SOC_ENUM_SINGLE_DECL(
2284 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2285 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2286
2287 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2288 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2289
2290 static SOC_ENUM_SINGLE_DECL(
2291 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2292 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2293
2294 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2295 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2296
2297 static SOC_ENUM_SINGLE_DECL(
2298 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2299 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2300
2301 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2302 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2303
2304 static SOC_ENUM_SINGLE_DECL(
2305 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2306 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2307
2308 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2309 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2310
2311 static SOC_ENUM_SINGLE_DECL(
2312 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2313 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2314
2315 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2316 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2317
2318 static SOC_ENUM_SINGLE_DECL(
2319 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2320 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2321
2322 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2323 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2324
2325 static SOC_ENUM_SINGLE_DECL(
2326 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2327 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2328
2329 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2330 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2331
2332 static SOC_ENUM_SINGLE_DECL(
2333 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2334 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2335
2336 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2337 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2338
2339 static SOC_ENUM_SINGLE_DECL(
2340 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2341 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2342
2343 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2344 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2345
2346 static SOC_ENUM_SINGLE_DECL(
2347 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2348 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2349
2350 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2351 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2352
2353 static SOC_ENUM_SINGLE_DECL(
2354 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2355 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2356
2357 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2358 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2359
2360 static SOC_ENUM_SINGLE_DECL(
2361 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2362 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2363
2364 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2365 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2366
2367 static SOC_ENUM_SINGLE_DECL(
2368 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2369 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2370
2371 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2372 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2373
2374 static SOC_ENUM_SINGLE_DECL(
2375 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2376 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2377
2378 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2379 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2380
2381 static SOC_ENUM_SINGLE_DECL(
2382 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2383 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2384
2385 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2386 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2387
2388 static SOC_ENUM_SINGLE_DECL(
2389 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2390 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2391
2392 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2393 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2394
2395 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2396 struct snd_kcontrol *kcontrol, int event)
2397 {
2398 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2399 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2400
2401 switch (event) {
2402 case SND_SOC_DAPM_POST_PMU:
2403 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2404 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2405 break;
2406
2407 case SND_SOC_DAPM_PRE_PMD:
2408 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2409 RT5677_PWR_BST1_P, 0);
2410 break;
2411
2412 default:
2413 return 0;
2414 }
2415
2416 return 0;
2417 }
2418
2419 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2420 struct snd_kcontrol *kcontrol, int event)
2421 {
2422 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2423 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2424
2425 switch (event) {
2426 case SND_SOC_DAPM_POST_PMU:
2427 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2428 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2429 break;
2430
2431 case SND_SOC_DAPM_PRE_PMD:
2432 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2433 RT5677_PWR_BST2_P, 0);
2434 break;
2435
2436 default:
2437 return 0;
2438 }
2439
2440 return 0;
2441 }
2442
2443 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2444 struct snd_kcontrol *kcontrol, int event)
2445 {
2446 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2447 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2448
2449 switch (event) {
2450 case SND_SOC_DAPM_PRE_PMU:
2451 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2452 break;
2453
2454 case SND_SOC_DAPM_POST_PMU:
2455 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2456 break;
2457
2458 default:
2459 return 0;
2460 }
2461
2462 return 0;
2463 }
2464
2465 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2466 struct snd_kcontrol *kcontrol, int event)
2467 {
2468 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2469 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2470
2471 switch (event) {
2472 case SND_SOC_DAPM_PRE_PMU:
2473 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2474 break;
2475
2476 case SND_SOC_DAPM_POST_PMU:
2477 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2478 break;
2479
2480 default:
2481 return 0;
2482 }
2483
2484 return 0;
2485 }
2486
2487 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2488 struct snd_kcontrol *kcontrol, int event)
2489 {
2490 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2491 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2492
2493 switch (event) {
2494 case SND_SOC_DAPM_POST_PMU:
2495 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2496 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2497 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2498 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2499 break;
2500
2501 case SND_SOC_DAPM_PRE_PMD:
2502 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2503 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2504 RT5677_PWR_CLK_MB, 0);
2505 break;
2506
2507 default:
2508 return 0;
2509 }
2510
2511 return 0;
2512 }
2513
2514 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2515 struct snd_kcontrol *kcontrol, int event)
2516 {
2517 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2518 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2519 unsigned int value;
2520
2521 switch (event) {
2522 case SND_SOC_DAPM_PRE_PMU:
2523 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2524 if (value & RT5677_IF1_ADC_CTRL_MASK)
2525 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2526 RT5677_IF1_ADC_MODE_MASK,
2527 RT5677_IF1_ADC_MODE_TDM);
2528 break;
2529
2530 default:
2531 return 0;
2532 }
2533
2534 return 0;
2535 }
2536
2537 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2538 struct snd_kcontrol *kcontrol, int event)
2539 {
2540 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2541 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2542 unsigned int value;
2543
2544 switch (event) {
2545 case SND_SOC_DAPM_PRE_PMU:
2546 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2547 if (value & RT5677_IF2_ADC_CTRL_MASK)
2548 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2549 RT5677_IF2_ADC_MODE_MASK,
2550 RT5677_IF2_ADC_MODE_TDM);
2551 break;
2552
2553 default:
2554 return 0;
2555 }
2556
2557 return 0;
2558 }
2559
2560 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2561 struct snd_kcontrol *kcontrol, int event)
2562 {
2563 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2564 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2565
2566 switch (event) {
2567 case SND_SOC_DAPM_POST_PMU:
2568 if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON &&
2569 !rt5677->is_vref_slow) {
2570 mdelay(20);
2571 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2572 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2573 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2574 rt5677->is_vref_slow = true;
2575 }
2576 break;
2577
2578 default:
2579 return 0;
2580 }
2581
2582 return 0;
2583 }
2584
2585 static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w,
2586 struct snd_kcontrol *kcontrol, int event)
2587 {
2588 switch (event) {
2589 case SND_SOC_DAPM_POST_PMU:
2590 msleep(50);
2591 break;
2592
2593 default:
2594 return 0;
2595 }
2596
2597 return 0;
2598 }
2599
2600 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2601 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2602 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2603 SND_SOC_DAPM_POST_PMU),
2604 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2605 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2606 SND_SOC_DAPM_POST_PMU),
2607
2608 /* ASRC */
2609 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2610 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2611 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2612 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2613 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0,
2614 rt5677_filter_power_event, SND_SOC_DAPM_POST_PMU),
2615 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2616 0),
2617 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2618 0),
2619 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2620 0),
2621 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2622 0),
2623 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2624 0),
2625 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2626 0),
2627 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2628 0),
2629 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2630 0),
2631 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2632 0),
2633 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2634 0),
2635 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2636 0),
2637 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2638 0),
2639 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2640 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2641 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2642 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2643 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2644 0),
2645 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2646 0),
2647
2648 /* Input Side */
2649 /* micbias */
2650 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2651 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2652 SND_SOC_DAPM_POST_PMU),
2653
2654 /* Input Lines */
2655 SND_SOC_DAPM_INPUT("DMIC L1"),
2656 SND_SOC_DAPM_INPUT("DMIC R1"),
2657 SND_SOC_DAPM_INPUT("DMIC L2"),
2658 SND_SOC_DAPM_INPUT("DMIC R2"),
2659 SND_SOC_DAPM_INPUT("DMIC L3"),
2660 SND_SOC_DAPM_INPUT("DMIC R3"),
2661 SND_SOC_DAPM_INPUT("DMIC L4"),
2662 SND_SOC_DAPM_INPUT("DMIC R4"),
2663
2664 SND_SOC_DAPM_INPUT("IN1P"),
2665 SND_SOC_DAPM_INPUT("IN1N"),
2666 SND_SOC_DAPM_INPUT("IN2P"),
2667 SND_SOC_DAPM_INPUT("IN2N"),
2668
2669 SND_SOC_DAPM_INPUT("Haptic Generator"),
2670
2671 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2672 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2673 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2674 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2675
2676 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2677 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2678 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2679 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2680 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2681 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2682 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2683 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2684
2685 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2686 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2687
2688 /* Boost */
2689 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2690 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2691 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2692 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2693 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2694 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2695
2696 /* ADCs */
2697 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2698 0, 0),
2699 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2700 0, 0),
2701 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2702
2703 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2704 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2705 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2706 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2707 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2708 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2709 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2710 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2711
2712 /* ADC Mux */
2713 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2714 &rt5677_sto1_dmic_mux),
2715 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2716 &rt5677_sto1_adc1_mux),
2717 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2718 &rt5677_sto1_adc2_mux),
2719 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2720 &rt5677_sto2_dmic_mux),
2721 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2722 &rt5677_sto2_adc1_mux),
2723 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2724 &rt5677_sto2_adc2_mux),
2725 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2726 &rt5677_sto2_adc_lr_mux),
2727 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2728 &rt5677_sto3_dmic_mux),
2729 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2730 &rt5677_sto3_adc1_mux),
2731 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2732 &rt5677_sto3_adc2_mux),
2733 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2734 &rt5677_sto4_dmic_mux),
2735 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2736 &rt5677_sto4_adc1_mux),
2737 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2738 &rt5677_sto4_adc2_mux),
2739 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2740 &rt5677_mono_dmic_l_mux),
2741 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2742 &rt5677_mono_dmic_r_mux),
2743 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2744 &rt5677_mono_adc2_l_mux),
2745 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2746 &rt5677_mono_adc1_l_mux),
2747 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2748 &rt5677_mono_adc1_r_mux),
2749 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2750 &rt5677_mono_adc2_r_mux),
2751
2752 /* ADC Mixer */
2753 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2754 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2755 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2756 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2757 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2758 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2759 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2760 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2761 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2762 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2763 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2764 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2765 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2766 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2767 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2768 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2769 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2770 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2771 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2772 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2773 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2774 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2775 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2776 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2777 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2778 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2779 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2780 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2781 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2782 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2783 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2784 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2785
2786 /* ADC PGA */
2787 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2788 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2789 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2790 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2791 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2792 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2793 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2794 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2795 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2796 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2797 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2798 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2799 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2800 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2801 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2802 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2803
2804 /* DSP */
2805 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2806 &rt5677_ib9_src_mux),
2807 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2808 &rt5677_ib8_src_mux),
2809 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2810 &rt5677_ib7_src_mux),
2811 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2812 &rt5677_ib6_src_mux),
2813 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2814 &rt5677_ib45_src_mux),
2815 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2816 &rt5677_ib23_src_mux),
2817 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2818 &rt5677_ib01_src_mux),
2819 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2820 &rt5677_ib45_bypass_src_mux),
2821 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2822 &rt5677_ib23_bypass_src_mux),
2823 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2824 &rt5677_ib01_bypass_src_mux),
2825 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2826 &rt5677_ob23_bypass_src_mux),
2827 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2828 &rt5677_ob01_bypass_src_mux),
2829
2830 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2831 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2832
2833 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2834 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2835 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2836 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2837 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2838 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2839
2840 /* Digital Interface */
2841 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2842 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2843 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2844 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2845 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2849 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2850 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2851 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2852 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2853 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2854 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2855 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2856 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2857 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2858 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2859
2860 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2861 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2869 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2870 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2872 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2873 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2875 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2877 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2878
2879 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2880 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2883 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2884 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2885 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2886 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2887
2888 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2889 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2890 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2891 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2892 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2893 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2894 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2895 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2896
2897 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2898 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2899 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2900 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2901 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2902 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2903 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2904 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2905 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2906 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2907 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2908 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2909 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2910 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2911 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2912 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2913 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2914 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2915
2916 /* Digital Interface Select */
2917 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2918 &rt5677_if1_adc1_mux),
2919 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2920 &rt5677_if1_adc2_mux),
2921 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2922 &rt5677_if1_adc3_mux),
2923 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2924 &rt5677_if1_adc4_mux),
2925 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2926 &rt5677_if1_adc1_swap_mux),
2927 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2928 &rt5677_if1_adc2_swap_mux),
2929 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2930 &rt5677_if1_adc3_swap_mux),
2931 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2932 &rt5677_if1_adc4_swap_mux),
2933 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2934 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2935 SND_SOC_DAPM_PRE_PMU),
2936 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2937 &rt5677_if2_adc1_mux),
2938 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2939 &rt5677_if2_adc2_mux),
2940 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2941 &rt5677_if2_adc3_mux),
2942 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2943 &rt5677_if2_adc4_mux),
2944 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2945 &rt5677_if2_adc1_swap_mux),
2946 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2947 &rt5677_if2_adc2_swap_mux),
2948 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2949 &rt5677_if2_adc3_swap_mux),
2950 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2951 &rt5677_if2_adc4_swap_mux),
2952 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2953 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2954 SND_SOC_DAPM_PRE_PMU),
2955 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2956 &rt5677_if3_adc_mux),
2957 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2958 &rt5677_if4_adc_mux),
2959 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2960 &rt5677_slb_adc1_mux),
2961 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2962 &rt5677_slb_adc2_mux),
2963 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2964 &rt5677_slb_adc3_mux),
2965 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5677_slb_adc4_mux),
2967
2968 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2969 &rt5677_if1_dac0_tdm_sel_mux),
2970 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2971 &rt5677_if1_dac1_tdm_sel_mux),
2972 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2973 &rt5677_if1_dac2_tdm_sel_mux),
2974 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2975 &rt5677_if1_dac3_tdm_sel_mux),
2976 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2977 &rt5677_if1_dac4_tdm_sel_mux),
2978 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2979 &rt5677_if1_dac5_tdm_sel_mux),
2980 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2981 &rt5677_if1_dac6_tdm_sel_mux),
2982 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2983 &rt5677_if1_dac7_tdm_sel_mux),
2984
2985 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2986 &rt5677_if2_dac0_tdm_sel_mux),
2987 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2988 &rt5677_if2_dac1_tdm_sel_mux),
2989 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2990 &rt5677_if2_dac2_tdm_sel_mux),
2991 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2992 &rt5677_if2_dac3_tdm_sel_mux),
2993 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2994 &rt5677_if2_dac4_tdm_sel_mux),
2995 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2996 &rt5677_if2_dac5_tdm_sel_mux),
2997 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2998 &rt5677_if2_dac6_tdm_sel_mux),
2999 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
3000 &rt5677_if2_dac7_tdm_sel_mux),
3001
3002 /* Audio Interface */
3003 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
3004 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
3005 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
3006 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3007 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3008 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3009 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3010 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3011 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3012 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3013
3014 /* Sidetone Mux */
3015 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3016 &rt5677_sidetone_mux),
3017 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3018 RT5677_ST_EN_SFT, 0, NULL, 0),
3019
3020 /* VAD Mux*/
3021 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3022 &rt5677_vad_src_mux),
3023
3024 /* Tensilica DSP */
3025 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3026 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3027 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3028 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3029 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3030 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3031 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3032 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3033 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3034 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3035 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3036 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3037 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3038
3039 /* Output Side */
3040 /* DAC mixer before sound effect */
3041 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3042 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3043 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3044 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3045 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3046
3047 /* DAC Mux */
3048 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3049 &rt5677_dac1_mux),
3050 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3051 &rt5677_adda1_mux),
3052 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3053 &rt5677_dac12_mux),
3054 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3055 &rt5677_dac3_mux),
3056
3057 /* DAC2 channel Mux */
3058 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3059 &rt5677_dac2_l_mux),
3060 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3061 &rt5677_dac2_r_mux),
3062
3063 /* DAC3 channel Mux */
3064 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3065 &rt5677_dac3_l_mux),
3066 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3067 &rt5677_dac3_r_mux),
3068
3069 /* DAC4 channel Mux */
3070 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3071 &rt5677_dac4_l_mux),
3072 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3073 &rt5677_dac4_r_mux),
3074
3075 /* DAC Mixer */
3076 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
3077 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event,
3078 SND_SOC_DAPM_POST_PMU),
3079 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
3080 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event,
3081 SND_SOC_DAPM_POST_PMU),
3082 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
3083 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event,
3084 SND_SOC_DAPM_POST_PMU),
3085 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
3086 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event,
3087 SND_SOC_DAPM_POST_PMU),
3088 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
3089 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event,
3090 SND_SOC_DAPM_POST_PMU),
3091 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
3092 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event,
3093 SND_SOC_DAPM_POST_PMU),
3094 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
3095 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event,
3096 SND_SOC_DAPM_POST_PMU),
3097
3098 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3099 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3100 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3101 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3102 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3103 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3104 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3105 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3106 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3107 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3108 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3109 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3110 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3111 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3112 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3113 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3114 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3115 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3116 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3117 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3118
3119 /* DACs */
3120 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3121 RT5677_PWR_DAC1_BIT, 0),
3122 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3123 RT5677_PWR_DAC2_BIT, 0),
3124 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3125 RT5677_PWR_DAC3_BIT, 0),
3126
3127 /* PDM */
3128 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3129 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3130 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3131 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3132
3133 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3134 1, &rt5677_pdm1_l_mux),
3135 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3136 1, &rt5677_pdm1_r_mux),
3137 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3138 1, &rt5677_pdm2_l_mux),
3139 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3140 1, &rt5677_pdm2_r_mux),
3141
3142 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
3143 0, NULL, 0),
3144 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
3145 0, NULL, 0),
3146 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
3147 0, NULL, 0),
3148
3149 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3150 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3151 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3152 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3153 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3154 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3155
3156 /* Output Lines */
3157 SND_SOC_DAPM_OUTPUT("LOUT1"),
3158 SND_SOC_DAPM_OUTPUT("LOUT2"),
3159 SND_SOC_DAPM_OUTPUT("LOUT3"),
3160 SND_SOC_DAPM_OUTPUT("PDM1L"),
3161 SND_SOC_DAPM_OUTPUT("PDM1R"),
3162 SND_SOC_DAPM_OUTPUT("PDM2L"),
3163 SND_SOC_DAPM_OUTPUT("PDM2R"),
3164
3165 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
3166 };
3167
3168 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
3169 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3170 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3171 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3172 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3173 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3174 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3175 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3176 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3177 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3178 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3179
3180 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3181 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3182 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3183 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3184 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3185 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3186 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3187 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3188 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3189 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3190 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3191 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3192 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3193
3194 { "DMIC1", NULL, "DMIC L1" },
3195 { "DMIC1", NULL, "DMIC R1" },
3196 { "DMIC2", NULL, "DMIC L2" },
3197 { "DMIC2", NULL, "DMIC R2" },
3198 { "DMIC3", NULL, "DMIC L3" },
3199 { "DMIC3", NULL, "DMIC R3" },
3200 { "DMIC4", NULL, "DMIC L4" },
3201 { "DMIC4", NULL, "DMIC R4" },
3202
3203 { "DMIC L1", NULL, "DMIC CLK" },
3204 { "DMIC R1", NULL, "DMIC CLK" },
3205 { "DMIC L2", NULL, "DMIC CLK" },
3206 { "DMIC R2", NULL, "DMIC CLK" },
3207 { "DMIC L3", NULL, "DMIC CLK" },
3208 { "DMIC R3", NULL, "DMIC CLK" },
3209 { "DMIC L4", NULL, "DMIC CLK" },
3210 { "DMIC R4", NULL, "DMIC CLK" },
3211
3212 { "DMIC L1", NULL, "DMIC1 power" },
3213 { "DMIC R1", NULL, "DMIC1 power" },
3214 { "DMIC L3", NULL, "DMIC3 power" },
3215 { "DMIC R3", NULL, "DMIC3 power" },
3216 { "DMIC L4", NULL, "DMIC4 power" },
3217 { "DMIC R4", NULL, "DMIC4 power" },
3218
3219 { "BST1", NULL, "IN1P" },
3220 { "BST1", NULL, "IN1N" },
3221 { "BST2", NULL, "IN2P" },
3222 { "BST2", NULL, "IN2N" },
3223
3224 { "IN1P", NULL, "MICBIAS1" },
3225 { "IN1N", NULL, "MICBIAS1" },
3226 { "IN2P", NULL, "MICBIAS1" },
3227 { "IN2N", NULL, "MICBIAS1" },
3228
3229 { "ADC 1", NULL, "BST1" },
3230 { "ADC 1", NULL, "ADC 1 power" },
3231 { "ADC 1", NULL, "ADC1 clock" },
3232 { "ADC 2", NULL, "BST2" },
3233 { "ADC 2", NULL, "ADC 2 power" },
3234 { "ADC 2", NULL, "ADC2 clock" },
3235
3236 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3237 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3238 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3239 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3240
3241 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3242 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3243 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3244 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3245
3246 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3247 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3248 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3249 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3250
3251 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3252 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3253 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3254 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3255
3256 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3257 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3258 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3259 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3260
3261 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3262 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3263 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3264 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3265
3266 { "ADC 1_2", NULL, "ADC 1" },
3267 { "ADC 1_2", NULL, "ADC 2" },
3268
3269 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3270 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3271 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3272
3273 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3274 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3275 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3276
3277 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3278 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3279 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3280
3281 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3282 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3283 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3284
3285 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3286 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3287 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3288
3289 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3290 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3291 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3292
3293 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3294 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3295 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3296
3297 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3298 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3299 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3300
3301 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3302 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3303 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3304
3305 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3306 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3307 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3308
3309 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3310 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3311 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3312
3313 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3314 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3315 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3316
3317 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3318 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3319 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3320 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3321
3322 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3323 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3324 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3325 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3326 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3327
3328 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3329 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3330
3331 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3332 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3333 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3334 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3335
3336 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3337 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3338
3339 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3340 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3341
3342 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3343 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3344 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3345 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3346 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3347
3348 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3349 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3350
3351 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3352 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3353 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3354 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3355
3356 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3357 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3358 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3359 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3360 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3361
3362 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3363 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3364
3365 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3366 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3367 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3368 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3369
3370 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3371 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3372 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3373 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3374 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3375
3376 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3377 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3378
3379 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3380 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3381 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3382 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3383
3384 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3385 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3386 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3387 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3388
3389 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3390 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3391
3392 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3393 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3394 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3395 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3396 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3397
3398 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3399 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3400 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3401
3402 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3403 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3404
3405 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3406 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3407 { "IF1 ADC3 Mux", "OB45", "OB45" },
3408
3409 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3410 { "IF1 ADC4 Mux", "OB67", "OB67" },
3411 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3412
3413 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3414 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3415 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3416 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3417
3418 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3419 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3420 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3421 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3422
3423 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3424 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3425 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3426 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3427
3428 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3429 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3430 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3431 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3432
3433 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3434 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3435 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3436 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3437
3438 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3439 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3440 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3441 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3442 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3443 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3444 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3445 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3446
3447 { "AIF1TX", NULL, "I2S1" },
3448 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3449
3450 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3451 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3452 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3453
3454 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3455 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3456
3457 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3458 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3459 { "IF2 ADC3 Mux", "OB45", "OB45" },
3460
3461 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3462 { "IF2 ADC4 Mux", "OB67", "OB67" },
3463 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3464
3465 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3466 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3467 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3468 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3469
3470 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3471 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3472 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3473 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3474
3475 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3476 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3477 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3478 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3479
3480 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3481 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3482 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3483 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3484
3485 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3486 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3487 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3488 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3489
3490 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3491 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3492 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3493 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3494 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3495 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3496 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3497 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3498
3499 { "AIF2TX", NULL, "I2S2" },
3500 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3501
3502 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3503 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3504 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3505 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3506 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3507 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3508 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3509 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3510
3511 { "AIF3TX", NULL, "I2S3" },
3512 { "AIF3TX", NULL, "IF3 ADC Mux" },
3513
3514 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3515 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3516 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3517 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3518 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3519 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3520 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3521 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3522
3523 { "AIF4TX", NULL, "I2S4" },
3524 { "AIF4TX", NULL, "IF4 ADC Mux" },
3525
3526 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3527 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3528 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3529
3530 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3531 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3532
3533 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3534 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3535 { "SLB ADC3 Mux", "OB45", "OB45" },
3536
3537 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3538 { "SLB ADC4 Mux", "OB67", "OB67" },
3539 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3540
3541 { "SLBTX", NULL, "SLB" },
3542 { "SLBTX", NULL, "SLB ADC1 Mux" },
3543 { "SLBTX", NULL, "SLB ADC2 Mux" },
3544 { "SLBTX", NULL, "SLB ADC3 Mux" },
3545 { "SLBTX", NULL, "SLB ADC4 Mux" },
3546
3547 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3548 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3549 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3550 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3551 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3552
3553 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3554 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3555
3556 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3557 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3558 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3559 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3560 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3561 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3562
3563 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3564 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3565
3566 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3567 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3568 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3569 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3570 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3571
3572 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3573 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3574
3575 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3576 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3577 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3578 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3579 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3580 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3581 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3582 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3583
3584 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3585 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3586 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3587 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3588 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3589 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3590 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3591 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3592
3593 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3594 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3595 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3596 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3597 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3598 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3599
3600 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3601 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3602 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3603 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3604 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3605 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3606 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3607
3608 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3609 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3610 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3611 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3612 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3613 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3614 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3615
3616 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3617 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3618 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3619 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3620 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3621 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3622 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3623
3624 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3625 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3626 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3627 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3628 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3629 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3630 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3631
3632 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3633 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3634 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3635 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3636 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3637 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3638 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3639
3640 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3641 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3642 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3643 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3644 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3645 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3646 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3647
3648 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3649 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3650 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3651 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3652 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3653 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3654 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3655
3656 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3657 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3658 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3659 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3660
3661 { "OutBound2", NULL, "OB23 Bypass Mux" },
3662 { "OutBound3", NULL, "OB23 Bypass Mux" },
3663 { "OutBound4", NULL, "OB4 MIX" },
3664 { "OutBound5", NULL, "OB5 MIX" },
3665 { "OutBound6", NULL, "OB6 MIX" },
3666 { "OutBound7", NULL, "OB7 MIX" },
3667
3668 { "OB45", NULL, "OutBound4" },
3669 { "OB45", NULL, "OutBound5" },
3670 { "OB67", NULL, "OutBound6" },
3671 { "OB67", NULL, "OutBound7" },
3672
3673 { "IF1 DAC0", NULL, "AIF1RX" },
3674 { "IF1 DAC1", NULL, "AIF1RX" },
3675 { "IF1 DAC2", NULL, "AIF1RX" },
3676 { "IF1 DAC3", NULL, "AIF1RX" },
3677 { "IF1 DAC4", NULL, "AIF1RX" },
3678 { "IF1 DAC5", NULL, "AIF1RX" },
3679 { "IF1 DAC6", NULL, "AIF1RX" },
3680 { "IF1 DAC7", NULL, "AIF1RX" },
3681 { "IF1 DAC0", NULL, "I2S1" },
3682 { "IF1 DAC1", NULL, "I2S1" },
3683 { "IF1 DAC2", NULL, "I2S1" },
3684 { "IF1 DAC3", NULL, "I2S1" },
3685 { "IF1 DAC4", NULL, "I2S1" },
3686 { "IF1 DAC5", NULL, "I2S1" },
3687 { "IF1 DAC6", NULL, "I2S1" },
3688 { "IF1 DAC7", NULL, "I2S1" },
3689
3690 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3691 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3692 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3693 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3694 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3695 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3696 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3697 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3698
3699 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3700 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3701 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3702 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3703 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3704 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3705 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3706 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3707
3708 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3709 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3710 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3711 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3712 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3713 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3714 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3715 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3716
3717 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3718 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3719 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3720 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3721 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3722 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3723 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3724 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3725
3726 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3727 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3728 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3729 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3730 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3731 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3732 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3733 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3734
3735 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3736 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3737 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3738 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3739 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3740 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3741 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3742 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3743
3744 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3745 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3746 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3747 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3748 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3749 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3750 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3751 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3752
3753 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3754 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3755 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3756 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3757 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3758 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3759 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3760 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3761
3762 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3763 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3764 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3765 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3766 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3767 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3768 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3769 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3770
3771 { "IF2 DAC0", NULL, "AIF2RX" },
3772 { "IF2 DAC1", NULL, "AIF2RX" },
3773 { "IF2 DAC2", NULL, "AIF2RX" },
3774 { "IF2 DAC3", NULL, "AIF2RX" },
3775 { "IF2 DAC4", NULL, "AIF2RX" },
3776 { "IF2 DAC5", NULL, "AIF2RX" },
3777 { "IF2 DAC6", NULL, "AIF2RX" },
3778 { "IF2 DAC7", NULL, "AIF2RX" },
3779 { "IF2 DAC0", NULL, "I2S2" },
3780 { "IF2 DAC1", NULL, "I2S2" },
3781 { "IF2 DAC2", NULL, "I2S2" },
3782 { "IF2 DAC3", NULL, "I2S2" },
3783 { "IF2 DAC4", NULL, "I2S2" },
3784 { "IF2 DAC5", NULL, "I2S2" },
3785 { "IF2 DAC6", NULL, "I2S2" },
3786 { "IF2 DAC7", NULL, "I2S2" },
3787
3788 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3789 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3790 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3791 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3792 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3793 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3794 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3795 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3796
3797 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3798 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3799 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3800 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3801 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3802 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3803 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3804 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3805
3806 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3807 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3808 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3809 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3810 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3811 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3812 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3813 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3814
3815 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3816 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3817 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3818 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3819 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3820 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3821 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3822 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3823
3824 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3825 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3826 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3827 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3828 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3829 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3830 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3831 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3832
3833 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3834 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3835 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3836 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3837 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3838 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3839 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3840 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3841
3842 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3843 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3844 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3845 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3846 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3847 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3848 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3849 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3850
3851 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3852 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3853 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3854 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3855 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3856 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3857 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3858 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3859
3860 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3861 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3862 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3863 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3864 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3865 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3866 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3867 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3868
3869 { "IF3 DAC", NULL, "AIF3RX" },
3870 { "IF3 DAC", NULL, "I2S3" },
3871
3872 { "IF4 DAC", NULL, "AIF4RX" },
3873 { "IF4 DAC", NULL, "I2S4" },
3874
3875 { "IF3 DAC L", NULL, "IF3 DAC" },
3876 { "IF3 DAC R", NULL, "IF3 DAC" },
3877
3878 { "IF4 DAC L", NULL, "IF4 DAC" },
3879 { "IF4 DAC R", NULL, "IF4 DAC" },
3880
3881 { "SLB DAC0", NULL, "SLBRX" },
3882 { "SLB DAC1", NULL, "SLBRX" },
3883 { "SLB DAC2", NULL, "SLBRX" },
3884 { "SLB DAC3", NULL, "SLBRX" },
3885 { "SLB DAC4", NULL, "SLBRX" },
3886 { "SLB DAC5", NULL, "SLBRX" },
3887 { "SLB DAC6", NULL, "SLBRX" },
3888 { "SLB DAC7", NULL, "SLBRX" },
3889 { "SLB DAC0", NULL, "SLB" },
3890 { "SLB DAC1", NULL, "SLB" },
3891 { "SLB DAC2", NULL, "SLB" },
3892 { "SLB DAC3", NULL, "SLB" },
3893 { "SLB DAC4", NULL, "SLB" },
3894 { "SLB DAC5", NULL, "SLB" },
3895 { "SLB DAC6", NULL, "SLB" },
3896 { "SLB DAC7", NULL, "SLB" },
3897
3898 { "SLB DAC01", NULL, "SLB DAC0" },
3899 { "SLB DAC01", NULL, "SLB DAC1" },
3900 { "SLB DAC23", NULL, "SLB DAC2" },
3901 { "SLB DAC23", NULL, "SLB DAC3" },
3902 { "SLB DAC45", NULL, "SLB DAC4" },
3903 { "SLB DAC45", NULL, "SLB DAC5" },
3904 { "SLB DAC67", NULL, "SLB DAC6" },
3905 { "SLB DAC67", NULL, "SLB DAC7" },
3906
3907 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3908 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3909 { "ADDA1 Mux", "OB 67", "OB67" },
3910
3911 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3912 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3913 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3914 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3915 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3916 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3917
3918 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3919 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3920 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3921 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3922
3923 { "DAC1 FS", NULL, "DAC1 MIXL" },
3924 { "DAC1 FS", NULL, "DAC1 MIXR" },
3925
3926 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3927 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
3928 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3929 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3930 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3931 { "DAC2 L Mux", "OB 2", "OutBound2" },
3932
3933 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3934 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
3935 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3936 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3937 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3938 { "DAC2 R Mux", "OB 3", "OutBound3" },
3939 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3940 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3941
3942 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3943 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
3944 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3945 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3946 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3947 { "DAC3 L Mux", "OB 4", "OutBound4" },
3948
3949 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3950 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
3951 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3952 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3953 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3954 { "DAC3 R Mux", "OB 5", "OutBound5" },
3955
3956 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3957 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3958 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3959 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3960 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3961 { "DAC4 L Mux", "OB 6", "OutBound6" },
3962
3963 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3964 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3965 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3966 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3967 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3968 { "DAC4 R Mux", "OB 7", "OutBound7" },
3969
3970 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3971 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3972 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3973 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3974 { "Sidetone Mux", "ADC1", "ADC 1" },
3975 { "Sidetone Mux", "ADC2", "ADC 2" },
3976 { "Sidetone Mux", NULL, "Sidetone Power" },
3977
3978 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3979 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3980 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3981 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3982 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3983 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3984 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3985 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3986 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3987 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3988 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3989
3990 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3991 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3992 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3993 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3994 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3995 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3996 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3997 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3998 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3999 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
4000 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
4001 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4002
4003 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4004 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4005 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
4006 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
4007 { "DD1 MIXL", NULL, "dac mono3 left filter" },
4008 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4009 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4010 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4011 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4012 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
4013 { "DD1 MIXR", NULL, "dac mono3 right filter" },
4014 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4015
4016 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4017 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4018 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4019 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
4020 { "DD2 MIXL", NULL, "dac mono4 left filter" },
4021 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4022 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4023 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4024 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4025 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
4026 { "DD2 MIXR", NULL, "dac mono4 right filter" },
4027 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4028
4029 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4030 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4031 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4032 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4033 { "DD1 MIX", NULL, "DD1 MIXL" },
4034 { "DD1 MIX", NULL, "DD1 MIXR" },
4035 { "DD2 MIX", NULL, "DD2 MIXL" },
4036 { "DD2 MIX", NULL, "DD2 MIXR" },
4037
4038 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4039 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4040 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4041 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4042
4043 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4044 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4045 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4046 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4047
4048 { "DAC 1", NULL, "DAC12 SRC Mux" },
4049 { "DAC 2", NULL, "DAC12 SRC Mux" },
4050 { "DAC 3", NULL, "DAC3 SRC Mux" },
4051
4052 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4053 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4054 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4055 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4056 { "PDM1 L Mux", NULL, "PDM1 Power" },
4057 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4058 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4059 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4060 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4061 { "PDM1 R Mux", NULL, "PDM1 Power" },
4062 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4063 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4064 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4065 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4066 { "PDM2 L Mux", NULL, "PDM2 Power" },
4067 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4068 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4069 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4070 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4071 { "PDM2 R Mux", NULL, "PDM2 Power" },
4072
4073 { "LOUT1 amp", NULL, "DAC 1" },
4074 { "LOUT2 amp", NULL, "DAC 2" },
4075 { "LOUT3 amp", NULL, "DAC 3" },
4076
4077 { "LOUT1 vref", NULL, "LOUT1 amp" },
4078 { "LOUT2 vref", NULL, "LOUT2 amp" },
4079 { "LOUT3 vref", NULL, "LOUT3 amp" },
4080
4081 { "LOUT1", NULL, "LOUT1 vref" },
4082 { "LOUT2", NULL, "LOUT2 vref" },
4083 { "LOUT3", NULL, "LOUT3 vref" },
4084
4085 { "PDM1L", NULL, "PDM1 L Mux" },
4086 { "PDM1R", NULL, "PDM1 R Mux" },
4087 { "PDM2L", NULL, "PDM2 L Mux" },
4088 { "PDM2R", NULL, "PDM2 R Mux" },
4089 };
4090
4091 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4092 { "DMIC L2", NULL, "DMIC1 power" },
4093 { "DMIC R2", NULL, "DMIC1 power" },
4094 };
4095
4096 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4097 { "DMIC L2", NULL, "DMIC2 power" },
4098 { "DMIC R2", NULL, "DMIC2 power" },
4099 };
4100
4101 static int rt5677_hw_params(struct snd_pcm_substream *substream,
4102 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4103 {
4104 struct snd_soc_component *component = dai->component;
4105 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4106 unsigned int val_len = 0, val_clk, mask_clk;
4107 int pre_div, bclk_ms, frame_size;
4108
4109 rt5677->lrck[dai->id] = params_rate(params);
4110 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4111 if (pre_div < 0) {
4112 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4113 rt5677->sysclk, rt5677->lrck[dai->id]);
4114 return -EINVAL;
4115 }
4116 frame_size = snd_soc_params_to_frame_size(params);
4117 if (frame_size < 0) {
4118 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
4119 return -EINVAL;
4120 }
4121 bclk_ms = frame_size > 32;
4122 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4123
4124 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4125 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4126 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4127 bclk_ms, pre_div, dai->id);
4128
4129 switch (params_width(params)) {
4130 case 16:
4131 break;
4132 case 20:
4133 val_len |= RT5677_I2S_DL_20;
4134 break;
4135 case 24:
4136 val_len |= RT5677_I2S_DL_24;
4137 break;
4138 case 8:
4139 val_len |= RT5677_I2S_DL_8;
4140 break;
4141 default:
4142 return -EINVAL;
4143 }
4144
4145 switch (dai->id) {
4146 case RT5677_AIF1:
4147 mask_clk = RT5677_I2S_PD1_MASK;
4148 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4149 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4150 RT5677_I2S_DL_MASK, val_len);
4151 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4152 mask_clk, val_clk);
4153 break;
4154 case RT5677_AIF2:
4155 mask_clk = RT5677_I2S_PD2_MASK;
4156 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4157 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4158 RT5677_I2S_DL_MASK, val_len);
4159 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4160 mask_clk, val_clk);
4161 break;
4162 case RT5677_AIF3:
4163 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4164 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4165 pre_div << RT5677_I2S_PD3_SFT;
4166 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4167 RT5677_I2S_DL_MASK, val_len);
4168 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4169 mask_clk, val_clk);
4170 break;
4171 case RT5677_AIF4:
4172 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4173 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4174 pre_div << RT5677_I2S_PD4_SFT;
4175 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4176 RT5677_I2S_DL_MASK, val_len);
4177 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4178 mask_clk, val_clk);
4179 break;
4180 default:
4181 break;
4182 }
4183
4184 return 0;
4185 }
4186
4187 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4188 {
4189 struct snd_soc_component *component = dai->component;
4190 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4191 unsigned int reg_val = 0;
4192
4193 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4194 case SND_SOC_DAIFMT_CBM_CFM:
4195 rt5677->master[dai->id] = 1;
4196 break;
4197 case SND_SOC_DAIFMT_CBS_CFS:
4198 reg_val |= RT5677_I2S_MS_S;
4199 rt5677->master[dai->id] = 0;
4200 break;
4201 default:
4202 return -EINVAL;
4203 }
4204
4205 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4206 case SND_SOC_DAIFMT_NB_NF:
4207 break;
4208 case SND_SOC_DAIFMT_IB_NF:
4209 reg_val |= RT5677_I2S_BP_INV;
4210 break;
4211 default:
4212 return -EINVAL;
4213 }
4214
4215 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4216 case SND_SOC_DAIFMT_I2S:
4217 break;
4218 case SND_SOC_DAIFMT_LEFT_J:
4219 reg_val |= RT5677_I2S_DF_LEFT;
4220 break;
4221 case SND_SOC_DAIFMT_DSP_A:
4222 reg_val |= RT5677_I2S_DF_PCM_A;
4223 break;
4224 case SND_SOC_DAIFMT_DSP_B:
4225 reg_val |= RT5677_I2S_DF_PCM_B;
4226 break;
4227 default:
4228 return -EINVAL;
4229 }
4230
4231 switch (dai->id) {
4232 case RT5677_AIF1:
4233 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4234 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4235 RT5677_I2S_DF_MASK, reg_val);
4236 break;
4237 case RT5677_AIF2:
4238 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4239 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4240 RT5677_I2S_DF_MASK, reg_val);
4241 break;
4242 case RT5677_AIF3:
4243 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4244 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4245 RT5677_I2S_DF_MASK, reg_val);
4246 break;
4247 case RT5677_AIF4:
4248 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4249 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4250 RT5677_I2S_DF_MASK, reg_val);
4251 break;
4252 default:
4253 break;
4254 }
4255
4256
4257 return 0;
4258 }
4259
4260 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4261 int clk_id, unsigned int freq, int dir)
4262 {
4263 struct snd_soc_component *component = dai->component;
4264 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4265 unsigned int reg_val = 0;
4266
4267 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4268 return 0;
4269
4270 switch (clk_id) {
4271 case RT5677_SCLK_S_MCLK:
4272 reg_val |= RT5677_SCLK_SRC_MCLK;
4273 break;
4274 case RT5677_SCLK_S_PLL1:
4275 reg_val |= RT5677_SCLK_SRC_PLL1;
4276 break;
4277 case RT5677_SCLK_S_RCCLK:
4278 reg_val |= RT5677_SCLK_SRC_RCCLK;
4279 break;
4280 default:
4281 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
4282 return -EINVAL;
4283 }
4284 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4285 RT5677_SCLK_SRC_MASK, reg_val);
4286 rt5677->sysclk = freq;
4287 rt5677->sysclk_src = clk_id;
4288
4289 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4290
4291 return 0;
4292 }
4293
4294 /**
4295 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4296 * @freq_in: external clock provided to codec.
4297 * @freq_out: target clock which codec works on.
4298 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4299 *
4300 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4301 *
4302 * Returns 0 for success or negative error code.
4303 */
4304 static int rt5677_pll_calc(const unsigned int freq_in,
4305 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4306 {
4307 if (RT5677_PLL_INP_MIN > freq_in)
4308 return -EINVAL;
4309
4310 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4311 }
4312
4313 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4314 unsigned int freq_in, unsigned int freq_out)
4315 {
4316 struct snd_soc_component *component = dai->component;
4317 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4318 struct rl6231_pll_code pll_code;
4319 int ret;
4320
4321 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4322 freq_out == rt5677->pll_out)
4323 return 0;
4324
4325 if (!freq_in || !freq_out) {
4326 dev_dbg(component->dev, "PLL disabled\n");
4327
4328 rt5677->pll_in = 0;
4329 rt5677->pll_out = 0;
4330 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4331 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4332 return 0;
4333 }
4334
4335 switch (source) {
4336 case RT5677_PLL1_S_MCLK:
4337 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4338 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4339 break;
4340 case RT5677_PLL1_S_BCLK1:
4341 case RT5677_PLL1_S_BCLK2:
4342 case RT5677_PLL1_S_BCLK3:
4343 case RT5677_PLL1_S_BCLK4:
4344 switch (dai->id) {
4345 case RT5677_AIF1:
4346 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4347 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4348 break;
4349 case RT5677_AIF2:
4350 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4351 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4352 break;
4353 case RT5677_AIF3:
4354 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4355 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4356 break;
4357 case RT5677_AIF4:
4358 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4359 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4360 break;
4361 default:
4362 break;
4363 }
4364 break;
4365 default:
4366 dev_err(component->dev, "Unknown PLL source %d\n", source);
4367 return -EINVAL;
4368 }
4369
4370 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4371 if (ret < 0) {
4372 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
4373 return ret;
4374 }
4375
4376 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4377 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4378 pll_code.n_code, pll_code.k_code);
4379
4380 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4381 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4382 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4383 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4384 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4385
4386 rt5677->pll_in = freq_in;
4387 rt5677->pll_out = freq_out;
4388 rt5677->pll_src = source;
4389
4390 return 0;
4391 }
4392
4393 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4394 unsigned int rx_mask, int slots, int slot_width)
4395 {
4396 struct snd_soc_component *component = dai->component;
4397 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4398 unsigned int val = 0, slot_width_25 = 0;
4399
4400 if (rx_mask || tx_mask)
4401 val |= (1 << 12);
4402
4403 switch (slots) {
4404 case 4:
4405 val |= (1 << 10);
4406 break;
4407 case 6:
4408 val |= (2 << 10);
4409 break;
4410 case 8:
4411 val |= (3 << 10);
4412 break;
4413 case 2:
4414 default:
4415 break;
4416 }
4417
4418 switch (slot_width) {
4419 case 20:
4420 val |= (1 << 8);
4421 break;
4422 case 25:
4423 slot_width_25 = 0x8080;
4424 /* fall through */
4425 case 24:
4426 val |= (2 << 8);
4427 break;
4428 case 32:
4429 val |= (3 << 8);
4430 break;
4431 case 16:
4432 default:
4433 break;
4434 }
4435
4436 switch (dai->id) {
4437 case RT5677_AIF1:
4438 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4439 val);
4440 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4441 slot_width_25);
4442 break;
4443 case RT5677_AIF2:
4444 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4445 val);
4446 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4447 slot_width_25);
4448 break;
4449 default:
4450 break;
4451 }
4452
4453 return 0;
4454 }
4455
4456 static int rt5677_set_bias_level(struct snd_soc_component *component,
4457 enum snd_soc_bias_level level)
4458 {
4459 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4460
4461 switch (level) {
4462 case SND_SOC_BIAS_ON:
4463 break;
4464
4465 case SND_SOC_BIAS_PREPARE:
4466 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
4467 rt5677_set_dsp_vad(component, false);
4468
4469 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4470 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4471 5 << RT5677_LDO1_SEL_SFT |
4472 5 << RT5677_LDO2_SEL_SFT);
4473 regmap_update_bits(rt5677->regmap,
4474 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4475 0x0f00, 0x0f00);
4476 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4477 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4478 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4479 RT5677_PWR_BG | RT5677_PWR_VREF2,
4480 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4481 RT5677_PWR_BG | RT5677_PWR_VREF2);
4482 rt5677->is_vref_slow = false;
4483 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4484 RT5677_PWR_CORE, RT5677_PWR_CORE);
4485 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4486 0x1, 0x1);
4487 }
4488 break;
4489
4490 case SND_SOC_BIAS_STANDBY:
4491 break;
4492
4493 case SND_SOC_BIAS_OFF:
4494 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4495 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4496 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1,
4497 2 << RT5677_LDO1_SEL_SFT |
4498 2 << RT5677_LDO2_SEL_SFT);
4499 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4500 RT5677_PWR_CORE, 0);
4501 regmap_update_bits(rt5677->regmap,
4502 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4503
4504 if (rt5677->dsp_vad_en)
4505 rt5677_set_dsp_vad(component, true);
4506 break;
4507
4508 default:
4509 break;
4510 }
4511
4512 return 0;
4513 }
4514
4515 #ifdef CONFIG_GPIOLIB
4516 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4517 {
4518 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4519
4520 switch (offset) {
4521 case RT5677_GPIO1 ... RT5677_GPIO5:
4522 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4523 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4524 break;
4525
4526 case RT5677_GPIO6:
4527 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4528 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4529 break;
4530
4531 default:
4532 break;
4533 }
4534 }
4535
4536 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4537 unsigned offset, int value)
4538 {
4539 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4540
4541 switch (offset) {
4542 case RT5677_GPIO1 ... RT5677_GPIO5:
4543 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4544 0x3 << (offset * 3 + 1),
4545 (0x2 | !!value) << (offset * 3 + 1));
4546 break;
4547
4548 case RT5677_GPIO6:
4549 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4550 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4551 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4552 break;
4553
4554 default:
4555 break;
4556 }
4557
4558 return 0;
4559 }
4560
4561 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4562 {
4563 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4564 int value, ret;
4565
4566 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4567 if (ret < 0)
4568 return ret;
4569
4570 return (value & (0x1 << offset)) >> offset;
4571 }
4572
4573 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4574 {
4575 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4576
4577 switch (offset) {
4578 case RT5677_GPIO1 ... RT5677_GPIO5:
4579 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4580 0x1 << (offset * 3 + 2), 0x0);
4581 break;
4582
4583 case RT5677_GPIO6:
4584 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4585 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4586 break;
4587
4588 default:
4589 break;
4590 }
4591
4592 return 0;
4593 }
4594
4595 /** Configures the gpio as
4596 * 0 - floating
4597 * 1 - pull down
4598 * 2 - pull up
4599 */
4600 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4601 int value)
4602 {
4603 int shift;
4604
4605 switch (offset) {
4606 case RT5677_GPIO1 ... RT5677_GPIO2:
4607 shift = 2 * (1 - offset);
4608 regmap_update_bits(rt5677->regmap,
4609 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4610 0x3 << shift,
4611 (value & 0x3) << shift);
4612 break;
4613
4614 case RT5677_GPIO3 ... RT5677_GPIO6:
4615 shift = 2 * (9 - offset);
4616 regmap_update_bits(rt5677->regmap,
4617 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4618 0x3 << shift,
4619 (value & 0x3) << shift);
4620 break;
4621
4622 default:
4623 break;
4624 }
4625 }
4626
4627 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4628 {
4629 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4630 int irq;
4631
4632 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4633 (rt5677->pdata.jd1_gpio == 2 &&
4634 offset == RT5677_GPIO2) ||
4635 (rt5677->pdata.jd1_gpio == 3 &&
4636 offset == RT5677_GPIO3)) {
4637 irq = RT5677_IRQ_JD1;
4638 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4639 (rt5677->pdata.jd2_gpio == 2 &&
4640 offset == RT5677_GPIO5) ||
4641 (rt5677->pdata.jd2_gpio == 3 &&
4642 offset == RT5677_GPIO6)) {
4643 irq = RT5677_IRQ_JD2;
4644 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4645 offset == RT5677_GPIO4) ||
4646 (rt5677->pdata.jd3_gpio == 2 &&
4647 offset == RT5677_GPIO5) ||
4648 (rt5677->pdata.jd3_gpio == 3 &&
4649 offset == RT5677_GPIO6)) {
4650 irq = RT5677_IRQ_JD3;
4651 } else {
4652 return -ENXIO;
4653 }
4654
4655 return irq_create_mapping(rt5677->domain, irq);
4656 }
4657
4658 static const struct gpio_chip rt5677_template_chip = {
4659 .label = RT5677_DRV_NAME,
4660 .owner = THIS_MODULE,
4661 .direction_output = rt5677_gpio_direction_out,
4662 .set = rt5677_gpio_set,
4663 .direction_input = rt5677_gpio_direction_in,
4664 .get = rt5677_gpio_get,
4665 .to_irq = rt5677_to_irq,
4666 .can_sleep = 1,
4667 };
4668
4669 static void rt5677_init_gpio(struct i2c_client *i2c)
4670 {
4671 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4672 int ret;
4673
4674 rt5677->gpio_chip = rt5677_template_chip;
4675 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4676 rt5677->gpio_chip.parent = &i2c->dev;
4677 rt5677->gpio_chip.base = -1;
4678
4679 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
4680 if (ret != 0)
4681 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4682 }
4683
4684 static void rt5677_free_gpio(struct i2c_client *i2c)
4685 {
4686 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4687
4688 gpiochip_remove(&rt5677->gpio_chip);
4689 }
4690 #else
4691 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4692 int value)
4693 {
4694 }
4695
4696 static void rt5677_init_gpio(struct i2c_client *i2c)
4697 {
4698 }
4699
4700 static void rt5677_free_gpio(struct i2c_client *i2c)
4701 {
4702 }
4703 #endif
4704
4705 static int rt5677_probe(struct snd_soc_component *component)
4706 {
4707 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
4708 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4709 int i;
4710
4711 rt5677->component = component;
4712
4713 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4714 snd_soc_dapm_add_routes(dapm,
4715 rt5677_dmic2_clk_2,
4716 ARRAY_SIZE(rt5677_dmic2_clk_2));
4717 } else { /*use dmic1 clock by default*/
4718 snd_soc_dapm_add_routes(dapm,
4719 rt5677_dmic2_clk_1,
4720 ARRAY_SIZE(rt5677_dmic2_clk_1));
4721 }
4722
4723 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
4724
4725 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4726 ~RT5677_IRQ_DEBOUNCE_SEL_MASK, 0x0020);
4727 regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
4728 RT5677_PWR_SLIM_ISO | RT5677_PWR_CORE_ISO);
4729
4730 for (i = 0; i < RT5677_GPIO_NUM; i++)
4731 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4732
4733 mutex_init(&rt5677->dsp_cmd_lock);
4734 mutex_init(&rt5677->dsp_pri_lock);
4735
4736 return 0;
4737 }
4738
4739 static void rt5677_remove(struct snd_soc_component *component)
4740 {
4741 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4742
4743 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4744 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4745 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4746 }
4747
4748 #ifdef CONFIG_PM
4749 static int rt5677_suspend(struct snd_soc_component *component)
4750 {
4751 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4752
4753 if (!rt5677->dsp_vad_en) {
4754 regcache_cache_only(rt5677->regmap, true);
4755 regcache_mark_dirty(rt5677->regmap);
4756
4757 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4758 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4759 }
4760
4761 return 0;
4762 }
4763
4764 static int rt5677_resume(struct snd_soc_component *component)
4765 {
4766 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4767
4768 if (!rt5677->dsp_vad_en) {
4769 rt5677->pll_src = 0;
4770 rt5677->pll_in = 0;
4771 rt5677->pll_out = 0;
4772 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4773 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4774 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4775 msleep(10);
4776
4777 regcache_cache_only(rt5677->regmap, false);
4778 regcache_sync(rt5677->regmap);
4779 }
4780
4781 return 0;
4782 }
4783 #else
4784 #define rt5677_suspend NULL
4785 #define rt5677_resume NULL
4786 #endif
4787
4788 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4789 {
4790 struct i2c_client *client = context;
4791 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4792
4793 if (rt5677->is_dsp_mode) {
4794 if (reg > 0xff) {
4795 mutex_lock(&rt5677->dsp_pri_lock);
4796 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4797 reg & 0xff);
4798 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4799 mutex_unlock(&rt5677->dsp_pri_lock);
4800 } else {
4801 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4802 }
4803 } else {
4804 regmap_read(rt5677->regmap_physical, reg, val);
4805 }
4806
4807 return 0;
4808 }
4809
4810 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4811 {
4812 struct i2c_client *client = context;
4813 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4814
4815 if (rt5677->is_dsp_mode) {
4816 if (reg > 0xff) {
4817 mutex_lock(&rt5677->dsp_pri_lock);
4818 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4819 reg & 0xff);
4820 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4821 val);
4822 mutex_unlock(&rt5677->dsp_pri_lock);
4823 } else {
4824 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4825 }
4826 } else {
4827 regmap_write(rt5677->regmap_physical, reg, val);
4828 }
4829
4830 return 0;
4831 }
4832
4833 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4834 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4835 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4836
4837 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4838 .hw_params = rt5677_hw_params,
4839 .set_fmt = rt5677_set_dai_fmt,
4840 .set_sysclk = rt5677_set_dai_sysclk,
4841 .set_pll = rt5677_set_dai_pll,
4842 .set_tdm_slot = rt5677_set_tdm_slot,
4843 };
4844
4845 static struct snd_soc_dai_driver rt5677_dai[] = {
4846 {
4847 .name = "rt5677-aif1",
4848 .id = RT5677_AIF1,
4849 .playback = {
4850 .stream_name = "AIF1 Playback",
4851 .channels_min = 1,
4852 .channels_max = 2,
4853 .rates = RT5677_STEREO_RATES,
4854 .formats = RT5677_FORMATS,
4855 },
4856 .capture = {
4857 .stream_name = "AIF1 Capture",
4858 .channels_min = 1,
4859 .channels_max = 2,
4860 .rates = RT5677_STEREO_RATES,
4861 .formats = RT5677_FORMATS,
4862 },
4863 .ops = &rt5677_aif_dai_ops,
4864 },
4865 {
4866 .name = "rt5677-aif2",
4867 .id = RT5677_AIF2,
4868 .playback = {
4869 .stream_name = "AIF2 Playback",
4870 .channels_min = 1,
4871 .channels_max = 2,
4872 .rates = RT5677_STEREO_RATES,
4873 .formats = RT5677_FORMATS,
4874 },
4875 .capture = {
4876 .stream_name = "AIF2 Capture",
4877 .channels_min = 1,
4878 .channels_max = 2,
4879 .rates = RT5677_STEREO_RATES,
4880 .formats = RT5677_FORMATS,
4881 },
4882 .ops = &rt5677_aif_dai_ops,
4883 },
4884 {
4885 .name = "rt5677-aif3",
4886 .id = RT5677_AIF3,
4887 .playback = {
4888 .stream_name = "AIF3 Playback",
4889 .channels_min = 1,
4890 .channels_max = 2,
4891 .rates = RT5677_STEREO_RATES,
4892 .formats = RT5677_FORMATS,
4893 },
4894 .capture = {
4895 .stream_name = "AIF3 Capture",
4896 .channels_min = 1,
4897 .channels_max = 2,
4898 .rates = RT5677_STEREO_RATES,
4899 .formats = RT5677_FORMATS,
4900 },
4901 .ops = &rt5677_aif_dai_ops,
4902 },
4903 {
4904 .name = "rt5677-aif4",
4905 .id = RT5677_AIF4,
4906 .playback = {
4907 .stream_name = "AIF4 Playback",
4908 .channels_min = 1,
4909 .channels_max = 2,
4910 .rates = RT5677_STEREO_RATES,
4911 .formats = RT5677_FORMATS,
4912 },
4913 .capture = {
4914 .stream_name = "AIF4 Capture",
4915 .channels_min = 1,
4916 .channels_max = 2,
4917 .rates = RT5677_STEREO_RATES,
4918 .formats = RT5677_FORMATS,
4919 },
4920 .ops = &rt5677_aif_dai_ops,
4921 },
4922 {
4923 .name = "rt5677-slimbus",
4924 .id = RT5677_AIF5,
4925 .playback = {
4926 .stream_name = "SLIMBus Playback",
4927 .channels_min = 1,
4928 .channels_max = 2,
4929 .rates = RT5677_STEREO_RATES,
4930 .formats = RT5677_FORMATS,
4931 },
4932 .capture = {
4933 .stream_name = "SLIMBus Capture",
4934 .channels_min = 1,
4935 .channels_max = 2,
4936 .rates = RT5677_STEREO_RATES,
4937 .formats = RT5677_FORMATS,
4938 },
4939 .ops = &rt5677_aif_dai_ops,
4940 },
4941 };
4942
4943 static const struct snd_soc_component_driver soc_component_dev_rt5677 = {
4944 .name = RT5677_DRV_NAME,
4945 .probe = rt5677_probe,
4946 .remove = rt5677_remove,
4947 .suspend = rt5677_suspend,
4948 .resume = rt5677_resume,
4949 .set_bias_level = rt5677_set_bias_level,
4950 .controls = rt5677_snd_controls,
4951 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4952 .dapm_widgets = rt5677_dapm_widgets,
4953 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4954 .dapm_routes = rt5677_dapm_routes,
4955 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4956 .use_pmdown_time = 1,
4957 .endianness = 1,
4958 .non_legacy_dai_naming = 1,
4959 };
4960
4961 static const struct regmap_config rt5677_regmap_physical = {
4962 .name = "physical",
4963 .reg_bits = 8,
4964 .val_bits = 16,
4965
4966 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4967 RT5677_PR_SPACING),
4968 .readable_reg = rt5677_readable_register,
4969
4970 .cache_type = REGCACHE_NONE,
4971 .ranges = rt5677_ranges,
4972 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4973 };
4974
4975 static const struct regmap_config rt5677_regmap = {
4976 .reg_bits = 8,
4977 .val_bits = 16,
4978
4979 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4980 RT5677_PR_SPACING),
4981
4982 .volatile_reg = rt5677_volatile_register,
4983 .readable_reg = rt5677_readable_register,
4984 .reg_read = rt5677_read,
4985 .reg_write = rt5677_write,
4986
4987 .cache_type = REGCACHE_RBTREE,
4988 .reg_defaults = rt5677_reg,
4989 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4990 .ranges = rt5677_ranges,
4991 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4992 };
4993
4994 static const struct of_device_id rt5677_of_match[] = {
4995 { .compatible = "realtek,rt5677", .data = (const void *)RT5677 },
4996 { }
4997 };
4998 MODULE_DEVICE_TABLE(of, rt5677_of_match);
4999
5000 static const struct acpi_device_id rt5677_acpi_match[] = {
5001 { "RT5677CE", RT5677 },
5002 { }
5003 };
5004 MODULE_DEVICE_TABLE(acpi, rt5677_acpi_match);
5005
5006 static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5007 struct device *dev)
5008 {
5009 u32 val;
5010
5011 rt5677->pdata.in1_diff =
5012 device_property_read_bool(dev, "IN1") ||
5013 device_property_read_bool(dev, "realtek,in1-differential");
5014
5015 rt5677->pdata.in2_diff =
5016 device_property_read_bool(dev, "IN2") ||
5017 device_property_read_bool(dev, "realtek,in2-differential");
5018
5019 rt5677->pdata.lout1_diff =
5020 device_property_read_bool(dev, "OUT1") ||
5021 device_property_read_bool(dev, "realtek,lout1-differential");
5022
5023 rt5677->pdata.lout2_diff =
5024 device_property_read_bool(dev, "OUT2") ||
5025 device_property_read_bool(dev, "realtek,lout2-differential");
5026
5027 rt5677->pdata.lout3_diff =
5028 device_property_read_bool(dev, "OUT3") ||
5029 device_property_read_bool(dev, "realtek,lout3-differential");
5030
5031 device_property_read_u8_array(dev, "realtek,gpio-config",
5032 rt5677->pdata.gpio_config,
5033 RT5677_GPIO_NUM);
5034
5035 if (!device_property_read_u32(dev, "DCLK", &val) ||
5036 !device_property_read_u32(dev, "realtek,dmic2_clk_pin", &val))
5037 rt5677->pdata.dmic2_clk_pin = val;
5038
5039 if (!device_property_read_u32(dev, "JD1", &val) ||
5040 !device_property_read_u32(dev, "realtek,jd1-gpio", &val))
5041 rt5677->pdata.jd1_gpio = val;
5042
5043 if (!device_property_read_u32(dev, "JD2", &val) ||
5044 !device_property_read_u32(dev, "realtek,jd2-gpio", &val))
5045 rt5677->pdata.jd2_gpio = val;
5046
5047 if (!device_property_read_u32(dev, "JD3", &val) ||
5048 !device_property_read_u32(dev, "realtek,jd3-gpio", &val))
5049 rt5677->pdata.jd3_gpio = val;
5050 }
5051
5052 struct rt5677_irq_desc {
5053 unsigned int enable_mask;
5054 unsigned int status_mask;
5055 unsigned int polarity_mask;
5056 };
5057
5058 static const struct rt5677_irq_desc rt5677_irq_descs[] = {
5059 [RT5677_IRQ_JD1] = {
5060 .enable_mask = RT5677_EN_IRQ_GPIO_JD1,
5061 .status_mask = RT5677_STA_GPIO_JD1,
5062 .polarity_mask = RT5677_INV_GPIO_JD1,
5063 },
5064 [RT5677_IRQ_JD2] = {
5065 .enable_mask = RT5677_EN_IRQ_GPIO_JD2,
5066 .status_mask = RT5677_STA_GPIO_JD2,
5067 .polarity_mask = RT5677_INV_GPIO_JD2,
5068 },
5069 [RT5677_IRQ_JD3] = {
5070 .enable_mask = RT5677_EN_IRQ_GPIO_JD3,
5071 .status_mask = RT5677_STA_GPIO_JD3,
5072 .polarity_mask = RT5677_INV_GPIO_JD3,
5073 },
5074 };
5075
5076 static irqreturn_t rt5677_irq(int unused, void *data)
5077 {
5078 struct rt5677_priv *rt5677 = data;
5079 int ret = 0, loop, i, reg_irq, virq;
5080 bool irq_fired = false;
5081
5082 mutex_lock(&rt5677->irq_lock);
5083
5084 /*
5085 * Loop to handle interrupts until the last i2c read shows no pending
5086 * irqs. The interrupt line is shared by multiple interrupt sources.
5087 * After the regmap_read() below, a new interrupt source line may
5088 * become high before the regmap_write() finishes, so there isn't a
5089 * rising edge on the shared interrupt line for the new interrupt. Thus,
5090 * the loop is needed to avoid missing irqs.
5091 *
5092 * A safeguard of 20 loops is used to avoid hanging in the irq handler
5093 * if there is something wrong with the interrupt status update. The
5094 * interrupt sources here are audio jack plug/unplug events which
5095 * shouldn't happen at a high frequency for a long period of time.
5096 * Empirically, more than 3 loops have never been seen.
5097 */
5098 for (loop = 0; loop < 20; loop++) {
5099 /* Read interrupt status */
5100 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, &reg_irq);
5101 if (ret) {
5102 dev_err(rt5677->dev, "failed reading IRQ status: %d\n",
5103 ret);
5104 goto exit;
5105 }
5106
5107 irq_fired = false;
5108 for (i = 0; i < RT5677_IRQ_NUM; i++) {
5109 if (reg_irq & rt5677_irq_descs[i].status_mask) {
5110 irq_fired = true;
5111 virq = irq_find_mapping(rt5677->domain, i);
5112 if (virq)
5113 handle_nested_irq(virq);
5114
5115 /* Clear the interrupt by flipping the polarity
5116 * of the interrupt source line that fired
5117 */
5118 reg_irq ^= rt5677_irq_descs[i].polarity_mask;
5119 }
5120 }
5121 if (!irq_fired)
5122 goto exit;
5123
5124 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq);
5125 if (ret) {
5126 dev_err(rt5677->dev, "failed updating IRQ status: %d\n",
5127 ret);
5128 goto exit;
5129 }
5130 }
5131 exit:
5132 mutex_unlock(&rt5677->irq_lock);
5133 if (irq_fired)
5134 return IRQ_HANDLED;
5135 else
5136 return IRQ_NONE;
5137 }
5138
5139 static void rt5677_irq_bus_lock(struct irq_data *data)
5140 {
5141 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5142
5143 mutex_lock(&rt5677->irq_lock);
5144 }
5145
5146 static void rt5677_irq_bus_sync_unlock(struct irq_data *data)
5147 {
5148 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5149
5150 // Set the enable/disable bits for the jack detect IRQs.
5151 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1,
5152 RT5677_EN_IRQ_GPIO_JD1 | RT5677_EN_IRQ_GPIO_JD2 |
5153 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en);
5154 mutex_unlock(&rt5677->irq_lock);
5155 }
5156
5157 static void rt5677_irq_enable(struct irq_data *data)
5158 {
5159 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5160
5161 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask;
5162 }
5163
5164 static void rt5677_irq_disable(struct irq_data *data)
5165 {
5166 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5167
5168 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask;
5169 }
5170
5171 static struct irq_chip rt5677_irq_chip = {
5172 .name = "rt5677_irq_chip",
5173 .irq_bus_lock = rt5677_irq_bus_lock,
5174 .irq_bus_sync_unlock = rt5677_irq_bus_sync_unlock,
5175 .irq_disable = rt5677_irq_disable,
5176 .irq_enable = rt5677_irq_enable,
5177 };
5178
5179 static int rt5677_irq_map(struct irq_domain *h, unsigned int virq,
5180 irq_hw_number_t hw)
5181 {
5182 struct rt5677_priv *rt5677 = h->host_data;
5183
5184 irq_set_chip_data(virq, rt5677);
5185 irq_set_chip(virq, &rt5677_irq_chip);
5186 irq_set_nested_thread(virq, 1);
5187 irq_set_noprobe(virq);
5188 return 0;
5189 }
5190
5191
5192 static const struct irq_domain_ops rt5677_domain_ops = {
5193 .map = rt5677_irq_map,
5194 .xlate = irq_domain_xlate_twocell,
5195 };
5196
5197 static int rt5677_init_irq(struct i2c_client *i2c)
5198 {
5199 int ret;
5200 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5201 unsigned int jd_mask = 0, jd_val = 0;
5202
5203 if (!rt5677->pdata.jd1_gpio &&
5204 !rt5677->pdata.jd2_gpio &&
5205 !rt5677->pdata.jd3_gpio)
5206 return 0;
5207
5208 if (!i2c->irq) {
5209 dev_err(&i2c->dev, "No interrupt specified\n");
5210 return -EINVAL;
5211 }
5212
5213 mutex_init(&rt5677->irq_lock);
5214
5215 /*
5216 * Select RC as the debounce clock so that GPIO works even when
5217 * MCLK is gated which happens when there is no audio stream
5218 * (SND_SOC_BIAS_OFF).
5219 */
5220 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
5221 RT5677_IRQ_DEBOUNCE_SEL_MASK,
5222 RT5677_IRQ_DEBOUNCE_SEL_RC);
5223 /* Enable auto power on RC when GPIO states are changed */
5224 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff);
5225
5226 /* Select and enable jack detection sources per platform data */
5227 if (rt5677->pdata.jd1_gpio) {
5228 jd_mask |= RT5677_SEL_GPIO_JD1_MASK;
5229 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT;
5230 }
5231 if (rt5677->pdata.jd2_gpio) {
5232 jd_mask |= RT5677_SEL_GPIO_JD2_MASK;
5233 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT;
5234 }
5235 if (rt5677->pdata.jd3_gpio) {
5236 jd_mask |= RT5677_SEL_GPIO_JD3_MASK;
5237 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT;
5238 }
5239 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val);
5240
5241 /* Set GPIO1 pin to be IRQ output */
5242 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
5243 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);
5244
5245 /* Ready to listen for interrupts */
5246 rt5677->domain = irq_domain_add_linear(i2c->dev.of_node,
5247 RT5677_IRQ_NUM, &rt5677_domain_ops, rt5677);
5248 if (!rt5677->domain) {
5249 dev_err(&i2c->dev, "Failed to create IRQ domain\n");
5250 return -ENOMEM;
5251 }
5252
5253 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq,
5254 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
5255 "rt5677", rt5677);
5256 if (ret)
5257 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
5258
5259 return ret;
5260 }
5261
5262 static int rt5677_i2c_probe(struct i2c_client *i2c)
5263 {
5264 struct rt5677_priv *rt5677;
5265 int ret;
5266 unsigned int val;
5267
5268 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5269 GFP_KERNEL);
5270 if (rt5677 == NULL)
5271 return -ENOMEM;
5272
5273 rt5677->dev = &i2c->dev;
5274 i2c_set_clientdata(i2c, rt5677);
5275
5276 if (i2c->dev.of_node) {
5277 const struct of_device_id *match_id;
5278
5279 match_id = of_match_device(rt5677_of_match, &i2c->dev);
5280 if (match_id)
5281 rt5677->type = (enum rt5677_type)match_id->data;
5282 } else if (ACPI_HANDLE(&i2c->dev)) {
5283 const struct acpi_device_id *acpi_id;
5284
5285 acpi_id = acpi_match_device(rt5677_acpi_match, &i2c->dev);
5286 if (acpi_id)
5287 rt5677->type = (enum rt5677_type)acpi_id->driver_data;
5288 } else {
5289 return -EINVAL;
5290 }
5291
5292 rt5677_read_device_properties(rt5677, &i2c->dev);
5293
5294 /* pow-ldo2 and reset are optional. The codec pins may be statically
5295 * connected on the board without gpios. If the gpio device property
5296 * isn't specified, devm_gpiod_get_optional returns NULL.
5297 */
5298 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5299 "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5300 if (IS_ERR(rt5677->pow_ldo2)) {
5301 ret = PTR_ERR(rt5677->pow_ldo2);
5302 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
5303 return ret;
5304 }
5305 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5306 "realtek,reset", GPIOD_OUT_LOW);
5307 if (IS_ERR(rt5677->reset_pin)) {
5308 ret = PTR_ERR(rt5677->reset_pin);
5309 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
5310 return ret;
5311 }
5312
5313 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5314 /* Wait a while until I2C bus becomes available. The datasheet
5315 * does not specify the exact we should wait but startup
5316 * sequence mentiones at least a few milliseconds.
5317 */
5318 msleep(10);
5319 }
5320
5321 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5322 &rt5677_regmap_physical);
5323 if (IS_ERR(rt5677->regmap_physical)) {
5324 ret = PTR_ERR(rt5677->regmap_physical);
5325 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5326 ret);
5327 return ret;
5328 }
5329
5330 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5331 if (IS_ERR(rt5677->regmap)) {
5332 ret = PTR_ERR(rt5677->regmap);
5333 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5334 ret);
5335 return ret;
5336 }
5337
5338 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5339 if (val != RT5677_DEVICE_ID) {
5340 dev_err(&i2c->dev,
5341 "Device with ID register %#x is not rt5677\n", val);
5342 return -ENODEV;
5343 }
5344
5345 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5346
5347 ret = regmap_register_patch(rt5677->regmap, init_list,
5348 ARRAY_SIZE(init_list));
5349 if (ret != 0)
5350 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5351
5352 if (rt5677->pdata.in1_diff)
5353 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5354 RT5677_IN_DF1, RT5677_IN_DF1);
5355
5356 if (rt5677->pdata.in2_diff)
5357 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5358 RT5677_IN_DF2, RT5677_IN_DF2);
5359
5360 if (rt5677->pdata.lout1_diff)
5361 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5362 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5363
5364 if (rt5677->pdata.lout2_diff)
5365 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5366 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5367
5368 if (rt5677->pdata.lout3_diff)
5369 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5370 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5371
5372 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5373 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5374 RT5677_GPIO5_FUNC_MASK,
5375 RT5677_GPIO5_FUNC_DMIC);
5376 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5377 RT5677_GPIO5_DIR_MASK,
5378 RT5677_GPIO5_DIR_OUT);
5379 }
5380
5381 if (rt5677->pdata.micbias1_vdd_3v3)
5382 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5383 RT5677_MICBIAS1_CTRL_VDD_MASK,
5384 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5385
5386 rt5677_init_gpio(i2c);
5387 ret = rt5677_init_irq(i2c);
5388 if (ret)
5389 dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret);
5390
5391 return devm_snd_soc_register_component(&i2c->dev,
5392 &soc_component_dev_rt5677,
5393 rt5677_dai, ARRAY_SIZE(rt5677_dai));
5394 }
5395
5396 static int rt5677_i2c_remove(struct i2c_client *i2c)
5397 {
5398 rt5677_free_gpio(i2c);
5399
5400 return 0;
5401 }
5402
5403 static struct i2c_driver rt5677_i2c_driver = {
5404 .driver = {
5405 .name = RT5677_DRV_NAME,
5406 .of_match_table = rt5677_of_match,
5407 .acpi_match_table = ACPI_PTR(rt5677_acpi_match),
5408 },
5409 .probe_new = rt5677_i2c_probe,
5410 .remove = rt5677_i2c_remove,
5411 };
5412 module_i2c_driver(rt5677_i2c_driver);
5413
5414 MODULE_DESCRIPTION("ASoC RT5677 driver");
5415 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5416 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support