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USB: idmouse: fix interface sanity checks
[linux/fpc-iii.git] / sound / soc / codecs / tlv320aic31xx.c
blobdf627a08def95d459f775d7983780a22f3cd820f
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ALSA SoC TLV320AIC31xx CODEC Driver
4 *
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
6 * Jyri Sarha <jsarha@ti.com>
7 *
8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
9 *
10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated
11 * high performance codecs which provides a stereo DAC, a mono ADC,
12 * and mono/stereo Class-D speaker driver.
13 */
14
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/pm.h>
20 #include <linux/i2c.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/acpi.h>
24 #include <linux/of.h>
25 #include <linux/of_gpio.h>
26 #include <linux/slab.h>
27 #include <sound/core.h>
28 #include <sound/jack.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/initval.h>
33 #include <sound/tlv.h>
34 #include <dt-bindings/sound/tlv320aic31xx-micbias.h>
35
36 #include "tlv320aic31xx.h"
37
38 static const struct reg_default aic31xx_reg_defaults[] = {
39 { AIC31XX_CLKMUX, 0x00 },
40 { AIC31XX_PLLPR, 0x11 },
41 { AIC31XX_PLLJ, 0x04 },
42 { AIC31XX_PLLDMSB, 0x00 },
43 { AIC31XX_PLLDLSB, 0x00 },
44 { AIC31XX_NDAC, 0x01 },
45 { AIC31XX_MDAC, 0x01 },
46 { AIC31XX_DOSRMSB, 0x00 },
47 { AIC31XX_DOSRLSB, 0x80 },
48 { AIC31XX_NADC, 0x01 },
49 { AIC31XX_MADC, 0x01 },
50 { AIC31XX_AOSR, 0x80 },
51 { AIC31XX_IFACE1, 0x00 },
52 { AIC31XX_DATA_OFFSET, 0x00 },
53 { AIC31XX_IFACE2, 0x00 },
54 { AIC31XX_BCLKN, 0x01 },
55 { AIC31XX_DACSETUP, 0x14 },
56 { AIC31XX_DACMUTE, 0x0c },
57 { AIC31XX_LDACVOL, 0x00 },
58 { AIC31XX_RDACVOL, 0x00 },
59 { AIC31XX_ADCSETUP, 0x00 },
60 { AIC31XX_ADCFGA, 0x80 },
61 { AIC31XX_ADCVOL, 0x00 },
62 { AIC31XX_HPDRIVER, 0x04 },
63 { AIC31XX_SPKAMP, 0x06 },
64 { AIC31XX_DACMIXERROUTE, 0x00 },
65 { AIC31XX_LANALOGHPL, 0x7f },
66 { AIC31XX_RANALOGHPR, 0x7f },
67 { AIC31XX_LANALOGSPL, 0x7f },
68 { AIC31XX_RANALOGSPR, 0x7f },
69 { AIC31XX_HPLGAIN, 0x02 },
70 { AIC31XX_HPRGAIN, 0x02 },
71 { AIC31XX_SPLGAIN, 0x00 },
72 { AIC31XX_SPRGAIN, 0x00 },
73 { AIC31XX_MICBIAS, 0x00 },
74 { AIC31XX_MICPGA, 0x80 },
75 { AIC31XX_MICPGAPI, 0x00 },
76 { AIC31XX_MICPGAMI, 0x00 },
77 };
78
79 static bool aic31xx_volatile(struct device *dev, unsigned int reg)
80 {
81 switch (reg) {
82 case AIC31XX_PAGECTL: /* regmap implementation requires this */
83 case AIC31XX_RESET: /* always clears after write */
84 case AIC31XX_OT_FLAG:
85 case AIC31XX_ADCFLAG:
86 case AIC31XX_DACFLAG1:
87 case AIC31XX_DACFLAG2:
88 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
89 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
90 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
91 case AIC31XX_INTRDACFLAG2:
92 case AIC31XX_INTRADCFLAG2:
93 case AIC31XX_HSDETECT:
94 return true;
95 }
96 return false;
97 }
98
99 static bool aic31xx_writeable(struct device *dev, unsigned int reg)
100 {
101 switch (reg) {
102 case AIC31XX_OT_FLAG:
103 case AIC31XX_ADCFLAG:
104 case AIC31XX_DACFLAG1:
105 case AIC31XX_DACFLAG2:
106 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
107 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
108 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
109 case AIC31XX_INTRDACFLAG2:
110 case AIC31XX_INTRADCFLAG2:
111 return false;
112 }
113 return true;
114 }
115
116 static const struct regmap_range_cfg aic31xx_ranges[] = {
117 {
118 .range_min = 0,
119 .range_max = 12 * 128,
120 .selector_reg = AIC31XX_PAGECTL,
121 .selector_mask = 0xff,
122 .selector_shift = 0,
123 .window_start = 0,
124 .window_len = 128,
125 },
126 };
127
128 static const struct regmap_config aic31xx_i2c_regmap = {
129 .reg_bits = 8,
130 .val_bits = 8,
131 .writeable_reg = aic31xx_writeable,
132 .volatile_reg = aic31xx_volatile,
133 .reg_defaults = aic31xx_reg_defaults,
134 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),
135 .cache_type = REGCACHE_RBTREE,
136 .ranges = aic31xx_ranges,
137 .num_ranges = ARRAY_SIZE(aic31xx_ranges),
138 .max_register = 12 * 128,
139 };
140
141 static const char * const aic31xx_supply_names[] = {
142 "HPVDD",
143 "SPRVDD",
144 "SPLVDD",
145 "AVDD",
146 "IOVDD",
147 "DVDD",
148 };
149
150 #define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names)
151
152 struct aic31xx_disable_nb {
153 struct notifier_block nb;
154 struct aic31xx_priv *aic31xx;
155 };
156
157 struct aic31xx_priv {
158 struct snd_soc_component *component;
159 u8 i2c_regs_status;
160 struct device *dev;
161 struct regmap *regmap;
162 enum aic31xx_type codec_type;
163 struct gpio_desc *gpio_reset;
164 int micbias_vg;
165 struct aic31xx_pdata pdata;
166 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
167 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
168 struct snd_soc_jack *jack;
169 unsigned int sysclk;
170 u8 p_div;
171 int rate_div_line;
172 bool master_dapm_route_applied;
173 int irq;
174 };
175
176 struct aic31xx_rate_divs {
177 u32 mclk_p;
178 u32 rate;
179 u8 pll_j;
180 u16 pll_d;
181 u16 dosr;
182 u8 ndac;
183 u8 mdac;
184 u8 aosr;
185 u8 nadc;
186 u8 madc;
187 };
188
189 /* ADC dividers can be disabled by configuring them to 0 */
190 static const struct aic31xx_rate_divs aic31xx_divs[] = {
191 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */
192 /* 8k rate */
193 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2},
194 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3},
195 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2},
196 /* 11.025k rate */
197 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2},
198 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3},
199 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2},
200 /* 16k rate */
201 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2},
202 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3},
203 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2},
204 /* 22.05k rate */
205 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2},
206 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3},
207 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2},
208 /* 32k rate */
209 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2},
210 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3},
211 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2},
212 /* 44.1k rate */
213 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2},
214 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3},
215 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2},
216 /* 48k rate */
217 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2},
218 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4},
219 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2},
220 /* 88.2k rate */
221 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2},
222 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3},
223 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2},
224 /* 96k rate */
225 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2},
226 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4},
227 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2},
228 /* 176.4k rate */
229 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2},
230 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3},
231 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2},
232 /* 192k rate */
233 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2},
234 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4},
235 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2},
236 };
237
238 static const char * const ldac_in_text[] = {
239 "Off", "Left Data", "Right Data", "Mono"
240 };
241
242 static const char * const rdac_in_text[] = {
243 "Off", "Right Data", "Left Data", "Mono"
244 };
245
246 static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);
247
248 static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);
249
250 static const char * const mic_select_text[] = {
251 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
252 };
253
254 static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,
255 mic_select_text);
256 static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,
257 mic_select_text);
258 static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
259 mic_select_text);
260
261 static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
262 mic_select_text);
263
264 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
265 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
266 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
267 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
268 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
269 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
270 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
271 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
272
273 /*
274 * controls to be exported to the user space
275 */
276 static const struct snd_kcontrol_new common31xx_snd_controls[] = {
277 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,
278 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
279
280 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,
281 AIC31XX_HPRGAIN, 2, 1, 0),
282 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,
283 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
284
285 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
286 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
287 };
288
289 static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
290 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,
291 adc_fgain_tlv),
292
293 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),
294 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,
295 0, -24, 40, 6, 0, adc_cgain_tlv),
296
297 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
298 119, 0, mic_pga_tlv),
299 };
300
301 static const struct snd_kcontrol_new aic311x_snd_controls[] = {
302 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
303 AIC31XX_SPRGAIN, 2, 1, 0),
304 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
305 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
306
307 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
308 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
309 };
310
311 static const struct snd_kcontrol_new aic310x_snd_controls[] = {
312 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
313 2, 1, 0),
314 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
315 3, 3, 0, class_D_drv_tlv),
316
317 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
318 0, 0x7F, 1, sp_vol_tlv),
319 };
320
321 static const struct snd_kcontrol_new ldac_in_control =
322 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);
323
324 static const struct snd_kcontrol_new rdac_in_control =
325 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);
326
327 static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,
328 unsigned int mask, unsigned int wbits, int sleep,
329 int count)
330 {
331 unsigned int bits;
332 int counter = count;
333 int ret = regmap_read(aic31xx->regmap, reg, &bits);
334
335 while ((bits & mask) != wbits && counter && !ret) {
336 usleep_range(sleep, sleep * 2);
337 ret = regmap_read(aic31xx->regmap, reg, &bits);
338 counter--;
339 }
340 if ((bits & mask) != wbits) {
341 dev_err(aic31xx->dev,
342 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
343 __func__, reg, bits, wbits, ret, mask,
344 (count - counter) * sleep);
345 ret = -1;
346 }
347 return ret;
348 }
349
350 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
351
352 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
353 struct snd_kcontrol *kcontrol, int event)
354 {
355 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
356 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
357 unsigned int reg = AIC31XX_DACFLAG1;
358 unsigned int mask;
359
360 switch (WIDGET_BIT(w->reg, w->shift)) {
361 case WIDGET_BIT(AIC31XX_DACSETUP, 7):
362 mask = AIC31XX_LDACPWRSTATUS_MASK;
363 break;
364 case WIDGET_BIT(AIC31XX_DACSETUP, 6):
365 mask = AIC31XX_RDACPWRSTATUS_MASK;
366 break;
367 case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
368 mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
369 break;
370 case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
371 mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
372 break;
373 case WIDGET_BIT(AIC31XX_SPKAMP, 7):
374 mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
375 break;
376 case WIDGET_BIT(AIC31XX_SPKAMP, 6):
377 mask = AIC31XX_SPRDRVPWRSTATUS_MASK;
378 break;
379 case WIDGET_BIT(AIC31XX_ADCSETUP, 7):
380 mask = AIC31XX_ADCPWRSTATUS_MASK;
381 reg = AIC31XX_ADCFLAG;
382 break;
383 default:
384 dev_err(component->dev, "Unknown widget '%s' calling %s\n",
385 w->name, __func__);
386 return -EINVAL;
387 }
388
389 switch (event) {
390 case SND_SOC_DAPM_POST_PMU:
391 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100);
392 case SND_SOC_DAPM_POST_PMD:
393 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100);
394 default:
395 dev_dbg(component->dev,
396 "Unhandled dapm widget event %d from %s\n",
397 event, w->name);
398 }
399 return 0;
400 }
401
402 static const struct snd_kcontrol_new aic31xx_left_output_switches[] = {
403 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
404 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
405 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
406 };
407
408 static const struct snd_kcontrol_new aic31xx_right_output_switches[] = {
409 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
410 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
411 };
412
413 static const struct snd_kcontrol_new dac31xx_left_output_switches[] = {
414 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
415 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0),
416 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0),
417 };
418
419 static const struct snd_kcontrol_new dac31xx_right_output_switches[] = {
420 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
421 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0),
422 };
423
424 static const struct snd_kcontrol_new p_term_mic1lp =
425 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
426
427 static const struct snd_kcontrol_new p_term_mic1rp =
428 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
429
430 static const struct snd_kcontrol_new p_term_mic1lm =
431 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
432
433 static const struct snd_kcontrol_new m_term_mic1lm =
434 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
435
436 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =
437 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
438
439 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =
440 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
441
442 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =
443 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
444
445 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =
446 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
447
448 static int mic_bias_event(struct snd_soc_dapm_widget *w,
449 struct snd_kcontrol *kcontrol, int event)
450 {
451 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
452 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
453
454 switch (event) {
455 case SND_SOC_DAPM_POST_PMU:
456 /* change mic bias voltage to user defined */
457 snd_soc_component_update_bits(component, AIC31XX_MICBIAS,
458 AIC31XX_MICBIAS_MASK,
459 aic31xx->micbias_vg <<
460 AIC31XX_MICBIAS_SHIFT);
461 dev_dbg(component->dev, "%s: turned on\n", __func__);
462 break;
463 case SND_SOC_DAPM_PRE_PMD:
464 /* turn mic bias off */
465 snd_soc_component_update_bits(component, AIC31XX_MICBIAS,
466 AIC31XX_MICBIAS_MASK, 0);
467 dev_dbg(component->dev, "%s: turned off\n", __func__);
468 break;
469 }
470 return 0;
471 }
472
473 static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = {
474 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
475
476 SND_SOC_DAPM_MUX("DAC Left Input",
477 SND_SOC_NOPM, 0, 0, &ldac_in_control),
478 SND_SOC_DAPM_MUX("DAC Right Input",
479 SND_SOC_NOPM, 0, 0, &rdac_in_control),
480 /* DACs */
481 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
482 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
483 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
484
485 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
486 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
487 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
488
489 /* HP */
490 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
491 &aic31xx_dapm_hpl_switch),
492 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
493 &aic31xx_dapm_hpr_switch),
494
495 /* Output drivers */
496 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
497 NULL, 0, aic31xx_dapm_power_event,
498 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
499 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
500 NULL, 0, aic31xx_dapm_power_event,
501 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
502
503 /* Mic Bias */
504 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
505 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
506
507 /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */
508 SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0,
509 NULL, 0),
510
511 /* Outputs */
512 SND_SOC_DAPM_OUTPUT("HPL"),
513 SND_SOC_DAPM_OUTPUT("HPR"),
514 };
515
516 static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = {
517 /* Inputs */
518 SND_SOC_DAPM_INPUT("AIN1"),
519 SND_SOC_DAPM_INPUT("AIN2"),
520
521 /* Output Mixers */
522 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
523 dac31xx_left_output_switches,
524 ARRAY_SIZE(dac31xx_left_output_switches)),
525 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
526 dac31xx_right_output_switches,
527 ARRAY_SIZE(dac31xx_right_output_switches)),
528 };
529
530 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
531 /* Inputs */
532 SND_SOC_DAPM_INPUT("MIC1LP"),
533 SND_SOC_DAPM_INPUT("MIC1RP"),
534 SND_SOC_DAPM_INPUT("MIC1LM"),
535
536 /* Input Selection to MIC_PGA */
537 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
538 &p_term_mic1lp),
539 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
540 &p_term_mic1rp),
541 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
542 &p_term_mic1lm),
543
544 /* ADC */
545 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
546 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
547 SND_SOC_DAPM_POST_PMD),
548
549 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
550 &m_term_mic1lm),
551
552 /* Enabling & Disabling MIC Gain Ctl */
553 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,
554 7, 1, NULL, 0),
555
556 /* Output Mixers */
557 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
558 aic31xx_left_output_switches,
559 ARRAY_SIZE(aic31xx_left_output_switches)),
560 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
561 aic31xx_right_output_switches,
562 ARRAY_SIZE(aic31xx_right_output_switches)),
563
564 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
565 };
566
567 static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {
568 /* AIC3111 and AIC3110 have stereo class-D amplifier */
569 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
570 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
571 SND_SOC_DAPM_POST_PMD),
572 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
573 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
574 SND_SOC_DAPM_POST_PMD),
575 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
576 &aic31xx_dapm_spl_switch),
577 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
578 &aic31xx_dapm_spr_switch),
579 SND_SOC_DAPM_OUTPUT("SPL"),
580 SND_SOC_DAPM_OUTPUT("SPR"),
581 };
582
583 /* AIC3100 and AIC3120 have only mono class-D amplifier */
584 static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {
585 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
586 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
587 SND_SOC_DAPM_POST_PMD),
588 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
589 &aic31xx_dapm_spl_switch),
590 SND_SOC_DAPM_OUTPUT("SPK"),
591 };
592
593 static const struct snd_soc_dapm_route
594 common31xx_audio_map[] = {
595 /* DAC Input Routing */
596 {"DAC Left Input", "Left Data", "AIF IN"},
597 {"DAC Left Input", "Right Data", "AIF IN"},
598 {"DAC Left Input", "Mono", "AIF IN"},
599 {"DAC Right Input", "Left Data", "AIF IN"},
600 {"DAC Right Input", "Right Data", "AIF IN"},
601 {"DAC Right Input", "Mono", "AIF IN"},
602 {"DAC Left", NULL, "DAC Left Input"},
603 {"DAC Right", NULL, "DAC Right Input"},
604
605 /* HPL path */
606 {"HP Left", "Switch", "Output Left"},
607 {"HPL Driver", NULL, "HP Left"},
608 {"HPL", NULL, "HPL Driver"},
609
610 /* HPR path */
611 {"HP Right", "Switch", "Output Right"},
612 {"HPR Driver", NULL, "HP Right"},
613 {"HPR", NULL, "HPR Driver"},
614 };
615
616 static const struct snd_soc_dapm_route
617 dac31xx_audio_map[] = {
618 /* Left Output */
619 {"Output Left", "From Left DAC", "DAC Left"},
620 {"Output Left", "From AIN1", "AIN1"},
621 {"Output Left", "From AIN2", "AIN2"},
622
623 /* Right Output */
624 {"Output Right", "From Right DAC", "DAC Right"},
625 {"Output Right", "From AIN2", "AIN2"},
626 };
627
628 static const struct snd_soc_dapm_route
629 aic31xx_audio_map[] = {
630 /* Mic input */
631 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
632 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
633 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
634 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
635 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
636 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
637 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
638 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
639 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
640
641 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
642 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
643 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
644
645 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
646 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
647 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
648 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
649
650 {"ADC", NULL, "MIC_GAIN_CTL"},
651
652 {"AIF OUT", NULL, "ADC"},
653
654 /* Left Output */
655 {"Output Left", "From Left DAC", "DAC Left"},
656 {"Output Left", "From MIC1LP", "MIC1LP"},
657 {"Output Left", "From MIC1RP", "MIC1RP"},
658
659 /* Right Output */
660 {"Output Right", "From Right DAC", "DAC Right"},
661 {"Output Right", "From MIC1RP", "MIC1RP"},
662 };
663
664 static const struct snd_soc_dapm_route
665 aic311x_audio_map[] = {
666 /* SP L path */
667 {"Speaker Left", "Switch", "Output Left"},
668 {"SPL ClassD", NULL, "Speaker Left"},
669 {"SPL", NULL, "SPL ClassD"},
670
671 /* SP R path */
672 {"Speaker Right", "Switch", "Output Right"},
673 {"SPR ClassD", NULL, "Speaker Right"},
674 {"SPR", NULL, "SPR ClassD"},
675 };
676
677 static const struct snd_soc_dapm_route
678 aic310x_audio_map[] = {
679 /* SP L path */
680 {"Speaker", "Switch", "Output Left"},
681 {"SPK ClassD", NULL, "Speaker"},
682 {"SPK", NULL, "SPK ClassD"},
683 };
684
685 /*
686 * Always connected DAPM routes for codec clock master modes.
687 * If the codec is the master on the I2S bus, we need to power up components
688 * to have valid DAC_CLK.
689 *
690 * In order to have the I2S clocks on the bus either the DACs/ADC need to be
691 * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set.
692 *
693 * Otherwise the codec will not generate clocks on the bus.
694 */
695 static const struct snd_soc_dapm_route
696 common31xx_cm_audio_map[] = {
697 {"HPL", NULL, "AIF IN"},
698 {"HPR", NULL, "AIF IN"},
699
700 {"AIF IN", NULL, "Activate I2S clocks"},
701 };
702
703 static const struct snd_soc_dapm_route
704 aic31xx_cm_audio_map[] = {
705 {"AIF OUT", NULL, "MIC1LP"},
706 {"AIF OUT", NULL, "MIC1RP"},
707 {"AIF OUT", NULL, "MIC1LM"},
708
709 {"AIF OUT", NULL, "Activate I2S clocks"},
710 };
711
712 static int aic31xx_add_controls(struct snd_soc_component *component)
713 {
714 int ret = 0;
715 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
716
717 if (!(aic31xx->codec_type & DAC31XX_BIT))
718 ret = snd_soc_add_component_controls(
719 component, aic31xx_snd_controls,
720 ARRAY_SIZE(aic31xx_snd_controls));
721 if (ret)
722 return ret;
723
724 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT)
725 ret = snd_soc_add_component_controls(
726 component, aic311x_snd_controls,
727 ARRAY_SIZE(aic311x_snd_controls));
728 else
729 ret = snd_soc_add_component_controls(
730 component, aic310x_snd_controls,
731 ARRAY_SIZE(aic310x_snd_controls));
732
733 return ret;
734 }
735
736 static int aic31xx_add_widgets(struct snd_soc_component *component)
737 {
738 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
739 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
740 int ret = 0;
741
742 if (aic31xx->codec_type & DAC31XX_BIT) {
743 ret = snd_soc_dapm_new_controls(
744 dapm, dac31xx_dapm_widgets,
745 ARRAY_SIZE(dac31xx_dapm_widgets));
746 if (ret)
747 return ret;
748
749 ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map,
750 ARRAY_SIZE(dac31xx_audio_map));
751 if (ret)
752 return ret;
753 } else {
754 ret = snd_soc_dapm_new_controls(
755 dapm, aic31xx_dapm_widgets,
756 ARRAY_SIZE(aic31xx_dapm_widgets));
757 if (ret)
758 return ret;
759
760 ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map,
761 ARRAY_SIZE(aic31xx_audio_map));
762 if (ret)
763 return ret;
764 }
765
766 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
767 ret = snd_soc_dapm_new_controls(
768 dapm, aic311x_dapm_widgets,
769 ARRAY_SIZE(aic311x_dapm_widgets));
770 if (ret)
771 return ret;
772
773 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
774 ARRAY_SIZE(aic311x_audio_map));
775 if (ret)
776 return ret;
777 } else {
778 ret = snd_soc_dapm_new_controls(
779 dapm, aic310x_dapm_widgets,
780 ARRAY_SIZE(aic310x_dapm_widgets));
781 if (ret)
782 return ret;
783
784 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
785 ARRAY_SIZE(aic310x_audio_map));
786 if (ret)
787 return ret;
788 }
789
790 return 0;
791 }
792
793 static int aic31xx_setup_pll(struct snd_soc_component *component,
794 struct snd_pcm_hw_params *params)
795 {
796 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
797 int bclk_score = snd_soc_params_to_frame_size(params);
798 int mclk_p;
799 int bclk_n = 0;
800 int match = -1;
801 int i;
802
803 if (!aic31xx->sysclk || !aic31xx->p_div) {
804 dev_err(component->dev, "Master clock not supplied\n");
805 return -EINVAL;
806 }
807 mclk_p = aic31xx->sysclk / aic31xx->p_div;
808
809 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
810 snd_soc_component_update_bits(component, AIC31XX_CLKMUX,
811 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
812 snd_soc_component_update_bits(component, AIC31XX_IFACE2,
813 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
814
815 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
816 if (aic31xx_divs[i].rate == params_rate(params) &&
817 aic31xx_divs[i].mclk_p == mclk_p) {
818 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
819 snd_soc_params_to_frame_size(params);
820 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
821 snd_soc_params_to_frame_size(params);
822 if (s < bclk_score && bn > 0) {
823 match = i;
824 bclk_n = bn;
825 bclk_score = s;
826 }
827 }
828 }
829
830 if (match == -1) {
831 dev_err(component->dev,
832 "%s: Sample rate (%u) and format not supported\n",
833 __func__, params_rate(params));
834 /* See bellow for details how fix this. */
835 return -EINVAL;
836 }
837 if (bclk_score != 0) {
838 dev_warn(component->dev, "Can not produce exact bitclock");
839 /* This is fine if using dsp format, but if using i2s
840 there may be trouble. To fix the issue edit the
841 aic31xx_divs table for your mclk and sample
842 rate. Details can be found from:
843 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
844 Section: 5.6 CLOCK Generation and PLL
845 */
846 }
847 i = match;
848
849 /* PLL configuration */
850 snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
851 (aic31xx->p_div << 4) | 0x01);
852 snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
853
854 snd_soc_component_write(component, AIC31XX_PLLDMSB,
855 aic31xx_divs[i].pll_d >> 8);
856 snd_soc_component_write(component, AIC31XX_PLLDLSB,
857 aic31xx_divs[i].pll_d & 0xff);
858
859 /* DAC dividers configuration */
860 snd_soc_component_update_bits(component, AIC31XX_NDAC, AIC31XX_PLL_MASK,
861 aic31xx_divs[i].ndac);
862 snd_soc_component_update_bits(component, AIC31XX_MDAC, AIC31XX_PLL_MASK,
863 aic31xx_divs[i].mdac);
864
865 snd_soc_component_write(component, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
866 snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
867
868 /* ADC dividers configuration. Write reset value 1 if not used. */
869 snd_soc_component_update_bits(component, AIC31XX_NADC, AIC31XX_PLL_MASK,
870 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
871 snd_soc_component_update_bits(component, AIC31XX_MADC, AIC31XX_PLL_MASK,
872 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
873
874 snd_soc_component_write(component, AIC31XX_AOSR, aic31xx_divs[i].aosr);
875
876 /* Bit clock divider configuration. */
877 snd_soc_component_update_bits(component, AIC31XX_BCLKN,
878 AIC31XX_PLL_MASK, bclk_n);
879
880 aic31xx->rate_div_line = i;
881
882 dev_dbg(component->dev,
883 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
884 aic31xx_divs[i].pll_j,
885 aic31xx_divs[i].pll_d,
886 aic31xx->p_div,
887 aic31xx_divs[i].dosr,
888 aic31xx_divs[i].ndac,
889 aic31xx_divs[i].mdac,
890 aic31xx_divs[i].aosr,
891 aic31xx_divs[i].nadc,
892 aic31xx_divs[i].madc,
893 bclk_n
894 );
895
896 return 0;
897 }
898
899 static int aic31xx_hw_params(struct snd_pcm_substream *substream,
900 struct snd_pcm_hw_params *params,
901 struct snd_soc_dai *dai)
902 {
903 struct snd_soc_component *component = dai->component;
904 u8 data = 0;
905
906 dev_dbg(component->dev, "## %s: width %d rate %d\n",
907 __func__, params_width(params),
908 params_rate(params));
909
910 switch (params_width(params)) {
911 case 16:
912 break;
913 case 20:
914 data = (AIC31XX_WORD_LEN_20BITS <<
915 AIC31XX_IFACE1_DATALEN_SHIFT);
916 break;
917 case 24:
918 data = (AIC31XX_WORD_LEN_24BITS <<
919 AIC31XX_IFACE1_DATALEN_SHIFT);
920 break;
921 case 32:
922 data = (AIC31XX_WORD_LEN_32BITS <<
923 AIC31XX_IFACE1_DATALEN_SHIFT);
924 break;
925 default:
926 dev_err(component->dev, "%s: Unsupported width %d\n",
927 __func__, params_width(params));
928 return -EINVAL;
929 }
930
931 snd_soc_component_update_bits(component, AIC31XX_IFACE1,
932 AIC31XX_IFACE1_DATALEN_MASK,
933 data);
934
935 return aic31xx_setup_pll(component, params);
936 }
937
938 static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute)
939 {
940 struct snd_soc_component *component = codec_dai->component;
941
942 if (mute) {
943 snd_soc_component_update_bits(component, AIC31XX_DACMUTE,
944 AIC31XX_DACMUTE_MASK,
945 AIC31XX_DACMUTE_MASK);
946 } else {
947 snd_soc_component_update_bits(component, AIC31XX_DACMUTE,
948 AIC31XX_DACMUTE_MASK, 0x0);
949 }
950
951 return 0;
952 }
953
954 static int aic31xx_clock_master_routes(struct snd_soc_component *component,
955 unsigned int fmt)
956 {
957 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
958 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
959 int ret;
960
961 fmt &= SND_SOC_DAIFMT_MASTER_MASK;
962 if (fmt == SND_SOC_DAIFMT_CBS_CFS &&
963 aic31xx->master_dapm_route_applied) {
964 /*
965 * Remove the DAPM route(s) for codec clock master modes,
966 * if applied
967 */
968 ret = snd_soc_dapm_del_routes(dapm, common31xx_cm_audio_map,
969 ARRAY_SIZE(common31xx_cm_audio_map));
970 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))
971 ret = snd_soc_dapm_del_routes(dapm,
972 aic31xx_cm_audio_map,
973 ARRAY_SIZE(aic31xx_cm_audio_map));
974
975 if (ret)
976 return ret;
977
978 aic31xx->master_dapm_route_applied = false;
979 } else if (fmt != SND_SOC_DAIFMT_CBS_CFS &&
980 !aic31xx->master_dapm_route_applied) {
981 /*
982 * Add the needed DAPM route(s) for codec clock master modes,
983 * if it is not done already
984 */
985 ret = snd_soc_dapm_add_routes(dapm, common31xx_cm_audio_map,
986 ARRAY_SIZE(common31xx_cm_audio_map));
987 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))
988 ret = snd_soc_dapm_add_routes(dapm,
989 aic31xx_cm_audio_map,
990 ARRAY_SIZE(aic31xx_cm_audio_map));
991
992 if (ret)
993 return ret;
994
995 aic31xx->master_dapm_route_applied = true;
996 }
997
998 return 0;
999 }
1000
1001 static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
1002 unsigned int fmt)
1003 {
1004 struct snd_soc_component *component = codec_dai->component;
1005 u8 iface_reg1 = 0;
1006 u8 iface_reg2 = 0;
1007 u8 dsp_a_val = 0;
1008
1009 dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt);
1010
1011 /* set master/slave audio interface */
1012 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1013 case SND_SOC_DAIFMT_CBM_CFM:
1014 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;
1015 break;
1016 case SND_SOC_DAIFMT_CBS_CFM:
1017 iface_reg1 |= AIC31XX_WCLK_MASTER;
1018 break;
1019 case SND_SOC_DAIFMT_CBM_CFS:
1020 iface_reg1 |= AIC31XX_BCLK_MASTER;
1021 break;
1022 case SND_SOC_DAIFMT_CBS_CFS:
1023 break;
1024 default:
1025 dev_err(component->dev, "Invalid DAI master/slave interface\n");
1026 return -EINVAL;
1027 }
1028
1029 /* signal polarity */
1030 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1031 case SND_SOC_DAIFMT_NB_NF:
1032 break;
1033 case SND_SOC_DAIFMT_IB_NF:
1034 iface_reg2 |= AIC31XX_BCLKINV_MASK;
1035 break;
1036 default:
1037 dev_err(component->dev, "Invalid DAI clock signal polarity\n");
1038 return -EINVAL;
1039 }
1040
1041 /* interface format */
1042 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1043 case SND_SOC_DAIFMT_I2S:
1044 break;
1045 case SND_SOC_DAIFMT_DSP_A:
1046 dsp_a_val = 0x1; /* fall through */
1047 case SND_SOC_DAIFMT_DSP_B:
1048 /*
1049 * NOTE: This CODEC samples on the falling edge of BCLK in
1050 * DSP mode, this is inverted compared to what most DAIs
1051 * expect, so we invert for this mode
1052 */
1053 iface_reg2 ^= AIC31XX_BCLKINV_MASK;
1054 iface_reg1 |= (AIC31XX_DSP_MODE <<
1055 AIC31XX_IFACE1_DATATYPE_SHIFT);
1056 break;
1057 case SND_SOC_DAIFMT_RIGHT_J:
1058 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<
1059 AIC31XX_IFACE1_DATATYPE_SHIFT);
1060 break;
1061 case SND_SOC_DAIFMT_LEFT_J:
1062 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<
1063 AIC31XX_IFACE1_DATATYPE_SHIFT);
1064 break;
1065 default:
1066 dev_err(component->dev, "Invalid DAI interface format\n");
1067 return -EINVAL;
1068 }
1069
1070 snd_soc_component_update_bits(component, AIC31XX_IFACE1,
1071 AIC31XX_IFACE1_DATATYPE_MASK |
1072 AIC31XX_IFACE1_MASTER_MASK,
1073 iface_reg1);
1074 snd_soc_component_update_bits(component, AIC31XX_DATA_OFFSET,
1075 AIC31XX_DATA_OFFSET_MASK,
1076 dsp_a_val);
1077 snd_soc_component_update_bits(component, AIC31XX_IFACE2,
1078 AIC31XX_BCLKINV_MASK,
1079 iface_reg2);
1080
1081 return aic31xx_clock_master_routes(component, fmt);
1082 }
1083
1084 static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1085 int clk_id, unsigned int freq, int dir)
1086 {
1087 struct snd_soc_component *component = codec_dai->component;
1088 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1089 int i;
1090
1091 dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
1092 __func__, clk_id, freq, dir);
1093
1094 for (i = 1; i < 8; i++)
1095 if (freq / i <= 20000000)
1096 break;
1097 if (freq/i > 20000000) {
1098 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
1099 __func__, freq);
1100 return -EINVAL;
1101 }
1102 aic31xx->p_div = i;
1103
1104 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++)
1105 if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div)
1106 break;
1107 if (i == ARRAY_SIZE(aic31xx_divs)) {
1108 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
1109 __func__, freq);
1110 return -EINVAL;
1111 }
1112
1113 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */
1114 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
1115 clk_id << AIC31XX_PLL_CLKIN_SHIFT);
1116
1117 aic31xx->sysclk = freq;
1118
1119 return 0;
1120 }
1121
1122 static int aic31xx_regulator_event(struct notifier_block *nb,
1123 unsigned long event, void *data)
1124 {
1125 struct aic31xx_disable_nb *disable_nb =
1126 container_of(nb, struct aic31xx_disable_nb, nb);
1127 struct aic31xx_priv *aic31xx = disable_nb->aic31xx;
1128
1129 if (event & REGULATOR_EVENT_DISABLE) {
1130 /*
1131 * Put codec to reset and as at least one of the
1132 * supplies was disabled.
1133 */
1134 if (aic31xx->gpio_reset)
1135 gpiod_set_value(aic31xx->gpio_reset, 1);
1136
1137 regcache_mark_dirty(aic31xx->regmap);
1138 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);
1139 }
1140
1141 return 0;
1142 }
1143
1144 static int aic31xx_reset(struct aic31xx_priv *aic31xx)
1145 {
1146 int ret = 0;
1147
1148 if (aic31xx->gpio_reset) {
1149 gpiod_set_value(aic31xx->gpio_reset, 1);
1150 ndelay(10); /* At least 10ns */
1151 gpiod_set_value(aic31xx->gpio_reset, 0);
1152 } else {
1153 ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1);
1154 }
1155 mdelay(1); /* At least 1ms */
1156
1157 return ret;
1158 }
1159
1160 static void aic31xx_clk_on(struct snd_soc_component *component)
1161 {
1162 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1163 u8 mask = AIC31XX_PM_MASK;
1164 u8 on = AIC31XX_PM_MASK;
1165
1166 dev_dbg(component->dev, "codec clock -> on (rate %d)\n",
1167 aic31xx_divs[aic31xx->rate_div_line].rate);
1168 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on);
1169 mdelay(10);
1170 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on);
1171 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on);
1172 if (aic31xx_divs[aic31xx->rate_div_line].nadc)
1173 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on);
1174 if (aic31xx_divs[aic31xx->rate_div_line].madc)
1175 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on);
1176 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on);
1177 }
1178
1179 static void aic31xx_clk_off(struct snd_soc_component *component)
1180 {
1181 u8 mask = AIC31XX_PM_MASK;
1182 u8 off = 0;
1183
1184 dev_dbg(component->dev, "codec clock -> off\n");
1185 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off);
1186 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off);
1187 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off);
1188 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off);
1189 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off);
1190 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off);
1191 }
1192
1193 static int aic31xx_power_on(struct snd_soc_component *component)
1194 {
1195 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1196 int ret;
1197
1198 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
1199 aic31xx->supplies);
1200 if (ret)
1201 return ret;
1202
1203 regcache_cache_only(aic31xx->regmap, false);
1204
1205 /* Reset device registers for a consistent power-on like state */
1206 ret = aic31xx_reset(aic31xx);
1207 if (ret < 0)
1208 dev_err(aic31xx->dev, "Could not reset device: %d\n", ret);
1209
1210 ret = regcache_sync(aic31xx->regmap);
1211 if (ret) {
1212 dev_err(component->dev,
1213 "Failed to restore cache: %d\n", ret);
1214 regcache_cache_only(aic31xx->regmap, true);
1215 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1216 aic31xx->supplies);
1217 return ret;
1218 }
1219
1220 return 0;
1221 }
1222
1223 static void aic31xx_power_off(struct snd_soc_component *component)
1224 {
1225 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1226
1227 regcache_cache_only(aic31xx->regmap, true);
1228 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1229 aic31xx->supplies);
1230 }
1231
1232 static int aic31xx_set_bias_level(struct snd_soc_component *component,
1233 enum snd_soc_bias_level level)
1234 {
1235 dev_dbg(component->dev, "## %s: %d -> %d\n", __func__,
1236 snd_soc_component_get_bias_level(component), level);
1237
1238 switch (level) {
1239 case SND_SOC_BIAS_ON:
1240 break;
1241 case SND_SOC_BIAS_PREPARE:
1242 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
1243 aic31xx_clk_on(component);
1244 break;
1245 case SND_SOC_BIAS_STANDBY:
1246 switch (snd_soc_component_get_bias_level(component)) {
1247 case SND_SOC_BIAS_OFF:
1248 aic31xx_power_on(component);
1249 break;
1250 case SND_SOC_BIAS_PREPARE:
1251 aic31xx_clk_off(component);
1252 break;
1253 default:
1254 BUG();
1255 }
1256 break;
1257 case SND_SOC_BIAS_OFF:
1258 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
1259 aic31xx_power_off(component);
1260 break;
1261 }
1262
1263 return 0;
1264 }
1265
1266 static int aic31xx_set_jack(struct snd_soc_component *component,
1267 struct snd_soc_jack *jack, void *data)
1268 {
1269 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1270
1271 aic31xx->jack = jack;
1272
1273 /* Enable/Disable jack detection */
1274 regmap_write(aic31xx->regmap, AIC31XX_HSDETECT,
1275 jack ? AIC31XX_HSD_ENABLE : 0);
1276
1277 return 0;
1278 }
1279
1280 static int aic31xx_codec_probe(struct snd_soc_component *component)
1281 {
1282 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1283 int i, ret;
1284
1285 dev_dbg(aic31xx->dev, "## %s\n", __func__);
1286
1287 aic31xx->component = component;
1288
1289 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {
1290 aic31xx->disable_nb[i].nb.notifier_call =
1291 aic31xx_regulator_event;
1292 aic31xx->disable_nb[i].aic31xx = aic31xx;
1293 ret = devm_regulator_register_notifier(
1294 aic31xx->supplies[i].consumer,
1295 &aic31xx->disable_nb[i].nb);
1296 if (ret) {
1297 dev_err(component->dev,
1298 "Failed to request regulator notifier: %d\n",
1299 ret);
1300 return ret;
1301 }
1302 }
1303
1304 regcache_cache_only(aic31xx->regmap, true);
1305 regcache_mark_dirty(aic31xx->regmap);
1306
1307 ret = aic31xx_add_controls(component);
1308 if (ret)
1309 return ret;
1310
1311 ret = aic31xx_add_widgets(component);
1312 if (ret)
1313 return ret;
1314
1315 return 0;
1316 }
1317
1318 static const struct snd_soc_component_driver soc_codec_driver_aic31xx = {
1319 .probe = aic31xx_codec_probe,
1320 .set_jack = aic31xx_set_jack,
1321 .set_bias_level = aic31xx_set_bias_level,
1322 .controls = common31xx_snd_controls,
1323 .num_controls = ARRAY_SIZE(common31xx_snd_controls),
1324 .dapm_widgets = common31xx_dapm_widgets,
1325 .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets),
1326 .dapm_routes = common31xx_audio_map,
1327 .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map),
1328 .suspend_bias_off = 1,
1329 .idle_bias_on = 1,
1330 .use_pmdown_time = 1,
1331 .endianness = 1,
1332 .non_legacy_dai_naming = 1,
1333 };
1334
1335 static const struct snd_soc_dai_ops aic31xx_dai_ops = {
1336 .hw_params = aic31xx_hw_params,
1337 .set_sysclk = aic31xx_set_dai_sysclk,
1338 .set_fmt = aic31xx_set_dai_fmt,
1339 .digital_mute = aic31xx_dac_mute,
1340 };
1341
1342 static struct snd_soc_dai_driver dac31xx_dai_driver[] = {
1343 {
1344 .name = "tlv320dac31xx-hifi",
1345 .playback = {
1346 .stream_name = "Playback",
1347 .channels_min = 2,
1348 .channels_max = 2,
1349 .rates = AIC31XX_RATES,
1350 .formats = AIC31XX_FORMATS,
1351 },
1352 .ops = &aic31xx_dai_ops,
1353 .symmetric_rates = 1,
1354 }
1355 };
1356
1357 static struct snd_soc_dai_driver aic31xx_dai_driver[] = {
1358 {
1359 .name = "tlv320aic31xx-hifi",
1360 .playback = {
1361 .stream_name = "Playback",
1362 .channels_min = 2,
1363 .channels_max = 2,
1364 .rates = AIC31XX_RATES,
1365 .formats = AIC31XX_FORMATS,
1366 },
1367 .capture = {
1368 .stream_name = "Capture",
1369 .channels_min = 2,
1370 .channels_max = 2,
1371 .rates = AIC31XX_RATES,
1372 .formats = AIC31XX_FORMATS,
1373 },
1374 .ops = &aic31xx_dai_ops,
1375 .symmetric_rates = 1,
1376 }
1377 };
1378
1379 #if defined(CONFIG_OF)
1380 static const struct of_device_id tlv320aic31xx_of_match[] = {
1381 { .compatible = "ti,tlv320aic310x" },
1382 { .compatible = "ti,tlv320aic311x" },
1383 { .compatible = "ti,tlv320aic3100" },
1384 { .compatible = "ti,tlv320aic3110" },
1385 { .compatible = "ti,tlv320aic3120" },
1386 { .compatible = "ti,tlv320aic3111" },
1387 { .compatible = "ti,tlv320dac3100" },
1388 { .compatible = "ti,tlv320dac3101" },
1389 {},
1390 };
1391 MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
1392 #endif /* CONFIG_OF */
1393
1394 #ifdef CONFIG_ACPI
1395 static const struct acpi_device_id aic31xx_acpi_match[] = {
1396 { "10TI3100", 0 },
1397 { }
1398 };
1399 MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match);
1400 #endif
1401
1402 static irqreturn_t aic31xx_irq(int irq, void *data)
1403 {
1404 struct aic31xx_priv *aic31xx = data;
1405 struct device *dev = aic31xx->dev;
1406 unsigned int value;
1407 bool handled = false;
1408 int ret;
1409
1410 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG, &value);
1411 if (ret) {
1412 dev_err(dev, "Failed to read interrupt mask: %d\n", ret);
1413 goto exit;
1414 }
1415
1416 if (value)
1417 handled = true;
1418 else
1419 goto read_overflow;
1420
1421 if (value & AIC31XX_HPLSCDETECT)
1422 dev_err(dev, "Short circuit on Left output is detected\n");
1423 if (value & AIC31XX_HPRSCDETECT)
1424 dev_err(dev, "Short circuit on Right output is detected\n");
1425 if (value & (AIC31XX_HSPLUG | AIC31XX_BUTTONPRESS)) {
1426 unsigned int val;
1427 int status = 0;
1428
1429 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG2,
1430 &val);
1431 if (ret) {
1432 dev_err(dev, "Failed to read interrupt mask: %d\n",
1433 ret);
1434 goto exit;
1435 }
1436
1437 if (val & AIC31XX_BUTTONPRESS)
1438 status |= SND_JACK_BTN_0;
1439
1440 ret = regmap_read(aic31xx->regmap, AIC31XX_HSDETECT, &val);
1441 if (ret) {
1442 dev_err(dev, "Failed to read headset type: %d\n", ret);
1443 goto exit;
1444 }
1445
1446 switch ((val & AIC31XX_HSD_TYPE_MASK) >>
1447 AIC31XX_HSD_TYPE_SHIFT) {
1448 case AIC31XX_HSD_HP:
1449 status |= SND_JACK_HEADPHONE;
1450 break;
1451 case AIC31XX_HSD_HS:
1452 status |= SND_JACK_HEADSET;
1453 break;
1454 default:
1455 break;
1456 }
1457
1458 if (aic31xx->jack)
1459 snd_soc_jack_report(aic31xx->jack, status,
1460 AIC31XX_JACK_MASK);
1461 }
1462 if (value & ~(AIC31XX_HPLSCDETECT |
1463 AIC31XX_HPRSCDETECT |
1464 AIC31XX_HSPLUG |
1465 AIC31XX_BUTTONPRESS))
1466 dev_err(dev, "Unknown DAC interrupt flags: 0x%08x\n", value);
1467
1468 read_overflow:
1469 ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value);
1470 if (ret) {
1471 dev_err(dev, "Failed to read overflow flag: %d\n", ret);
1472 goto exit;
1473 }
1474
1475 if (value)
1476 handled = true;
1477 else
1478 goto exit;
1479
1480 if (value & AIC31XX_DAC_OF_LEFT)
1481 dev_warn(dev, "Left-channel DAC overflow has occurred\n");
1482 if (value & AIC31XX_DAC_OF_RIGHT)
1483 dev_warn(dev, "Right-channel DAC overflow has occurred\n");
1484 if (value & AIC31XX_DAC_OF_SHIFTER)
1485 dev_warn(dev, "DAC barrel shifter overflow has occurred\n");
1486 if (value & AIC31XX_ADC_OF)
1487 dev_warn(dev, "ADC overflow has occurred\n");
1488 if (value & AIC31XX_ADC_OF_SHIFTER)
1489 dev_warn(dev, "ADC barrel shifter overflow has occurred\n");
1490 if (value & ~(AIC31XX_DAC_OF_LEFT |
1491 AIC31XX_DAC_OF_RIGHT |
1492 AIC31XX_DAC_OF_SHIFTER |
1493 AIC31XX_ADC_OF |
1494 AIC31XX_ADC_OF_SHIFTER))
1495 dev_warn(dev, "Unknown overflow interrupt flags: 0x%08x\n", value);
1496
1497 exit:
1498 if (handled)
1499 return IRQ_HANDLED;
1500 else
1501 return IRQ_NONE;
1502 }
1503
1504 static int aic31xx_i2c_probe(struct i2c_client *i2c,
1505 const struct i2c_device_id *id)
1506 {
1507 struct aic31xx_priv *aic31xx;
1508 unsigned int micbias_value = MICBIAS_2_0V;
1509 int i, ret;
1510
1511 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,
1512 id->name, (int)id->driver_data);
1513
1514 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);
1515 if (!aic31xx)
1516 return -ENOMEM;
1517
1518 aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap);
1519 if (IS_ERR(aic31xx->regmap)) {
1520 ret = PTR_ERR(aic31xx->regmap);
1521 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1522 ret);
1523 return ret;
1524 }
1525 aic31xx->dev = &i2c->dev;
1526 aic31xx->irq = i2c->irq;
1527
1528 aic31xx->codec_type = id->driver_data;
1529
1530 dev_set_drvdata(aic31xx->dev, aic31xx);
1531
1532 fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg",
1533 &micbias_value);
1534 switch (micbias_value) {
1535 case MICBIAS_2_0V:
1536 case MICBIAS_2_5V:
1537 case MICBIAS_AVDDV:
1538 aic31xx->micbias_vg = micbias_value;
1539 break;
1540 default:
1541 dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n",
1542 micbias_value);
1543 aic31xx->micbias_vg = MICBIAS_2_0V;
1544 }
1545
1546 if (dev_get_platdata(aic31xx->dev)) {
1547 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata));
1548 aic31xx->codec_type = aic31xx->pdata.codec_type;
1549 aic31xx->micbias_vg = aic31xx->pdata.micbias_vg;
1550 }
1551
1552 aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset",
1553 GPIOD_OUT_LOW);
1554 if (IS_ERR(aic31xx->gpio_reset)) {
1555 if (PTR_ERR(aic31xx->gpio_reset) != -EPROBE_DEFER)
1556 dev_err(aic31xx->dev, "not able to acquire gpio\n");
1557 return PTR_ERR(aic31xx->gpio_reset);
1558 }
1559
1560 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1561 aic31xx->supplies[i].supply = aic31xx_supply_names[i];
1562
1563 ret = devm_regulator_bulk_get(aic31xx->dev,
1564 ARRAY_SIZE(aic31xx->supplies),
1565 aic31xx->supplies);
1566 if (ret) {
1567 if (ret != -EPROBE_DEFER)
1568 dev_err(aic31xx->dev,
1569 "Failed to request supplies: %d\n", ret);
1570 return ret;
1571 }
1572
1573 if (aic31xx->irq > 0) {
1574 regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1,
1575 AIC31XX_GPIO1_FUNC_MASK,
1576 AIC31XX_GPIO1_INT1 <<
1577 AIC31XX_GPIO1_FUNC_SHIFT);
1578
1579 regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL,
1580 AIC31XX_HSPLUGDET |
1581 AIC31XX_BUTTONPRESSDET |
1582 AIC31XX_SC |
1583 AIC31XX_ENGINE);
1584
1585 ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq,
1586 NULL, aic31xx_irq,
1587 IRQF_ONESHOT, "aic31xx-irq",
1588 aic31xx);
1589 if (ret) {
1590 dev_err(aic31xx->dev, "Unable to request IRQ\n");
1591 return ret;
1592 }
1593 }
1594
1595 if (aic31xx->codec_type & DAC31XX_BIT)
1596 return devm_snd_soc_register_component(&i2c->dev,
1597 &soc_codec_driver_aic31xx,
1598 dac31xx_dai_driver,
1599 ARRAY_SIZE(dac31xx_dai_driver));
1600 else
1601 return devm_snd_soc_register_component(&i2c->dev,
1602 &soc_codec_driver_aic31xx,
1603 aic31xx_dai_driver,
1604 ARRAY_SIZE(aic31xx_dai_driver));
1605 }
1606
1607 static const struct i2c_device_id aic31xx_i2c_id[] = {
1608 { "tlv320aic310x", AIC3100 },
1609 { "tlv320aic311x", AIC3110 },
1610 { "tlv320aic3100", AIC3100 },
1611 { "tlv320aic3110", AIC3110 },
1612 { "tlv320aic3120", AIC3120 },
1613 { "tlv320aic3111", AIC3111 },
1614 { "tlv320dac3100", DAC3100 },
1615 { "tlv320dac3101", DAC3101 },
1616 { }
1617 };
1618 MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
1619
1620 static struct i2c_driver aic31xx_i2c_driver = {
1621 .driver = {
1622 .name = "tlv320aic31xx-codec",
1623 .of_match_table = of_match_ptr(tlv320aic31xx_of_match),
1624 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match),
1625 },
1626 .probe = aic31xx_i2c_probe,
1627 .id_table = aic31xx_i2c_id,
1628 };
1629 module_i2c_driver(aic31xx_i2c_driver);
1630
1631 MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>");
1632 MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver");
1633 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support