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[linux/fpc-iii.git] / arch / arm / mach-s3c2410 / mach-bast.c
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1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
3 * Copyright (c) 2003-2005,2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * http://www.simtec.co.uk/products/EB2410ITX/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/gpio.h>
20 #include <linux/sysdev.h>
21 #include <linux/serial_core.h>
22 #include <linux/platform_device.h>
23 #include <linux/dm9000.h>
24 #include <linux/ata_platform.h>
25 #include <linux/i2c.h>
26 #include <linux/io.h>
28 #include <net/ax88796.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/irq.h>
34 #include <mach/bast-map.h>
35 #include <mach/bast-irq.h>
36 #include <mach/bast-cpld.h>
38 #include <mach/hardware.h>
39 #include <asm/irq.h>
40 #include <asm/mach-types.h>
42 //#include <asm/debug-ll.h>
43 #include <plat/regs-serial.h>
44 #include <mach/regs-gpio.h>
45 #include <mach/regs-mem.h>
46 #include <mach/regs-lcd.h>
48 #include <plat/nand.h>
49 #include <plat/iic.h>
50 #include <mach/fb.h>
52 #include <linux/mtd/mtd.h>
53 #include <linux/mtd/nand.h>
54 #include <linux/mtd/nand_ecc.h>
55 #include <linux/mtd/partitions.h>
57 #include <linux/serial_8250.h>
59 #include <plat/clock.h>
60 #include <plat/devs.h>
61 #include <plat/cpu.h>
63 #include "usb-simtec.h"
64 #include "nor-simtec.h"
66 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
68 /* macros for virtual address mods for the io space entries */
69 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
70 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
71 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
72 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
74 /* macros to modify the physical addresses for io space */
76 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
77 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
78 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
79 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
81 static struct map_desc bast_iodesc[] __initdata = {
82 /* ISA IO areas */
84 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
85 .pfn = PA_CS2(BAST_PA_ISAIO),
86 .length = SZ_16M,
87 .type = MT_DEVICE,
88 }, {
89 .virtual = (u32)S3C24XX_VA_ISA_WORD,
90 .pfn = PA_CS3(BAST_PA_ISAIO),
91 .length = SZ_16M,
92 .type = MT_DEVICE,
94 /* bast CPLD control registers, and external interrupt controls */
96 .virtual = (u32)BAST_VA_CTRL1,
97 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
98 .length = SZ_1M,
99 .type = MT_DEVICE,
100 }, {
101 .virtual = (u32)BAST_VA_CTRL2,
102 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
103 .length = SZ_1M,
104 .type = MT_DEVICE,
105 }, {
106 .virtual = (u32)BAST_VA_CTRL3,
107 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
108 .length = SZ_1M,
109 .type = MT_DEVICE,
110 }, {
111 .virtual = (u32)BAST_VA_CTRL4,
112 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
113 .length = SZ_1M,
114 .type = MT_DEVICE,
116 /* PC104 IRQ mux */
118 .virtual = (u32)BAST_VA_PC104_IRQREQ,
119 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
120 .length = SZ_1M,
121 .type = MT_DEVICE,
122 }, {
123 .virtual = (u32)BAST_VA_PC104_IRQRAW,
124 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
125 .length = SZ_1M,
126 .type = MT_DEVICE,
127 }, {
128 .virtual = (u32)BAST_VA_PC104_IRQMASK,
129 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
130 .length = SZ_1M,
131 .type = MT_DEVICE,
134 /* peripheral space... one for each of fast/slow/byte/16bit */
135 /* note, ide is only decoded in word space, even though some registers
136 * are only 8bit */
138 /* slow, byte */
139 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
140 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
141 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
143 /* slow, word */
144 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
145 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
146 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
148 /* fast, byte */
149 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
150 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
151 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
153 /* fast, word */
154 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
155 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
156 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
159 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
160 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
161 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
163 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
164 [0] = {
165 .name = "uclk",
166 .divisor = 1,
167 .min_baud = 0,
168 .max_baud = 0,
170 [1] = {
171 .name = "pclk",
172 .divisor = 1,
173 .min_baud = 0,
174 .max_baud = 0,
179 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
180 [0] = {
181 .hwport = 0,
182 .flags = 0,
183 .ucon = UCON,
184 .ulcon = ULCON,
185 .ufcon = UFCON,
186 .clocks = bast_serial_clocks,
187 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
189 [1] = {
190 .hwport = 1,
191 .flags = 0,
192 .ucon = UCON,
193 .ulcon = ULCON,
194 .ufcon = UFCON,
195 .clocks = bast_serial_clocks,
196 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
198 /* port 2 is not actually used */
199 [2] = {
200 .hwport = 2,
201 .flags = 0,
202 .ucon = UCON,
203 .ulcon = ULCON,
204 .ufcon = UFCON,
205 .clocks = bast_serial_clocks,
206 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
210 /* NAND Flash on BAST board */
212 #ifdef CONFIG_PM
213 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
215 /* ensure that an nRESET is not generated on resume. */
216 s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
217 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
219 return 0;
222 static int bast_pm_resume(struct sys_device *sd)
224 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
225 return 0;
228 #else
229 #define bast_pm_suspend NULL
230 #define bast_pm_resume NULL
231 #endif
233 static struct sysdev_class bast_pm_sysclass = {
234 .name = "mach-bast",
235 .suspend = bast_pm_suspend,
236 .resume = bast_pm_resume,
239 static struct sys_device bast_pm_sysdev = {
240 .cls = &bast_pm_sysclass,
243 static int smartmedia_map[] = { 0 };
244 static int chip0_map[] = { 1 };
245 static int chip1_map[] = { 2 };
246 static int chip2_map[] = { 3 };
248 static struct mtd_partition bast_default_nand_part[] = {
249 [0] = {
250 .name = "Boot Agent",
251 .size = SZ_16K,
252 .offset = 0,
254 [1] = {
255 .name = "/boot",
256 .size = SZ_4M - SZ_16K,
257 .offset = SZ_16K,
259 [2] = {
260 .name = "user",
261 .offset = SZ_4M,
262 .size = MTDPART_SIZ_FULL,
266 /* the bast has 4 selectable slots for nand-flash, the three
267 * on-board chip areas, as well as the external SmartMedia
268 * slot.
270 * Note, there is no current hot-plug support for the SmartMedia
271 * socket.
274 static struct s3c2410_nand_set bast_nand_sets[] = {
275 [0] = {
276 .name = "SmartMedia",
277 .nr_chips = 1,
278 .nr_map = smartmedia_map,
279 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
280 .partitions = bast_default_nand_part,
282 [1] = {
283 .name = "chip0",
284 .nr_chips = 1,
285 .nr_map = chip0_map,
286 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
287 .partitions = bast_default_nand_part,
289 [2] = {
290 .name = "chip1",
291 .nr_chips = 1,
292 .nr_map = chip1_map,
293 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
294 .partitions = bast_default_nand_part,
296 [3] = {
297 .name = "chip2",
298 .nr_chips = 1,
299 .nr_map = chip2_map,
300 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
301 .partitions = bast_default_nand_part,
305 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
307 unsigned int tmp;
309 slot = set->nr_map[slot] & 3;
311 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
312 slot, set, set->nr_map);
314 tmp = __raw_readb(BAST_VA_CTRL2);
315 tmp &= BAST_CPLD_CTLR2_IDERST;
316 tmp |= slot;
317 tmp |= BAST_CPLD_CTRL2_WNAND;
319 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
321 __raw_writeb(tmp, BAST_VA_CTRL2);
324 static struct s3c2410_platform_nand bast_nand_info = {
325 .tacls = 30,
326 .twrph0 = 60,
327 .twrph1 = 60,
328 .nr_sets = ARRAY_SIZE(bast_nand_sets),
329 .sets = bast_nand_sets,
330 .select_chip = bast_nand_select,
333 /* DM9000 */
335 static struct resource bast_dm9k_resource[] = {
336 [0] = {
337 .start = S3C2410_CS5 + BAST_PA_DM9000,
338 .end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
339 .flags = IORESOURCE_MEM,
341 [1] = {
342 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
343 .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
344 .flags = IORESOURCE_MEM,
346 [2] = {
347 .start = IRQ_DM9000,
348 .end = IRQ_DM9000,
349 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
354 /* for the moment we limit ourselves to 16bit IO until some
355 * better IO routines can be written and tested
358 static struct dm9000_plat_data bast_dm9k_platdata = {
359 .flags = DM9000_PLATF_16BITONLY,
362 static struct platform_device bast_device_dm9k = {
363 .name = "dm9000",
364 .id = 0,
365 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
366 .resource = bast_dm9k_resource,
367 .dev = {
368 .platform_data = &bast_dm9k_platdata,
372 /* serial devices */
374 #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
375 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
376 #define SERIAL_CLK (1843200)
378 static struct plat_serial8250_port bast_sio_data[] = {
379 [0] = {
380 .mapbase = SERIAL_BASE + 0x2f8,
381 .irq = IRQ_PCSERIAL1,
382 .flags = SERIAL_FLAGS,
383 .iotype = UPIO_MEM,
384 .regshift = 0,
385 .uartclk = SERIAL_CLK,
387 [1] = {
388 .mapbase = SERIAL_BASE + 0x3f8,
389 .irq = IRQ_PCSERIAL2,
390 .flags = SERIAL_FLAGS,
391 .iotype = UPIO_MEM,
392 .regshift = 0,
393 .uartclk = SERIAL_CLK,
398 static struct platform_device bast_sio = {
399 .name = "serial8250",
400 .id = PLAT8250_DEV_PLATFORM,
401 .dev = {
402 .platform_data = &bast_sio_data,
406 /* we have devices on the bus which cannot work much over the
407 * standard 100KHz i2c bus frequency
410 static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
411 .flags = 0,
412 .slave_addr = 0x10,
413 .frequency = 100*1000,
416 /* Asix AX88796 10/100 ethernet controller */
418 static struct ax_plat_data bast_asix_platdata = {
419 .flags = AXFLG_MAC_FROMDEV,
420 .wordlength = 2,
421 .dcr_val = 0x48,
422 .rcr_val = 0x40,
425 static struct resource bast_asix_resource[] = {
426 [0] = {
427 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
428 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
429 .flags = IORESOURCE_MEM,
431 [1] = {
432 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
433 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
434 .flags = IORESOURCE_MEM,
436 [2] = {
437 .start = IRQ_ASIX,
438 .end = IRQ_ASIX,
439 .flags = IORESOURCE_IRQ
443 static struct platform_device bast_device_asix = {
444 .name = "ax88796",
445 .id = 0,
446 .num_resources = ARRAY_SIZE(bast_asix_resource),
447 .resource = bast_asix_resource,
448 .dev = {
449 .platform_data = &bast_asix_platdata
453 /* Asix AX88796 10/100 ethernet controller parallel port */
455 static struct resource bast_asixpp_resource[] = {
456 [0] = {
457 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
458 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
459 .flags = IORESOURCE_MEM,
463 static struct platform_device bast_device_axpp = {
464 .name = "ax88796-pp",
465 .id = 0,
466 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
467 .resource = bast_asixpp_resource,
470 /* LCD/VGA controller */
472 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
474 .type = S3C2410_LCDCON1_TFT,
475 .width = 640,
476 .height = 480,
478 .pixclock = 33333,
479 .xres = 640,
480 .yres = 480,
481 .bpp = 4,
482 .left_margin = 40,
483 .right_margin = 20,
484 .hsync_len = 88,
485 .upper_margin = 30,
486 .lower_margin = 32,
487 .vsync_len = 3,
489 .lcdcon5 = 0x00014b02,
492 .type = S3C2410_LCDCON1_TFT,
493 .width = 640,
494 .height = 480,
496 .pixclock = 33333,
497 .xres = 640,
498 .yres = 480,
499 .bpp = 8,
500 .left_margin = 40,
501 .right_margin = 20,
502 .hsync_len = 88,
503 .upper_margin = 30,
504 .lower_margin = 32,
505 .vsync_len = 3,
507 .lcdcon5 = 0x00014b02,
510 .type = S3C2410_LCDCON1_TFT,
511 .width = 640,
512 .height = 480,
514 .pixclock = 33333,
515 .xres = 640,
516 .yres = 480,
517 .bpp = 16,
518 .left_margin = 40,
519 .right_margin = 20,
520 .hsync_len = 88,
521 .upper_margin = 30,
522 .lower_margin = 32,
523 .vsync_len = 3,
525 .lcdcon5 = 0x00014b02,
529 /* LCD/VGA controller */
531 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
533 .displays = bast_lcd_info,
534 .num_displays = ARRAY_SIZE(bast_lcd_info),
535 .default_display = 1,
538 /* I2C devices fitted. */
540 static struct i2c_board_info bast_i2c_devs[] __initdata = {
542 I2C_BOARD_INFO("tlv320aic23", 0x1a),
543 }, {
544 I2C_BOARD_INFO("simtec-pmu", 0x6b),
545 }, {
546 I2C_BOARD_INFO("ch7013", 0x75),
550 /* Standard BAST devices */
552 static struct platform_device *bast_devices[] __initdata = {
553 &s3c_device_usb,
554 &s3c_device_lcd,
555 &s3c_device_wdt,
556 &s3c_device_i2c0,
557 &s3c_device_rtc,
558 &s3c_device_nand,
559 &bast_device_dm9k,
560 &bast_device_asix,
561 &bast_device_axpp,
562 &bast_sio,
565 static struct clk *bast_clocks[] __initdata = {
566 &s3c24xx_dclk0,
567 &s3c24xx_dclk1,
568 &s3c24xx_clkout0,
569 &s3c24xx_clkout1,
570 &s3c24xx_uclk,
573 static void __init bast_map_io(void)
575 /* initialise the clocks */
577 s3c24xx_dclk0.parent = &clk_upll;
578 s3c24xx_dclk0.rate = 12*1000*1000;
580 s3c24xx_dclk1.parent = &clk_upll;
581 s3c24xx_dclk1.rate = 24*1000*1000;
583 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
584 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
586 s3c24xx_uclk.parent = &s3c24xx_clkout1;
588 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
590 s3c_device_nand.dev.platform_data = &bast_nand_info;
592 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
593 s3c24xx_init_clocks(0);
594 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
597 static void __init bast_init(void)
599 sysdev_class_register(&bast_pm_sysclass);
600 sysdev_register(&bast_pm_sysdev);
602 s3c_i2c0_set_platdata(&bast_i2c_info);
603 s3c24xx_fb_set_platdata(&bast_fb_info);
604 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
606 i2c_register_board_info(0, bast_i2c_devs,
607 ARRAY_SIZE(bast_i2c_devs));
609 usb_simtec_init();
610 nor_simtec_init();
613 MACHINE_START(BAST, "Simtec-BAST")
614 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
615 .phys_io = S3C2410_PA_UART,
616 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
617 .boot_params = S3C2410_SDRAM_PA + 0x100,
618 .map_io = bast_map_io,
619 .init_irq = s3c24xx_init_irq,
620 .init_machine = bast_init,
621 .timer = &s3c24xx_timer,
622 MACHINE_END