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Linux 2.6.31.6
[linux/fpc-iii.git] / arch / arm / plat-omap / include / mach / mux.h
blob80281c458baf26b74dee1bbcc0f516772272fd2a
1 /*
2 * arch/arm/plat-omap/include/mach/mux.h
3 *
4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations.
6 *
7 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
8 * Copyright (C) 2003 - 2008 Nokia Corporation
9 *
10 * Written by Tony Lindgren
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * NOTE: Please use the following naming style for new pin entries.
27 * For example, W8_1610_MMC2_DAT0, where:
28 * - W8 = ball
29 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
30 * - MMC2_DAT0 = function
31 */
32
33 #ifndef __ASM_ARCH_MUX_H
34 #define __ASM_ARCH_MUX_H
35
36 #define PU_PD_SEL_NA 0 /* No pu_pd reg available */
37 #define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
38
39 #ifdef CONFIG_OMAP_MUX_DEBUG
40 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
41 .mux_reg = FUNC_MUX_CTRL_##reg, \
42 .mask_offset = mode_offset, \
43 .mask = mode,
44
45 #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
46 .pull_reg = PULL_DWN_CTRL_##reg, \
47 .pull_bit = bit, \
48 .pull_val = status,
49
50 #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
51 .pu_pd_reg = PU_PD_SEL_##reg, \
52 .pu_pd_val = status,
53
54 #define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
55 .mux_reg = OMAP730_IO_CONF_##reg, \
56 .mask_offset = mode_offset, \
57 .mask = mode,
58
59 #define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \
60 .pull_reg = OMAP730_IO_CONF_##reg, \
61 .pull_bit = bit, \
62 .pull_val = status,
63
64 #define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
65 .mux_reg = OMAP850_IO_CONF_##reg, \
66 .mask_offset = mode_offset, \
67 .mask = mode,
68
69 #define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \
70 .pull_reg = OMAP850_IO_CONF_##reg, \
71 .pull_bit = bit, \
72 .pull_val = status,
73
74 #else
75
76 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
77 .mask_offset = mode_offset, \
78 .mask = mode,
79
80 #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
81 .pull_bit = bit, \
82 .pull_val = status,
83
84 #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
85 .pu_pd_val = status,
86
87 #define MUX_REG_730(reg, mode_offset, mode) \
88 .mux_reg = OMAP730_IO_CONF_##reg, \
89 .mask_offset = mode_offset, \
90 .mask = mode,
91
92 #define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \
93 .pull_bit = bit, \
94 .pull_val = status,
95
96 #define MUX_REG_850(reg, mode_offset, mode) \
97 .mux_reg = OMAP850_IO_CONF_##reg, \
98 .mask_offset = mode_offset, \
99 .mask = mode,
100
101 #define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \
102 .pull_bit = bit, \
103 .pull_val = status,
104
105 #endif /* CONFIG_OMAP_MUX_DEBUG */
106
107 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \
108 pull_reg, pull_bit, pull_status, \
109 pu_pd_reg, pu_pd_status, debug_status) \
110 { \
111 .name = desc, \
112 .debug = debug_status, \
113 MUX_REG(mux_reg, mode_offset, mode) \
114 PULL_REG(pull_reg, pull_bit, pull_status) \
115 PU_PD_REG(pu_pd_reg, pu_pd_status) \
116 },
117
118
119 /*
120 * OMAP730/850 has a slightly different config for the pin mux.
121 * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
122 * not the FUNC_MUX_CTRL_x regs from hardware.h
123 * - for pull-up/down, only has one enable bit which is is in the same register
124 * as mux config
125 */
126 #define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \
127 pull_bit, pull_status, debug_status)\
128 { \
129 .name = desc, \
130 .debug = debug_status, \
131 MUX_REG_730(mux_reg, mode_offset, mode) \
132 PULL_REG_730(mux_reg, pull_bit, pull_status) \
133 PU_PD_REG(NA, 0) \
134 },
135
136 #define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \
137 pull_bit, pull_status, debug_status)\
138 { \
139 .name = desc, \
140 .debug = debug_status, \
141 MUX_REG_850(mux_reg, mode_offset, mode) \
142 PULL_REG_850(mux_reg, pull_bit, pull_status) \
143 PU_PD_REG(NA, 0) \
144 },
145
146
147 #define MUX_CFG_24XX(desc, reg_offset, mode, \
148 pull_en, pull_mode, dbg) \
149 { \
150 .name = desc, \
151 .debug = dbg, \
152 .mux_reg = reg_offset, \
153 .mask = mode, \
154 .pull_val = pull_en, \
155 .pu_pd_val = pull_mode, \
156 },
157
158 /* 24xx/34xx mux bit defines */
159 #define OMAP2_PULL_ENA (1 << 3)
160 #define OMAP2_PULL_UP (1 << 4)
161 #define OMAP2_ALTELECTRICALSEL (1 << 5)
162
163 /* 34xx specific mux bit defines */
164 #define OMAP3_INPUT_EN (1 << 8)
165 #define OMAP3_OFF_EN (1 << 9)
166 #define OMAP3_OFFOUT_EN (1 << 10)
167 #define OMAP3_OFFOUT_VAL (1 << 11)
168 #define OMAP3_OFF_PULL_EN (1 << 12)
169 #define OMAP3_OFF_PULL_UP (1 << 13)
170 #define OMAP3_WAKEUP_EN (1 << 14)
171
172 /* 34xx mux mode options for each pin. See TRM for options */
173 #define OMAP34XX_MUX_MODE0 0
174 #define OMAP34XX_MUX_MODE1 1
175 #define OMAP34XX_MUX_MODE2 2
176 #define OMAP34XX_MUX_MODE3 3
177 #define OMAP34XX_MUX_MODE4 4
178 #define OMAP34XX_MUX_MODE5 5
179 #define OMAP34XX_MUX_MODE6 6
180 #define OMAP34XX_MUX_MODE7 7
181
182 /* 34xx active pin states */
183 #define OMAP34XX_PIN_OUTPUT 0
184 #define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
185 #define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
186 | OMAP2_PULL_UP)
187 #define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
188
189 /* 34xx off mode states */
190 #define OMAP34XX_PIN_OFF_NONE 0
191 #define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
192 | OMAP3_OFFOUT_VAL)
193 #define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
194 #define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
195 | OMAP3_OFF_PULL_UP)
196 #define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
197 #define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
198
199 #define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
200 .name = desc, \
201 .debug = 0, \
202 .mux_reg = reg_offset, \
203 .mux_val = mux_value \
204 },
205
206 struct pin_config {
207 char *name;
208 const unsigned int mux_reg;
209 unsigned char debug;
210
211 #if defined(CONFIG_ARCH_OMAP34XX)
212 u16 mux_val; /* Wake-up, off mode, pull, mux mode */
213 #endif
214
215 #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
216 const unsigned char mask_offset;
217 const unsigned char mask;
218
219 const char *pull_name;
220 const unsigned int pull_reg;
221 const unsigned char pull_val;
222 const unsigned char pull_bit;
223
224 const char *pu_pd_name;
225 const unsigned int pu_pd_reg;
226 const unsigned char pu_pd_val;
227 #endif
228
229 #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
230 const char *mux_reg_name;
231 #endif
232
233 };
234
235 enum omap730_index {
236 /* OMAP 730 keyboard */
237 E2_730_KBR0,
238 J7_730_KBR1,
239 E1_730_KBR2,
240 F3_730_KBR3,
241 D2_730_KBR4,
242 C2_730_KBC0,
243 D3_730_KBC1,
244 E4_730_KBC2,
245 F4_730_KBC3,
246 E3_730_KBC4,
247
248 /* USB */
249 AA17_730_USB_DM,
250 W16_730_USB_PU_EN,
251 W17_730_USB_VBUSI,
252 };
253
254 enum omap850_index {
255 /* OMAP 850 keyboard */
256 E2_850_KBR0,
257 J7_850_KBR1,
258 E1_850_KBR2,
259 F3_850_KBR3,
260 D2_850_KBR4,
261 C2_850_KBC0,
262 D3_850_KBC1,
263 E4_850_KBC2,
264 F4_850_KBC3,
265 E3_850_KBC4,
266
267 /* USB */
268 AA17_850_USB_DM,
269 W16_850_USB_PU_EN,
270 W17_850_USB_VBUSI,
271 };
272
273
274 enum omap1xxx_index {
275 /* UART1 (BT_UART_GATING)*/
276 UART1_TX = 0,
277 UART1_RTS,
278
279 /* UART2 (COM_UART_GATING)*/
280 UART2_TX,
281 UART2_RX,
282 UART2_CTS,
283 UART2_RTS,
284
285 /* UART3 (GIGA_UART_GATING) */
286 UART3_TX,
287 UART3_RX,
288 UART3_CTS,
289 UART3_RTS,
290 UART3_CLKREQ,
291 UART3_BCLK, /* 12MHz clock out */
292 Y15_1610_UART3_RTS,
293
294 /* PWT & PWL */
295 PWT,
296 PWL,
297
298 /* USB master generic */
299 R18_USB_VBUS,
300 R18_1510_USB_GPIO0,
301 W4_USB_PUEN,
302 W4_USB_CLKO,
303 W4_USB_HIGHZ,
304 W4_GPIO58,
305
306 /* USB1 master */
307 USB1_SUSP,
308 USB1_SEO,
309 W13_1610_USB1_SE0,
310 USB1_TXEN,
311 USB1_TXD,
312 USB1_VP,
313 USB1_VM,
314 USB1_RCV,
315 USB1_SPEED,
316 R13_1610_USB1_SPEED,
317 R13_1710_USB1_SE0,
318
319 /* USB2 master */
320 USB2_SUSP,
321 USB2_VP,
322 USB2_TXEN,
323 USB2_VM,
324 USB2_RCV,
325 USB2_SEO,
326 USB2_TXD,
327
328 /* OMAP-1510 GPIO */
329 R18_1510_GPIO0,
330 R19_1510_GPIO1,
331 M14_1510_GPIO2,
332
333 /* OMAP1610 GPIO */
334 P18_1610_GPIO3,
335 Y15_1610_GPIO17,
336
337 /* OMAP-1710 GPIO */
338 R18_1710_GPIO0,
339 V2_1710_GPIO10,
340 N21_1710_GPIO14,
341 W15_1710_GPIO40,
342
343 /* MPUIO */
344 MPUIO2,
345 N15_1610_MPUIO2,
346 MPUIO4,
347 MPUIO5,
348 T20_1610_MPUIO5,
349 W11_1610_MPUIO6,
350 V10_1610_MPUIO7,
351 W11_1610_MPUIO9,
352 V10_1610_MPUIO10,
353 W10_1610_MPUIO11,
354 E20_1610_MPUIO13,
355 U20_1610_MPUIO14,
356 E19_1610_MPUIO15,
357
358 /* MCBSP2 */
359 MCBSP2_CLKR,
360 MCBSP2_CLKX,
361 MCBSP2_DR,
362 MCBSP2_DX,
363 MCBSP2_FSR,
364 MCBSP2_FSX,
365
366 /* MCBSP3 */
367 MCBSP3_CLKX,
368
369 /* Misc ballouts */
370 BALLOUT_V8_ARMIO3,
371 N20_HDQ,
372
373 /* OMAP-1610 MMC2 */
374 W8_1610_MMC2_DAT0,
375 V8_1610_MMC2_DAT1,
376 W15_1610_MMC2_DAT2,
377 R10_1610_MMC2_DAT3,
378 Y10_1610_MMC2_CLK,
379 Y8_1610_MMC2_CMD,
380 V9_1610_MMC2_CMDDIR,
381 V5_1610_MMC2_DATDIR0,
382 W19_1610_MMC2_DATDIR1,
383 R18_1610_MMC2_CLKIN,
384
385 /* OMAP-1610 External Trace Interface */
386 M19_1610_ETM_PSTAT0,
387 L15_1610_ETM_PSTAT1,
388 L18_1610_ETM_PSTAT2,
389 L19_1610_ETM_D0,
390 J19_1610_ETM_D6,
391 J18_1610_ETM_D7,
392
393 /* OMAP16XX GPIO */
394 P20_1610_GPIO4,
395 V9_1610_GPIO7,
396 W8_1610_GPIO9,
397 N20_1610_GPIO11,
398 N19_1610_GPIO13,
399 P10_1610_GPIO22,
400 V5_1610_GPIO24,
401 AA20_1610_GPIO_41,
402 W19_1610_GPIO48,
403 M7_1610_GPIO62,
404 V14_16XX_GPIO37,
405 R9_16XX_GPIO18,
406 L14_16XX_GPIO49,
407
408 /* OMAP-1610 uWire */
409 V19_1610_UWIRE_SCLK,
410 U18_1610_UWIRE_SDI,
411 W21_1610_UWIRE_SDO,
412 N14_1610_UWIRE_CS0,
413 P15_1610_UWIRE_CS3,
414 N15_1610_UWIRE_CS1,
415
416 /* OMAP-1610 SPI */
417 U19_1610_SPIF_SCK,
418 U18_1610_SPIF_DIN,
419 P20_1610_SPIF_DIN,
420 W21_1610_SPIF_DOUT,
421 R18_1610_SPIF_DOUT,
422 N14_1610_SPIF_CS0,
423 N15_1610_SPIF_CS1,
424 T19_1610_SPIF_CS2,
425 P15_1610_SPIF_CS3,
426
427 /* OMAP-1610 Flash */
428 L3_1610_FLASH_CS2B_OE,
429 M8_1610_FLASH_CS2B_WE,
430
431 /* First MMC */
432 MMC_CMD,
433 MMC_DAT1,
434 MMC_DAT2,
435 MMC_DAT0,
436 MMC_CLK,
437 MMC_DAT3,
438
439 /* OMAP-1710 MMC CMDDIR and DATDIR0 */
440 M15_1710_MMC_CLKI,
441 P19_1710_MMC_CMDDIR,
442 P20_1710_MMC_DATDIR0,
443
444 /* OMAP-1610 USB0 alternate pin configuration */
445 W9_USB0_TXEN,
446 AA9_USB0_VP,
447 Y5_USB0_RCV,
448 R9_USB0_VM,
449 V6_USB0_TXD,
450 W5_USB0_SE0,
451 V9_USB0_SPEED,
452 V9_USB0_SUSP,
453
454 /* USB2 */
455 W9_USB2_TXEN,
456 AA9_USB2_VP,
457 Y5_USB2_RCV,
458 R9_USB2_VM,
459 V6_USB2_TXD,
460 W5_USB2_SE0,
461
462 /* 16XX UART */
463 R13_1610_UART1_TX,
464 V14_16XX_UART1_RX,
465 R14_1610_UART1_CTS,
466 AA15_1610_UART1_RTS,
467 R9_16XX_UART2_RX,
468 L14_16XX_UART3_RX,
469
470 /* I2C OMAP-1610 */
471 I2C_SCL,
472 I2C_SDA,
473
474 /* Keypad */
475 F18_1610_KBC0,
476 D20_1610_KBC1,
477 D19_1610_KBC2,
478 E18_1610_KBC3,
479 C21_1610_KBC4,
480 G18_1610_KBR0,
481 F19_1610_KBR1,
482 H14_1610_KBR2,
483 E20_1610_KBR3,
484 E19_1610_KBR4,
485 N19_1610_KBR5,
486
487 /* Power management */
488 T20_1610_LOW_PWR,
489
490 /* MCLK Settings */
491 V5_1710_MCLK_ON,
492 V5_1710_MCLK_OFF,
493 R10_1610_MCLK_ON,
494 R10_1610_MCLK_OFF,
495
496 /* CompactFlash controller */
497 P11_1610_CF_CD2,
498 R11_1610_CF_IOIS16,
499 V10_1610_CF_IREQ,
500 W10_1610_CF_RESET,
501 W11_1610_CF_CD1,
502
503 /* parallel camera */
504 J15_1610_CAM_LCLK,
505 J18_1610_CAM_D7,
506 J19_1610_CAM_D6,
507 J14_1610_CAM_D5,
508 K18_1610_CAM_D4,
509 K19_1610_CAM_D3,
510 K15_1610_CAM_D2,
511 K14_1610_CAM_D1,
512 L19_1610_CAM_D0,
513 L18_1610_CAM_VS,
514 L15_1610_CAM_HS,
515 M19_1610_CAM_RSTZ,
516 Y15_1610_CAM_OUTCLK,
517
518 /* serial camera */
519 H19_1610_CAM_EXCLK,
520 Y12_1610_CCP_CLKP,
521 W13_1610_CCP_CLKM,
522 W14_1610_CCP_DATAP,
523 Y14_1610_CCP_DATAM,
524
525 };
526
527 enum omap24xx_index {
528 /* 24xx I2C */
529 M19_24XX_I2C1_SCL,
530 L15_24XX_I2C1_SDA,
531 J15_24XX_I2C2_SCL,
532 H19_24XX_I2C2_SDA,
533
534 /* 24xx Menelaus interrupt */
535 W19_24XX_SYS_NIRQ,
536
537 /* 24xx clock */
538 W14_24XX_SYS_CLKOUT,
539
540 /* 24xx GPMC chipselects, wait pin monitoring */
541 E2_GPMC_NCS2,
542 L2_GPMC_NCS7,
543 L3_GPMC_WAIT0,
544 N7_GPMC_WAIT1,
545 M1_GPMC_WAIT2,
546 P1_GPMC_WAIT3,
547
548 /* 242X McBSP */
549 Y15_24XX_MCBSP2_CLKX,
550 R14_24XX_MCBSP2_FSX,
551 W15_24XX_MCBSP2_DR,
552 V15_24XX_MCBSP2_DX,
553
554 /* 24xx GPIO */
555 M21_242X_GPIO11,
556 P21_242X_GPIO12,
557 AA10_242X_GPIO13,
558 AA6_242X_GPIO14,
559 AA4_242X_GPIO15,
560 Y11_242X_GPIO16,
561 AA12_242X_GPIO17,
562 AA8_242X_GPIO58,
563 Y20_24XX_GPIO60,
564 W4__24XX_GPIO74,
565 N15_24XX_GPIO85,
566 M15_24XX_GPIO92,
567 P20_24XX_GPIO93,
568 P18_24XX_GPIO95,
569 M18_24XX_GPIO96,
570 L14_24XX_GPIO97,
571 J15_24XX_GPIO99,
572 V14_24XX_GPIO117,
573 P14_24XX_GPIO125,
574
575 /* 242x DBG GPIO */
576 V4_242X_GPIO49,
577 W2_242X_GPIO50,
578 U4_242X_GPIO51,
579 V3_242X_GPIO52,
580 V2_242X_GPIO53,
581 V6_242X_GPIO53,
582 T4_242X_GPIO54,
583 Y4_242X_GPIO54,
584 T3_242X_GPIO55,
585 U2_242X_GPIO56,
586
587 /* 24xx external DMA requests */
588 AA10_242X_DMAREQ0,
589 AA6_242X_DMAREQ1,
590 E4_242X_DMAREQ2,
591 G4_242X_DMAREQ3,
592 D3_242X_DMAREQ4,
593 E3_242X_DMAREQ5,
594
595 /* UART3 */
596 K15_24XX_UART3_TX,
597 K14_24XX_UART3_RX,
598
599 /* MMC/SDIO */
600 G19_24XX_MMC_CLKO,
601 H18_24XX_MMC_CMD,
602 F20_24XX_MMC_DAT0,
603 H14_24XX_MMC_DAT1,
604 E19_24XX_MMC_DAT2,
605 D19_24XX_MMC_DAT3,
606 F19_24XX_MMC_DAT_DIR0,
607 E20_24XX_MMC_DAT_DIR1,
608 F18_24XX_MMC_DAT_DIR2,
609 E18_24XX_MMC_DAT_DIR3,
610 G18_24XX_MMC_CMD_DIR,
611 H15_24XX_MMC_CLKI,
612
613 /* Full speed USB */
614 J20_24XX_USB0_PUEN,
615 J19_24XX_USB0_VP,
616 K20_24XX_USB0_VM,
617 J18_24XX_USB0_RCV,
618 K19_24XX_USB0_TXEN,
619 J14_24XX_USB0_SE0,
620 K18_24XX_USB0_DAT,
621
622 N14_24XX_USB1_SE0,
623 W12_24XX_USB1_SE0,
624 P15_24XX_USB1_DAT,
625 R13_24XX_USB1_DAT,
626 W20_24XX_USB1_TXEN,
627 P13_24XX_USB1_TXEN,
628 V19_24XX_USB1_RCV,
629 V12_24XX_USB1_RCV,
630
631 AA10_24XX_USB2_SE0,
632 Y11_24XX_USB2_DAT,
633 AA12_24XX_USB2_TXEN,
634 AA6_24XX_USB2_RCV,
635 AA4_24XX_USB2_TLLSE0,
636
637 /* Keypad GPIO*/
638 T19_24XX_KBR0,
639 R19_24XX_KBR1,
640 V18_24XX_KBR2,
641 M21_24XX_KBR3,
642 E5__24XX_KBR4,
643 M18_24XX_KBR5,
644 R20_24XX_KBC0,
645 M14_24XX_KBC1,
646 H19_24XX_KBC2,
647 V17_24XX_KBC3,
648 P21_24XX_KBC4,
649 L14_24XX_KBC5,
650 N19_24XX_KBC6,
651
652 /* 24xx Menelaus Keypad GPIO */
653 B3__24XX_KBR5,
654 AA4_24XX_KBC2,
655 B13_24XX_KBC6,
656
657 /* 2430 USB */
658 AD9_2430_USB0_PUEN,
659 Y11_2430_USB0_VP,
660 AD7_2430_USB0_VM,
661 AE7_2430_USB0_RCV,
662 AD4_2430_USB0_TXEN,
663 AF9_2430_USB0_SE0,
664 AE6_2430_USB0_DAT,
665 AD24_2430_USB1_SE0,
666 AB24_2430_USB1_RCV,
667 Y25_2430_USB1_TXEN,
668 AA26_2430_USB1_DAT,
669
670 /* 2430 HS-USB */
671 AD9_2430_USB0HS_DATA3,
672 Y11_2430_USB0HS_DATA4,
673 AD7_2430_USB0HS_DATA5,
674 AE7_2430_USB0HS_DATA6,
675 AD4_2430_USB0HS_DATA2,
676 AF9_2430_USB0HS_DATA0,
677 AE6_2430_USB0HS_DATA1,
678 AE8_2430_USB0HS_CLK,
679 AD8_2430_USB0HS_DIR,
680 AE5_2430_USB0HS_STP,
681 AE9_2430_USB0HS_NXT,
682 AC7_2430_USB0HS_DATA7,
683
684 /* 2430 McBSP */
685 AD6_2430_MCBSP_CLKS,
686
687 AB2_2430_MCBSP1_CLKR,
688 AD5_2430_MCBSP1_FSR,
689 AA1_2430_MCBSP1_DX,
690 AF3_2430_MCBSP1_DR,
691 AB3_2430_MCBSP1_FSX,
692 Y9_2430_MCBSP1_CLKX,
693
694 AC10_2430_MCBSP2_FSX,
695 AD16_2430_MCBSP2_CLX,
696 AE13_2430_MCBSP2_DX,
697 AD13_2430_MCBSP2_DR,
698 AC10_2430_MCBSP2_FSX_OFF,
699 AD16_2430_MCBSP2_CLX_OFF,
700 AE13_2430_MCBSP2_DX_OFF,
701 AD13_2430_MCBSP2_DR_OFF,
702
703 AC9_2430_MCBSP3_CLKX,
704 AE4_2430_MCBSP3_FSX,
705 AE2_2430_MCBSP3_DR,
706 AF4_2430_MCBSP3_DX,
707
708 N3_2430_MCBSP4_CLKX,
709 AD23_2430_MCBSP4_DR,
710 AB25_2430_MCBSP4_DX,
711 AC25_2430_MCBSP4_FSX,
712
713 AE16_2430_MCBSP5_CLKX,
714 AF12_2430_MCBSP5_FSX,
715 K7_2430_MCBSP5_DX,
716 M1_2430_MCBSP5_DR,
717
718 /* 2430 McSPI*/
719 Y18_2430_MCSPI1_CLK,
720 AD15_2430_MCSPI1_SIMO,
721 AE17_2430_MCSPI1_SOMI,
722 U1_2430_MCSPI1_CS0,
723
724 /* Touchscreen GPIO */
725 AF19_2430_GPIO_85,
726
727 };
728
729 enum omap34xx_index {
730 /* 34xx I2C */
731 K21_34XX_I2C1_SCL,
732 J21_34XX_I2C1_SDA,
733 AF15_34XX_I2C2_SCL,
734 AE15_34XX_I2C2_SDA,
735 AF14_34XX_I2C3_SCL,
736 AG14_34XX_I2C3_SDA,
737 AD26_34XX_I2C4_SCL,
738 AE26_34XX_I2C4_SDA,
739
740 /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
741 Y8_3430_USB1HS_PHY_CLK,
742 Y9_3430_USB1HS_PHY_STP,
743 AA14_3430_USB1HS_PHY_DIR,
744 AA11_3430_USB1HS_PHY_NXT,
745 W13_3430_USB1HS_PHY_DATA0,
746 W12_3430_USB1HS_PHY_DATA1,
747 W11_3430_USB1HS_PHY_DATA2,
748 Y11_3430_USB1HS_PHY_DATA3,
749 W9_3430_USB1HS_PHY_DATA4,
750 Y12_3430_USB1HS_PHY_DATA5,
751 W8_3430_USB1HS_PHY_DATA6,
752 Y13_3430_USB1HS_PHY_DATA7,
753
754 /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
755 AA8_3430_USB2HS_PHY_CLK,
756 AA10_3430_USB2HS_PHY_STP,
757 AA9_3430_USB2HS_PHY_DIR,
758 AB11_3430_USB2HS_PHY_NXT,
759 AB10_3430_USB2HS_PHY_DATA0,
760 AB9_3430_USB2HS_PHY_DATA1,
761 W3_3430_USB2HS_PHY_DATA2,
762 T4_3430_USB2HS_PHY_DATA3,
763 T3_3430_USB2HS_PHY_DATA4,
764 R3_3430_USB2HS_PHY_DATA5,
765 R4_3430_USB2HS_PHY_DATA6,
766 T2_3430_USB2HS_PHY_DATA7,
767
768
769 /* TLL - HSUSB: 12-pin TLL Port 1*/
770 Y8_3430_USB1HS_TLL_CLK,
771 Y9_3430_USB1HS_TLL_STP,
772 AA14_3430_USB1HS_TLL_DIR,
773 AA11_3430_USB1HS_TLL_NXT,
774 W13_3430_USB1HS_TLL_DATA0,
775 W12_3430_USB1HS_TLL_DATA1,
776 W11_3430_USB1HS_TLL_DATA2,
777 Y11_3430_USB1HS_TLL_DATA3,
778 W9_3430_USB1HS_TLL_DATA4,
779 Y12_3430_USB1HS_TLL_DATA5,
780 W8_3430_USB1HS_TLL_DATA6,
781 Y13_3430_USB1HS_TLL_DATA7,
782
783 /* TLL - HSUSB: 12-pin TLL Port 2*/
784 AA8_3430_USB2HS_TLL_CLK,
785 AA10_3430_USB2HS_TLL_STP,
786 AA9_3430_USB2HS_TLL_DIR,
787 AB11_3430_USB2HS_TLL_NXT,
788 AB10_3430_USB2HS_TLL_DATA0,
789 AB9_3430_USB2HS_TLL_DATA1,
790 W3_3430_USB2HS_TLL_DATA2,
791 T4_3430_USB2HS_TLL_DATA3,
792 T3_3430_USB2HS_TLL_DATA4,
793 R3_3430_USB2HS_TLL_DATA5,
794 R4_3430_USB2HS_TLL_DATA6,
795 T2_3430_USB2HS_TLL_DATA7,
796
797 /* TLL - HSUSB: 12-pin TLL Port 3*/
798 AA6_3430_USB3HS_TLL_CLK,
799 AB3_3430_USB3HS_TLL_STP,
800 AA3_3430_USB3HS_TLL_DIR,
801 Y3_3430_USB3HS_TLL_NXT,
802 AA5_3430_USB3HS_TLL_DATA0,
803 Y4_3430_USB3HS_TLL_DATA1,
804 Y5_3430_USB3HS_TLL_DATA2,
805 W5_3430_USB3HS_TLL_DATA3,
806 AB12_3430_USB3HS_TLL_DATA4,
807 AB13_3430_USB3HS_TLL_DATA5,
808 AA13_3430_USB3HS_TLL_DATA6,
809 AA12_3430_USB3HS_TLL_DATA7,
810
811 /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
812 AF10_3430_USB1FS_PHY_MM1_RXDP,
813 AG9_3430_USB1FS_PHY_MM1_RXDM,
814 W13_3430_USB1FS_PHY_MM1_RXRCV,
815 W12_3430_USB1FS_PHY_MM1_TXSE0,
816 W11_3430_USB1FS_PHY_MM1_TXDAT,
817 Y11_3430_USB1FS_PHY_MM1_TXEN_N,
818
819 /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
820 AF7_3430_USB2FS_PHY_MM2_RXDP,
821 AH7_3430_USB2FS_PHY_MM2_RXDM,
822 AB10_3430_USB2FS_PHY_MM2_RXRCV,
823 AB9_3430_USB2FS_PHY_MM2_TXSE0,
824 W3_3430_USB2FS_PHY_MM2_TXDAT,
825 T4_3430_USB2FS_PHY_MM2_TXEN_N,
826
827 /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
828 AH3_3430_USB3FS_PHY_MM3_RXDP,
829 AE3_3430_USB3FS_PHY_MM3_RXDM,
830 AD1_3430_USB3FS_PHY_MM3_RXRCV,
831 AE1_3430_USB3FS_PHY_MM3_TXSE0,
832 AD2_3430_USB3FS_PHY_MM3_TXDAT,
833 AC1_3430_USB3FS_PHY_MM3_TXEN_N,
834
835 /* 34xx GPIO
836 * - normally these are bidirectional, no internal pullup/pulldown
837 * - "_UP" suffix (GPIO3_UP) if internal pullup is configured
838 * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
839 * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
840 */
841 AF26_34XX_GPIO0,
842 AF22_34XX_GPIO9,
843 AH8_34XX_GPIO29,
844 U8_34XX_GPIO54_OUT,
845 U8_34XX_GPIO54_DOWN,
846 L8_34XX_GPIO63,
847 G25_34XX_GPIO86_OUT,
848 AG4_34XX_GPIO134_OUT,
849 AE4_34XX_GPIO136_OUT,
850 AF6_34XX_GPIO140_UP,
851 AE6_34XX_GPIO141,
852 AF5_34XX_GPIO142,
853 AE5_34XX_GPIO143,
854 H19_34XX_GPIO164_OUT,
855 J25_34XX_GPIO170,
856
857 /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
858 H16_34XX_SDRC_CKE0,
859 H17_34XX_SDRC_CKE1,
860 };
861
862 struct omap_mux_cfg {
863 struct pin_config *pins;
864 unsigned long size;
865 int (*cfg_reg)(const struct pin_config *cfg);
866 };
867
868 #ifdef CONFIG_OMAP_MUX
869 /* setup pin muxing in Linux */
870 extern int omap1_mux_init(void);
871 extern int omap2_mux_init(void);
872 extern int omap_mux_register(struct omap_mux_cfg *);
873 extern int omap_cfg_reg(unsigned long reg_cfg);
874 #else
875 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
876 static inline int omap1_mux_init(void) { return 0; }
877 static inline int omap2_mux_init(void) { return 0; }
878 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
879 #endif
880
881 #endif
Linux with added FPC-III support