arch/blackfin/include/asm/cacheflush.h

   1 /*
   2  * File:         include/asm-blackfin/cacheflush.h
   3  * Based on:     include/asm-m68knommu/cacheflush.h
   4  * Author:       LG Soft India
   5  *               Copyright (C) 2004 Analog Devices Inc.
   6  * Created:      Tue Sep 21 2004
   7  * Description:  Blackfin low-level cache routines adapted from the i386
   8  *               and PPC versions by Greg Ungerer (gerg@snapgear.com)
   9  *
  10  * Modified:
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2, or (at your option)
  17  * any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; see the file COPYING.
  26  * If not, write to the Free Software Foundation,
  27  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  28  */
  29
  30 #ifndef _BLACKFIN_CACHEFLUSH_H
  31 #define _BLACKFIN_CACHEFLUSH_H
  32
  33 #include <asm/blackfin.h>       /* for SSYNC() */
  34
  35 extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
  36 extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
  37 extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
  38 extern void blackfin_dflush_page(void *page);
  39 extern void blackfin_invalidate_entire_dcache(void);
  40 extern void blackfin_invalidate_entire_icache(void);
  41
  42 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
  43 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
  44 #define flush_cache_mm(mm)                      do { } while (0)
  45 #define flush_cache_range(vma, start, end)      do { } while (0)
  46 #define flush_cache_page(vma, vmaddr)           do { } while (0)
  47 #define flush_cache_vmap(start, end)            do { } while (0)
  48 #define flush_cache_vunmap(start, end)          do { } while (0)
  49
  50 #ifdef CONFIG_SMP
  51 #define flush_icache_range_others(start, end)   \
  52         smp_icache_flush_range_others((start), (end))
  53 #else
  54 #define flush_icache_range_others(start, end)   do { } while (0)
  55 #endif
  56
  57 static inline void flush_icache_range(unsigned start, unsigned end)
  58 {
  59 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
  60         blackfin_dcache_flush_range(start, end);
  61 #endif
  62
  63         /* Make sure all write buffers in the data side of the core
  64          * are flushed before trying to invalidate the icache.  This
  65          * needs to be after the data flush and before the icache
  66          * flush so that the SSYNC does the right thing in preventing
  67          * the instruction prefetcher from hitting things in cached
  68          * memory at the wrong time -- it runs much further ahead than
  69          * the pipeline.
  70          */
  71         SSYNC();
  72 #if defined(CONFIG_BFIN_ICACHE)
  73         blackfin_icache_flush_range(start, end);
  74         flush_icache_range_others(start, end);
  75 #endif
  76 }
  77
  78 #define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
  79 do { memcpy(dst, src, len);                                             \
  80      flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len));    \
  81 } while (0)
  82
  83 #define copy_from_user_page(vma, page, vaddr, dst, src, len)    memcpy(dst, src, len)
  84
  85 #if defined(CONFIG_BFIN_DCACHE)
  86 # define invalidate_dcache_range(start,end)     blackfin_dcache_invalidate_range((start), (end))
  87 #else
  88 # define invalidate_dcache_range(start,end)     do { } while (0)
  89 #endif
  90 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
  91 # define flush_dcache_range(start,end)          blackfin_dcache_flush_range((start), (end))
  92 # define flush_dcache_page(page)                blackfin_dflush_page(page_address(page))
  93 #else
  94 # define flush_dcache_range(start,end)          do { } while (0)
  95 # define flush_dcache_page(page)                do { } while (0)
  96 #endif
  97
  98 extern unsigned long reserved_mem_dcache_on;
  99 extern unsigned long reserved_mem_icache_on;
 100
 101 static inline int bfin_addr_dcacheable(unsigned long addr)
 102 {
 103 #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
 104         if (addr < (_ramend - DMA_UNCACHED_REGION))
 105                 return 1;
 106 #endif
 107
 108         if (reserved_mem_dcache_on &&
 109                 addr >= _ramend && addr < physical_mem_end)
 110                 return 1;
 111
 112 #ifdef CONFIG_BFIN_L2_DCACHEABLE
 113         if (addr >= L2_START && addr < L2_START + L2_LENGTH)
 114                 return 1;
 115 #endif
 116
 117         return 0;
 118 }
 119
 120 #endif                          /* _BLACKFIN_ICACHEFLUSH_H */