Linux 2.6.31.6
[linux/fpc-iii.git] / arch / microblaze / kernel / intc.c
blob6eea6f92b84e19780b781bdad3da277fed57a4bb
1 /*
2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
4 * Copyright (C) 2006 Atmark Techno, Inc.
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
11 #include <linux/init.h>
12 #include <linux/irq.h>
13 #include <asm/page.h>
14 #include <linux/io.h>
15 #include <linux/bug.h>
17 #include <asm/prom.h>
18 #include <asm/irq.h>
20 #ifdef CONFIG_SELFMOD_INTC
21 #include <asm/selfmod.h>
22 #define INTC_BASE BARRIER_BASE_ADDR
23 #else
24 static unsigned int intc_baseaddr;
25 #define INTC_BASE intc_baseaddr
26 #endif
28 unsigned int nr_irq;
30 /* No one else should require these constants, so define them locally here. */
31 #define ISR 0x00 /* Interrupt Status Register */
32 #define IPR 0x04 /* Interrupt Pending Register */
33 #define IER 0x08 /* Interrupt Enable Register */
34 #define IAR 0x0c /* Interrupt Acknowledge Register */
35 #define SIE 0x10 /* Set Interrupt Enable bits */
36 #define CIE 0x14 /* Clear Interrupt Enable bits */
37 #define IVR 0x18 /* Interrupt Vector Register */
38 #define MER 0x1c /* Master Enable Register */
40 #define MER_ME (1<<0)
41 #define MER_HIE (1<<1)
43 static void intc_enable_or_unmask(unsigned int irq)
45 pr_debug("enable_or_unmask: %d\n", irq);
46 out_be32(INTC_BASE + SIE, 1 << irq);
49 static void intc_disable_or_mask(unsigned int irq)
51 pr_debug("disable: %d\n", irq);
52 out_be32(INTC_BASE + CIE, 1 << irq);
55 static void intc_ack(unsigned int irq)
57 pr_debug("ack: %d\n", irq);
58 out_be32(INTC_BASE + IAR, 1 << irq);
61 static void intc_mask_ack(unsigned int irq)
63 unsigned long mask = 1 << irq;
64 pr_debug("disable_and_ack: %d\n", irq);
65 out_be32(INTC_BASE + CIE, mask);
66 out_be32(INTC_BASE + IAR, mask);
69 static void intc_end(unsigned int irq)
71 unsigned long mask = 1 << irq;
72 pr_debug("end: %d\n", irq);
73 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
74 out_be32(INTC_BASE + SIE, mask);
75 /* ack level sensitive intr */
76 if (irq_desc[irq].status & IRQ_LEVEL)
77 out_be32(INTC_BASE + IAR, mask);
81 static struct irq_chip intc_dev = {
82 .name = "Xilinx INTC",
83 .unmask = intc_enable_or_unmask,
84 .mask = intc_disable_or_mask,
85 .ack = intc_ack,
86 .mask_ack = intc_mask_ack,
87 .end = intc_end,
90 unsigned int get_irq(struct pt_regs *regs)
92 int irq;
95 * NOTE: This function is the one that needs to be improved in
96 * order to handle multiple interrupt controllers. It currently
97 * is hardcoded to check for interrupts only on the first INTC.
99 irq = in_be32(INTC_BASE + IVR);
100 pr_debug("get_irq: %d\n", irq);
102 return irq;
105 void __init init_IRQ(void)
107 u32 i, j, intr_type;
108 struct device_node *intc = NULL;
109 #ifdef CONFIG_SELFMOD_INTC
110 unsigned int intc_baseaddr = 0;
111 static int arr_func[] = {
112 (int)&get_irq,
113 (int)&intc_enable_or_unmask,
114 (int)&intc_disable_or_mask,
115 (int)&intc_mask_ack,
116 (int)&intc_ack,
117 (int)&intc_end,
120 #endif
121 static char *intc_list[] = {
122 "xlnx,xps-intc-1.00.a",
123 "xlnx,opb-intc-1.00.c",
124 "xlnx,opb-intc-1.00.b",
125 "xlnx,opb-intc-1.00.a",
126 NULL
129 for (j = 0; intc_list[j] != NULL; j++) {
130 intc = of_find_compatible_node(NULL, NULL, intc_list[j]);
131 if (intc)
132 break;
134 BUG_ON(!intc);
136 intc_baseaddr = *(int *) of_get_property(intc, "reg", NULL);
137 intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
138 nr_irq = *(int *) of_get_property(intc, "xlnx,num-intr-inputs", NULL);
140 intr_type =
141 *(int *) of_get_property(intc, "xlnx,kind-of-intr", NULL);
142 if (intr_type >= (1 << (nr_irq + 1)))
143 printk(KERN_INFO " ERROR: Mismatch in kind-of-intr param\n");
145 #ifdef CONFIG_SELFMOD_INTC
146 selfmod_function((int *) arr_func, intc_baseaddr);
147 #endif
148 printk(KERN_INFO "%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
149 intc_list[j], intc_baseaddr, nr_irq, intr_type);
152 * Disable all external interrupts until they are
153 * explicity requested.
155 out_be32(intc_baseaddr + IER, 0);
157 /* Acknowledge any pending interrupts just in case. */
158 out_be32(intc_baseaddr + IAR, 0xffffffff);
160 /* Turn on the Master Enable. */
161 out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);
163 for (i = 0; i < nr_irq; ++i) {
164 if (intr_type & (0x00000001 << i)) {
165 set_irq_chip_and_handler_name(i, &intc_dev,
166 handle_edge_irq, intc_dev.name);
167 irq_desc[i].status &= ~IRQ_LEVEL;
168 } else {
169 set_irq_chip_and_handler_name(i, &intc_dev,
170 handle_level_irq, intc_dev.name);
171 irq_desc[i].status |= IRQ_LEVEL;