Linux 2.6.31.6
[linux/fpc-iii.git] / arch / mips / pci / pci.c
blobb0eb9e75c6829444c10815312f0e0a145cb331e9
1 /*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
7 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
8 */
9 #include <linux/kernel.h>
10 #include <linux/mm.h>
11 #include <linux/bootmem.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/pci.h>
17 * Indicate whether we respect the PCI setup left by the firmware.
19 * Make this long-lived so that we know when shutting down
20 * whether we probed only or not.
22 int pci_probe_only;
24 #define PCI_ASSIGN_ALL_BUSSES 1
26 unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
29 * The PCI controller list.
32 static struct pci_controller *hose_head, **hose_tail = &hose_head;
34 unsigned long PCIBIOS_MIN_IO = 0x0000;
35 unsigned long PCIBIOS_MIN_MEM = 0;
37 static int pci_initialized;
40 * We need to avoid collisions with `mirrored' VGA ports
41 * and other strange ISA hardware, so we always want the
42 * addresses to be allocated in the 0x000-0x0ff region
43 * modulo 0x400.
45 * Why? Because some silly external IO cards only decode
46 * the low 10 bits of the IO address. The 0x00-0xff region
47 * is reserved for motherboard devices that decode all 16
48 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
49 * but we want to try to avoid allocating at 0x2900-0x2bff
50 * which might have be mirrored at 0x0100-0x03ff..
52 void
53 pcibios_align_resource(void *data, struct resource *res,
54 resource_size_t size, resource_size_t align)
56 struct pci_dev *dev = data;
57 struct pci_controller *hose = dev->sysdata;
58 resource_size_t start = res->start;
60 if (res->flags & IORESOURCE_IO) {
61 /* Make sure we start at our min on all hoses */
62 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
63 start = PCIBIOS_MIN_IO + hose->io_resource->start;
66 * Put everything into 0x00-0xff region modulo 0x400
68 if (start & 0x300)
69 start = (start + 0x3ff) & ~0x3ff;
70 } else if (res->flags & IORESOURCE_MEM) {
71 /* Make sure we start at our min on all hoses */
72 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
73 start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
76 res->start = start;
79 static void __devinit pcibios_scanbus(struct pci_controller *hose)
81 static int next_busno;
82 static int need_domain_info;
83 struct pci_bus *bus;
85 if (!hose->iommu)
86 PCI_DMA_BUS_IS_PHYS = 1;
88 if (hose->get_busno && pci_probe_only)
89 next_busno = (*hose->get_busno)();
91 bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
92 hose->bus = bus;
94 need_domain_info = need_domain_info || hose->index;
95 hose->need_domain_info = need_domain_info;
96 if (bus) {
97 next_busno = bus->subordinate + 1;
98 /* Don't allow 8-bit bus number overflow inside the hose -
99 reserve some space for bridges. */
100 if (next_busno > 224) {
101 next_busno = 0;
102 need_domain_info = 1;
105 if (!pci_probe_only) {
106 pci_bus_size_bridges(bus);
107 pci_bus_assign_resources(bus);
108 pci_enable_bridges(bus);
113 static DEFINE_MUTEX(pci_scan_mutex);
115 void __devinit register_pci_controller(struct pci_controller *hose)
117 if (request_resource(&iomem_resource, hose->mem_resource) < 0)
118 goto out;
119 if (request_resource(&ioport_resource, hose->io_resource) < 0) {
120 release_resource(hose->mem_resource);
121 goto out;
124 *hose_tail = hose;
125 hose_tail = &hose->next;
128 * Do not panic here but later - this might hapen before console init.
130 if (!hose->io_map_base) {
131 printk(KERN_WARNING
132 "registering PCI controller with io_map_base unset\n");
136 * Scan the bus if it is register after the PCI subsystem
137 * initialization.
139 if (pci_initialized) {
140 mutex_lock(&pci_scan_mutex);
141 pcibios_scanbus(hose);
142 mutex_unlock(&pci_scan_mutex);
145 return;
147 out:
148 printk(KERN_WARNING
149 "Skipping PCI bus scan due to resource conflict\n");
152 static int __init pcibios_init(void)
154 struct pci_controller *hose;
156 /* Scan all of the recorded PCI controllers. */
157 for (hose = hose_head; hose; hose = hose->next)
158 pcibios_scanbus(hose);
160 pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
162 pci_initialized = 1;
164 return 0;
167 subsys_initcall(pcibios_init);
169 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
171 u16 cmd, old_cmd;
172 int idx;
173 struct resource *r;
175 pci_read_config_word(dev, PCI_COMMAND, &cmd);
176 old_cmd = cmd;
177 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
178 /* Only set up the requested stuff */
179 if (!(mask & (1<<idx)))
180 continue;
182 r = &dev->resource[idx];
183 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
184 continue;
185 if ((idx == PCI_ROM_RESOURCE) &&
186 (!(r->flags & IORESOURCE_ROM_ENABLE)))
187 continue;
188 if (!r->start && r->end) {
189 printk(KERN_ERR "PCI: Device %s not available "
190 "because of resource collisions\n",
191 pci_name(dev));
192 return -EINVAL;
194 if (r->flags & IORESOURCE_IO)
195 cmd |= PCI_COMMAND_IO;
196 if (r->flags & IORESOURCE_MEM)
197 cmd |= PCI_COMMAND_MEMORY;
199 if (cmd != old_cmd) {
200 printk("PCI: Enabling device %s (%04x -> %04x)\n",
201 pci_name(dev), old_cmd, cmd);
202 pci_write_config_word(dev, PCI_COMMAND, cmd);
204 return 0;
208 * If we set up a device for bus mastering, we need to check the latency
209 * timer as certain crappy BIOSes forget to set it properly.
211 static unsigned int pcibios_max_latency = 255;
213 void pcibios_set_master(struct pci_dev *dev)
215 u8 lat;
216 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
217 if (lat < 16)
218 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
219 else if (lat > pcibios_max_latency)
220 lat = pcibios_max_latency;
221 else
222 return;
223 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
224 pci_name(dev), lat);
225 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
228 unsigned int pcibios_assign_all_busses(void)
230 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
233 int pcibios_enable_device(struct pci_dev *dev, int mask)
235 int err;
237 if ((err = pcibios_enable_resources(dev, mask)) < 0)
238 return err;
240 return pcibios_plat_dev_init(dev);
243 static void pcibios_fixup_device_resources(struct pci_dev *dev,
244 struct pci_bus *bus)
246 /* Update device resources. */
247 struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
248 unsigned long offset = 0;
249 int i;
251 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
252 if (!dev->resource[i].start)
253 continue;
254 if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
255 continue;
256 if (dev->resource[i].flags & IORESOURCE_IO)
257 offset = hose->io_offset;
258 else if (dev->resource[i].flags & IORESOURCE_MEM)
259 offset = hose->mem_offset;
261 dev->resource[i].start += offset;
262 dev->resource[i].end += offset;
266 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
268 /* Propagate hose info into the subordinate devices. */
270 struct pci_controller *hose = bus->sysdata;
271 struct list_head *ln;
272 struct pci_dev *dev = bus->self;
274 if (!dev) {
275 bus->resource[0] = hose->io_resource;
276 bus->resource[1] = hose->mem_resource;
277 } else if (pci_probe_only &&
278 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
279 pci_read_bridge_bases(bus);
280 pcibios_fixup_device_resources(dev, bus);
283 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
284 dev = pci_dev_b(ln);
286 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
287 pcibios_fixup_device_resources(dev, bus);
291 void __init
292 pcibios_update_irq(struct pci_dev *dev, int irq)
294 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
297 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
298 struct resource *res)
300 struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
301 unsigned long offset = 0;
303 if (res->flags & IORESOURCE_IO)
304 offset = hose->io_offset;
305 else if (res->flags & IORESOURCE_MEM)
306 offset = hose->mem_offset;
308 region->start = res->start - offset;
309 region->end = res->end - offset;
312 void __devinit
313 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
314 struct pci_bus_region *region)
316 struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
317 unsigned long offset = 0;
319 if (res->flags & IORESOURCE_IO)
320 offset = hose->io_offset;
321 else if (res->flags & IORESOURCE_MEM)
322 offset = hose->mem_offset;
324 res->start = region->start + offset;
325 res->end = region->end + offset;
328 #ifdef CONFIG_HOTPLUG
329 EXPORT_SYMBOL(pcibios_resource_to_bus);
330 EXPORT_SYMBOL(pcibios_bus_to_resource);
331 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
332 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
333 #endif
335 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
336 enum pci_mmap_state mmap_state, int write_combine)
338 unsigned long prot;
341 * I/O space can be accessed via normal processor loads and stores on
342 * this platform but for now we elect not to do this and portable
343 * drivers should not do this anyway.
345 if (mmap_state == pci_mmap_io)
346 return -EINVAL;
349 * Ignore write-combine; for now only return uncached mappings.
351 prot = pgprot_val(vma->vm_page_prot);
352 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
353 vma->vm_page_prot = __pgprot(prot);
355 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
356 vma->vm_end - vma->vm_start, vma->vm_page_prot);
359 char * (*pcibios_plat_setup)(char *str) __devinitdata;
361 char *__devinit pcibios_setup(char *str)
363 if (pcibios_plat_setup)
364 return pcibios_plat_setup(str);
365 return str;